1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_IMPL_H 36 #define _SYS_EFX_IMPL_H 37 38 #include "efx.h" 39 #include "efx_regs.h" 40 #include "efx_regs_ef10.h" 41 42 /* FIXME: Add definition for driver generated software events */ 43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 45 #endif 46 47 48 #if EFSYS_OPT_SIENA 49 #include "siena_impl.h" 50 #endif /* EFSYS_OPT_SIENA */ 51 52 #if EFSYS_OPT_HUNTINGTON 53 #include "hunt_impl.h" 54 #endif /* EFSYS_OPT_HUNTINGTON */ 55 56 #if EFSYS_OPT_MEDFORD 57 #include "medford_impl.h" 58 #endif /* EFSYS_OPT_MEDFORD */ 59 60 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 61 #include "ef10_impl.h" 62 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif 67 68 #define EFX_MOD_MCDI 0x00000001 69 #define EFX_MOD_PROBE 0x00000002 70 #define EFX_MOD_NVRAM 0x00000004 71 #define EFX_MOD_VPD 0x00000008 72 #define EFX_MOD_NIC 0x00000010 73 #define EFX_MOD_INTR 0x00000020 74 #define EFX_MOD_EV 0x00000040 75 #define EFX_MOD_RX 0x00000080 76 #define EFX_MOD_TX 0x00000100 77 #define EFX_MOD_PORT 0x00000200 78 #define EFX_MOD_MON 0x00000400 79 #define EFX_MOD_FILTER 0x00001000 80 #define EFX_MOD_LIC 0x00002000 81 82 #define EFX_RESET_PHY 0x00000001 83 #define EFX_RESET_RXQ_ERR 0x00000002 84 #define EFX_RESET_TXQ_ERR 0x00000004 85 86 typedef enum efx_mac_type_e { 87 EFX_MAC_INVALID = 0, 88 EFX_MAC_SIENA, 89 EFX_MAC_HUNTINGTON, 90 EFX_MAC_MEDFORD, 91 EFX_MAC_NTYPES 92 } efx_mac_type_t; 93 94 typedef struct efx_ev_ops_s { 95 efx_rc_t (*eevo_init)(efx_nic_t *); 96 void (*eevo_fini)(efx_nic_t *); 97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 98 efsys_mem_t *, size_t, uint32_t, 99 uint32_t, uint32_t, efx_evq_t *); 100 void (*eevo_qdestroy)(efx_evq_t *); 101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 102 void (*eevo_qpost)(efx_evq_t *, uint16_t); 103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 104 #if EFSYS_OPT_QSTATS 105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 106 #endif 107 } efx_ev_ops_t; 108 109 typedef struct efx_tx_ops_s { 110 efx_rc_t (*etxo_init)(efx_nic_t *); 111 void (*etxo_fini)(efx_nic_t *); 112 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 113 unsigned int, unsigned int, 114 efsys_mem_t *, size_t, 115 uint32_t, uint16_t, 116 efx_evq_t *, efx_txq_t *, 117 unsigned int *); 118 void (*etxo_qdestroy)(efx_txq_t *); 119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 120 unsigned int, unsigned int, 121 unsigned int *); 122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 124 efx_rc_t (*etxo_qflush)(efx_txq_t *); 125 void (*etxo_qenable)(efx_txq_t *); 126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 127 void (*etxo_qpio_disable)(efx_txq_t *); 128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 129 size_t); 130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 131 unsigned int *); 132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 133 unsigned int, unsigned int, 134 unsigned int *); 135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 136 size_t, boolean_t, 137 efx_desc_t *); 138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 139 uint32_t, uint8_t, 140 efx_desc_t *); 141 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 142 uint32_t, uint16_t, 143 efx_desc_t *, int); 144 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 145 efx_desc_t *); 146 #if EFSYS_OPT_QSTATS 147 void (*etxo_qstats_update)(efx_txq_t *, 148 efsys_stat_t *); 149 #endif 150 } efx_tx_ops_t; 151 152 typedef struct efx_rx_ops_s { 153 efx_rc_t (*erxo_init)(efx_nic_t *); 154 void (*erxo_fini)(efx_nic_t *); 155 #if EFSYS_OPT_RX_SCATTER 156 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 157 #endif 158 #if EFSYS_OPT_RX_SCALE 159 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 160 efx_rx_scale_context_type_t, 161 uint32_t, uint32_t *); 162 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 163 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 164 efx_rx_hash_alg_t, 165 efx_rx_hash_type_t, boolean_t); 166 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 167 uint8_t *, size_t); 168 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 169 unsigned int *, size_t); 170 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 171 uint8_t *); 172 #endif /* EFSYS_OPT_RX_SCALE */ 173 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 174 uint16_t *); 175 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 176 unsigned int, unsigned int, 177 unsigned int); 178 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 179 #if EFSYS_OPT_RX_PACKED_STREAM 180 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 181 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 182 uint32_t, uint32_t, 183 uint16_t *, uint32_t *, uint32_t *); 184 #endif 185 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 186 void (*erxo_qenable)(efx_rxq_t *); 187 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 188 unsigned int, efx_rxq_type_t, 189 efsys_mem_t *, size_t, uint32_t, 190 efx_evq_t *, efx_rxq_t *); 191 void (*erxo_qdestroy)(efx_rxq_t *); 192 } efx_rx_ops_t; 193 194 typedef struct efx_mac_ops_s { 195 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 196 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 197 efx_rc_t (*emo_addr_set)(efx_nic_t *); 198 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 199 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 200 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 201 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 202 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 203 efx_rxq_t *, boolean_t); 204 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 205 #if EFSYS_OPT_LOOPBACK 206 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 207 efx_loopback_type_t); 208 #endif /* EFSYS_OPT_LOOPBACK */ 209 #if EFSYS_OPT_MAC_STATS 210 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 211 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 212 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 213 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 214 uint16_t, boolean_t); 215 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 216 efsys_stat_t *, uint32_t *); 217 #endif /* EFSYS_OPT_MAC_STATS */ 218 } efx_mac_ops_t; 219 220 typedef struct efx_phy_ops_s { 221 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 222 efx_rc_t (*epo_reset)(efx_nic_t *); 223 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 224 efx_rc_t (*epo_verify)(efx_nic_t *); 225 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 226 #if EFSYS_OPT_PHY_STATS 227 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 228 uint32_t *); 229 #endif /* EFSYS_OPT_PHY_STATS */ 230 #if EFSYS_OPT_BIST 231 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 232 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 233 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 234 efx_bist_result_t *, uint32_t *, 235 unsigned long *, size_t); 236 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 237 #endif /* EFSYS_OPT_BIST */ 238 } efx_phy_ops_t; 239 240 #if EFSYS_OPT_FILTER 241 typedef struct efx_filter_ops_s { 242 efx_rc_t (*efo_init)(efx_nic_t *); 243 void (*efo_fini)(efx_nic_t *); 244 efx_rc_t (*efo_restore)(efx_nic_t *); 245 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 246 boolean_t may_replace); 247 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 248 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 249 size_t, size_t *); 250 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 251 boolean_t, boolean_t, boolean_t, 252 uint8_t const *, uint32_t); 253 } efx_filter_ops_t; 254 255 extern __checkReturn efx_rc_t 256 efx_filter_reconfigure( 257 __in efx_nic_t *enp, 258 __in_ecount(6) uint8_t const *mac_addr, 259 __in boolean_t all_unicst, 260 __in boolean_t mulcst, 261 __in boolean_t all_mulcst, 262 __in boolean_t brdcst, 263 __in_ecount(6*count) uint8_t const *addrs, 264 __in uint32_t count); 265 266 #endif /* EFSYS_OPT_FILTER */ 267 268 269 typedef struct efx_port_s { 270 efx_mac_type_t ep_mac_type; 271 uint32_t ep_phy_type; 272 uint8_t ep_port; 273 uint32_t ep_mac_pdu; 274 uint8_t ep_mac_addr[6]; 275 efx_link_mode_t ep_link_mode; 276 boolean_t ep_all_unicst; 277 boolean_t ep_mulcst; 278 boolean_t ep_all_mulcst; 279 boolean_t ep_brdcst; 280 unsigned int ep_fcntl; 281 boolean_t ep_fcntl_autoneg; 282 efx_oword_t ep_multicst_hash[2]; 283 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 284 EFX_MAC_MULTICAST_LIST_MAX]; 285 uint32_t ep_mulcst_addr_count; 286 #if EFSYS_OPT_LOOPBACK 287 efx_loopback_type_t ep_loopback_type; 288 efx_link_mode_t ep_loopback_link_mode; 289 #endif /* EFSYS_OPT_LOOPBACK */ 290 #if EFSYS_OPT_PHY_FLAGS 291 uint32_t ep_phy_flags; 292 #endif /* EFSYS_OPT_PHY_FLAGS */ 293 #if EFSYS_OPT_PHY_LED_CONTROL 294 efx_phy_led_mode_t ep_phy_led_mode; 295 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 296 efx_phy_media_type_t ep_fixed_port_type; 297 efx_phy_media_type_t ep_module_type; 298 uint32_t ep_adv_cap_mask; 299 uint32_t ep_lp_cap_mask; 300 uint32_t ep_default_adv_cap_mask; 301 uint32_t ep_phy_cap_mask; 302 boolean_t ep_mac_drain; 303 boolean_t ep_mac_stats_pending; 304 #if EFSYS_OPT_BIST 305 efx_bist_type_t ep_current_bist; 306 #endif 307 const efx_mac_ops_t *ep_emop; 308 const efx_phy_ops_t *ep_epop; 309 } efx_port_t; 310 311 typedef struct efx_mon_ops_s { 312 #if EFSYS_OPT_MON_STATS 313 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 314 efx_mon_stat_value_t *); 315 #endif /* EFSYS_OPT_MON_STATS */ 316 } efx_mon_ops_t; 317 318 typedef struct efx_mon_s { 319 efx_mon_type_t em_type; 320 const efx_mon_ops_t *em_emop; 321 } efx_mon_t; 322 323 typedef struct efx_intr_ops_s { 324 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 325 void (*eio_enable)(efx_nic_t *); 326 void (*eio_disable)(efx_nic_t *); 327 void (*eio_disable_unlocked)(efx_nic_t *); 328 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 329 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 330 void (*eio_status_message)(efx_nic_t *, unsigned int, 331 boolean_t *); 332 void (*eio_fatal)(efx_nic_t *); 333 void (*eio_fini)(efx_nic_t *); 334 } efx_intr_ops_t; 335 336 typedef struct efx_intr_s { 337 const efx_intr_ops_t *ei_eiop; 338 efsys_mem_t *ei_esmp; 339 efx_intr_type_t ei_type; 340 unsigned int ei_level; 341 } efx_intr_t; 342 343 typedef struct efx_nic_ops_s { 344 efx_rc_t (*eno_probe)(efx_nic_t *); 345 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 346 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 347 efx_rc_t (*eno_reset)(efx_nic_t *); 348 efx_rc_t (*eno_init)(efx_nic_t *); 349 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 350 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 351 uint32_t *, size_t *); 352 #if EFSYS_OPT_DIAG 353 efx_rc_t (*eno_register_test)(efx_nic_t *); 354 #endif /* EFSYS_OPT_DIAG */ 355 void (*eno_fini)(efx_nic_t *); 356 void (*eno_unprobe)(efx_nic_t *); 357 } efx_nic_ops_t; 358 359 #ifndef EFX_TXQ_LIMIT_TARGET 360 #define EFX_TXQ_LIMIT_TARGET 259 361 #endif 362 #ifndef EFX_RXQ_LIMIT_TARGET 363 #define EFX_RXQ_LIMIT_TARGET 512 364 #endif 365 366 367 #if EFSYS_OPT_FILTER 368 369 typedef struct siena_filter_spec_s { 370 uint8_t sfs_type; 371 uint32_t sfs_flags; 372 uint32_t sfs_dmaq_id; 373 uint32_t sfs_dword[3]; 374 } siena_filter_spec_t; 375 376 typedef enum siena_filter_type_e { 377 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 378 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 379 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 380 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 381 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 382 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 383 384 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 385 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 386 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 387 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 388 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 389 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 390 391 EFX_SIENA_FILTER_NTYPES 392 } siena_filter_type_t; 393 394 typedef enum siena_filter_tbl_id_e { 395 EFX_SIENA_FILTER_TBL_RX_IP = 0, 396 EFX_SIENA_FILTER_TBL_RX_MAC, 397 EFX_SIENA_FILTER_TBL_TX_IP, 398 EFX_SIENA_FILTER_TBL_TX_MAC, 399 EFX_SIENA_FILTER_NTBLS 400 } siena_filter_tbl_id_t; 401 402 typedef struct siena_filter_tbl_s { 403 int sft_size; /* number of entries */ 404 int sft_used; /* active count */ 405 uint32_t *sft_bitmap; /* active bitmap */ 406 siena_filter_spec_t *sft_spec; /* array of saved specs */ 407 } siena_filter_tbl_t; 408 409 typedef struct siena_filter_s { 410 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 411 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 412 } siena_filter_t; 413 414 typedef struct efx_filter_s { 415 #if EFSYS_OPT_SIENA 416 siena_filter_t *ef_siena_filter; 417 #endif /* EFSYS_OPT_SIENA */ 418 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 419 ef10_filter_table_t *ef_ef10_filter_table; 420 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 421 } efx_filter_t; 422 423 extern void 424 siena_filter_tbl_clear( 425 __in efx_nic_t *enp, 426 __in siena_filter_tbl_id_t tbl); 427 428 #endif /* EFSYS_OPT_FILTER */ 429 430 #if EFSYS_OPT_MCDI 431 432 typedef struct efx_mcdi_ops_s { 433 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 434 void (*emco_send_request)(efx_nic_t *, void *, size_t, 435 void *, size_t); 436 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 437 boolean_t (*emco_poll_response)(efx_nic_t *); 438 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 439 void (*emco_fini)(efx_nic_t *); 440 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 441 efx_mcdi_feature_id_t, boolean_t *); 442 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 443 uint32_t *); 444 } efx_mcdi_ops_t; 445 446 typedef struct efx_mcdi_s { 447 const efx_mcdi_ops_t *em_emcop; 448 const efx_mcdi_transport_t *em_emtp; 449 efx_mcdi_iface_t em_emip; 450 } efx_mcdi_t; 451 452 #endif /* EFSYS_OPT_MCDI */ 453 454 #if EFSYS_OPT_NVRAM 455 456 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 457 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 458 459 typedef struct efx_nvram_ops_s { 460 #if EFSYS_OPT_DIAG 461 efx_rc_t (*envo_test)(efx_nic_t *); 462 #endif /* EFSYS_OPT_DIAG */ 463 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 464 uint32_t *); 465 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 466 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 467 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 468 unsigned int, caddr_t, size_t); 469 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 470 unsigned int, caddr_t, size_t); 471 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 472 unsigned int, size_t); 473 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 474 unsigned int, caddr_t, size_t); 475 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 476 uint32_t *); 477 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 478 uint32_t *, uint16_t *); 479 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 480 uint16_t *); 481 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t, 482 caddr_t, size_t); 483 } efx_nvram_ops_t; 484 #endif /* EFSYS_OPT_NVRAM */ 485 486 #if EFSYS_OPT_VPD 487 typedef struct efx_vpd_ops_s { 488 efx_rc_t (*evpdo_init)(efx_nic_t *); 489 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 490 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 491 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 492 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 493 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 494 efx_vpd_value_t *); 495 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 496 efx_vpd_value_t *); 497 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 498 efx_vpd_value_t *, unsigned int *); 499 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 500 void (*evpdo_fini)(efx_nic_t *); 501 } efx_vpd_ops_t; 502 #endif /* EFSYS_OPT_VPD */ 503 504 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 505 506 __checkReturn efx_rc_t 507 efx_mcdi_nvram_partitions( 508 __in efx_nic_t *enp, 509 __out_bcount(size) caddr_t data, 510 __in size_t size, 511 __out unsigned int *npartnp); 512 513 __checkReturn efx_rc_t 514 efx_mcdi_nvram_metadata( 515 __in efx_nic_t *enp, 516 __in uint32_t partn, 517 __out uint32_t *subtypep, 518 __out_ecount(4) uint16_t version[4], 519 __out_bcount_opt(size) char *descp, 520 __in size_t size); 521 522 __checkReturn efx_rc_t 523 efx_mcdi_nvram_info( 524 __in efx_nic_t *enp, 525 __in uint32_t partn, 526 __out_opt size_t *sizep, 527 __out_opt uint32_t *addressp, 528 __out_opt uint32_t *erase_sizep, 529 __out_opt uint32_t *write_sizep); 530 531 __checkReturn efx_rc_t 532 efx_mcdi_nvram_update_start( 533 __in efx_nic_t *enp, 534 __in uint32_t partn); 535 536 __checkReturn efx_rc_t 537 efx_mcdi_nvram_read( 538 __in efx_nic_t *enp, 539 __in uint32_t partn, 540 __in uint32_t offset, 541 __out_bcount(size) caddr_t data, 542 __in size_t size, 543 __in uint32_t mode); 544 545 __checkReturn efx_rc_t 546 efx_mcdi_nvram_erase( 547 __in efx_nic_t *enp, 548 __in uint32_t partn, 549 __in uint32_t offset, 550 __in size_t size); 551 552 __checkReturn efx_rc_t 553 efx_mcdi_nvram_write( 554 __in efx_nic_t *enp, 555 __in uint32_t partn, 556 __in uint32_t offset, 557 __out_bcount(size) caddr_t data, 558 __in size_t size); 559 560 __checkReturn efx_rc_t 561 efx_mcdi_nvram_update_finish( 562 __in efx_nic_t *enp, 563 __in uint32_t partn, 564 __in boolean_t reboot, 565 __out_opt uint32_t *verify_resultp); 566 567 #if EFSYS_OPT_DIAG 568 569 __checkReturn efx_rc_t 570 efx_mcdi_nvram_test( 571 __in efx_nic_t *enp, 572 __in uint32_t partn); 573 574 #endif /* EFSYS_OPT_DIAG */ 575 576 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 577 578 #if EFSYS_OPT_LICENSING 579 580 typedef struct efx_lic_ops_s { 581 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 582 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 583 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 584 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 585 size_t *, uint8_t *); 586 efx_rc_t (*elo_find_start) 587 (efx_nic_t *, caddr_t, size_t, uint32_t *); 588 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 589 uint32_t, uint32_t *); 590 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 591 uint32_t, uint32_t *, uint32_t *); 592 boolean_t (*elo_validate_key)(efx_nic_t *, 593 caddr_t, uint32_t); 594 efx_rc_t (*elo_read_key)(efx_nic_t *, 595 caddr_t, size_t, uint32_t, uint32_t, 596 caddr_t, size_t, uint32_t *); 597 efx_rc_t (*elo_write_key)(efx_nic_t *, 598 caddr_t, size_t, uint32_t, 599 caddr_t, uint32_t, uint32_t *); 600 efx_rc_t (*elo_delete_key)(efx_nic_t *, 601 caddr_t, size_t, uint32_t, 602 uint32_t, uint32_t, uint32_t *); 603 efx_rc_t (*elo_create_partition)(efx_nic_t *, 604 caddr_t, size_t); 605 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 606 caddr_t, size_t); 607 } efx_lic_ops_t; 608 609 #endif 610 611 typedef struct efx_drv_cfg_s { 612 uint32_t edc_min_vi_count; 613 uint32_t edc_max_vi_count; 614 615 uint32_t edc_max_piobuf_count; 616 uint32_t edc_pio_alloc_size; 617 } efx_drv_cfg_t; 618 619 struct efx_nic_s { 620 uint32_t en_magic; 621 efx_family_t en_family; 622 uint32_t en_features; 623 efsys_identifier_t *en_esip; 624 efsys_lock_t *en_eslp; 625 efsys_bar_t *en_esbp; 626 unsigned int en_mod_flags; 627 unsigned int en_reset_flags; 628 efx_nic_cfg_t en_nic_cfg; 629 efx_drv_cfg_t en_drv_cfg; 630 efx_port_t en_port; 631 efx_mon_t en_mon; 632 efx_intr_t en_intr; 633 uint32_t en_ev_qcount; 634 uint32_t en_rx_qcount; 635 uint32_t en_tx_qcount; 636 const efx_nic_ops_t *en_enop; 637 const efx_ev_ops_t *en_eevop; 638 const efx_tx_ops_t *en_etxop; 639 const efx_rx_ops_t *en_erxop; 640 #if EFSYS_OPT_FILTER 641 efx_filter_t en_filter; 642 const efx_filter_ops_t *en_efop; 643 #endif /* EFSYS_OPT_FILTER */ 644 #if EFSYS_OPT_MCDI 645 efx_mcdi_t en_mcdi; 646 #endif /* EFSYS_OPT_MCDI */ 647 #if EFSYS_OPT_NVRAM 648 uint32_t en_nvram_partn_locked; 649 const efx_nvram_ops_t *en_envop; 650 #endif /* EFSYS_OPT_NVRAM */ 651 #if EFSYS_OPT_VPD 652 const efx_vpd_ops_t *en_evpdop; 653 #endif /* EFSYS_OPT_VPD */ 654 #if EFSYS_OPT_RX_SCALE 655 efx_rx_hash_support_t en_hash_support; 656 efx_rx_scale_context_type_t en_rss_context_type; 657 uint32_t en_rss_context; 658 #endif /* EFSYS_OPT_RX_SCALE */ 659 uint32_t en_vport_id; 660 #if EFSYS_OPT_LICENSING 661 const efx_lic_ops_t *en_elop; 662 boolean_t en_licensing_supported; 663 #endif 664 union { 665 #if EFSYS_OPT_SIENA 666 struct { 667 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 668 unsigned int enu_partn_mask; 669 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 670 #if EFSYS_OPT_VPD 671 caddr_t enu_svpd; 672 size_t enu_svpd_length; 673 #endif /* EFSYS_OPT_VPD */ 674 int enu_unused; 675 } siena; 676 #endif /* EFSYS_OPT_SIENA */ 677 int enu_unused; 678 } en_u; 679 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 680 union en_arch { 681 struct { 682 int ena_vi_base; 683 int ena_vi_count; 684 int ena_vi_shift; 685 #if EFSYS_OPT_VPD 686 caddr_t ena_svpd; 687 size_t ena_svpd_length; 688 #endif /* EFSYS_OPT_VPD */ 689 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 690 uint32_t ena_piobuf_count; 691 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 692 uint32_t ena_pio_write_vi_base; 693 /* Memory BAR mapping regions */ 694 uint32_t ena_uc_mem_map_offset; 695 size_t ena_uc_mem_map_size; 696 uint32_t ena_wc_mem_map_offset; 697 size_t ena_wc_mem_map_size; 698 } ef10; 699 } en_arch; 700 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 701 }; 702 703 704 #define EFX_NIC_MAGIC 0x02121996 705 706 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 707 const efx_ev_callbacks_t *, void *); 708 709 typedef struct efx_evq_rxq_state_s { 710 unsigned int eers_rx_read_ptr; 711 unsigned int eers_rx_mask; 712 #if EFSYS_OPT_RX_PACKED_STREAM 713 unsigned int eers_rx_stream_npackets; 714 boolean_t eers_rx_packed_stream; 715 unsigned int eers_rx_packed_stream_credits; 716 #endif 717 } efx_evq_rxq_state_t; 718 719 struct efx_evq_s { 720 uint32_t ee_magic; 721 efx_nic_t *ee_enp; 722 unsigned int ee_index; 723 unsigned int ee_mask; 724 efsys_mem_t *ee_esmp; 725 #if EFSYS_OPT_QSTATS 726 uint32_t ee_stat[EV_NQSTATS]; 727 #endif /* EFSYS_OPT_QSTATS */ 728 729 efx_ev_handler_t ee_rx; 730 efx_ev_handler_t ee_tx; 731 efx_ev_handler_t ee_driver; 732 efx_ev_handler_t ee_global; 733 efx_ev_handler_t ee_drv_gen; 734 #if EFSYS_OPT_MCDI 735 efx_ev_handler_t ee_mcdi; 736 #endif /* EFSYS_OPT_MCDI */ 737 738 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 739 740 uint32_t ee_flags; 741 }; 742 743 #define EFX_EVQ_MAGIC 0x08081997 744 745 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 746 747 struct efx_rxq_s { 748 uint32_t er_magic; 749 efx_nic_t *er_enp; 750 efx_evq_t *er_eep; 751 unsigned int er_index; 752 unsigned int er_label; 753 unsigned int er_mask; 754 efsys_mem_t *er_esmp; 755 efx_evq_rxq_state_t *er_ev_qstate; 756 }; 757 758 #define EFX_RXQ_MAGIC 0x15022005 759 760 struct efx_txq_s { 761 uint32_t et_magic; 762 efx_nic_t *et_enp; 763 unsigned int et_index; 764 unsigned int et_mask; 765 efsys_mem_t *et_esmp; 766 #if EFSYS_OPT_HUNTINGTON 767 uint32_t et_pio_bufnum; 768 uint32_t et_pio_blknum; 769 uint32_t et_pio_write_offset; 770 uint32_t et_pio_offset; 771 size_t et_pio_size; 772 #endif 773 #if EFSYS_OPT_QSTATS 774 uint32_t et_stat[TX_NQSTATS]; 775 #endif /* EFSYS_OPT_QSTATS */ 776 }; 777 778 #define EFX_TXQ_MAGIC 0x05092005 779 780 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 781 do { \ 782 (_dst)[0] = (_src)[0]; \ 783 (_dst)[1] = (_src)[1]; \ 784 (_dst)[2] = (_src)[2]; \ 785 (_dst)[3] = (_src)[3]; \ 786 (_dst)[4] = (_src)[4]; \ 787 (_dst)[5] = (_src)[5]; \ 788 _NOTE(CONSTANTCONDITION) \ 789 } while (B_FALSE) 790 791 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 792 do { \ 793 uint16_t *_d = (uint16_t *)(_dst); \ 794 _d[0] = 0xffff; \ 795 _d[1] = 0xffff; \ 796 _d[2] = 0xffff; \ 797 _NOTE(CONSTANTCONDITION) \ 798 } while (B_FALSE) 799 800 #if EFSYS_OPT_CHECK_REG 801 #define EFX_CHECK_REG(_enp, _reg) \ 802 do { \ 803 const char *name = #_reg; \ 804 char min = name[4]; \ 805 char max = name[5]; \ 806 char rev; \ 807 \ 808 switch ((_enp)->en_family) { \ 809 case EFX_FAMILY_SIENA: \ 810 rev = 'C'; \ 811 break; \ 812 \ 813 case EFX_FAMILY_HUNTINGTON: \ 814 rev = 'D'; \ 815 break; \ 816 \ 817 case EFX_FAMILY_MEDFORD: \ 818 rev = 'E'; \ 819 break; \ 820 \ 821 default: \ 822 rev = '?'; \ 823 break; \ 824 } \ 825 \ 826 EFSYS_ASSERT3S(rev, >=, min); \ 827 EFSYS_ASSERT3S(rev, <=, max); \ 828 \ 829 _NOTE(CONSTANTCONDITION) \ 830 } while (B_FALSE) 831 #else 832 #define EFX_CHECK_REG(_enp, _reg) do { \ 833 _NOTE(CONSTANTCONDITION) \ 834 } while (B_FALSE) 835 #endif 836 837 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 838 do { \ 839 EFX_CHECK_REG((_enp), (_reg)); \ 840 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 841 (_edp), (_lock)); \ 842 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 843 uint32_t, _reg ## _OFST, \ 844 uint32_t, (_edp)->ed_u32[0]); \ 845 _NOTE(CONSTANTCONDITION) \ 846 } while (B_FALSE) 847 848 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 849 do { \ 850 EFX_CHECK_REG((_enp), (_reg)); \ 851 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 852 uint32_t, _reg ## _OFST, \ 853 uint32_t, (_edp)->ed_u32[0]); \ 854 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 855 (_edp), (_lock)); \ 856 _NOTE(CONSTANTCONDITION) \ 857 } while (B_FALSE) 858 859 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 860 do { \ 861 EFX_CHECK_REG((_enp), (_reg)); \ 862 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 863 (_eqp)); \ 864 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 865 uint32_t, _reg ## _OFST, \ 866 uint32_t, (_eqp)->eq_u32[1], \ 867 uint32_t, (_eqp)->eq_u32[0]); \ 868 _NOTE(CONSTANTCONDITION) \ 869 } while (B_FALSE) 870 871 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 872 do { \ 873 EFX_CHECK_REG((_enp), (_reg)); \ 874 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 875 uint32_t, _reg ## _OFST, \ 876 uint32_t, (_eqp)->eq_u32[1], \ 877 uint32_t, (_eqp)->eq_u32[0]); \ 878 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 879 (_eqp)); \ 880 _NOTE(CONSTANTCONDITION) \ 881 } while (B_FALSE) 882 883 #define EFX_BAR_READO(_enp, _reg, _eop) \ 884 do { \ 885 EFX_CHECK_REG((_enp), (_reg)); \ 886 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 887 (_eop), B_TRUE); \ 888 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 889 uint32_t, _reg ## _OFST, \ 890 uint32_t, (_eop)->eo_u32[3], \ 891 uint32_t, (_eop)->eo_u32[2], \ 892 uint32_t, (_eop)->eo_u32[1], \ 893 uint32_t, (_eop)->eo_u32[0]); \ 894 _NOTE(CONSTANTCONDITION) \ 895 } while (B_FALSE) 896 897 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 898 do { \ 899 EFX_CHECK_REG((_enp), (_reg)); \ 900 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 901 uint32_t, _reg ## _OFST, \ 902 uint32_t, (_eop)->eo_u32[3], \ 903 uint32_t, (_eop)->eo_u32[2], \ 904 uint32_t, (_eop)->eo_u32[1], \ 905 uint32_t, (_eop)->eo_u32[0]); \ 906 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 907 (_eop), B_TRUE); \ 908 _NOTE(CONSTANTCONDITION) \ 909 } while (B_FALSE) 910 911 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 912 do { \ 913 EFX_CHECK_REG((_enp), (_reg)); \ 914 EFSYS_BAR_READD((_enp)->en_esbp, \ 915 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 916 (_edp), (_lock)); \ 917 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 918 uint32_t, (_index), \ 919 uint32_t, _reg ## _OFST, \ 920 uint32_t, (_edp)->ed_u32[0]); \ 921 _NOTE(CONSTANTCONDITION) \ 922 } while (B_FALSE) 923 924 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 925 do { \ 926 EFX_CHECK_REG((_enp), (_reg)); \ 927 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 928 uint32_t, (_index), \ 929 uint32_t, _reg ## _OFST, \ 930 uint32_t, (_edp)->ed_u32[0]); \ 931 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 932 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 933 (_edp), (_lock)); \ 934 _NOTE(CONSTANTCONDITION) \ 935 } while (B_FALSE) 936 937 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 938 do { \ 939 EFX_CHECK_REG((_enp), (_reg)); \ 940 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 941 uint32_t, (_index), \ 942 uint32_t, _reg ## _OFST, \ 943 uint32_t, (_edp)->ed_u32[0]); \ 944 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 945 (_reg ## _OFST + \ 946 (2 * sizeof (efx_dword_t)) + \ 947 ((_index) * _reg ## _STEP)), \ 948 (_edp), (_lock)); \ 949 _NOTE(CONSTANTCONDITION) \ 950 } while (B_FALSE) 951 952 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 953 do { \ 954 EFX_CHECK_REG((_enp), (_reg)); \ 955 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 956 uint32_t, (_index), \ 957 uint32_t, _reg ## _OFST, \ 958 uint32_t, (_edp)->ed_u32[0]); \ 959 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 960 (_reg ## _OFST + \ 961 (3 * sizeof (efx_dword_t)) + \ 962 ((_index) * _reg ## _STEP)), \ 963 (_edp), (_lock)); \ 964 _NOTE(CONSTANTCONDITION) \ 965 } while (B_FALSE) 966 967 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 968 do { \ 969 EFX_CHECK_REG((_enp), (_reg)); \ 970 EFSYS_BAR_READQ((_enp)->en_esbp, \ 971 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 972 (_eqp)); \ 973 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 974 uint32_t, (_index), \ 975 uint32_t, _reg ## _OFST, \ 976 uint32_t, (_eqp)->eq_u32[1], \ 977 uint32_t, (_eqp)->eq_u32[0]); \ 978 _NOTE(CONSTANTCONDITION) \ 979 } while (B_FALSE) 980 981 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 982 do { \ 983 EFX_CHECK_REG((_enp), (_reg)); \ 984 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 985 uint32_t, (_index), \ 986 uint32_t, _reg ## _OFST, \ 987 uint32_t, (_eqp)->eq_u32[1], \ 988 uint32_t, (_eqp)->eq_u32[0]); \ 989 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 990 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 991 (_eqp)); \ 992 _NOTE(CONSTANTCONDITION) \ 993 } while (B_FALSE) 994 995 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 996 do { \ 997 EFX_CHECK_REG((_enp), (_reg)); \ 998 EFSYS_BAR_READO((_enp)->en_esbp, \ 999 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1000 (_eop), (_lock)); \ 1001 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1002 uint32_t, (_index), \ 1003 uint32_t, _reg ## _OFST, \ 1004 uint32_t, (_eop)->eo_u32[3], \ 1005 uint32_t, (_eop)->eo_u32[2], \ 1006 uint32_t, (_eop)->eo_u32[1], \ 1007 uint32_t, (_eop)->eo_u32[0]); \ 1008 _NOTE(CONSTANTCONDITION) \ 1009 } while (B_FALSE) 1010 1011 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1012 do { \ 1013 EFX_CHECK_REG((_enp), (_reg)); \ 1014 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1015 uint32_t, (_index), \ 1016 uint32_t, _reg ## _OFST, \ 1017 uint32_t, (_eop)->eo_u32[3], \ 1018 uint32_t, (_eop)->eo_u32[2], \ 1019 uint32_t, (_eop)->eo_u32[1], \ 1020 uint32_t, (_eop)->eo_u32[0]); \ 1021 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1022 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1023 (_eop), (_lock)); \ 1024 _NOTE(CONSTANTCONDITION) \ 1025 } while (B_FALSE) 1026 1027 /* 1028 * Allow drivers to perform optimised 128-bit doorbell writes. 1029 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1030 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1031 * the need for locking in the host, and are the only ones known to be safe to 1032 * use 128-bites write with. 1033 */ 1034 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1035 do { \ 1036 EFX_CHECK_REG((_enp), (_reg)); \ 1037 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1038 const char *, #_reg, \ 1039 uint32_t, (_index), \ 1040 uint32_t, _reg ## _OFST, \ 1041 uint32_t, (_eop)->eo_u32[3], \ 1042 uint32_t, (_eop)->eo_u32[2], \ 1043 uint32_t, (_eop)->eo_u32[1], \ 1044 uint32_t, (_eop)->eo_u32[0]); \ 1045 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1046 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1047 (_eop)); \ 1048 _NOTE(CONSTANTCONDITION) \ 1049 } while (B_FALSE) 1050 1051 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1052 do { \ 1053 unsigned int _new = (_wptr); \ 1054 unsigned int _old = (_owptr); \ 1055 \ 1056 if ((_new) >= (_old)) \ 1057 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1058 (_old) * sizeof (efx_desc_t), \ 1059 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1060 else \ 1061 /* \ 1062 * It is cheaper to sync entire map than sync \ 1063 * two parts especially when offset/size are \ 1064 * ignored and entire map is synced in any case.\ 1065 */ \ 1066 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1067 0, \ 1068 (_entries) * sizeof (efx_desc_t)); \ 1069 _NOTE(CONSTANTCONDITION) \ 1070 } while (B_FALSE) 1071 1072 extern __checkReturn efx_rc_t 1073 efx_nic_biu_test( 1074 __in efx_nic_t *enp); 1075 1076 extern __checkReturn efx_rc_t 1077 efx_mac_select( 1078 __in efx_nic_t *enp); 1079 1080 extern void 1081 efx_mac_multicast_hash_compute( 1082 __in_ecount(6*count) uint8_t const *addrs, 1083 __in int count, 1084 __out efx_oword_t *hash_low, 1085 __out efx_oword_t *hash_high); 1086 1087 extern __checkReturn efx_rc_t 1088 efx_phy_probe( 1089 __in efx_nic_t *enp); 1090 1091 extern void 1092 efx_phy_unprobe( 1093 __in efx_nic_t *enp); 1094 1095 #if EFSYS_OPT_VPD 1096 1097 /* VPD utility functions */ 1098 1099 extern __checkReturn efx_rc_t 1100 efx_vpd_hunk_length( 1101 __in_bcount(size) caddr_t data, 1102 __in size_t size, 1103 __out size_t *lengthp); 1104 1105 extern __checkReturn efx_rc_t 1106 efx_vpd_hunk_verify( 1107 __in_bcount(size) caddr_t data, 1108 __in size_t size, 1109 __out_opt boolean_t *cksummedp); 1110 1111 extern __checkReturn efx_rc_t 1112 efx_vpd_hunk_reinit( 1113 __in_bcount(size) caddr_t data, 1114 __in size_t size, 1115 __in boolean_t wantpid); 1116 1117 extern __checkReturn efx_rc_t 1118 efx_vpd_hunk_get( 1119 __in_bcount(size) caddr_t data, 1120 __in size_t size, 1121 __in efx_vpd_tag_t tag, 1122 __in efx_vpd_keyword_t keyword, 1123 __out unsigned int *payloadp, 1124 __out uint8_t *paylenp); 1125 1126 extern __checkReturn efx_rc_t 1127 efx_vpd_hunk_next( 1128 __in_bcount(size) caddr_t data, 1129 __in size_t size, 1130 __out efx_vpd_tag_t *tagp, 1131 __out efx_vpd_keyword_t *keyword, 1132 __out_opt unsigned int *payloadp, 1133 __out_opt uint8_t *paylenp, 1134 __inout unsigned int *contp); 1135 1136 extern __checkReturn efx_rc_t 1137 efx_vpd_hunk_set( 1138 __in_bcount(size) caddr_t data, 1139 __in size_t size, 1140 __in efx_vpd_value_t *evvp); 1141 1142 #endif /* EFSYS_OPT_VPD */ 1143 1144 #if EFSYS_OPT_DIAG 1145 1146 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1147 1148 typedef struct efx_register_set_s { 1149 unsigned int address; 1150 unsigned int step; 1151 unsigned int rows; 1152 efx_oword_t mask; 1153 } efx_register_set_t; 1154 1155 extern __checkReturn efx_rc_t 1156 efx_nic_test_registers( 1157 __in efx_nic_t *enp, 1158 __in efx_register_set_t *rsp, 1159 __in size_t count); 1160 1161 extern __checkReturn efx_rc_t 1162 efx_nic_test_tables( 1163 __in efx_nic_t *enp, 1164 __in efx_register_set_t *rsp, 1165 __in efx_pattern_type_t pattern, 1166 __in size_t count); 1167 1168 #endif /* EFSYS_OPT_DIAG */ 1169 1170 #if EFSYS_OPT_MCDI 1171 1172 extern __checkReturn efx_rc_t 1173 efx_mcdi_set_workaround( 1174 __in efx_nic_t *enp, 1175 __in uint32_t type, 1176 __in boolean_t enabled, 1177 __out_opt uint32_t *flagsp); 1178 1179 extern __checkReturn efx_rc_t 1180 efx_mcdi_get_workarounds( 1181 __in efx_nic_t *enp, 1182 __out_opt uint32_t *implementedp, 1183 __out_opt uint32_t *enabledp); 1184 1185 #endif /* EFSYS_OPT_MCDI */ 1186 1187 #if EFSYS_OPT_MAC_STATS 1188 1189 /* 1190 * Closed range of stats (i.e. the first and the last are included). 1191 * The last must be greater or equal (if the range is one item only) to 1192 * the first. 1193 */ 1194 struct efx_mac_stats_range { 1195 efx_mac_stat_t first; 1196 efx_mac_stat_t last; 1197 }; 1198 1199 extern efx_rc_t 1200 efx_mac_stats_mask_add_ranges( 1201 __inout_bcount(mask_size) uint32_t *maskp, 1202 __in size_t mask_size, 1203 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1204 __in unsigned int rng_count); 1205 1206 #endif /* EFSYS_OPT_MAC_STATS */ 1207 1208 #ifdef __cplusplus 1209 } 1210 #endif 1211 1212 #endif /* _SYS_EFX_IMPL_H */ 1213