1 /*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EFX_IMPL_H 34 #define _SYS_EFX_IMPL_H 35 36 #include "efsys.h" 37 #include "efx.h" 38 #include "efx_regs.h" 39 #include "efx_regs_ef10.h" 40 41 /* FIXME: Add definition for driver generated software events */ 42 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 43 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 44 #endif 45 46 #include "efx_check.h" 47 48 49 #if EFSYS_OPT_FALCON 50 #include "falcon_impl.h" 51 #endif /* EFSYS_OPT_FALCON */ 52 53 #if EFSYS_OPT_SIENA 54 #include "siena_impl.h" 55 #endif /* EFSYS_OPT_SIENA */ 56 57 #if EFSYS_OPT_HUNTINGTON 58 #include "hunt_impl.h" 59 #endif /* EFSYS_OPT_HUNTINGTON */ 60 61 #if EFSYS_OPT_MEDFORD 62 #include "medford_impl.h" 63 #endif /* EFSYS_OPT_MEDFORD */ 64 65 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 66 #include "ef10_impl.h" 67 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 68 69 #ifdef __cplusplus 70 extern "C" { 71 #endif 72 73 #define EFX_MOD_MCDI 0x00000001 74 #define EFX_MOD_PROBE 0x00000002 75 #define EFX_MOD_NVRAM 0x00000004 76 #define EFX_MOD_VPD 0x00000008 77 #define EFX_MOD_NIC 0x00000010 78 #define EFX_MOD_INTR 0x00000020 79 #define EFX_MOD_EV 0x00000040 80 #define EFX_MOD_RX 0x00000080 81 #define EFX_MOD_TX 0x00000100 82 #define EFX_MOD_PORT 0x00000200 83 #define EFX_MOD_MON 0x00000400 84 #define EFX_MOD_WOL 0x00000800 85 #define EFX_MOD_FILTER 0x00001000 86 #define EFX_MOD_PKTFILTER 0x00002000 87 88 #define EFX_RESET_MAC 0x00000001 89 #define EFX_RESET_PHY 0x00000002 90 #define EFX_RESET_RXQ_ERR 0x00000004 91 #define EFX_RESET_TXQ_ERR 0x00000008 92 93 typedef enum efx_mac_type_e { 94 EFX_MAC_INVALID = 0, 95 EFX_MAC_FALCON_GMAC, 96 EFX_MAC_FALCON_XMAC, 97 EFX_MAC_SIENA, 98 EFX_MAC_HUNTINGTON, 99 EFX_MAC_NTYPES 100 } efx_mac_type_t; 101 102 typedef struct efx_ev_ops_s { 103 efx_rc_t (*eevo_init)(efx_nic_t *); 104 void (*eevo_fini)(efx_nic_t *); 105 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 106 efsys_mem_t *, size_t, uint32_t, 107 efx_evq_t *); 108 void (*eevo_qdestroy)(efx_evq_t *); 109 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 110 void (*eevo_qpost)(efx_evq_t *, uint16_t); 111 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 112 #if EFSYS_OPT_QSTATS 113 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 114 #endif 115 } efx_ev_ops_t; 116 117 typedef struct efx_tx_ops_s { 118 efx_rc_t (*etxo_init)(efx_nic_t *); 119 void (*etxo_fini)(efx_nic_t *); 120 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 121 unsigned int, unsigned int, 122 efsys_mem_t *, size_t, 123 uint32_t, uint16_t, 124 efx_evq_t *, efx_txq_t *, 125 unsigned int *); 126 void (*etxo_qdestroy)(efx_txq_t *); 127 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 128 unsigned int, unsigned int, 129 unsigned int *); 130 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 131 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 132 efx_rc_t (*etxo_qflush)(efx_txq_t *); 133 void (*etxo_qenable)(efx_txq_t *); 134 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 135 void (*etxo_qpio_disable)(efx_txq_t *); 136 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, 137 size_t); 138 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 139 unsigned int *); 140 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 141 unsigned int, unsigned int, 142 unsigned int *); 143 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 144 size_t, boolean_t, 145 efx_desc_t *); 146 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 147 uint32_t, uint8_t, 148 efx_desc_t *); 149 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 150 efx_desc_t *); 151 #if EFSYS_OPT_QSTATS 152 void (*etxo_qstats_update)(efx_txq_t *, 153 efsys_stat_t *); 154 #endif 155 } efx_tx_ops_t; 156 157 typedef struct efx_rx_ops_s { 158 efx_rc_t (*erxo_init)(efx_nic_t *); 159 void (*erxo_fini)(efx_nic_t *); 160 #if EFSYS_OPT_RX_SCATTER 161 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 162 #endif 163 #if EFSYS_OPT_RX_SCALE 164 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, 165 efx_rx_hash_type_t, boolean_t); 166 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); 167 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, 168 size_t); 169 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 170 uint8_t *); 171 #endif /* EFSYS_OPT_RX_SCALE */ 172 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 173 uint16_t *); 174 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 175 unsigned int, unsigned int, 176 unsigned int); 177 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 178 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 179 void (*erxo_qenable)(efx_rxq_t *); 180 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 181 unsigned int, efx_rxq_type_t, 182 efsys_mem_t *, size_t, uint32_t, 183 efx_evq_t *, efx_rxq_t *); 184 void (*erxo_qdestroy)(efx_rxq_t *); 185 } efx_rx_ops_t; 186 187 typedef struct efx_mac_ops_s { 188 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */ 189 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 190 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 191 efx_rc_t (*emo_addr_set)(efx_nic_t *); 192 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 193 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 194 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 195 efx_rxq_t *, boolean_t); 196 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 197 #if EFSYS_OPT_LOOPBACK 198 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 199 efx_loopback_type_t); 200 #endif /* EFSYS_OPT_LOOPBACK */ 201 #if EFSYS_OPT_MAC_STATS 202 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 203 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 204 uint16_t, boolean_t); 205 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 206 efsys_stat_t *, uint32_t *); 207 #endif /* EFSYS_OPT_MAC_STATS */ 208 } efx_mac_ops_t; 209 210 typedef struct efx_phy_ops_s { 211 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 212 efx_rc_t (*epo_reset)(efx_nic_t *); 213 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 214 efx_rc_t (*epo_verify)(efx_nic_t *); 215 efx_rc_t (*epo_uplink_check)(efx_nic_t *, 216 boolean_t *); /* optional */ 217 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, 218 unsigned int *, uint32_t *); 219 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 220 #if EFSYS_OPT_PHY_STATS 221 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 222 uint32_t *); 223 #endif /* EFSYS_OPT_PHY_STATS */ 224 #if EFSYS_OPT_PHY_PROPS 225 #if EFSYS_OPT_NAMES 226 const char *(*epo_prop_name)(efx_nic_t *, unsigned int); 227 #endif /* EFSYS_OPT_PHY_PROPS */ 228 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, 229 uint32_t *); 230 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); 231 #endif /* EFSYS_OPT_PHY_PROPS */ 232 #if EFSYS_OPT_BIST 233 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 234 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 235 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 236 efx_bist_result_t *, uint32_t *, 237 unsigned long *, size_t); 238 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 239 #endif /* EFSYS_OPT_BIST */ 240 } efx_phy_ops_t; 241 242 #if EFSYS_OPT_FILTER 243 typedef struct efx_filter_ops_s { 244 efx_rc_t (*efo_init)(efx_nic_t *); 245 void (*efo_fini)(efx_nic_t *); 246 efx_rc_t (*efo_restore)(efx_nic_t *); 247 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 248 boolean_t may_replace); 249 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 250 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); 251 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 252 boolean_t, boolean_t, boolean_t, 253 uint8_t const *, int); 254 } efx_filter_ops_t; 255 256 extern __checkReturn efx_rc_t 257 efx_filter_reconfigure( 258 __in efx_nic_t *enp, 259 __in_ecount(6) uint8_t const *mac_addr, 260 __in boolean_t all_unicst, 261 __in boolean_t mulcst, 262 __in boolean_t all_mulcst, 263 __in boolean_t brdcst, 264 __in_ecount(6*count) uint8_t const *addrs, 265 __in int count); 266 267 #endif /* EFSYS_OPT_FILTER */ 268 269 270 typedef struct efx_port_s { 271 efx_mac_type_t ep_mac_type; 272 uint32_t ep_phy_type; 273 uint8_t ep_port; 274 uint32_t ep_mac_pdu; 275 uint8_t ep_mac_addr[6]; 276 efx_link_mode_t ep_link_mode; 277 boolean_t ep_all_unicst; 278 boolean_t ep_mulcst; 279 boolean_t ep_all_mulcst; 280 boolean_t ep_brdcst; 281 unsigned int ep_fcntl; 282 boolean_t ep_fcntl_autoneg; 283 efx_oword_t ep_multicst_hash[2]; 284 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 285 EFX_MAC_MULTICAST_LIST_MAX]; 286 uint32_t ep_mulcst_addr_count; 287 #if EFSYS_OPT_LOOPBACK 288 efx_loopback_type_t ep_loopback_type; 289 efx_link_mode_t ep_loopback_link_mode; 290 #endif /* EFSYS_OPT_LOOPBACK */ 291 #if EFSYS_OPT_PHY_FLAGS 292 uint32_t ep_phy_flags; 293 #endif /* EFSYS_OPT_PHY_FLAGS */ 294 #if EFSYS_OPT_PHY_LED_CONTROL 295 efx_phy_led_mode_t ep_phy_led_mode; 296 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 297 efx_phy_media_type_t ep_fixed_port_type; 298 efx_phy_media_type_t ep_module_type; 299 uint32_t ep_adv_cap_mask; 300 uint32_t ep_lp_cap_mask; 301 uint32_t ep_default_adv_cap_mask; 302 uint32_t ep_phy_cap_mask; 303 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C 304 union { 305 struct { 306 unsigned int bug10934_count; 307 } ep_txc43128; 308 struct { 309 unsigned int bug17190_count; 310 } ep_qt2025c; 311 }; 312 #endif 313 boolean_t ep_mac_poll_needed; /* falcon only */ 314 boolean_t ep_mac_up; /* falcon only */ 315 uint32_t ep_fwver; /* falcon only */ 316 boolean_t ep_mac_drain; 317 boolean_t ep_mac_stats_pending; 318 #if EFSYS_OPT_BIST 319 efx_bist_type_t ep_current_bist; 320 #endif 321 efx_mac_ops_t *ep_emop; 322 efx_phy_ops_t *ep_epop; 323 } efx_port_t; 324 325 typedef struct efx_mon_ops_s { 326 efx_rc_t (*emo_reset)(efx_nic_t *); 327 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 328 #if EFSYS_OPT_MON_STATS 329 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 330 efx_mon_stat_value_t *); 331 #endif /* EFSYS_OPT_MON_STATS */ 332 } efx_mon_ops_t; 333 334 typedef struct efx_mon_s { 335 efx_mon_type_t em_type; 336 efx_mon_ops_t *em_emop; 337 } efx_mon_t; 338 339 typedef struct efx_intr_ops_s { 340 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 341 void (*eio_enable)(efx_nic_t *); 342 void (*eio_disable)(efx_nic_t *); 343 void (*eio_disable_unlocked)(efx_nic_t *); 344 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 345 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 346 void (*eio_status_message)(efx_nic_t *, unsigned int, 347 boolean_t *); 348 void (*eio_fatal)(efx_nic_t *); 349 void (*eio_fini)(efx_nic_t *); 350 } efx_intr_ops_t; 351 352 typedef struct efx_intr_s { 353 efx_intr_ops_t *ei_eiop; 354 efsys_mem_t *ei_esmp; 355 efx_intr_type_t ei_type; 356 unsigned int ei_level; 357 } efx_intr_t; 358 359 typedef struct efx_nic_ops_s { 360 efx_rc_t (*eno_probe)(efx_nic_t *); 361 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 362 efx_rc_t (*eno_reset)(efx_nic_t *); 363 efx_rc_t (*eno_init)(efx_nic_t *); 364 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 365 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 366 uint32_t *, size_t *); 367 #if EFSYS_OPT_DIAG 368 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); 369 efx_rc_t (*eno_register_test)(efx_nic_t *); 370 #endif /* EFSYS_OPT_DIAG */ 371 void (*eno_fini)(efx_nic_t *); 372 void (*eno_unprobe)(efx_nic_t *); 373 } efx_nic_ops_t; 374 375 #ifndef EFX_TXQ_LIMIT_TARGET 376 #define EFX_TXQ_LIMIT_TARGET 259 377 #endif 378 #ifndef EFX_RXQ_LIMIT_TARGET 379 #define EFX_RXQ_LIMIT_TARGET 512 380 #endif 381 #ifndef EFX_TXQ_DC_SIZE 382 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 383 #endif 384 #ifndef EFX_RXQ_DC_SIZE 385 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 386 #endif 387 388 #if EFSYS_OPT_FILTER 389 390 typedef struct falconsiena_filter_spec_s { 391 uint8_t fsfs_type; 392 uint32_t fsfs_flags; 393 uint32_t fsfs_dmaq_id; 394 uint32_t fsfs_dword[3]; 395 } falconsiena_filter_spec_t; 396 397 typedef enum falconsiena_filter_type_e { 398 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ 399 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ 400 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ 401 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ 402 403 #if EFSYS_OPT_SIENA 404 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 405 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 406 407 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 408 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 409 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 410 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ 411 412 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ 413 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ 414 #endif /* EFSYS_OPT_SIENA */ 415 416 EFX_FS_FILTER_NTYPES 417 } falconsiena_filter_type_t; 418 419 typedef enum falconsiena_filter_tbl_id_e { 420 EFX_FS_FILTER_TBL_RX_IP = 0, 421 EFX_FS_FILTER_TBL_RX_MAC, 422 EFX_FS_FILTER_TBL_TX_IP, 423 EFX_FS_FILTER_TBL_TX_MAC, 424 EFX_FS_FILTER_NTBLS 425 } falconsiena_filter_tbl_id_t; 426 427 typedef struct falconsiena_filter_tbl_s { 428 int fsft_size; /* number of entries */ 429 int fsft_used; /* active count */ 430 uint32_t *fsft_bitmap; /* active bitmap */ 431 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */ 432 } falconsiena_filter_tbl_t; 433 434 typedef struct falconsiena_filter_s { 435 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS]; 436 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES]; 437 } falconsiena_filter_t; 438 439 typedef struct efx_filter_s { 440 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA 441 falconsiena_filter_t *ef_falconsiena_filter; 442 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ 443 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 444 ef10_filter_table_t *ef_ef10_filter_table; 445 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 446 } efx_filter_t; 447 448 extern void 449 falconsiena_filter_tbl_clear( 450 __in efx_nic_t *enp, 451 __in falconsiena_filter_tbl_id_t tbl); 452 453 #endif /* EFSYS_OPT_FILTER */ 454 455 #if EFSYS_OPT_MCDI 456 457 typedef struct efx_mcdi_ops_s { 458 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 459 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *, 460 unsigned int, boolean_t, boolean_t); 461 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *); 462 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 463 boolean_t (*emco_poll_response)(efx_nic_t *); 464 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 465 void (*emco_fini)(efx_nic_t *); 466 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *); 467 } efx_mcdi_ops_t; 468 469 typedef struct efx_mcdi_s { 470 efx_mcdi_ops_t *em_emcop; 471 const efx_mcdi_transport_t *em_emtp; 472 efx_mcdi_iface_t em_emip; 473 } efx_mcdi_t; 474 475 #endif /* EFSYS_OPT_MCDI */ 476 477 #if EFSYS_OPT_NVRAM 478 typedef struct efx_nvram_ops_s { 479 #if EFSYS_OPT_DIAG 480 efx_rc_t (*envo_test)(efx_nic_t *); 481 #endif /* EFSYS_OPT_DIAG */ 482 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); 483 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, 484 uint32_t *, uint16_t *); 485 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); 486 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, 487 unsigned int, caddr_t, size_t); 488 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t); 489 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, 490 unsigned int, caddr_t, size_t); 491 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); 492 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, 493 uint16_t *); 494 495 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 496 uint32_t *); 497 } efx_nvram_ops_t; 498 #endif /* EFSYS_OPT_NVRAM */ 499 500 #if EFSYS_OPT_VPD 501 typedef struct efx_vpd_ops_s { 502 efx_rc_t (*evpdo_init)(efx_nic_t *); 503 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 504 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 505 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 506 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 507 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 508 efx_vpd_value_t *); 509 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 510 efx_vpd_value_t *); 511 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 512 efx_vpd_value_t *, unsigned int *); 513 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 514 void (*evpdo_fini)(efx_nic_t *); 515 } efx_vpd_ops_t; 516 #endif /* EFSYS_OPT_VPD */ 517 518 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 519 520 __checkReturn efx_rc_t 521 efx_mcdi_nvram_partitions( 522 __in efx_nic_t *enp, 523 __out_bcount(size) caddr_t data, 524 __in size_t size, 525 __out unsigned int *npartnp); 526 527 __checkReturn efx_rc_t 528 efx_mcdi_nvram_metadata( 529 __in efx_nic_t *enp, 530 __in uint32_t partn, 531 __out uint32_t *subtypep, 532 __out_ecount(4) uint16_t version[4], 533 __out_bcount_opt(size) char *descp, 534 __in size_t size); 535 536 __checkReturn efx_rc_t 537 efx_mcdi_nvram_info( 538 __in efx_nic_t *enp, 539 __in uint32_t partn, 540 __out_opt size_t *sizep, 541 __out_opt uint32_t *addressp, 542 __out_opt uint32_t *erase_sizep, 543 __out_opt uint32_t *write_sizep); 544 545 __checkReturn efx_rc_t 546 efx_mcdi_nvram_update_start( 547 __in efx_nic_t *enp, 548 __in uint32_t partn); 549 550 __checkReturn efx_rc_t 551 efx_mcdi_nvram_read( 552 __in efx_nic_t *enp, 553 __in uint32_t partn, 554 __in uint32_t offset, 555 __out_bcount(size) caddr_t data, 556 __in size_t size); 557 558 __checkReturn efx_rc_t 559 efx_mcdi_nvram_erase( 560 __in efx_nic_t *enp, 561 __in uint32_t partn, 562 __in uint32_t offset, 563 __in size_t size); 564 565 __checkReturn efx_rc_t 566 efx_mcdi_nvram_write( 567 __in efx_nic_t *enp, 568 __in uint32_t partn, 569 __in uint32_t offset, 570 __out_bcount(size) caddr_t data, 571 __in size_t size); 572 573 __checkReturn efx_rc_t 574 efx_mcdi_nvram_update_finish( 575 __in efx_nic_t *enp, 576 __in uint32_t partn, 577 __in boolean_t reboot); 578 579 #if EFSYS_OPT_DIAG 580 581 __checkReturn efx_rc_t 582 efx_mcdi_nvram_test( 583 __in efx_nic_t *enp, 584 __in uint32_t partn); 585 586 #endif /* EFSYS_OPT_DIAG */ 587 588 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 589 590 typedef struct efx_drv_cfg_s { 591 uint32_t edc_min_vi_count; 592 uint32_t edc_max_vi_count; 593 594 uint32_t edc_max_piobuf_count; 595 uint32_t edc_pio_alloc_size; 596 } efx_drv_cfg_t; 597 598 struct efx_nic_s { 599 uint32_t en_magic; 600 efx_family_t en_family; 601 uint32_t en_features; 602 efsys_identifier_t *en_esip; 603 efsys_lock_t *en_eslp; 604 efsys_bar_t *en_esbp; 605 unsigned int en_mod_flags; 606 unsigned int en_reset_flags; 607 efx_nic_cfg_t en_nic_cfg; 608 efx_drv_cfg_t en_drv_cfg; 609 efx_port_t en_port; 610 efx_mon_t en_mon; 611 efx_intr_t en_intr; 612 uint32_t en_ev_qcount; 613 uint32_t en_rx_qcount; 614 uint32_t en_tx_qcount; 615 efx_nic_ops_t *en_enop; 616 efx_ev_ops_t *en_eevop; 617 efx_tx_ops_t *en_etxop; 618 efx_rx_ops_t *en_erxop; 619 #if EFSYS_OPT_FILTER 620 efx_filter_t en_filter; 621 efx_filter_ops_t *en_efop; 622 #endif /* EFSYS_OPT_FILTER */ 623 #if EFSYS_OPT_MCDI 624 efx_mcdi_t en_mcdi; 625 #endif /* EFSYS_OPT_MCDI */ 626 #if EFSYS_OPT_NVRAM 627 efx_nvram_type_t en_nvram_locked; 628 efx_nvram_ops_t *en_envop; 629 #endif /* EFSYS_OPT_NVRAM */ 630 #if EFSYS_OPT_VPD 631 efx_vpd_ops_t *en_evpdop; 632 #endif /* EFSYS_OPT_VPD */ 633 #if EFSYS_OPT_RX_SCALE 634 efx_rx_hash_support_t en_hash_support; 635 efx_rx_scale_support_t en_rss_support; 636 uint32_t en_rss_context; 637 #endif /* EFSYS_OPT_RX_SCALE */ 638 uint32_t en_vport_id; 639 union { 640 #if EFSYS_OPT_FALCON 641 struct { 642 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES]; 643 falcon_i2c_t enu_fip; 644 boolean_t enu_i2c_locked; 645 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 646 const uint8_t *enu_forced_cfg; 647 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ 648 uint8_t enu_mon_devid; 649 #if EFSYS_OPT_PCIE_TUNE 650 unsigned int enu_nlanes; 651 #endif /* EFSYS_OPT_PCIE_TUNE */ 652 uint16_t enu_board_rev; 653 boolean_t enu_internal_sram; 654 uint8_t enu_sram_num_bank; 655 uint8_t enu_sram_bank_size; 656 } falcon; 657 #endif /* EFSYS_OPT_FALCON */ 658 #if EFSYS_OPT_SIENA 659 struct { 660 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 661 unsigned int enu_partn_mask; 662 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 663 #if EFSYS_OPT_VPD 664 caddr_t enu_svpd; 665 size_t enu_svpd_length; 666 #endif /* EFSYS_OPT_VPD */ 667 int enu_unused; 668 } siena; 669 #endif /* EFSYS_OPT_SIENA */ 670 int enu_unused; 671 } en_u; 672 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 673 union en_arch { 674 struct { 675 int ena_vi_base; 676 int ena_vi_count; 677 int ena_vi_shift; 678 #if EFSYS_OPT_VPD 679 caddr_t ena_svpd; 680 size_t ena_svpd_length; 681 #endif /* EFSYS_OPT_VPD */ 682 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 683 uint32_t ena_piobuf_count; 684 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 685 uint32_t ena_pio_write_vi_base; 686 /* Memory BAR mapping regions */ 687 uint32_t ena_uc_mem_map_offset; 688 size_t ena_uc_mem_map_size; 689 uint32_t ena_wc_mem_map_offset; 690 size_t ena_wc_mem_map_size; 691 } ef10; 692 } en_arch; 693 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 694 }; 695 696 697 #define EFX_NIC_MAGIC 0x02121996 698 699 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 700 const efx_ev_callbacks_t *, void *); 701 702 typedef struct efx_evq_rxq_state_s { 703 unsigned int eers_rx_read_ptr; 704 unsigned int eers_rx_mask; 705 } efx_evq_rxq_state_t; 706 707 struct efx_evq_s { 708 uint32_t ee_magic; 709 efx_nic_t *ee_enp; 710 unsigned int ee_index; 711 unsigned int ee_mask; 712 efsys_mem_t *ee_esmp; 713 #if EFSYS_OPT_QSTATS 714 uint32_t ee_stat[EV_NQSTATS]; 715 #endif /* EFSYS_OPT_QSTATS */ 716 717 efx_ev_handler_t ee_rx; 718 efx_ev_handler_t ee_tx; 719 efx_ev_handler_t ee_driver; 720 efx_ev_handler_t ee_global; 721 efx_ev_handler_t ee_drv_gen; 722 #if EFSYS_OPT_MCDI 723 efx_ev_handler_t ee_mcdi; 724 #endif /* EFSYS_OPT_MCDI */ 725 726 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 727 }; 728 729 #define EFX_EVQ_MAGIC 0x08081997 730 731 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */ 732 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 733 734 struct efx_rxq_s { 735 uint32_t er_magic; 736 efx_nic_t *er_enp; 737 efx_evq_t *er_eep; 738 unsigned int er_index; 739 unsigned int er_label; 740 unsigned int er_mask; 741 efsys_mem_t *er_esmp; 742 }; 743 744 #define EFX_RXQ_MAGIC 0x15022005 745 746 struct efx_txq_s { 747 uint32_t et_magic; 748 efx_nic_t *et_enp; 749 unsigned int et_index; 750 unsigned int et_mask; 751 efsys_mem_t *et_esmp; 752 #if EFSYS_OPT_HUNTINGTON 753 uint32_t et_pio_bufnum; 754 uint32_t et_pio_blknum; 755 uint32_t et_pio_write_offset; 756 uint32_t et_pio_offset; 757 size_t et_pio_size; 758 #endif 759 #if EFSYS_OPT_QSTATS 760 uint32_t et_stat[TX_NQSTATS]; 761 #endif /* EFSYS_OPT_QSTATS */ 762 }; 763 764 #define EFX_TXQ_MAGIC 0x05092005 765 766 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 767 do { \ 768 (_dst)[0] = (_src)[0]; \ 769 (_dst)[1] = (_src)[1]; \ 770 (_dst)[2] = (_src)[2]; \ 771 (_dst)[3] = (_src)[3]; \ 772 (_dst)[4] = (_src)[4]; \ 773 (_dst)[5] = (_src)[5]; \ 774 _NOTE(CONSTANTCONDITION) \ 775 } while (B_FALSE) 776 777 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 778 do { \ 779 uint16_t *_d = (uint16_t *)(_dst); \ 780 _d[0] = 0xffff; \ 781 _d[1] = 0xffff; \ 782 _d[2] = 0xffff; \ 783 _NOTE(CONSTANTCONDITION) \ 784 } while (B_FALSE) 785 786 #if EFSYS_OPT_CHECK_REG 787 #define EFX_CHECK_REG(_enp, _reg) \ 788 do { \ 789 const char *name = #_reg; \ 790 char min = name[4]; \ 791 char max = name[5]; \ 792 char rev; \ 793 \ 794 switch ((_enp)->en_family) { \ 795 case EFX_FAMILY_FALCON: \ 796 rev = 'B'; \ 797 break; \ 798 \ 799 case EFX_FAMILY_SIENA: \ 800 rev = 'C'; \ 801 break; \ 802 \ 803 case EFX_FAMILY_HUNTINGTON: \ 804 rev = 'D'; \ 805 break; \ 806 \ 807 case EFX_FAMILY_MEDFORD: \ 808 rev = 'E'; \ 809 break; \ 810 \ 811 default: \ 812 rev = '?'; \ 813 break; \ 814 } \ 815 \ 816 EFSYS_ASSERT3S(rev, >=, min); \ 817 EFSYS_ASSERT3S(rev, <=, max); \ 818 \ 819 _NOTE(CONSTANTCONDITION) \ 820 } while (B_FALSE) 821 #else 822 #define EFX_CHECK_REG(_enp, _reg) do { \ 823 _NOTE(CONSTANTCONDITION) \ 824 } while(B_FALSE) 825 #endif 826 827 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 828 do { \ 829 EFX_CHECK_REG((_enp), (_reg)); \ 830 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 831 (_edp), (_lock)); \ 832 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 833 uint32_t, _reg ## _OFST, \ 834 uint32_t, (_edp)->ed_u32[0]); \ 835 _NOTE(CONSTANTCONDITION) \ 836 } while (B_FALSE) 837 838 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 839 do { \ 840 EFX_CHECK_REG((_enp), (_reg)); \ 841 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 842 uint32_t, _reg ## _OFST, \ 843 uint32_t, (_edp)->ed_u32[0]); \ 844 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 845 (_edp), (_lock)); \ 846 _NOTE(CONSTANTCONDITION) \ 847 } while (B_FALSE) 848 849 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 850 do { \ 851 EFX_CHECK_REG((_enp), (_reg)); \ 852 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 853 (_eqp)); \ 854 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 855 uint32_t, _reg ## _OFST, \ 856 uint32_t, (_eqp)->eq_u32[1], \ 857 uint32_t, (_eqp)->eq_u32[0]); \ 858 _NOTE(CONSTANTCONDITION) \ 859 } while (B_FALSE) 860 861 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 862 do { \ 863 EFX_CHECK_REG((_enp), (_reg)); \ 864 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 865 uint32_t, _reg ## _OFST, \ 866 uint32_t, (_eqp)->eq_u32[1], \ 867 uint32_t, (_eqp)->eq_u32[0]); \ 868 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 869 (_eqp)); \ 870 _NOTE(CONSTANTCONDITION) \ 871 } while (B_FALSE) 872 873 #define EFX_BAR_READO(_enp, _reg, _eop) \ 874 do { \ 875 EFX_CHECK_REG((_enp), (_reg)); \ 876 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 877 (_eop), B_TRUE); \ 878 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 879 uint32_t, _reg ## _OFST, \ 880 uint32_t, (_eop)->eo_u32[3], \ 881 uint32_t, (_eop)->eo_u32[2], \ 882 uint32_t, (_eop)->eo_u32[1], \ 883 uint32_t, (_eop)->eo_u32[0]); \ 884 _NOTE(CONSTANTCONDITION) \ 885 } while (B_FALSE) 886 887 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 888 do { \ 889 EFX_CHECK_REG((_enp), (_reg)); \ 890 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 891 uint32_t, _reg ## _OFST, \ 892 uint32_t, (_eop)->eo_u32[3], \ 893 uint32_t, (_eop)->eo_u32[2], \ 894 uint32_t, (_eop)->eo_u32[1], \ 895 uint32_t, (_eop)->eo_u32[0]); \ 896 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 897 (_eop), B_TRUE); \ 898 _NOTE(CONSTANTCONDITION) \ 899 } while (B_FALSE) 900 901 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 902 do { \ 903 EFX_CHECK_REG((_enp), (_reg)); \ 904 EFSYS_BAR_READD((_enp)->en_esbp, \ 905 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 906 (_edp), (_lock)); \ 907 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 908 uint32_t, (_index), \ 909 uint32_t, _reg ## _OFST, \ 910 uint32_t, (_edp)->ed_u32[0]); \ 911 _NOTE(CONSTANTCONDITION) \ 912 } while (B_FALSE) 913 914 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 915 do { \ 916 EFX_CHECK_REG((_enp), (_reg)); \ 917 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 918 uint32_t, (_index), \ 919 uint32_t, _reg ## _OFST, \ 920 uint32_t, (_edp)->ed_u32[0]); \ 921 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 922 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 923 (_edp), (_lock)); \ 924 _NOTE(CONSTANTCONDITION) \ 925 } while (B_FALSE) 926 927 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 928 do { \ 929 EFX_CHECK_REG((_enp), (_reg)); \ 930 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 931 uint32_t, (_index), \ 932 uint32_t, _reg ## _OFST, \ 933 uint32_t, (_edp)->ed_u32[0]); \ 934 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 935 (_reg ## _OFST + \ 936 (2 * sizeof (efx_dword_t)) + \ 937 ((_index) * _reg ## _STEP)), \ 938 (_edp), (_lock)); \ 939 _NOTE(CONSTANTCONDITION) \ 940 } while (B_FALSE) 941 942 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 943 do { \ 944 EFX_CHECK_REG((_enp), (_reg)); \ 945 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 946 uint32_t, (_index), \ 947 uint32_t, _reg ## _OFST, \ 948 uint32_t, (_edp)->ed_u32[0]); \ 949 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 950 (_reg ## _OFST + \ 951 (3 * sizeof (efx_dword_t)) + \ 952 ((_index) * _reg ## _STEP)), \ 953 (_edp), (_lock)); \ 954 _NOTE(CONSTANTCONDITION) \ 955 } while (B_FALSE) 956 957 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 958 do { \ 959 EFX_CHECK_REG((_enp), (_reg)); \ 960 EFSYS_BAR_READQ((_enp)->en_esbp, \ 961 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 962 (_eqp)); \ 963 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 964 uint32_t, (_index), \ 965 uint32_t, _reg ## _OFST, \ 966 uint32_t, (_eqp)->eq_u32[1], \ 967 uint32_t, (_eqp)->eq_u32[0]); \ 968 _NOTE(CONSTANTCONDITION) \ 969 } while (B_FALSE) 970 971 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 972 do { \ 973 EFX_CHECK_REG((_enp), (_reg)); \ 974 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 975 uint32_t, (_index), \ 976 uint32_t, _reg ## _OFST, \ 977 uint32_t, (_eqp)->eq_u32[1], \ 978 uint32_t, (_eqp)->eq_u32[0]); \ 979 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 980 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 981 (_eqp)); \ 982 _NOTE(CONSTANTCONDITION) \ 983 } while (B_FALSE) 984 985 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 986 do { \ 987 EFX_CHECK_REG((_enp), (_reg)); \ 988 EFSYS_BAR_READO((_enp)->en_esbp, \ 989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 990 (_eop), (_lock)); \ 991 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 992 uint32_t, (_index), \ 993 uint32_t, _reg ## _OFST, \ 994 uint32_t, (_eop)->eo_u32[3], \ 995 uint32_t, (_eop)->eo_u32[2], \ 996 uint32_t, (_eop)->eo_u32[1], \ 997 uint32_t, (_eop)->eo_u32[0]); \ 998 _NOTE(CONSTANTCONDITION) \ 999 } while (B_FALSE) 1000 1001 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1002 do { \ 1003 EFX_CHECK_REG((_enp), (_reg)); \ 1004 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1005 uint32_t, (_index), \ 1006 uint32_t, _reg ## _OFST, \ 1007 uint32_t, (_eop)->eo_u32[3], \ 1008 uint32_t, (_eop)->eo_u32[2], \ 1009 uint32_t, (_eop)->eo_u32[1], \ 1010 uint32_t, (_eop)->eo_u32[0]); \ 1011 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1012 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1013 (_eop), (_lock)); \ 1014 _NOTE(CONSTANTCONDITION) \ 1015 } while (B_FALSE) 1016 1017 /* 1018 * Allow drivers to perform optimised 128-bit doorbell writes. 1019 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1020 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1021 * the need for locking in the host, and are the only ones known to be safe to 1022 * use 128-bites write with. 1023 */ 1024 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1025 do { \ 1026 EFX_CHECK_REG((_enp), (_reg)); \ 1027 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1028 const char *, \ 1029 #_reg, \ 1030 uint32_t, (_index), \ 1031 uint32_t, _reg ## _OFST, \ 1032 uint32_t, (_eop)->eo_u32[3], \ 1033 uint32_t, (_eop)->eo_u32[2], \ 1034 uint32_t, (_eop)->eo_u32[1], \ 1035 uint32_t, (_eop)->eo_u32[0]); \ 1036 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1037 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1038 (_eop)); \ 1039 _NOTE(CONSTANTCONDITION) \ 1040 } while (B_FALSE) 1041 1042 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1043 do { \ 1044 unsigned int _new = (_wptr); \ 1045 unsigned int _old = (_owptr); \ 1046 \ 1047 if ((_new) >= (_old)) \ 1048 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1049 (_old) * sizeof (efx_desc_t), \ 1050 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1051 else \ 1052 /* \ 1053 * It is cheaper to sync entire map than sync \ 1054 * two parts especially when offset/size are \ 1055 * ignored and entire map is synced in any case.\ 1056 */ \ 1057 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1058 0, \ 1059 (_entries) * sizeof (efx_desc_t)); \ 1060 _NOTE(CONSTANTCONDITION) \ 1061 } while (B_FALSE) 1062 1063 extern __checkReturn efx_rc_t 1064 efx_nic_biu_test( 1065 __in efx_nic_t *enp); 1066 1067 extern __checkReturn efx_rc_t 1068 efx_mac_select( 1069 __in efx_nic_t *enp); 1070 1071 extern void 1072 efx_mac_multicast_hash_compute( 1073 __in_ecount(6*count) uint8_t const *addrs, 1074 __in int count, 1075 __out efx_oword_t *hash_low, 1076 __out efx_oword_t *hash_high); 1077 1078 extern __checkReturn efx_rc_t 1079 efx_phy_probe( 1080 __in efx_nic_t *enp); 1081 1082 extern void 1083 efx_phy_unprobe( 1084 __in efx_nic_t *enp); 1085 1086 #if EFSYS_OPT_VPD 1087 1088 /* VPD utility functions */ 1089 1090 extern __checkReturn efx_rc_t 1091 efx_vpd_hunk_length( 1092 __in_bcount(size) caddr_t data, 1093 __in size_t size, 1094 __out size_t *lengthp); 1095 1096 extern __checkReturn efx_rc_t 1097 efx_vpd_hunk_verify( 1098 __in_bcount(size) caddr_t data, 1099 __in size_t size, 1100 __out_opt boolean_t *cksummedp); 1101 1102 extern __checkReturn efx_rc_t 1103 efx_vpd_hunk_reinit( 1104 __in_bcount(size) caddr_t data, 1105 __in size_t size, 1106 __in boolean_t wantpid); 1107 1108 extern __checkReturn efx_rc_t 1109 efx_vpd_hunk_get( 1110 __in_bcount(size) caddr_t data, 1111 __in size_t size, 1112 __in efx_vpd_tag_t tag, 1113 __in efx_vpd_keyword_t keyword, 1114 __out unsigned int *payloadp, 1115 __out uint8_t *paylenp); 1116 1117 extern __checkReturn efx_rc_t 1118 efx_vpd_hunk_next( 1119 __in_bcount(size) caddr_t data, 1120 __in size_t size, 1121 __out efx_vpd_tag_t *tagp, 1122 __out efx_vpd_keyword_t *keyword, 1123 __out_opt unsigned int *payloadp, 1124 __out_opt uint8_t *paylenp, 1125 __inout unsigned int *contp); 1126 1127 extern __checkReturn efx_rc_t 1128 efx_vpd_hunk_set( 1129 __in_bcount(size) caddr_t data, 1130 __in size_t size, 1131 __in efx_vpd_value_t *evvp); 1132 1133 #endif /* EFSYS_OPT_VPD */ 1134 1135 #if EFSYS_OPT_DIAG 1136 1137 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1138 1139 typedef struct efx_register_set_s { 1140 unsigned int address; 1141 unsigned int step; 1142 unsigned int rows; 1143 efx_oword_t mask; 1144 } efx_register_set_t; 1145 1146 extern __checkReturn efx_rc_t 1147 efx_nic_test_registers( 1148 __in efx_nic_t *enp, 1149 __in efx_register_set_t *rsp, 1150 __in size_t count); 1151 1152 extern __checkReturn efx_rc_t 1153 efx_nic_test_tables( 1154 __in efx_nic_t *enp, 1155 __in efx_register_set_t *rsp, 1156 __in efx_pattern_type_t pattern, 1157 __in size_t count); 1158 1159 #endif /* EFSYS_OPT_DIAG */ 1160 1161 #if EFSYS_OPT_MCDI 1162 1163 extern __checkReturn efx_rc_t 1164 efx_mcdi_set_workaround( 1165 __in efx_nic_t *enp, 1166 __in uint32_t type, 1167 __in boolean_t enabled, 1168 __out_opt uint32_t *flagsp); 1169 1170 extern __checkReturn efx_rc_t 1171 efx_mcdi_get_workarounds( 1172 __in efx_nic_t *enp, 1173 __out_opt uint32_t *implementedp, 1174 __out_opt uint32_t *enabledp); 1175 1176 #endif /* EFSYS_OPT_MCDI */ 1177 1178 #ifdef __cplusplus 1179 } 1180 #endif 1181 1182 #endif /* _SYS_EFX_IMPL_H */ 1183