1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_IMPL_H 36 #define _SYS_EFX_IMPL_H 37 38 #include "efx.h" 39 #include "efx_regs.h" 40 #include "efx_regs_ef10.h" 41 42 /* FIXME: Add definition for driver generated software events */ 43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 45 #endif 46 47 48 #if EFSYS_OPT_SIENA 49 #include "siena_impl.h" 50 #endif /* EFSYS_OPT_SIENA */ 51 52 #if EFSYS_OPT_HUNTINGTON 53 #include "hunt_impl.h" 54 #endif /* EFSYS_OPT_HUNTINGTON */ 55 56 #if EFSYS_OPT_MEDFORD 57 #include "medford_impl.h" 58 #endif /* EFSYS_OPT_MEDFORD */ 59 60 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 61 #include "ef10_impl.h" 62 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif 67 68 #define EFX_MOD_MCDI 0x00000001 69 #define EFX_MOD_PROBE 0x00000002 70 #define EFX_MOD_NVRAM 0x00000004 71 #define EFX_MOD_VPD 0x00000008 72 #define EFX_MOD_NIC 0x00000010 73 #define EFX_MOD_INTR 0x00000020 74 #define EFX_MOD_EV 0x00000040 75 #define EFX_MOD_RX 0x00000080 76 #define EFX_MOD_TX 0x00000100 77 #define EFX_MOD_PORT 0x00000200 78 #define EFX_MOD_MON 0x00000400 79 #define EFX_MOD_FILTER 0x00001000 80 #define EFX_MOD_LIC 0x00002000 81 82 #define EFX_RESET_PHY 0x00000001 83 #define EFX_RESET_RXQ_ERR 0x00000002 84 #define EFX_RESET_TXQ_ERR 0x00000004 85 86 typedef enum efx_mac_type_e { 87 EFX_MAC_INVALID = 0, 88 EFX_MAC_SIENA, 89 EFX_MAC_HUNTINGTON, 90 EFX_MAC_MEDFORD, 91 EFX_MAC_NTYPES 92 } efx_mac_type_t; 93 94 typedef struct efx_ev_ops_s { 95 efx_rc_t (*eevo_init)(efx_nic_t *); 96 void (*eevo_fini)(efx_nic_t *); 97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 98 efsys_mem_t *, size_t, uint32_t, 99 uint32_t, uint32_t, efx_evq_t *); 100 void (*eevo_qdestroy)(efx_evq_t *); 101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 102 void (*eevo_qpost)(efx_evq_t *, uint16_t); 103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 104 #if EFSYS_OPT_QSTATS 105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 106 #endif 107 } efx_ev_ops_t; 108 109 typedef struct efx_tx_ops_s { 110 efx_rc_t (*etxo_init)(efx_nic_t *); 111 void (*etxo_fini)(efx_nic_t *); 112 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 113 unsigned int, unsigned int, 114 efsys_mem_t *, size_t, 115 uint32_t, uint16_t, 116 efx_evq_t *, efx_txq_t *, 117 unsigned int *); 118 void (*etxo_qdestroy)(efx_txq_t *); 119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 120 unsigned int, unsigned int, 121 unsigned int *); 122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 124 efx_rc_t (*etxo_qflush)(efx_txq_t *); 125 void (*etxo_qenable)(efx_txq_t *); 126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 127 void (*etxo_qpio_disable)(efx_txq_t *); 128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 129 size_t); 130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 131 unsigned int *); 132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 133 unsigned int, unsigned int, 134 unsigned int *); 135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 136 size_t, boolean_t, 137 efx_desc_t *); 138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 139 uint32_t, uint8_t, 140 efx_desc_t *); 141 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 142 uint32_t, uint16_t, 143 efx_desc_t *, int); 144 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 145 efx_desc_t *); 146 #if EFSYS_OPT_QSTATS 147 void (*etxo_qstats_update)(efx_txq_t *, 148 efsys_stat_t *); 149 #endif 150 } efx_tx_ops_t; 151 152 typedef struct efx_rx_ops_s { 153 efx_rc_t (*erxo_init)(efx_nic_t *); 154 void (*erxo_fini)(efx_nic_t *); 155 #if EFSYS_OPT_RX_SCATTER 156 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 157 #endif 158 #if EFSYS_OPT_RX_SCALE 159 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 160 efx_rx_scale_context_type_t, 161 uint32_t, uint32_t *); 162 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 163 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 164 efx_rx_hash_alg_t, 165 efx_rx_hash_type_t, boolean_t); 166 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 167 uint8_t *, size_t); 168 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 169 unsigned int *, size_t); 170 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 171 uint8_t *); 172 #endif /* EFSYS_OPT_RX_SCALE */ 173 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 174 uint16_t *); 175 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 176 unsigned int, unsigned int, 177 unsigned int); 178 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 179 #if EFSYS_OPT_RX_PACKED_STREAM 180 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 181 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 182 uint32_t, uint32_t, 183 uint16_t *, uint32_t *, uint32_t *); 184 #endif 185 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 186 void (*erxo_qenable)(efx_rxq_t *); 187 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 188 unsigned int, efx_rxq_type_t, 189 efsys_mem_t *, size_t, uint32_t, 190 efx_evq_t *, efx_rxq_t *); 191 void (*erxo_qdestroy)(efx_rxq_t *); 192 } efx_rx_ops_t; 193 194 typedef struct efx_mac_ops_s { 195 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 196 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 197 efx_rc_t (*emo_addr_set)(efx_nic_t *); 198 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 199 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 200 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 201 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 202 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 203 efx_rxq_t *, boolean_t); 204 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 205 #if EFSYS_OPT_LOOPBACK 206 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 207 efx_loopback_type_t); 208 #endif /* EFSYS_OPT_LOOPBACK */ 209 #if EFSYS_OPT_MAC_STATS 210 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 211 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 212 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 213 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 214 uint16_t, boolean_t); 215 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 216 efsys_stat_t *, uint32_t *); 217 #endif /* EFSYS_OPT_MAC_STATS */ 218 } efx_mac_ops_t; 219 220 typedef struct efx_phy_ops_s { 221 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 222 efx_rc_t (*epo_reset)(efx_nic_t *); 223 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 224 efx_rc_t (*epo_verify)(efx_nic_t *); 225 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 226 #if EFSYS_OPT_PHY_STATS 227 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 228 uint32_t *); 229 #endif /* EFSYS_OPT_PHY_STATS */ 230 #if EFSYS_OPT_BIST 231 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 232 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 233 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 234 efx_bist_result_t *, uint32_t *, 235 unsigned long *, size_t); 236 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 237 #endif /* EFSYS_OPT_BIST */ 238 } efx_phy_ops_t; 239 240 #if EFSYS_OPT_FILTER 241 typedef struct efx_filter_ops_s { 242 efx_rc_t (*efo_init)(efx_nic_t *); 243 void (*efo_fini)(efx_nic_t *); 244 efx_rc_t (*efo_restore)(efx_nic_t *); 245 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 246 boolean_t may_replace); 247 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 248 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 249 size_t, size_t *); 250 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 251 boolean_t, boolean_t, boolean_t, 252 uint8_t const *, uint32_t); 253 } efx_filter_ops_t; 254 255 extern __checkReturn efx_rc_t 256 efx_filter_reconfigure( 257 __in efx_nic_t *enp, 258 __in_ecount(6) uint8_t const *mac_addr, 259 __in boolean_t all_unicst, 260 __in boolean_t mulcst, 261 __in boolean_t all_mulcst, 262 __in boolean_t brdcst, 263 __in_ecount(6*count) uint8_t const *addrs, 264 __in uint32_t count); 265 266 #endif /* EFSYS_OPT_FILTER */ 267 268 269 typedef struct efx_port_s { 270 efx_mac_type_t ep_mac_type; 271 uint32_t ep_phy_type; 272 uint8_t ep_port; 273 uint32_t ep_mac_pdu; 274 uint8_t ep_mac_addr[6]; 275 efx_link_mode_t ep_link_mode; 276 boolean_t ep_all_unicst; 277 boolean_t ep_mulcst; 278 boolean_t ep_all_mulcst; 279 boolean_t ep_brdcst; 280 unsigned int ep_fcntl; 281 boolean_t ep_fcntl_autoneg; 282 efx_oword_t ep_multicst_hash[2]; 283 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 284 EFX_MAC_MULTICAST_LIST_MAX]; 285 uint32_t ep_mulcst_addr_count; 286 #if EFSYS_OPT_LOOPBACK 287 efx_loopback_type_t ep_loopback_type; 288 efx_link_mode_t ep_loopback_link_mode; 289 #endif /* EFSYS_OPT_LOOPBACK */ 290 #if EFSYS_OPT_PHY_FLAGS 291 uint32_t ep_phy_flags; 292 #endif /* EFSYS_OPT_PHY_FLAGS */ 293 #if EFSYS_OPT_PHY_LED_CONTROL 294 efx_phy_led_mode_t ep_phy_led_mode; 295 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 296 efx_phy_media_type_t ep_fixed_port_type; 297 efx_phy_media_type_t ep_module_type; 298 uint32_t ep_adv_cap_mask; 299 uint32_t ep_lp_cap_mask; 300 uint32_t ep_default_adv_cap_mask; 301 uint32_t ep_phy_cap_mask; 302 boolean_t ep_mac_drain; 303 boolean_t ep_mac_stats_pending; 304 #if EFSYS_OPT_BIST 305 efx_bist_type_t ep_current_bist; 306 #endif 307 const efx_mac_ops_t *ep_emop; 308 const efx_phy_ops_t *ep_epop; 309 } efx_port_t; 310 311 typedef struct efx_mon_ops_s { 312 #if EFSYS_OPT_MON_STATS 313 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 314 efx_mon_stat_value_t *); 315 #endif /* EFSYS_OPT_MON_STATS */ 316 } efx_mon_ops_t; 317 318 typedef struct efx_mon_s { 319 efx_mon_type_t em_type; 320 const efx_mon_ops_t *em_emop; 321 } efx_mon_t; 322 323 typedef struct efx_intr_ops_s { 324 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 325 void (*eio_enable)(efx_nic_t *); 326 void (*eio_disable)(efx_nic_t *); 327 void (*eio_disable_unlocked)(efx_nic_t *); 328 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 329 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 330 void (*eio_status_message)(efx_nic_t *, unsigned int, 331 boolean_t *); 332 void (*eio_fatal)(efx_nic_t *); 333 void (*eio_fini)(efx_nic_t *); 334 } efx_intr_ops_t; 335 336 typedef struct efx_intr_s { 337 const efx_intr_ops_t *ei_eiop; 338 efsys_mem_t *ei_esmp; 339 efx_intr_type_t ei_type; 340 unsigned int ei_level; 341 } efx_intr_t; 342 343 typedef struct efx_nic_ops_s { 344 efx_rc_t (*eno_probe)(efx_nic_t *); 345 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 346 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 347 efx_rc_t (*eno_reset)(efx_nic_t *); 348 efx_rc_t (*eno_init)(efx_nic_t *); 349 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 350 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 351 uint32_t *, size_t *); 352 #if EFSYS_OPT_DIAG 353 efx_rc_t (*eno_register_test)(efx_nic_t *); 354 #endif /* EFSYS_OPT_DIAG */ 355 void (*eno_fini)(efx_nic_t *); 356 void (*eno_unprobe)(efx_nic_t *); 357 } efx_nic_ops_t; 358 359 #ifndef EFX_TXQ_LIMIT_TARGET 360 #define EFX_TXQ_LIMIT_TARGET 259 361 #endif 362 #ifndef EFX_RXQ_LIMIT_TARGET 363 #define EFX_RXQ_LIMIT_TARGET 512 364 #endif 365 #ifndef EFX_TXQ_DC_SIZE 366 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 367 #endif 368 #ifndef EFX_RXQ_DC_SIZE 369 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 370 #endif 371 372 #if EFSYS_OPT_FILTER 373 374 typedef struct siena_filter_spec_s { 375 uint8_t sfs_type; 376 uint32_t sfs_flags; 377 uint32_t sfs_dmaq_id; 378 uint32_t sfs_dword[3]; 379 } siena_filter_spec_t; 380 381 typedef enum siena_filter_type_e { 382 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 383 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 384 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 385 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 386 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 387 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 388 389 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 390 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 391 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 392 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 393 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 394 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 395 396 EFX_SIENA_FILTER_NTYPES 397 } siena_filter_type_t; 398 399 typedef enum siena_filter_tbl_id_e { 400 EFX_SIENA_FILTER_TBL_RX_IP = 0, 401 EFX_SIENA_FILTER_TBL_RX_MAC, 402 EFX_SIENA_FILTER_TBL_TX_IP, 403 EFX_SIENA_FILTER_TBL_TX_MAC, 404 EFX_SIENA_FILTER_NTBLS 405 } siena_filter_tbl_id_t; 406 407 typedef struct siena_filter_tbl_s { 408 int sft_size; /* number of entries */ 409 int sft_used; /* active count */ 410 uint32_t *sft_bitmap; /* active bitmap */ 411 siena_filter_spec_t *sft_spec; /* array of saved specs */ 412 } siena_filter_tbl_t; 413 414 typedef struct siena_filter_s { 415 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 416 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 417 } siena_filter_t; 418 419 typedef struct efx_filter_s { 420 #if EFSYS_OPT_SIENA 421 siena_filter_t *ef_siena_filter; 422 #endif /* EFSYS_OPT_SIENA */ 423 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 424 ef10_filter_table_t *ef_ef10_filter_table; 425 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 426 } efx_filter_t; 427 428 extern void 429 siena_filter_tbl_clear( 430 __in efx_nic_t *enp, 431 __in siena_filter_tbl_id_t tbl); 432 433 #endif /* EFSYS_OPT_FILTER */ 434 435 #if EFSYS_OPT_MCDI 436 437 typedef struct efx_mcdi_ops_s { 438 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 439 void (*emco_send_request)(efx_nic_t *, void *, size_t, 440 void *, size_t); 441 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 442 boolean_t (*emco_poll_response)(efx_nic_t *); 443 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 444 void (*emco_fini)(efx_nic_t *); 445 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 446 efx_mcdi_feature_id_t, boolean_t *); 447 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 448 uint32_t *); 449 } efx_mcdi_ops_t; 450 451 typedef struct efx_mcdi_s { 452 const efx_mcdi_ops_t *em_emcop; 453 const efx_mcdi_transport_t *em_emtp; 454 efx_mcdi_iface_t em_emip; 455 } efx_mcdi_t; 456 457 #endif /* EFSYS_OPT_MCDI */ 458 459 #if EFSYS_OPT_NVRAM 460 461 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 462 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 463 464 typedef struct efx_nvram_ops_s { 465 #if EFSYS_OPT_DIAG 466 efx_rc_t (*envo_test)(efx_nic_t *); 467 #endif /* EFSYS_OPT_DIAG */ 468 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 469 uint32_t *); 470 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 471 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 472 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 473 unsigned int, caddr_t, size_t); 474 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 475 unsigned int, caddr_t, size_t); 476 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 477 unsigned int, size_t); 478 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 479 unsigned int, caddr_t, size_t); 480 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 481 uint32_t *); 482 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 483 uint32_t *, uint16_t *); 484 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 485 uint16_t *); 486 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t, 487 caddr_t, size_t); 488 } efx_nvram_ops_t; 489 #endif /* EFSYS_OPT_NVRAM */ 490 491 #if EFSYS_OPT_VPD 492 typedef struct efx_vpd_ops_s { 493 efx_rc_t (*evpdo_init)(efx_nic_t *); 494 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 495 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 496 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 497 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 498 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 499 efx_vpd_value_t *); 500 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 501 efx_vpd_value_t *); 502 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 503 efx_vpd_value_t *, unsigned int *); 504 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 505 void (*evpdo_fini)(efx_nic_t *); 506 } efx_vpd_ops_t; 507 #endif /* EFSYS_OPT_VPD */ 508 509 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 510 511 __checkReturn efx_rc_t 512 efx_mcdi_nvram_partitions( 513 __in efx_nic_t *enp, 514 __out_bcount(size) caddr_t data, 515 __in size_t size, 516 __out unsigned int *npartnp); 517 518 __checkReturn efx_rc_t 519 efx_mcdi_nvram_metadata( 520 __in efx_nic_t *enp, 521 __in uint32_t partn, 522 __out uint32_t *subtypep, 523 __out_ecount(4) uint16_t version[4], 524 __out_bcount_opt(size) char *descp, 525 __in size_t size); 526 527 __checkReturn efx_rc_t 528 efx_mcdi_nvram_info( 529 __in efx_nic_t *enp, 530 __in uint32_t partn, 531 __out_opt size_t *sizep, 532 __out_opt uint32_t *addressp, 533 __out_opt uint32_t *erase_sizep, 534 __out_opt uint32_t *write_sizep); 535 536 __checkReturn efx_rc_t 537 efx_mcdi_nvram_update_start( 538 __in efx_nic_t *enp, 539 __in uint32_t partn); 540 541 __checkReturn efx_rc_t 542 efx_mcdi_nvram_read( 543 __in efx_nic_t *enp, 544 __in uint32_t partn, 545 __in uint32_t offset, 546 __out_bcount(size) caddr_t data, 547 __in size_t size, 548 __in uint32_t mode); 549 550 __checkReturn efx_rc_t 551 efx_mcdi_nvram_erase( 552 __in efx_nic_t *enp, 553 __in uint32_t partn, 554 __in uint32_t offset, 555 __in size_t size); 556 557 __checkReturn efx_rc_t 558 efx_mcdi_nvram_write( 559 __in efx_nic_t *enp, 560 __in uint32_t partn, 561 __in uint32_t offset, 562 __out_bcount(size) caddr_t data, 563 __in size_t size); 564 565 __checkReturn efx_rc_t 566 efx_mcdi_nvram_update_finish( 567 __in efx_nic_t *enp, 568 __in uint32_t partn, 569 __in boolean_t reboot, 570 __out_opt uint32_t *verify_resultp); 571 572 #if EFSYS_OPT_DIAG 573 574 __checkReturn efx_rc_t 575 efx_mcdi_nvram_test( 576 __in efx_nic_t *enp, 577 __in uint32_t partn); 578 579 #endif /* EFSYS_OPT_DIAG */ 580 581 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 582 583 #if EFSYS_OPT_LICENSING 584 585 typedef struct efx_lic_ops_s { 586 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 587 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 588 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 589 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 590 size_t *, uint8_t *); 591 efx_rc_t (*elo_find_start) 592 (efx_nic_t *, caddr_t, size_t, uint32_t *); 593 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 594 uint32_t, uint32_t *); 595 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 596 uint32_t, uint32_t *, uint32_t *); 597 boolean_t (*elo_validate_key)(efx_nic_t *, 598 caddr_t, uint32_t); 599 efx_rc_t (*elo_read_key)(efx_nic_t *, 600 caddr_t, size_t, uint32_t, uint32_t, 601 caddr_t, size_t, uint32_t *); 602 efx_rc_t (*elo_write_key)(efx_nic_t *, 603 caddr_t, size_t, uint32_t, 604 caddr_t, uint32_t, uint32_t *); 605 efx_rc_t (*elo_delete_key)(efx_nic_t *, 606 caddr_t, size_t, uint32_t, 607 uint32_t, uint32_t, uint32_t *); 608 efx_rc_t (*elo_create_partition)(efx_nic_t *, 609 caddr_t, size_t); 610 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 611 caddr_t, size_t); 612 } efx_lic_ops_t; 613 614 #endif 615 616 typedef struct efx_drv_cfg_s { 617 uint32_t edc_min_vi_count; 618 uint32_t edc_max_vi_count; 619 620 uint32_t edc_max_piobuf_count; 621 uint32_t edc_pio_alloc_size; 622 } efx_drv_cfg_t; 623 624 struct efx_nic_s { 625 uint32_t en_magic; 626 efx_family_t en_family; 627 uint32_t en_features; 628 efsys_identifier_t *en_esip; 629 efsys_lock_t *en_eslp; 630 efsys_bar_t *en_esbp; 631 unsigned int en_mod_flags; 632 unsigned int en_reset_flags; 633 efx_nic_cfg_t en_nic_cfg; 634 efx_drv_cfg_t en_drv_cfg; 635 efx_port_t en_port; 636 efx_mon_t en_mon; 637 efx_intr_t en_intr; 638 uint32_t en_ev_qcount; 639 uint32_t en_rx_qcount; 640 uint32_t en_tx_qcount; 641 const efx_nic_ops_t *en_enop; 642 const efx_ev_ops_t *en_eevop; 643 const efx_tx_ops_t *en_etxop; 644 const efx_rx_ops_t *en_erxop; 645 #if EFSYS_OPT_FILTER 646 efx_filter_t en_filter; 647 const efx_filter_ops_t *en_efop; 648 #endif /* EFSYS_OPT_FILTER */ 649 #if EFSYS_OPT_MCDI 650 efx_mcdi_t en_mcdi; 651 #endif /* EFSYS_OPT_MCDI */ 652 #if EFSYS_OPT_NVRAM 653 uint32_t en_nvram_partn_locked; 654 const efx_nvram_ops_t *en_envop; 655 #endif /* EFSYS_OPT_NVRAM */ 656 #if EFSYS_OPT_VPD 657 const efx_vpd_ops_t *en_evpdop; 658 #endif /* EFSYS_OPT_VPD */ 659 #if EFSYS_OPT_RX_SCALE 660 efx_rx_hash_support_t en_hash_support; 661 efx_rx_scale_context_type_t en_rss_context_type; 662 uint32_t en_rss_context; 663 #endif /* EFSYS_OPT_RX_SCALE */ 664 uint32_t en_vport_id; 665 #if EFSYS_OPT_LICENSING 666 const efx_lic_ops_t *en_elop; 667 boolean_t en_licensing_supported; 668 #endif 669 union { 670 #if EFSYS_OPT_SIENA 671 struct { 672 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 673 unsigned int enu_partn_mask; 674 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 675 #if EFSYS_OPT_VPD 676 caddr_t enu_svpd; 677 size_t enu_svpd_length; 678 #endif /* EFSYS_OPT_VPD */ 679 int enu_unused; 680 } siena; 681 #endif /* EFSYS_OPT_SIENA */ 682 int enu_unused; 683 } en_u; 684 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 685 union en_arch { 686 struct { 687 int ena_vi_base; 688 int ena_vi_count; 689 int ena_vi_shift; 690 #if EFSYS_OPT_VPD 691 caddr_t ena_svpd; 692 size_t ena_svpd_length; 693 #endif /* EFSYS_OPT_VPD */ 694 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 695 uint32_t ena_piobuf_count; 696 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 697 uint32_t ena_pio_write_vi_base; 698 /* Memory BAR mapping regions */ 699 uint32_t ena_uc_mem_map_offset; 700 size_t ena_uc_mem_map_size; 701 uint32_t ena_wc_mem_map_offset; 702 size_t ena_wc_mem_map_size; 703 } ef10; 704 } en_arch; 705 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 706 }; 707 708 709 #define EFX_NIC_MAGIC 0x02121996 710 711 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 712 const efx_ev_callbacks_t *, void *); 713 714 typedef struct efx_evq_rxq_state_s { 715 unsigned int eers_rx_read_ptr; 716 unsigned int eers_rx_mask; 717 #if EFSYS_OPT_RX_PACKED_STREAM 718 unsigned int eers_rx_stream_npackets; 719 boolean_t eers_rx_packed_stream; 720 unsigned int eers_rx_packed_stream_credits; 721 #endif 722 } efx_evq_rxq_state_t; 723 724 struct efx_evq_s { 725 uint32_t ee_magic; 726 efx_nic_t *ee_enp; 727 unsigned int ee_index; 728 unsigned int ee_mask; 729 efsys_mem_t *ee_esmp; 730 #if EFSYS_OPT_QSTATS 731 uint32_t ee_stat[EV_NQSTATS]; 732 #endif /* EFSYS_OPT_QSTATS */ 733 734 efx_ev_handler_t ee_rx; 735 efx_ev_handler_t ee_tx; 736 efx_ev_handler_t ee_driver; 737 efx_ev_handler_t ee_global; 738 efx_ev_handler_t ee_drv_gen; 739 #if EFSYS_OPT_MCDI 740 efx_ev_handler_t ee_mcdi; 741 #endif /* EFSYS_OPT_MCDI */ 742 743 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 744 745 uint32_t ee_flags; 746 }; 747 748 #define EFX_EVQ_MAGIC 0x08081997 749 750 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 751 752 struct efx_rxq_s { 753 uint32_t er_magic; 754 efx_nic_t *er_enp; 755 efx_evq_t *er_eep; 756 unsigned int er_index; 757 unsigned int er_label; 758 unsigned int er_mask; 759 efsys_mem_t *er_esmp; 760 efx_evq_rxq_state_t *er_ev_qstate; 761 }; 762 763 #define EFX_RXQ_MAGIC 0x15022005 764 765 struct efx_txq_s { 766 uint32_t et_magic; 767 efx_nic_t *et_enp; 768 unsigned int et_index; 769 unsigned int et_mask; 770 efsys_mem_t *et_esmp; 771 #if EFSYS_OPT_HUNTINGTON 772 uint32_t et_pio_bufnum; 773 uint32_t et_pio_blknum; 774 uint32_t et_pio_write_offset; 775 uint32_t et_pio_offset; 776 size_t et_pio_size; 777 #endif 778 #if EFSYS_OPT_QSTATS 779 uint32_t et_stat[TX_NQSTATS]; 780 #endif /* EFSYS_OPT_QSTATS */ 781 }; 782 783 #define EFX_TXQ_MAGIC 0x05092005 784 785 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 786 do { \ 787 (_dst)[0] = (_src)[0]; \ 788 (_dst)[1] = (_src)[1]; \ 789 (_dst)[2] = (_src)[2]; \ 790 (_dst)[3] = (_src)[3]; \ 791 (_dst)[4] = (_src)[4]; \ 792 (_dst)[5] = (_src)[5]; \ 793 _NOTE(CONSTANTCONDITION) \ 794 } while (B_FALSE) 795 796 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 797 do { \ 798 uint16_t *_d = (uint16_t *)(_dst); \ 799 _d[0] = 0xffff; \ 800 _d[1] = 0xffff; \ 801 _d[2] = 0xffff; \ 802 _NOTE(CONSTANTCONDITION) \ 803 } while (B_FALSE) 804 805 #if EFSYS_OPT_CHECK_REG 806 #define EFX_CHECK_REG(_enp, _reg) \ 807 do { \ 808 const char *name = #_reg; \ 809 char min = name[4]; \ 810 char max = name[5]; \ 811 char rev; \ 812 \ 813 switch ((_enp)->en_family) { \ 814 case EFX_FAMILY_SIENA: \ 815 rev = 'C'; \ 816 break; \ 817 \ 818 case EFX_FAMILY_HUNTINGTON: \ 819 rev = 'D'; \ 820 break; \ 821 \ 822 case EFX_FAMILY_MEDFORD: \ 823 rev = 'E'; \ 824 break; \ 825 \ 826 default: \ 827 rev = '?'; \ 828 break; \ 829 } \ 830 \ 831 EFSYS_ASSERT3S(rev, >=, min); \ 832 EFSYS_ASSERT3S(rev, <=, max); \ 833 \ 834 _NOTE(CONSTANTCONDITION) \ 835 } while (B_FALSE) 836 #else 837 #define EFX_CHECK_REG(_enp, _reg) do { \ 838 _NOTE(CONSTANTCONDITION) \ 839 } while (B_FALSE) 840 #endif 841 842 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 843 do { \ 844 EFX_CHECK_REG((_enp), (_reg)); \ 845 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 846 (_edp), (_lock)); \ 847 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 848 uint32_t, _reg ## _OFST, \ 849 uint32_t, (_edp)->ed_u32[0]); \ 850 _NOTE(CONSTANTCONDITION) \ 851 } while (B_FALSE) 852 853 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 854 do { \ 855 EFX_CHECK_REG((_enp), (_reg)); \ 856 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 857 uint32_t, _reg ## _OFST, \ 858 uint32_t, (_edp)->ed_u32[0]); \ 859 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 860 (_edp), (_lock)); \ 861 _NOTE(CONSTANTCONDITION) \ 862 } while (B_FALSE) 863 864 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 865 do { \ 866 EFX_CHECK_REG((_enp), (_reg)); \ 867 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 868 (_eqp)); \ 869 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 870 uint32_t, _reg ## _OFST, \ 871 uint32_t, (_eqp)->eq_u32[1], \ 872 uint32_t, (_eqp)->eq_u32[0]); \ 873 _NOTE(CONSTANTCONDITION) \ 874 } while (B_FALSE) 875 876 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 877 do { \ 878 EFX_CHECK_REG((_enp), (_reg)); \ 879 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 880 uint32_t, _reg ## _OFST, \ 881 uint32_t, (_eqp)->eq_u32[1], \ 882 uint32_t, (_eqp)->eq_u32[0]); \ 883 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 884 (_eqp)); \ 885 _NOTE(CONSTANTCONDITION) \ 886 } while (B_FALSE) 887 888 #define EFX_BAR_READO(_enp, _reg, _eop) \ 889 do { \ 890 EFX_CHECK_REG((_enp), (_reg)); \ 891 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 892 (_eop), B_TRUE); \ 893 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 894 uint32_t, _reg ## _OFST, \ 895 uint32_t, (_eop)->eo_u32[3], \ 896 uint32_t, (_eop)->eo_u32[2], \ 897 uint32_t, (_eop)->eo_u32[1], \ 898 uint32_t, (_eop)->eo_u32[0]); \ 899 _NOTE(CONSTANTCONDITION) \ 900 } while (B_FALSE) 901 902 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 903 do { \ 904 EFX_CHECK_REG((_enp), (_reg)); \ 905 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 906 uint32_t, _reg ## _OFST, \ 907 uint32_t, (_eop)->eo_u32[3], \ 908 uint32_t, (_eop)->eo_u32[2], \ 909 uint32_t, (_eop)->eo_u32[1], \ 910 uint32_t, (_eop)->eo_u32[0]); \ 911 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 912 (_eop), B_TRUE); \ 913 _NOTE(CONSTANTCONDITION) \ 914 } while (B_FALSE) 915 916 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 917 do { \ 918 EFX_CHECK_REG((_enp), (_reg)); \ 919 EFSYS_BAR_READD((_enp)->en_esbp, \ 920 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 921 (_edp), (_lock)); \ 922 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 923 uint32_t, (_index), \ 924 uint32_t, _reg ## _OFST, \ 925 uint32_t, (_edp)->ed_u32[0]); \ 926 _NOTE(CONSTANTCONDITION) \ 927 } while (B_FALSE) 928 929 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 930 do { \ 931 EFX_CHECK_REG((_enp), (_reg)); \ 932 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 933 uint32_t, (_index), \ 934 uint32_t, _reg ## _OFST, \ 935 uint32_t, (_edp)->ed_u32[0]); \ 936 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 937 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 938 (_edp), (_lock)); \ 939 _NOTE(CONSTANTCONDITION) \ 940 } while (B_FALSE) 941 942 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 943 do { \ 944 EFX_CHECK_REG((_enp), (_reg)); \ 945 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 946 uint32_t, (_index), \ 947 uint32_t, _reg ## _OFST, \ 948 uint32_t, (_edp)->ed_u32[0]); \ 949 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 950 (_reg ## _OFST + \ 951 (2 * sizeof (efx_dword_t)) + \ 952 ((_index) * _reg ## _STEP)), \ 953 (_edp), (_lock)); \ 954 _NOTE(CONSTANTCONDITION) \ 955 } while (B_FALSE) 956 957 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 958 do { \ 959 EFX_CHECK_REG((_enp), (_reg)); \ 960 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 961 uint32_t, (_index), \ 962 uint32_t, _reg ## _OFST, \ 963 uint32_t, (_edp)->ed_u32[0]); \ 964 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 965 (_reg ## _OFST + \ 966 (3 * sizeof (efx_dword_t)) + \ 967 ((_index) * _reg ## _STEP)), \ 968 (_edp), (_lock)); \ 969 _NOTE(CONSTANTCONDITION) \ 970 } while (B_FALSE) 971 972 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 973 do { \ 974 EFX_CHECK_REG((_enp), (_reg)); \ 975 EFSYS_BAR_READQ((_enp)->en_esbp, \ 976 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 977 (_eqp)); \ 978 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 979 uint32_t, (_index), \ 980 uint32_t, _reg ## _OFST, \ 981 uint32_t, (_eqp)->eq_u32[1], \ 982 uint32_t, (_eqp)->eq_u32[0]); \ 983 _NOTE(CONSTANTCONDITION) \ 984 } while (B_FALSE) 985 986 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 987 do { \ 988 EFX_CHECK_REG((_enp), (_reg)); \ 989 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 990 uint32_t, (_index), \ 991 uint32_t, _reg ## _OFST, \ 992 uint32_t, (_eqp)->eq_u32[1], \ 993 uint32_t, (_eqp)->eq_u32[0]); \ 994 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 995 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 996 (_eqp)); \ 997 _NOTE(CONSTANTCONDITION) \ 998 } while (B_FALSE) 999 1000 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1001 do { \ 1002 EFX_CHECK_REG((_enp), (_reg)); \ 1003 EFSYS_BAR_READO((_enp)->en_esbp, \ 1004 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1005 (_eop), (_lock)); \ 1006 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1007 uint32_t, (_index), \ 1008 uint32_t, _reg ## _OFST, \ 1009 uint32_t, (_eop)->eo_u32[3], \ 1010 uint32_t, (_eop)->eo_u32[2], \ 1011 uint32_t, (_eop)->eo_u32[1], \ 1012 uint32_t, (_eop)->eo_u32[0]); \ 1013 _NOTE(CONSTANTCONDITION) \ 1014 } while (B_FALSE) 1015 1016 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1017 do { \ 1018 EFX_CHECK_REG((_enp), (_reg)); \ 1019 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1020 uint32_t, (_index), \ 1021 uint32_t, _reg ## _OFST, \ 1022 uint32_t, (_eop)->eo_u32[3], \ 1023 uint32_t, (_eop)->eo_u32[2], \ 1024 uint32_t, (_eop)->eo_u32[1], \ 1025 uint32_t, (_eop)->eo_u32[0]); \ 1026 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1027 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1028 (_eop), (_lock)); \ 1029 _NOTE(CONSTANTCONDITION) \ 1030 } while (B_FALSE) 1031 1032 /* 1033 * Allow drivers to perform optimised 128-bit doorbell writes. 1034 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1035 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1036 * the need for locking in the host, and are the only ones known to be safe to 1037 * use 128-bites write with. 1038 */ 1039 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1040 do { \ 1041 EFX_CHECK_REG((_enp), (_reg)); \ 1042 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1043 const char *, \ 1044 #_reg, \ 1045 uint32_t, (_index), \ 1046 uint32_t, _reg ## _OFST, \ 1047 uint32_t, (_eop)->eo_u32[3], \ 1048 uint32_t, (_eop)->eo_u32[2], \ 1049 uint32_t, (_eop)->eo_u32[1], \ 1050 uint32_t, (_eop)->eo_u32[0]); \ 1051 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1052 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1053 (_eop)); \ 1054 _NOTE(CONSTANTCONDITION) \ 1055 } while (B_FALSE) 1056 1057 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1058 do { \ 1059 unsigned int _new = (_wptr); \ 1060 unsigned int _old = (_owptr); \ 1061 \ 1062 if ((_new) >= (_old)) \ 1063 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1064 (_old) * sizeof (efx_desc_t), \ 1065 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1066 else \ 1067 /* \ 1068 * It is cheaper to sync entire map than sync \ 1069 * two parts especially when offset/size are \ 1070 * ignored and entire map is synced in any case.\ 1071 */ \ 1072 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1073 0, \ 1074 (_entries) * sizeof (efx_desc_t)); \ 1075 _NOTE(CONSTANTCONDITION) \ 1076 } while (B_FALSE) 1077 1078 extern __checkReturn efx_rc_t 1079 efx_nic_biu_test( 1080 __in efx_nic_t *enp); 1081 1082 extern __checkReturn efx_rc_t 1083 efx_mac_select( 1084 __in efx_nic_t *enp); 1085 1086 extern void 1087 efx_mac_multicast_hash_compute( 1088 __in_ecount(6*count) uint8_t const *addrs, 1089 __in int count, 1090 __out efx_oword_t *hash_low, 1091 __out efx_oword_t *hash_high); 1092 1093 extern __checkReturn efx_rc_t 1094 efx_phy_probe( 1095 __in efx_nic_t *enp); 1096 1097 extern void 1098 efx_phy_unprobe( 1099 __in efx_nic_t *enp); 1100 1101 #if EFSYS_OPT_VPD 1102 1103 /* VPD utility functions */ 1104 1105 extern __checkReturn efx_rc_t 1106 efx_vpd_hunk_length( 1107 __in_bcount(size) caddr_t data, 1108 __in size_t size, 1109 __out size_t *lengthp); 1110 1111 extern __checkReturn efx_rc_t 1112 efx_vpd_hunk_verify( 1113 __in_bcount(size) caddr_t data, 1114 __in size_t size, 1115 __out_opt boolean_t *cksummedp); 1116 1117 extern __checkReturn efx_rc_t 1118 efx_vpd_hunk_reinit( 1119 __in_bcount(size) caddr_t data, 1120 __in size_t size, 1121 __in boolean_t wantpid); 1122 1123 extern __checkReturn efx_rc_t 1124 efx_vpd_hunk_get( 1125 __in_bcount(size) caddr_t data, 1126 __in size_t size, 1127 __in efx_vpd_tag_t tag, 1128 __in efx_vpd_keyword_t keyword, 1129 __out unsigned int *payloadp, 1130 __out uint8_t *paylenp); 1131 1132 extern __checkReturn efx_rc_t 1133 efx_vpd_hunk_next( 1134 __in_bcount(size) caddr_t data, 1135 __in size_t size, 1136 __out efx_vpd_tag_t *tagp, 1137 __out efx_vpd_keyword_t *keyword, 1138 __out_opt unsigned int *payloadp, 1139 __out_opt uint8_t *paylenp, 1140 __inout unsigned int *contp); 1141 1142 extern __checkReturn efx_rc_t 1143 efx_vpd_hunk_set( 1144 __in_bcount(size) caddr_t data, 1145 __in size_t size, 1146 __in efx_vpd_value_t *evvp); 1147 1148 #endif /* EFSYS_OPT_VPD */ 1149 1150 #if EFSYS_OPT_DIAG 1151 1152 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1153 1154 typedef struct efx_register_set_s { 1155 unsigned int address; 1156 unsigned int step; 1157 unsigned int rows; 1158 efx_oword_t mask; 1159 } efx_register_set_t; 1160 1161 extern __checkReturn efx_rc_t 1162 efx_nic_test_registers( 1163 __in efx_nic_t *enp, 1164 __in efx_register_set_t *rsp, 1165 __in size_t count); 1166 1167 extern __checkReturn efx_rc_t 1168 efx_nic_test_tables( 1169 __in efx_nic_t *enp, 1170 __in efx_register_set_t *rsp, 1171 __in efx_pattern_type_t pattern, 1172 __in size_t count); 1173 1174 #endif /* EFSYS_OPT_DIAG */ 1175 1176 #if EFSYS_OPT_MCDI 1177 1178 extern __checkReturn efx_rc_t 1179 efx_mcdi_set_workaround( 1180 __in efx_nic_t *enp, 1181 __in uint32_t type, 1182 __in boolean_t enabled, 1183 __out_opt uint32_t *flagsp); 1184 1185 extern __checkReturn efx_rc_t 1186 efx_mcdi_get_workarounds( 1187 __in efx_nic_t *enp, 1188 __out_opt uint32_t *implementedp, 1189 __out_opt uint32_t *enabledp); 1190 1191 #endif /* EFSYS_OPT_MCDI */ 1192 1193 #if EFSYS_OPT_MAC_STATS 1194 1195 /* 1196 * Closed range of stats (i.e. the first and the last are included). 1197 * The last must be greater or equal (if the range is one item only) to 1198 * the first. 1199 */ 1200 struct efx_mac_stats_range { 1201 efx_mac_stat_t first; 1202 efx_mac_stat_t last; 1203 }; 1204 1205 extern efx_rc_t 1206 efx_mac_stats_mask_add_ranges( 1207 __inout_bcount(mask_size) uint32_t *maskp, 1208 __in size_t mask_size, 1209 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1210 __in unsigned int rng_count); 1211 1212 #endif /* EFSYS_OPT_MAC_STATS */ 1213 1214 #ifdef __cplusplus 1215 } 1216 #endif 1217 1218 #endif /* _SYS_EFX_IMPL_H */ 1219