1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #ifndef _SYS_EFX_IMPL_H 34 #define _SYS_EFX_IMPL_H 35 36 #include "efx.h" 37 #include "efx_regs.h" 38 #include "efx_regs_ef10.h" 39 40 /* FIXME: Add definition for driver generated software events */ 41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 43 #endif 44 45 #if EFSYS_OPT_SIENA 46 #include "siena_impl.h" 47 #endif /* EFSYS_OPT_SIENA */ 48 49 #if EFSYS_OPT_HUNTINGTON 50 #include "hunt_impl.h" 51 #endif /* EFSYS_OPT_HUNTINGTON */ 52 53 #if EFSYS_OPT_MEDFORD 54 #include "medford_impl.h" 55 #endif /* EFSYS_OPT_MEDFORD */ 56 57 #if EFSYS_OPT_MEDFORD2 58 #include "medford2_impl.h" 59 #endif /* EFSYS_OPT_MEDFORD2 */ 60 61 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) 62 #include "ef10_impl.h" 63 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ 64 65 #ifdef __cplusplus 66 extern "C" { 67 #endif 68 69 #define EFX_MOD_MCDI 0x00000001 70 #define EFX_MOD_PROBE 0x00000002 71 #define EFX_MOD_NVRAM 0x00000004 72 #define EFX_MOD_VPD 0x00000008 73 #define EFX_MOD_NIC 0x00000010 74 #define EFX_MOD_INTR 0x00000020 75 #define EFX_MOD_EV 0x00000040 76 #define EFX_MOD_RX 0x00000080 77 #define EFX_MOD_TX 0x00000100 78 #define EFX_MOD_PORT 0x00000200 79 #define EFX_MOD_MON 0x00000400 80 #define EFX_MOD_FILTER 0x00001000 81 #define EFX_MOD_LIC 0x00002000 82 #define EFX_MOD_TUNNEL 0x00004000 83 84 #define EFX_RESET_PHY 0x00000001 85 #define EFX_RESET_RXQ_ERR 0x00000002 86 #define EFX_RESET_TXQ_ERR 0x00000004 87 #define EFX_RESET_HW_UNAVAIL 0x00000008 88 89 typedef enum efx_mac_type_e { 90 EFX_MAC_INVALID = 0, 91 EFX_MAC_SIENA, 92 EFX_MAC_HUNTINGTON, 93 EFX_MAC_MEDFORD, 94 EFX_MAC_MEDFORD2, 95 EFX_MAC_NTYPES 96 } efx_mac_type_t; 97 98 typedef struct efx_ev_ops_s { 99 efx_rc_t (*eevo_init)(efx_nic_t *); 100 void (*eevo_fini)(efx_nic_t *); 101 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 102 efsys_mem_t *, size_t, uint32_t, 103 uint32_t, uint32_t, efx_evq_t *); 104 void (*eevo_qdestroy)(efx_evq_t *); 105 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 106 void (*eevo_qpost)(efx_evq_t *, uint16_t); 107 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 108 #if EFSYS_OPT_QSTATS 109 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 110 #endif 111 } efx_ev_ops_t; 112 113 typedef struct efx_tx_ops_s { 114 efx_rc_t (*etxo_init)(efx_nic_t *); 115 void (*etxo_fini)(efx_nic_t *); 116 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 117 unsigned int, unsigned int, 118 efsys_mem_t *, size_t, 119 uint32_t, uint16_t, 120 efx_evq_t *, efx_txq_t *, 121 unsigned int *); 122 void (*etxo_qdestroy)(efx_txq_t *); 123 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 124 unsigned int, unsigned int, 125 unsigned int *); 126 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 127 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 128 efx_rc_t (*etxo_qflush)(efx_txq_t *); 129 void (*etxo_qenable)(efx_txq_t *); 130 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 131 void (*etxo_qpio_disable)(efx_txq_t *); 132 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 133 size_t); 134 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 135 unsigned int *); 136 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 137 unsigned int, unsigned int, 138 unsigned int *); 139 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 140 size_t, boolean_t, 141 efx_desc_t *); 142 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 143 uint32_t, uint8_t, 144 efx_desc_t *); 145 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 146 uint16_t, uint32_t, uint16_t, 147 efx_desc_t *, int); 148 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 149 efx_desc_t *); 150 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 151 efx_desc_t *); 152 #if EFSYS_OPT_QSTATS 153 void (*etxo_qstats_update)(efx_txq_t *, 154 efsys_stat_t *); 155 #endif 156 } efx_tx_ops_t; 157 158 typedef union efx_rxq_type_data_u { 159 /* Dummy member to have non-empty union if no options are enabled */ 160 uint32_t ertd_dummy; 161 #if EFSYS_OPT_RX_PACKED_STREAM 162 struct { 163 uint32_t eps_buf_size; 164 } ertd_packed_stream; 165 #endif 166 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 167 struct { 168 uint32_t eessb_bufs_per_desc; 169 uint32_t eessb_max_dma_len; 170 uint32_t eessb_buf_stride; 171 uint32_t eessb_hol_block_timeout; 172 } ertd_es_super_buffer; 173 #endif 174 } efx_rxq_type_data_t; 175 176 typedef struct efx_rx_ops_s { 177 efx_rc_t (*erxo_init)(efx_nic_t *); 178 void (*erxo_fini)(efx_nic_t *); 179 #if EFSYS_OPT_RX_SCATTER 180 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 181 #endif 182 #if EFSYS_OPT_RX_SCALE 183 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 184 efx_rx_scale_context_type_t, 185 uint32_t, uint32_t *); 186 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 187 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 188 efx_rx_hash_alg_t, 189 efx_rx_hash_type_t, boolean_t); 190 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 191 uint8_t *, size_t); 192 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 193 unsigned int *, size_t); 194 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 195 uint8_t *); 196 #endif /* EFSYS_OPT_RX_SCALE */ 197 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 198 uint16_t *); 199 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 200 unsigned int, unsigned int, 201 unsigned int); 202 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 203 #if EFSYS_OPT_RX_PACKED_STREAM 204 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 205 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 206 uint32_t, uint32_t, 207 uint16_t *, uint32_t *, uint32_t *); 208 #endif 209 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 210 void (*erxo_qenable)(efx_rxq_t *); 211 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 212 unsigned int, efx_rxq_type_t, 213 const efx_rxq_type_data_t *, 214 efsys_mem_t *, size_t, uint32_t, 215 unsigned int, 216 efx_evq_t *, efx_rxq_t *); 217 void (*erxo_qdestroy)(efx_rxq_t *); 218 } efx_rx_ops_t; 219 220 typedef struct efx_mac_ops_s { 221 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 222 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 223 efx_rc_t (*emo_addr_set)(efx_nic_t *); 224 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 225 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 226 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 227 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 228 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 229 efx_rxq_t *, boolean_t); 230 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 231 #if EFSYS_OPT_LOOPBACK 232 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 233 efx_loopback_type_t); 234 #endif /* EFSYS_OPT_LOOPBACK */ 235 #if EFSYS_OPT_MAC_STATS 236 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 237 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 238 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 239 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 240 uint16_t, boolean_t); 241 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 242 efsys_stat_t *, uint32_t *); 243 #endif /* EFSYS_OPT_MAC_STATS */ 244 } efx_mac_ops_t; 245 246 typedef struct efx_phy_ops_s { 247 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 248 efx_rc_t (*epo_reset)(efx_nic_t *); 249 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 250 efx_rc_t (*epo_verify)(efx_nic_t *); 251 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 252 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 253 #if EFSYS_OPT_PHY_STATS 254 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 255 uint32_t *); 256 #endif /* EFSYS_OPT_PHY_STATS */ 257 #if EFSYS_OPT_BIST 258 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 259 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 260 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 261 efx_bist_result_t *, uint32_t *, 262 unsigned long *, size_t); 263 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 264 #endif /* EFSYS_OPT_BIST */ 265 } efx_phy_ops_t; 266 267 #if EFSYS_OPT_FILTER 268 typedef struct efx_filter_ops_s { 269 efx_rc_t (*efo_init)(efx_nic_t *); 270 void (*efo_fini)(efx_nic_t *); 271 efx_rc_t (*efo_restore)(efx_nic_t *); 272 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 273 boolean_t may_replace); 274 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 275 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 276 size_t, size_t *); 277 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 278 boolean_t, boolean_t, boolean_t, 279 uint8_t const *, uint32_t); 280 } efx_filter_ops_t; 281 282 extern __checkReturn efx_rc_t 283 efx_filter_reconfigure( 284 __in efx_nic_t *enp, 285 __in_ecount(6) uint8_t const *mac_addr, 286 __in boolean_t all_unicst, 287 __in boolean_t mulcst, 288 __in boolean_t all_mulcst, 289 __in boolean_t brdcst, 290 __in_ecount(6*count) uint8_t const *addrs, 291 __in uint32_t count); 292 293 #endif /* EFSYS_OPT_FILTER */ 294 295 #if EFSYS_OPT_TUNNEL 296 typedef struct efx_tunnel_ops_s { 297 boolean_t (*eto_udp_encap_supported)(efx_nic_t *); 298 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 299 } efx_tunnel_ops_t; 300 #endif /* EFSYS_OPT_TUNNEL */ 301 302 typedef struct efx_port_s { 303 efx_mac_type_t ep_mac_type; 304 uint32_t ep_phy_type; 305 uint8_t ep_port; 306 uint32_t ep_mac_pdu; 307 uint8_t ep_mac_addr[6]; 308 efx_link_mode_t ep_link_mode; 309 boolean_t ep_all_unicst; 310 boolean_t ep_mulcst; 311 boolean_t ep_all_mulcst; 312 boolean_t ep_brdcst; 313 unsigned int ep_fcntl; 314 boolean_t ep_fcntl_autoneg; 315 efx_oword_t ep_multicst_hash[2]; 316 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 317 EFX_MAC_MULTICAST_LIST_MAX]; 318 uint32_t ep_mulcst_addr_count; 319 #if EFSYS_OPT_LOOPBACK 320 efx_loopback_type_t ep_loopback_type; 321 efx_link_mode_t ep_loopback_link_mode; 322 #endif /* EFSYS_OPT_LOOPBACK */ 323 #if EFSYS_OPT_PHY_FLAGS 324 uint32_t ep_phy_flags; 325 #endif /* EFSYS_OPT_PHY_FLAGS */ 326 #if EFSYS_OPT_PHY_LED_CONTROL 327 efx_phy_led_mode_t ep_phy_led_mode; 328 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 329 efx_phy_media_type_t ep_fixed_port_type; 330 efx_phy_media_type_t ep_module_type; 331 uint32_t ep_adv_cap_mask; 332 uint32_t ep_lp_cap_mask; 333 uint32_t ep_default_adv_cap_mask; 334 uint32_t ep_phy_cap_mask; 335 boolean_t ep_mac_drain; 336 #if EFSYS_OPT_BIST 337 efx_bist_type_t ep_current_bist; 338 #endif 339 const efx_mac_ops_t *ep_emop; 340 const efx_phy_ops_t *ep_epop; 341 } efx_port_t; 342 343 typedef struct efx_mon_ops_s { 344 #if EFSYS_OPT_MON_STATS 345 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 346 efx_mon_stat_value_t *); 347 efx_rc_t (*emo_limits_update)(efx_nic_t *, 348 efx_mon_stat_limits_t *); 349 #endif /* EFSYS_OPT_MON_STATS */ 350 } efx_mon_ops_t; 351 352 typedef struct efx_mon_s { 353 efx_mon_type_t em_type; 354 const efx_mon_ops_t *em_emop; 355 } efx_mon_t; 356 357 typedef struct efx_intr_ops_s { 358 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 359 void (*eio_enable)(efx_nic_t *); 360 void (*eio_disable)(efx_nic_t *); 361 void (*eio_disable_unlocked)(efx_nic_t *); 362 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 363 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 364 void (*eio_status_message)(efx_nic_t *, unsigned int, 365 boolean_t *); 366 void (*eio_fatal)(efx_nic_t *); 367 void (*eio_fini)(efx_nic_t *); 368 } efx_intr_ops_t; 369 370 typedef struct efx_intr_s { 371 const efx_intr_ops_t *ei_eiop; 372 efsys_mem_t *ei_esmp; 373 efx_intr_type_t ei_type; 374 unsigned int ei_level; 375 } efx_intr_t; 376 377 typedef struct efx_nic_ops_s { 378 efx_rc_t (*eno_probe)(efx_nic_t *); 379 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 380 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 381 efx_rc_t (*eno_reset)(efx_nic_t *); 382 efx_rc_t (*eno_init)(efx_nic_t *); 383 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 384 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 385 uint32_t *, size_t *); 386 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 387 void (*eno_set_hw_unavailable)(efx_nic_t *); 388 #if EFSYS_OPT_DIAG 389 efx_rc_t (*eno_register_test)(efx_nic_t *); 390 #endif /* EFSYS_OPT_DIAG */ 391 void (*eno_fini)(efx_nic_t *); 392 void (*eno_unprobe)(efx_nic_t *); 393 } efx_nic_ops_t; 394 395 #ifndef EFX_TXQ_LIMIT_TARGET 396 #define EFX_TXQ_LIMIT_TARGET 259 397 #endif 398 #ifndef EFX_RXQ_LIMIT_TARGET 399 #define EFX_RXQ_LIMIT_TARGET 512 400 #endif 401 402 #if EFSYS_OPT_FILTER 403 404 #if EFSYS_OPT_SIENA 405 406 typedef struct siena_filter_spec_s { 407 uint8_t sfs_type; 408 uint32_t sfs_flags; 409 uint32_t sfs_dmaq_id; 410 uint32_t sfs_dword[3]; 411 } siena_filter_spec_t; 412 413 typedef enum siena_filter_type_e { 414 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 415 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 416 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 417 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 418 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 419 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 420 421 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 422 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 423 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 424 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 425 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 426 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 427 428 EFX_SIENA_FILTER_NTYPES 429 } siena_filter_type_t; 430 431 typedef enum siena_filter_tbl_id_e { 432 EFX_SIENA_FILTER_TBL_RX_IP = 0, 433 EFX_SIENA_FILTER_TBL_RX_MAC, 434 EFX_SIENA_FILTER_TBL_TX_IP, 435 EFX_SIENA_FILTER_TBL_TX_MAC, 436 EFX_SIENA_FILTER_NTBLS 437 } siena_filter_tbl_id_t; 438 439 typedef struct siena_filter_tbl_s { 440 int sft_size; /* number of entries */ 441 int sft_used; /* active count */ 442 uint32_t *sft_bitmap; /* active bitmap */ 443 siena_filter_spec_t *sft_spec; /* array of saved specs */ 444 } siena_filter_tbl_t; 445 446 typedef struct siena_filter_s { 447 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 448 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 449 } siena_filter_t; 450 451 #endif /* EFSYS_OPT_SIENA */ 452 453 typedef struct efx_filter_s { 454 #if EFSYS_OPT_SIENA 455 siena_filter_t *ef_siena_filter; 456 #endif /* EFSYS_OPT_SIENA */ 457 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 458 ef10_filter_table_t *ef_ef10_filter_table; 459 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 460 } efx_filter_t; 461 462 #if EFSYS_OPT_SIENA 463 464 extern void 465 siena_filter_tbl_clear( 466 __in efx_nic_t *enp, 467 __in siena_filter_tbl_id_t tbl); 468 469 #endif /* EFSYS_OPT_SIENA */ 470 471 #endif /* EFSYS_OPT_FILTER */ 472 473 #if EFSYS_OPT_MCDI 474 475 #define EFX_TUNNEL_MAXNENTRIES (16) 476 477 #if EFSYS_OPT_TUNNEL 478 479 typedef struct efx_tunnel_udp_entry_s { 480 uint16_t etue_port; /* host/cpu-endian */ 481 uint16_t etue_protocol; 482 } efx_tunnel_udp_entry_t; 483 484 typedef struct efx_tunnel_cfg_s { 485 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 486 unsigned int etc_udp_entries_num; 487 } efx_tunnel_cfg_t; 488 489 #endif /* EFSYS_OPT_TUNNEL */ 490 491 typedef struct efx_mcdi_ops_s { 492 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 493 void (*emco_send_request)(efx_nic_t *, void *, size_t, 494 void *, size_t); 495 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 496 boolean_t (*emco_poll_response)(efx_nic_t *); 497 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 498 void (*emco_fini)(efx_nic_t *); 499 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 500 efx_mcdi_feature_id_t, boolean_t *); 501 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 502 uint32_t *); 503 } efx_mcdi_ops_t; 504 505 typedef struct efx_mcdi_s { 506 const efx_mcdi_ops_t *em_emcop; 507 const efx_mcdi_transport_t *em_emtp; 508 efx_mcdi_iface_t em_emip; 509 } efx_mcdi_t; 510 511 #endif /* EFSYS_OPT_MCDI */ 512 513 #if EFSYS_OPT_NVRAM 514 515 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 516 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 517 518 typedef struct efx_nvram_ops_s { 519 #if EFSYS_OPT_DIAG 520 efx_rc_t (*envo_test)(efx_nic_t *); 521 #endif /* EFSYS_OPT_DIAG */ 522 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 523 uint32_t *); 524 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 525 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 526 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 527 unsigned int, caddr_t, size_t); 528 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 529 unsigned int, caddr_t, size_t); 530 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 531 unsigned int, size_t); 532 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 533 unsigned int, caddr_t, size_t); 534 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 535 uint32_t *); 536 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 537 uint32_t *, uint16_t *); 538 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 539 uint16_t *); 540 efx_rc_t (*envo_buffer_validate)(uint32_t, 541 caddr_t, size_t); 542 } efx_nvram_ops_t; 543 #endif /* EFSYS_OPT_NVRAM */ 544 545 #if EFSYS_OPT_VPD 546 typedef struct efx_vpd_ops_s { 547 efx_rc_t (*evpdo_init)(efx_nic_t *); 548 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 549 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 550 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 551 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 552 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 553 efx_vpd_value_t *); 554 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 555 efx_vpd_value_t *); 556 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 557 efx_vpd_value_t *, unsigned int *); 558 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 559 void (*evpdo_fini)(efx_nic_t *); 560 } efx_vpd_ops_t; 561 #endif /* EFSYS_OPT_VPD */ 562 563 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 564 565 __checkReturn efx_rc_t 566 efx_mcdi_nvram_partitions( 567 __in efx_nic_t *enp, 568 __out_bcount(size) caddr_t data, 569 __in size_t size, 570 __out unsigned int *npartnp); 571 572 __checkReturn efx_rc_t 573 efx_mcdi_nvram_metadata( 574 __in efx_nic_t *enp, 575 __in uint32_t partn, 576 __out uint32_t *subtypep, 577 __out_ecount(4) uint16_t version[4], 578 __out_bcount_opt(size) char *descp, 579 __in size_t size); 580 581 __checkReturn efx_rc_t 582 efx_mcdi_nvram_info( 583 __in efx_nic_t *enp, 584 __in uint32_t partn, 585 __out_opt size_t *sizep, 586 __out_opt uint32_t *addressp, 587 __out_opt uint32_t *erase_sizep, 588 __out_opt uint32_t *write_sizep); 589 590 __checkReturn efx_rc_t 591 efx_mcdi_nvram_update_start( 592 __in efx_nic_t *enp, 593 __in uint32_t partn); 594 595 __checkReturn efx_rc_t 596 efx_mcdi_nvram_read( 597 __in efx_nic_t *enp, 598 __in uint32_t partn, 599 __in uint32_t offset, 600 __out_bcount(size) caddr_t data, 601 __in size_t size, 602 __in uint32_t mode); 603 604 __checkReturn efx_rc_t 605 efx_mcdi_nvram_erase( 606 __in efx_nic_t *enp, 607 __in uint32_t partn, 608 __in uint32_t offset, 609 __in size_t size); 610 611 __checkReturn efx_rc_t 612 efx_mcdi_nvram_write( 613 __in efx_nic_t *enp, 614 __in uint32_t partn, 615 __in uint32_t offset, 616 __in_bcount(size) caddr_t data, 617 __in size_t size); 618 619 __checkReturn efx_rc_t 620 efx_mcdi_nvram_update_finish( 621 __in efx_nic_t *enp, 622 __in uint32_t partn, 623 __in boolean_t reboot, 624 __out_opt uint32_t *verify_resultp); 625 626 #if EFSYS_OPT_DIAG 627 628 __checkReturn efx_rc_t 629 efx_mcdi_nvram_test( 630 __in efx_nic_t *enp, 631 __in uint32_t partn); 632 633 #endif /* EFSYS_OPT_DIAG */ 634 635 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 636 637 #if EFSYS_OPT_LICENSING 638 639 typedef struct efx_lic_ops_s { 640 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 641 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 642 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 643 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 644 size_t *, uint8_t *); 645 efx_rc_t (*elo_find_start) 646 (efx_nic_t *, caddr_t, size_t, uint32_t *); 647 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 648 uint32_t, uint32_t *); 649 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 650 uint32_t, uint32_t *, uint32_t *); 651 boolean_t (*elo_validate_key)(efx_nic_t *, 652 caddr_t, uint32_t); 653 efx_rc_t (*elo_read_key)(efx_nic_t *, 654 caddr_t, size_t, uint32_t, uint32_t, 655 caddr_t, size_t, uint32_t *); 656 efx_rc_t (*elo_write_key)(efx_nic_t *, 657 caddr_t, size_t, uint32_t, 658 caddr_t, uint32_t, uint32_t *); 659 efx_rc_t (*elo_delete_key)(efx_nic_t *, 660 caddr_t, size_t, uint32_t, 661 uint32_t, uint32_t, uint32_t *); 662 efx_rc_t (*elo_create_partition)(efx_nic_t *, 663 caddr_t, size_t); 664 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 665 caddr_t, size_t); 666 } efx_lic_ops_t; 667 668 #endif 669 670 typedef struct efx_drv_cfg_s { 671 uint32_t edc_min_vi_count; 672 uint32_t edc_max_vi_count; 673 674 uint32_t edc_max_piobuf_count; 675 uint32_t edc_pio_alloc_size; 676 } efx_drv_cfg_t; 677 678 struct efx_nic_s { 679 uint32_t en_magic; 680 efx_family_t en_family; 681 uint32_t en_features; 682 efsys_identifier_t *en_esip; 683 efsys_lock_t *en_eslp; 684 efsys_bar_t *en_esbp; 685 unsigned int en_mod_flags; 686 unsigned int en_reset_flags; 687 efx_nic_cfg_t en_nic_cfg; 688 efx_drv_cfg_t en_drv_cfg; 689 efx_port_t en_port; 690 efx_mon_t en_mon; 691 efx_intr_t en_intr; 692 uint32_t en_ev_qcount; 693 uint32_t en_rx_qcount; 694 uint32_t en_tx_qcount; 695 const efx_nic_ops_t *en_enop; 696 const efx_ev_ops_t *en_eevop; 697 const efx_tx_ops_t *en_etxop; 698 const efx_rx_ops_t *en_erxop; 699 efx_fw_variant_t efv; 700 #if EFSYS_OPT_FILTER 701 efx_filter_t en_filter; 702 const efx_filter_ops_t *en_efop; 703 #endif /* EFSYS_OPT_FILTER */ 704 #if EFSYS_OPT_TUNNEL 705 efx_tunnel_cfg_t en_tunnel_cfg; 706 const efx_tunnel_ops_t *en_etop; 707 #endif /* EFSYS_OPT_TUNNEL */ 708 #if EFSYS_OPT_MCDI 709 efx_mcdi_t en_mcdi; 710 #endif /* EFSYS_OPT_MCDI */ 711 #if EFSYS_OPT_NVRAM 712 uint32_t en_nvram_partn_locked; 713 const efx_nvram_ops_t *en_envop; 714 #endif /* EFSYS_OPT_NVRAM */ 715 #if EFSYS_OPT_VPD 716 const efx_vpd_ops_t *en_evpdop; 717 #endif /* EFSYS_OPT_VPD */ 718 #if EFSYS_OPT_RX_SCALE 719 efx_rx_hash_support_t en_hash_support; 720 efx_rx_scale_context_type_t en_rss_context_type; 721 uint32_t en_rss_context; 722 #endif /* EFSYS_OPT_RX_SCALE */ 723 uint32_t en_vport_id; 724 #if EFSYS_OPT_LICENSING 725 const efx_lic_ops_t *en_elop; 726 boolean_t en_licensing_supported; 727 #endif 728 union { 729 #if EFSYS_OPT_SIENA 730 struct { 731 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 732 unsigned int enu_partn_mask; 733 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 734 #if EFSYS_OPT_VPD 735 caddr_t enu_svpd; 736 size_t enu_svpd_length; 737 #endif /* EFSYS_OPT_VPD */ 738 int enu_unused; 739 } siena; 740 #endif /* EFSYS_OPT_SIENA */ 741 int enu_unused; 742 } en_u; 743 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) 744 union en_arch { 745 struct { 746 int ena_vi_base; 747 int ena_vi_count; 748 int ena_vi_shift; 749 #if EFSYS_OPT_VPD 750 caddr_t ena_svpd; 751 size_t ena_svpd_length; 752 #endif /* EFSYS_OPT_VPD */ 753 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 754 uint32_t ena_piobuf_count; 755 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 756 uint32_t ena_pio_write_vi_base; 757 /* Memory BAR mapping regions */ 758 uint32_t ena_uc_mem_map_offset; 759 size_t ena_uc_mem_map_size; 760 uint32_t ena_wc_mem_map_offset; 761 size_t ena_wc_mem_map_size; 762 } ef10; 763 } en_arch; 764 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ 765 }; 766 767 #define EFX_NIC_MAGIC 0x02121996 768 769 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 770 const efx_ev_callbacks_t *, void *); 771 772 typedef struct efx_evq_rxq_state_s { 773 unsigned int eers_rx_read_ptr; 774 unsigned int eers_rx_mask; 775 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 776 unsigned int eers_rx_stream_npackets; 777 boolean_t eers_rx_packed_stream; 778 #endif 779 #if EFSYS_OPT_RX_PACKED_STREAM 780 unsigned int eers_rx_packed_stream_credits; 781 #endif 782 } efx_evq_rxq_state_t; 783 784 struct efx_evq_s { 785 uint32_t ee_magic; 786 efx_nic_t *ee_enp; 787 unsigned int ee_index; 788 unsigned int ee_mask; 789 efsys_mem_t *ee_esmp; 790 #if EFSYS_OPT_QSTATS 791 uint32_t ee_stat[EV_NQSTATS]; 792 #endif /* EFSYS_OPT_QSTATS */ 793 794 efx_ev_handler_t ee_rx; 795 efx_ev_handler_t ee_tx; 796 efx_ev_handler_t ee_driver; 797 efx_ev_handler_t ee_global; 798 efx_ev_handler_t ee_drv_gen; 799 #if EFSYS_OPT_MCDI 800 efx_ev_handler_t ee_mcdi; 801 #endif /* EFSYS_OPT_MCDI */ 802 803 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 804 805 uint32_t ee_flags; 806 }; 807 808 #define EFX_EVQ_MAGIC 0x08081997 809 810 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 811 812 struct efx_rxq_s { 813 uint32_t er_magic; 814 efx_nic_t *er_enp; 815 efx_evq_t *er_eep; 816 unsigned int er_index; 817 unsigned int er_label; 818 unsigned int er_mask; 819 efsys_mem_t *er_esmp; 820 efx_evq_rxq_state_t *er_ev_qstate; 821 }; 822 823 #define EFX_RXQ_MAGIC 0x15022005 824 825 struct efx_txq_s { 826 uint32_t et_magic; 827 efx_nic_t *et_enp; 828 unsigned int et_index; 829 unsigned int et_mask; 830 efsys_mem_t *et_esmp; 831 #if EFSYS_OPT_HUNTINGTON 832 uint32_t et_pio_bufnum; 833 uint32_t et_pio_blknum; 834 uint32_t et_pio_write_offset; 835 uint32_t et_pio_offset; 836 size_t et_pio_size; 837 #endif 838 #if EFSYS_OPT_QSTATS 839 uint32_t et_stat[TX_NQSTATS]; 840 #endif /* EFSYS_OPT_QSTATS */ 841 }; 842 843 #define EFX_TXQ_MAGIC 0x05092005 844 845 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 846 do { \ 847 (_dst)[0] = (_src)[0]; \ 848 (_dst)[1] = (_src)[1]; \ 849 (_dst)[2] = (_src)[2]; \ 850 (_dst)[3] = (_src)[3]; \ 851 (_dst)[4] = (_src)[4]; \ 852 (_dst)[5] = (_src)[5]; \ 853 _NOTE(CONSTANTCONDITION) \ 854 } while (B_FALSE) 855 856 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 857 do { \ 858 uint16_t *_d = (uint16_t *)(_dst); \ 859 _d[0] = 0xffff; \ 860 _d[1] = 0xffff; \ 861 _d[2] = 0xffff; \ 862 _NOTE(CONSTANTCONDITION) \ 863 } while (B_FALSE) 864 865 #if EFSYS_OPT_CHECK_REG 866 #define EFX_CHECK_REG(_enp, _reg) \ 867 do { \ 868 const char *name = #_reg; \ 869 char min = name[4]; \ 870 char max = name[5]; \ 871 char rev; \ 872 \ 873 switch ((_enp)->en_family) { \ 874 case EFX_FAMILY_SIENA: \ 875 rev = 'C'; \ 876 break; \ 877 \ 878 case EFX_FAMILY_HUNTINGTON: \ 879 rev = 'D'; \ 880 break; \ 881 \ 882 case EFX_FAMILY_MEDFORD: \ 883 rev = 'E'; \ 884 break; \ 885 \ 886 case EFX_FAMILY_MEDFORD2: \ 887 rev = 'F'; \ 888 break; \ 889 \ 890 default: \ 891 rev = '?'; \ 892 break; \ 893 } \ 894 \ 895 EFSYS_ASSERT3S(rev, >=, min); \ 896 EFSYS_ASSERT3S(rev, <=, max); \ 897 \ 898 _NOTE(CONSTANTCONDITION) \ 899 } while (B_FALSE) 900 #else 901 #define EFX_CHECK_REG(_enp, _reg) do { \ 902 _NOTE(CONSTANTCONDITION) \ 903 } while (B_FALSE) 904 #endif 905 906 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 907 do { \ 908 EFX_CHECK_REG((_enp), (_reg)); \ 909 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 910 (_edp), (_lock)); \ 911 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 912 uint32_t, _reg ## _OFST, \ 913 uint32_t, (_edp)->ed_u32[0]); \ 914 _NOTE(CONSTANTCONDITION) \ 915 } while (B_FALSE) 916 917 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 918 do { \ 919 EFX_CHECK_REG((_enp), (_reg)); \ 920 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 921 uint32_t, _reg ## _OFST, \ 922 uint32_t, (_edp)->ed_u32[0]); \ 923 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 924 (_edp), (_lock)); \ 925 _NOTE(CONSTANTCONDITION) \ 926 } while (B_FALSE) 927 928 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 929 do { \ 930 EFX_CHECK_REG((_enp), (_reg)); \ 931 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 932 (_eqp)); \ 933 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 934 uint32_t, _reg ## _OFST, \ 935 uint32_t, (_eqp)->eq_u32[1], \ 936 uint32_t, (_eqp)->eq_u32[0]); \ 937 _NOTE(CONSTANTCONDITION) \ 938 } while (B_FALSE) 939 940 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 941 do { \ 942 EFX_CHECK_REG((_enp), (_reg)); \ 943 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 944 uint32_t, _reg ## _OFST, \ 945 uint32_t, (_eqp)->eq_u32[1], \ 946 uint32_t, (_eqp)->eq_u32[0]); \ 947 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 948 (_eqp)); \ 949 _NOTE(CONSTANTCONDITION) \ 950 } while (B_FALSE) 951 952 #define EFX_BAR_READO(_enp, _reg, _eop) \ 953 do { \ 954 EFX_CHECK_REG((_enp), (_reg)); \ 955 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 956 (_eop), B_TRUE); \ 957 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 958 uint32_t, _reg ## _OFST, \ 959 uint32_t, (_eop)->eo_u32[3], \ 960 uint32_t, (_eop)->eo_u32[2], \ 961 uint32_t, (_eop)->eo_u32[1], \ 962 uint32_t, (_eop)->eo_u32[0]); \ 963 _NOTE(CONSTANTCONDITION) \ 964 } while (B_FALSE) 965 966 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 967 do { \ 968 EFX_CHECK_REG((_enp), (_reg)); \ 969 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 970 uint32_t, _reg ## _OFST, \ 971 uint32_t, (_eop)->eo_u32[3], \ 972 uint32_t, (_eop)->eo_u32[2], \ 973 uint32_t, (_eop)->eo_u32[1], \ 974 uint32_t, (_eop)->eo_u32[0]); \ 975 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 976 (_eop), B_TRUE); \ 977 _NOTE(CONSTANTCONDITION) \ 978 } while (B_FALSE) 979 980 /* 981 * Accessors for memory BAR non-VI tables. 982 * 983 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 984 * to ensure the correct runtime VI window size is used on Medford2. 985 * 986 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 987 */ 988 989 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 990 do { \ 991 EFX_CHECK_REG((_enp), (_reg)); \ 992 EFSYS_BAR_READD((_enp)->en_esbp, \ 993 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 994 (_edp), (_lock)); \ 995 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 996 uint32_t, (_index), \ 997 uint32_t, _reg ## _OFST, \ 998 uint32_t, (_edp)->ed_u32[0]); \ 999 _NOTE(CONSTANTCONDITION) \ 1000 } while (B_FALSE) 1001 1002 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1003 do { \ 1004 EFX_CHECK_REG((_enp), (_reg)); \ 1005 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1006 uint32_t, (_index), \ 1007 uint32_t, _reg ## _OFST, \ 1008 uint32_t, (_edp)->ed_u32[0]); \ 1009 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1010 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1011 (_edp), (_lock)); \ 1012 _NOTE(CONSTANTCONDITION) \ 1013 } while (B_FALSE) 1014 1015 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1016 do { \ 1017 EFX_CHECK_REG((_enp), (_reg)); \ 1018 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1019 uint32_t, (_index), \ 1020 uint32_t, _reg ## _OFST, \ 1021 uint32_t, (_edp)->ed_u32[0]); \ 1022 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1023 (_reg ## _OFST + \ 1024 (3 * sizeof (efx_dword_t)) + \ 1025 ((_index) * _reg ## _STEP)), \ 1026 (_edp), (_lock)); \ 1027 _NOTE(CONSTANTCONDITION) \ 1028 } while (B_FALSE) 1029 1030 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1031 do { \ 1032 EFX_CHECK_REG((_enp), (_reg)); \ 1033 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1034 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1035 (_eqp)); \ 1036 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1037 uint32_t, (_index), \ 1038 uint32_t, _reg ## _OFST, \ 1039 uint32_t, (_eqp)->eq_u32[1], \ 1040 uint32_t, (_eqp)->eq_u32[0]); \ 1041 _NOTE(CONSTANTCONDITION) \ 1042 } while (B_FALSE) 1043 1044 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1045 do { \ 1046 EFX_CHECK_REG((_enp), (_reg)); \ 1047 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1048 uint32_t, (_index), \ 1049 uint32_t, _reg ## _OFST, \ 1050 uint32_t, (_eqp)->eq_u32[1], \ 1051 uint32_t, (_eqp)->eq_u32[0]); \ 1052 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1053 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1054 (_eqp)); \ 1055 _NOTE(CONSTANTCONDITION) \ 1056 } while (B_FALSE) 1057 1058 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1059 do { \ 1060 EFX_CHECK_REG((_enp), (_reg)); \ 1061 EFSYS_BAR_READO((_enp)->en_esbp, \ 1062 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1063 (_eop), (_lock)); \ 1064 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1065 uint32_t, (_index), \ 1066 uint32_t, _reg ## _OFST, \ 1067 uint32_t, (_eop)->eo_u32[3], \ 1068 uint32_t, (_eop)->eo_u32[2], \ 1069 uint32_t, (_eop)->eo_u32[1], \ 1070 uint32_t, (_eop)->eo_u32[0]); \ 1071 _NOTE(CONSTANTCONDITION) \ 1072 } while (B_FALSE) 1073 1074 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1075 do { \ 1076 EFX_CHECK_REG((_enp), (_reg)); \ 1077 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1078 uint32_t, (_index), \ 1079 uint32_t, _reg ## _OFST, \ 1080 uint32_t, (_eop)->eo_u32[3], \ 1081 uint32_t, (_eop)->eo_u32[2], \ 1082 uint32_t, (_eop)->eo_u32[1], \ 1083 uint32_t, (_eop)->eo_u32[0]); \ 1084 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1085 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1086 (_eop), (_lock)); \ 1087 _NOTE(CONSTANTCONDITION) \ 1088 } while (B_FALSE) 1089 1090 /* 1091 * Accessors for memory BAR per-VI registers. 1092 * 1093 * The VI window size is 8KB for Medford and all earlier controllers. 1094 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1095 */ 1096 1097 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1098 do { \ 1099 EFX_CHECK_REG((_enp), (_reg)); \ 1100 EFSYS_BAR_READD((_enp)->en_esbp, \ 1101 ((_reg ## _OFST) + \ 1102 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1103 (_edp), (_lock)); \ 1104 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1105 uint32_t, (_index), \ 1106 uint32_t, _reg ## _OFST, \ 1107 uint32_t, (_edp)->ed_u32[0]); \ 1108 _NOTE(CONSTANTCONDITION) \ 1109 } while (B_FALSE) 1110 1111 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1112 do { \ 1113 EFX_CHECK_REG((_enp), (_reg)); \ 1114 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1115 uint32_t, (_index), \ 1116 uint32_t, _reg ## _OFST, \ 1117 uint32_t, (_edp)->ed_u32[0]); \ 1118 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1119 ((_reg ## _OFST) + \ 1120 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1121 (_edp), (_lock)); \ 1122 _NOTE(CONSTANTCONDITION) \ 1123 } while (B_FALSE) 1124 1125 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1126 do { \ 1127 EFX_CHECK_REG((_enp), (_reg)); \ 1128 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1129 uint32_t, (_index), \ 1130 uint32_t, _reg ## _OFST, \ 1131 uint32_t, (_edp)->ed_u32[0]); \ 1132 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1133 ((_reg ## _OFST) + \ 1134 (2 * sizeof (efx_dword_t)) + \ 1135 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1136 (_edp), (_lock)); \ 1137 _NOTE(CONSTANTCONDITION) \ 1138 } while (B_FALSE) 1139 1140 /* 1141 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1142 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1143 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1144 * the need for locking in the host, and are the only ones known to be safe to 1145 * use 128-bites write with. 1146 */ 1147 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1148 do { \ 1149 EFX_CHECK_REG((_enp), (_reg)); \ 1150 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1151 const char *, #_reg, \ 1152 uint32_t, (_index), \ 1153 uint32_t, _reg ## _OFST, \ 1154 uint32_t, (_eop)->eo_u32[3], \ 1155 uint32_t, (_eop)->eo_u32[2], \ 1156 uint32_t, (_eop)->eo_u32[1], \ 1157 uint32_t, (_eop)->eo_u32[0]); \ 1158 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1159 (_reg ## _OFST + \ 1160 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1161 (_eop)); \ 1162 _NOTE(CONSTANTCONDITION) \ 1163 } while (B_FALSE) 1164 1165 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1166 do { \ 1167 unsigned int _new = (_wptr); \ 1168 unsigned int _old = (_owptr); \ 1169 \ 1170 if ((_new) >= (_old)) \ 1171 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1172 (_old) * sizeof (efx_desc_t), \ 1173 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1174 else \ 1175 /* \ 1176 * It is cheaper to sync entire map than sync \ 1177 * two parts especially when offset/size are \ 1178 * ignored and entire map is synced in any case.\ 1179 */ \ 1180 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1181 0, \ 1182 (_entries) * sizeof (efx_desc_t)); \ 1183 _NOTE(CONSTANTCONDITION) \ 1184 } while (B_FALSE) 1185 1186 extern __checkReturn efx_rc_t 1187 efx_mac_select( 1188 __in efx_nic_t *enp); 1189 1190 extern void 1191 efx_mac_multicast_hash_compute( 1192 __in_ecount(6*count) uint8_t const *addrs, 1193 __in int count, 1194 __out efx_oword_t *hash_low, 1195 __out efx_oword_t *hash_high); 1196 1197 extern __checkReturn efx_rc_t 1198 efx_phy_probe( 1199 __in efx_nic_t *enp); 1200 1201 extern void 1202 efx_phy_unprobe( 1203 __in efx_nic_t *enp); 1204 1205 #if EFSYS_OPT_VPD 1206 1207 /* VPD utility functions */ 1208 1209 extern __checkReturn efx_rc_t 1210 efx_vpd_hunk_length( 1211 __in_bcount(size) caddr_t data, 1212 __in size_t size, 1213 __out size_t *lengthp); 1214 1215 extern __checkReturn efx_rc_t 1216 efx_vpd_hunk_verify( 1217 __in_bcount(size) caddr_t data, 1218 __in size_t size, 1219 __out_opt boolean_t *cksummedp); 1220 1221 extern __checkReturn efx_rc_t 1222 efx_vpd_hunk_reinit( 1223 __in_bcount(size) caddr_t data, 1224 __in size_t size, 1225 __in boolean_t wantpid); 1226 1227 extern __checkReturn efx_rc_t 1228 efx_vpd_hunk_get( 1229 __in_bcount(size) caddr_t data, 1230 __in size_t size, 1231 __in efx_vpd_tag_t tag, 1232 __in efx_vpd_keyword_t keyword, 1233 __out unsigned int *payloadp, 1234 __out uint8_t *paylenp); 1235 1236 extern __checkReturn efx_rc_t 1237 efx_vpd_hunk_next( 1238 __in_bcount(size) caddr_t data, 1239 __in size_t size, 1240 __out efx_vpd_tag_t *tagp, 1241 __out efx_vpd_keyword_t *keyword, 1242 __out_opt unsigned int *payloadp, 1243 __out_opt uint8_t *paylenp, 1244 __inout unsigned int *contp); 1245 1246 extern __checkReturn efx_rc_t 1247 efx_vpd_hunk_set( 1248 __in_bcount(size) caddr_t data, 1249 __in size_t size, 1250 __in efx_vpd_value_t *evvp); 1251 1252 #endif /* EFSYS_OPT_VPD */ 1253 1254 #if EFSYS_OPT_MCDI 1255 1256 extern __checkReturn efx_rc_t 1257 efx_mcdi_set_workaround( 1258 __in efx_nic_t *enp, 1259 __in uint32_t type, 1260 __in boolean_t enabled, 1261 __out_opt uint32_t *flagsp); 1262 1263 extern __checkReturn efx_rc_t 1264 efx_mcdi_get_workarounds( 1265 __in efx_nic_t *enp, 1266 __out_opt uint32_t *implementedp, 1267 __out_opt uint32_t *enabledp); 1268 1269 #endif /* EFSYS_OPT_MCDI */ 1270 1271 #if EFSYS_OPT_MAC_STATS 1272 1273 /* 1274 * Closed range of stats (i.e. the first and the last are included). 1275 * The last must be greater or equal (if the range is one item only) to 1276 * the first. 1277 */ 1278 struct efx_mac_stats_range { 1279 efx_mac_stat_t first; 1280 efx_mac_stat_t last; 1281 }; 1282 1283 extern efx_rc_t 1284 efx_mac_stats_mask_add_ranges( 1285 __inout_bcount(mask_size) uint32_t *maskp, 1286 __in size_t mask_size, 1287 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1288 __in unsigned int rng_count); 1289 1290 #endif /* EFSYS_OPT_MAC_STATS */ 1291 1292 #ifdef __cplusplus 1293 } 1294 #endif 1295 1296 #endif /* _SYS_EFX_IMPL_H */ 1297