1 /*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EFX_IMPL_H 34 #define _SYS_EFX_IMPL_H 35 36 #include "efx.h" 37 #include "efx_regs.h" 38 #include "efx_regs_ef10.h" 39 40 /* FIXME: Add definition for driver generated software events */ 41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 43 #endif 44 45 46 #if EFSYS_OPT_SIENA 47 #include "siena_impl.h" 48 #endif /* EFSYS_OPT_SIENA */ 49 50 #if EFSYS_OPT_HUNTINGTON 51 #include "hunt_impl.h" 52 #endif /* EFSYS_OPT_HUNTINGTON */ 53 54 #if EFSYS_OPT_MEDFORD 55 #include "medford_impl.h" 56 #endif /* EFSYS_OPT_MEDFORD */ 57 58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 59 #include "ef10_impl.h" 60 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 61 62 #ifdef __cplusplus 63 extern "C" { 64 #endif 65 66 #define EFX_MOD_MCDI 0x00000001 67 #define EFX_MOD_PROBE 0x00000002 68 #define EFX_MOD_NVRAM 0x00000004 69 #define EFX_MOD_VPD 0x00000008 70 #define EFX_MOD_NIC 0x00000010 71 #define EFX_MOD_INTR 0x00000020 72 #define EFX_MOD_EV 0x00000040 73 #define EFX_MOD_RX 0x00000080 74 #define EFX_MOD_TX 0x00000100 75 #define EFX_MOD_PORT 0x00000200 76 #define EFX_MOD_MON 0x00000400 77 #define EFX_MOD_WOL 0x00000800 78 #define EFX_MOD_FILTER 0x00001000 79 #define EFX_MOD_LIC 0x00002000 80 81 #define EFX_RESET_PHY 0x00000001 82 #define EFX_RESET_RXQ_ERR 0x00000002 83 #define EFX_RESET_TXQ_ERR 0x00000004 84 85 typedef enum efx_mac_type_e { 86 EFX_MAC_INVALID = 0, 87 EFX_MAC_SIENA, 88 EFX_MAC_HUNTINGTON, 89 EFX_MAC_MEDFORD, 90 EFX_MAC_NTYPES 91 } efx_mac_type_t; 92 93 typedef struct efx_ev_ops_s { 94 efx_rc_t (*eevo_init)(efx_nic_t *); 95 void (*eevo_fini)(efx_nic_t *); 96 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 97 efsys_mem_t *, size_t, uint32_t, 98 efx_evq_t *); 99 void (*eevo_qdestroy)(efx_evq_t *); 100 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 101 void (*eevo_qpost)(efx_evq_t *, uint16_t); 102 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 103 #if EFSYS_OPT_QSTATS 104 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 105 #endif 106 } efx_ev_ops_t; 107 108 typedef struct efx_tx_ops_s { 109 efx_rc_t (*etxo_init)(efx_nic_t *); 110 void (*etxo_fini)(efx_nic_t *); 111 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 112 unsigned int, unsigned int, 113 efsys_mem_t *, size_t, 114 uint32_t, uint16_t, 115 efx_evq_t *, efx_txq_t *, 116 unsigned int *); 117 void (*etxo_qdestroy)(efx_txq_t *); 118 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 119 unsigned int, unsigned int, 120 unsigned int *); 121 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 122 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 123 efx_rc_t (*etxo_qflush)(efx_txq_t *); 124 void (*etxo_qenable)(efx_txq_t *); 125 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 126 void (*etxo_qpio_disable)(efx_txq_t *); 127 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, 128 size_t); 129 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 130 unsigned int *); 131 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 132 unsigned int, unsigned int, 133 unsigned int *); 134 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 135 size_t, boolean_t, 136 efx_desc_t *); 137 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 138 uint32_t, uint8_t, 139 efx_desc_t *); 140 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 141 uint32_t, uint16_t, 142 efx_desc_t *, int); 143 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 144 efx_desc_t *); 145 #if EFSYS_OPT_QSTATS 146 void (*etxo_qstats_update)(efx_txq_t *, 147 efsys_stat_t *); 148 #endif 149 } efx_tx_ops_t; 150 151 typedef struct efx_rx_ops_s { 152 efx_rc_t (*erxo_init)(efx_nic_t *); 153 void (*erxo_fini)(efx_nic_t *); 154 #if EFSYS_OPT_RX_SCATTER 155 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 156 #endif 157 #if EFSYS_OPT_RX_SCALE 158 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, 159 efx_rx_hash_type_t, boolean_t); 160 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); 161 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, 162 size_t); 163 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 164 uint8_t *); 165 #endif /* EFSYS_OPT_RX_SCALE */ 166 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 167 uint16_t *); 168 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 169 unsigned int, unsigned int, 170 unsigned int); 171 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 172 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 173 void (*erxo_qenable)(efx_rxq_t *); 174 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 175 unsigned int, efx_rxq_type_t, 176 efsys_mem_t *, size_t, uint32_t, 177 efx_evq_t *, efx_rxq_t *); 178 void (*erxo_qdestroy)(efx_rxq_t *); 179 } efx_rx_ops_t; 180 181 typedef struct efx_mac_ops_s { 182 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 183 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 184 efx_rc_t (*emo_addr_set)(efx_nic_t *); 185 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 186 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 187 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 188 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 189 efx_rxq_t *, boolean_t); 190 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 191 #if EFSYS_OPT_LOOPBACK 192 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 193 efx_loopback_type_t); 194 #endif /* EFSYS_OPT_LOOPBACK */ 195 #if EFSYS_OPT_MAC_STATS 196 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 197 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 198 uint16_t, boolean_t); 199 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 200 efsys_stat_t *, uint32_t *); 201 #endif /* EFSYS_OPT_MAC_STATS */ 202 } efx_mac_ops_t; 203 204 typedef struct efx_phy_ops_s { 205 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 206 efx_rc_t (*epo_reset)(efx_nic_t *); 207 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 208 efx_rc_t (*epo_verify)(efx_nic_t *); 209 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 210 #if EFSYS_OPT_PHY_STATS 211 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 212 uint32_t *); 213 #endif /* EFSYS_OPT_PHY_STATS */ 214 #if EFSYS_OPT_BIST 215 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 216 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 217 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 218 efx_bist_result_t *, uint32_t *, 219 unsigned long *, size_t); 220 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 221 #endif /* EFSYS_OPT_BIST */ 222 } efx_phy_ops_t; 223 224 #if EFSYS_OPT_FILTER 225 typedef struct efx_filter_ops_s { 226 efx_rc_t (*efo_init)(efx_nic_t *); 227 void (*efo_fini)(efx_nic_t *); 228 efx_rc_t (*efo_restore)(efx_nic_t *); 229 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 230 boolean_t may_replace); 231 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 232 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); 233 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 234 boolean_t, boolean_t, boolean_t, 235 uint8_t const *, uint32_t); 236 } efx_filter_ops_t; 237 238 extern __checkReturn efx_rc_t 239 efx_filter_reconfigure( 240 __in efx_nic_t *enp, 241 __in_ecount(6) uint8_t const *mac_addr, 242 __in boolean_t all_unicst, 243 __in boolean_t mulcst, 244 __in boolean_t all_mulcst, 245 __in boolean_t brdcst, 246 __in_ecount(6*count) uint8_t const *addrs, 247 __in uint32_t count); 248 249 #endif /* EFSYS_OPT_FILTER */ 250 251 252 typedef struct efx_port_s { 253 efx_mac_type_t ep_mac_type; 254 uint32_t ep_phy_type; 255 uint8_t ep_port; 256 uint32_t ep_mac_pdu; 257 uint8_t ep_mac_addr[6]; 258 efx_link_mode_t ep_link_mode; 259 boolean_t ep_all_unicst; 260 boolean_t ep_mulcst; 261 boolean_t ep_all_mulcst; 262 boolean_t ep_brdcst; 263 unsigned int ep_fcntl; 264 boolean_t ep_fcntl_autoneg; 265 efx_oword_t ep_multicst_hash[2]; 266 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 267 EFX_MAC_MULTICAST_LIST_MAX]; 268 uint32_t ep_mulcst_addr_count; 269 #if EFSYS_OPT_LOOPBACK 270 efx_loopback_type_t ep_loopback_type; 271 efx_link_mode_t ep_loopback_link_mode; 272 #endif /* EFSYS_OPT_LOOPBACK */ 273 #if EFSYS_OPT_PHY_FLAGS 274 uint32_t ep_phy_flags; 275 #endif /* EFSYS_OPT_PHY_FLAGS */ 276 #if EFSYS_OPT_PHY_LED_CONTROL 277 efx_phy_led_mode_t ep_phy_led_mode; 278 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 279 efx_phy_media_type_t ep_fixed_port_type; 280 efx_phy_media_type_t ep_module_type; 281 uint32_t ep_adv_cap_mask; 282 uint32_t ep_lp_cap_mask; 283 uint32_t ep_default_adv_cap_mask; 284 uint32_t ep_phy_cap_mask; 285 boolean_t ep_mac_drain; 286 boolean_t ep_mac_stats_pending; 287 #if EFSYS_OPT_BIST 288 efx_bist_type_t ep_current_bist; 289 #endif 290 const efx_mac_ops_t *ep_emop; 291 const efx_phy_ops_t *ep_epop; 292 } efx_port_t; 293 294 typedef struct efx_mon_ops_s { 295 #if EFSYS_OPT_MON_STATS 296 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 297 efx_mon_stat_value_t *); 298 #endif /* EFSYS_OPT_MON_STATS */ 299 } efx_mon_ops_t; 300 301 typedef struct efx_mon_s { 302 efx_mon_type_t em_type; 303 const efx_mon_ops_t *em_emop; 304 } efx_mon_t; 305 306 typedef struct efx_intr_ops_s { 307 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 308 void (*eio_enable)(efx_nic_t *); 309 void (*eio_disable)(efx_nic_t *); 310 void (*eio_disable_unlocked)(efx_nic_t *); 311 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 312 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 313 void (*eio_status_message)(efx_nic_t *, unsigned int, 314 boolean_t *); 315 void (*eio_fatal)(efx_nic_t *); 316 void (*eio_fini)(efx_nic_t *); 317 } efx_intr_ops_t; 318 319 typedef struct efx_intr_s { 320 const efx_intr_ops_t *ei_eiop; 321 efsys_mem_t *ei_esmp; 322 efx_intr_type_t ei_type; 323 unsigned int ei_level; 324 } efx_intr_t; 325 326 typedef struct efx_nic_ops_s { 327 efx_rc_t (*eno_probe)(efx_nic_t *); 328 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 329 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 330 efx_rc_t (*eno_reset)(efx_nic_t *); 331 efx_rc_t (*eno_init)(efx_nic_t *); 332 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 333 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 334 uint32_t *, size_t *); 335 #if EFSYS_OPT_DIAG 336 efx_rc_t (*eno_register_test)(efx_nic_t *); 337 #endif /* EFSYS_OPT_DIAG */ 338 void (*eno_fini)(efx_nic_t *); 339 void (*eno_unprobe)(efx_nic_t *); 340 } efx_nic_ops_t; 341 342 #ifndef EFX_TXQ_LIMIT_TARGET 343 #define EFX_TXQ_LIMIT_TARGET 259 344 #endif 345 #ifndef EFX_RXQ_LIMIT_TARGET 346 #define EFX_RXQ_LIMIT_TARGET 512 347 #endif 348 #ifndef EFX_TXQ_DC_SIZE 349 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 350 #endif 351 #ifndef EFX_RXQ_DC_SIZE 352 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 353 #endif 354 355 #if EFSYS_OPT_FILTER 356 357 typedef struct siena_filter_spec_s { 358 uint8_t sfs_type; 359 uint32_t sfs_flags; 360 uint32_t sfs_dmaq_id; 361 uint32_t sfs_dword[3]; 362 } siena_filter_spec_t; 363 364 typedef enum siena_filter_type_e { 365 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 366 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 367 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 368 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 369 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 370 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 371 372 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 373 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 374 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 375 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 376 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 377 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 378 379 EFX_SIENA_FILTER_NTYPES 380 } siena_filter_type_t; 381 382 typedef enum siena_filter_tbl_id_e { 383 EFX_SIENA_FILTER_TBL_RX_IP = 0, 384 EFX_SIENA_FILTER_TBL_RX_MAC, 385 EFX_SIENA_FILTER_TBL_TX_IP, 386 EFX_SIENA_FILTER_TBL_TX_MAC, 387 EFX_SIENA_FILTER_NTBLS 388 } siena_filter_tbl_id_t; 389 390 typedef struct siena_filter_tbl_s { 391 int sft_size; /* number of entries */ 392 int sft_used; /* active count */ 393 uint32_t *sft_bitmap; /* active bitmap */ 394 siena_filter_spec_t *sft_spec; /* array of saved specs */ 395 } siena_filter_tbl_t; 396 397 typedef struct siena_filter_s { 398 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 399 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 400 } siena_filter_t; 401 402 typedef struct efx_filter_s { 403 #if EFSYS_OPT_SIENA 404 siena_filter_t *ef_siena_filter; 405 #endif /* EFSYS_OPT_SIENA */ 406 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 407 ef10_filter_table_t *ef_ef10_filter_table; 408 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 409 } efx_filter_t; 410 411 extern void 412 siena_filter_tbl_clear( 413 __in efx_nic_t *enp, 414 __in siena_filter_tbl_id_t tbl); 415 416 #endif /* EFSYS_OPT_FILTER */ 417 418 #if EFSYS_OPT_MCDI 419 420 typedef struct efx_mcdi_ops_s { 421 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 422 void (*emco_send_request)(efx_nic_t *, void *, size_t, 423 void *, size_t); 424 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 425 boolean_t (*emco_poll_response)(efx_nic_t *); 426 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 427 void (*emco_fini)(efx_nic_t *); 428 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *); 429 } efx_mcdi_ops_t; 430 431 typedef struct efx_mcdi_s { 432 const efx_mcdi_ops_t *em_emcop; 433 const efx_mcdi_transport_t *em_emtp; 434 efx_mcdi_iface_t em_emip; 435 } efx_mcdi_t; 436 437 #endif /* EFSYS_OPT_MCDI */ 438 439 #if EFSYS_OPT_NVRAM 440 typedef struct efx_nvram_ops_s { 441 #if EFSYS_OPT_DIAG 442 efx_rc_t (*envo_test)(efx_nic_t *); 443 #endif /* EFSYS_OPT_DIAG */ 444 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 445 uint32_t *); 446 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 447 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 448 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 449 unsigned int, caddr_t, size_t); 450 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 451 unsigned int, size_t); 452 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 453 unsigned int, caddr_t, size_t); 454 void (*envo_partn_rw_finish)(efx_nic_t *, uint32_t); 455 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 456 uint32_t *, uint16_t *); 457 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 458 uint16_t *); 459 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t, 460 caddr_t, size_t); 461 } efx_nvram_ops_t; 462 #endif /* EFSYS_OPT_NVRAM */ 463 464 extern __checkReturn efx_rc_t 465 efx_nvram_tlv_validate( 466 __in efx_nic_t *enp, 467 __in uint32_t partn, 468 __in_bcount(partn_size) caddr_t partn_data, 469 __in size_t partn_size); 470 471 472 #if EFSYS_OPT_VPD 473 typedef struct efx_vpd_ops_s { 474 efx_rc_t (*evpdo_init)(efx_nic_t *); 475 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 476 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 477 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 478 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 479 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 480 efx_vpd_value_t *); 481 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 482 efx_vpd_value_t *); 483 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 484 efx_vpd_value_t *, unsigned int *); 485 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 486 void (*evpdo_fini)(efx_nic_t *); 487 } efx_vpd_ops_t; 488 #endif /* EFSYS_OPT_VPD */ 489 490 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 491 492 __checkReturn efx_rc_t 493 efx_mcdi_nvram_partitions( 494 __in efx_nic_t *enp, 495 __out_bcount(size) caddr_t data, 496 __in size_t size, 497 __out unsigned int *npartnp); 498 499 __checkReturn efx_rc_t 500 efx_mcdi_nvram_metadata( 501 __in efx_nic_t *enp, 502 __in uint32_t partn, 503 __out uint32_t *subtypep, 504 __out_ecount(4) uint16_t version[4], 505 __out_bcount_opt(size) char *descp, 506 __in size_t size); 507 508 __checkReturn efx_rc_t 509 efx_mcdi_nvram_info( 510 __in efx_nic_t *enp, 511 __in uint32_t partn, 512 __out_opt size_t *sizep, 513 __out_opt uint32_t *addressp, 514 __out_opt uint32_t *erase_sizep, 515 __out_opt uint32_t *write_sizep); 516 517 __checkReturn efx_rc_t 518 efx_mcdi_nvram_update_start( 519 __in efx_nic_t *enp, 520 __in uint32_t partn); 521 522 __checkReturn efx_rc_t 523 efx_mcdi_nvram_read( 524 __in efx_nic_t *enp, 525 __in uint32_t partn, 526 __in uint32_t offset, 527 __out_bcount(size) caddr_t data, 528 __in size_t size, 529 __in uint32_t mode); 530 531 __checkReturn efx_rc_t 532 efx_mcdi_nvram_erase( 533 __in efx_nic_t *enp, 534 __in uint32_t partn, 535 __in uint32_t offset, 536 __in size_t size); 537 538 __checkReturn efx_rc_t 539 efx_mcdi_nvram_write( 540 __in efx_nic_t *enp, 541 __in uint32_t partn, 542 __in uint32_t offset, 543 __out_bcount(size) caddr_t data, 544 __in size_t size); 545 546 __checkReturn efx_rc_t 547 efx_mcdi_nvram_update_finish( 548 __in efx_nic_t *enp, 549 __in uint32_t partn, 550 __in boolean_t reboot); 551 552 #if EFSYS_OPT_DIAG 553 554 __checkReturn efx_rc_t 555 efx_mcdi_nvram_test( 556 __in efx_nic_t *enp, 557 __in uint32_t partn); 558 559 #endif /* EFSYS_OPT_DIAG */ 560 561 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 562 563 #if EFSYS_OPT_LICENSING 564 565 typedef struct efx_lic_ops_s { 566 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 567 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 568 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 569 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 570 size_t *, uint8_t *); 571 } efx_lic_ops_t; 572 573 #endif 574 575 typedef struct efx_drv_cfg_s { 576 uint32_t edc_min_vi_count; 577 uint32_t edc_max_vi_count; 578 579 uint32_t edc_max_piobuf_count; 580 uint32_t edc_pio_alloc_size; 581 } efx_drv_cfg_t; 582 583 struct efx_nic_s { 584 uint32_t en_magic; 585 efx_family_t en_family; 586 uint32_t en_features; 587 efsys_identifier_t *en_esip; 588 efsys_lock_t *en_eslp; 589 efsys_bar_t *en_esbp; 590 unsigned int en_mod_flags; 591 unsigned int en_reset_flags; 592 efx_nic_cfg_t en_nic_cfg; 593 efx_drv_cfg_t en_drv_cfg; 594 efx_port_t en_port; 595 efx_mon_t en_mon; 596 efx_intr_t en_intr; 597 uint32_t en_ev_qcount; 598 uint32_t en_rx_qcount; 599 uint32_t en_tx_qcount; 600 const efx_nic_ops_t *en_enop; 601 const efx_ev_ops_t *en_eevop; 602 const efx_tx_ops_t *en_etxop; 603 const efx_rx_ops_t *en_erxop; 604 #if EFSYS_OPT_FILTER 605 efx_filter_t en_filter; 606 const efx_filter_ops_t *en_efop; 607 #endif /* EFSYS_OPT_FILTER */ 608 #if EFSYS_OPT_MCDI 609 efx_mcdi_t en_mcdi; 610 #endif /* EFSYS_OPT_MCDI */ 611 #if EFSYS_OPT_NVRAM 612 efx_nvram_type_t en_nvram_locked; 613 const efx_nvram_ops_t *en_envop; 614 #endif /* EFSYS_OPT_NVRAM */ 615 #if EFSYS_OPT_VPD 616 const efx_vpd_ops_t *en_evpdop; 617 #endif /* EFSYS_OPT_VPD */ 618 #if EFSYS_OPT_RX_SCALE 619 efx_rx_hash_support_t en_hash_support; 620 efx_rx_scale_support_t en_rss_support; 621 uint32_t en_rss_context; 622 #endif /* EFSYS_OPT_RX_SCALE */ 623 uint32_t en_vport_id; 624 #if EFSYS_OPT_LICENSING 625 const efx_lic_ops_t *en_elop; 626 #endif 627 union { 628 #if EFSYS_OPT_SIENA 629 struct { 630 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 631 unsigned int enu_partn_mask; 632 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 633 #if EFSYS_OPT_VPD 634 caddr_t enu_svpd; 635 size_t enu_svpd_length; 636 #endif /* EFSYS_OPT_VPD */ 637 int enu_unused; 638 } siena; 639 #endif /* EFSYS_OPT_SIENA */ 640 int enu_unused; 641 } en_u; 642 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 643 union en_arch { 644 struct { 645 int ena_vi_base; 646 int ena_vi_count; 647 int ena_vi_shift; 648 #if EFSYS_OPT_VPD 649 caddr_t ena_svpd; 650 size_t ena_svpd_length; 651 #endif /* EFSYS_OPT_VPD */ 652 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 653 uint32_t ena_piobuf_count; 654 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 655 uint32_t ena_pio_write_vi_base; 656 /* Memory BAR mapping regions */ 657 uint32_t ena_uc_mem_map_offset; 658 size_t ena_uc_mem_map_size; 659 uint32_t ena_wc_mem_map_offset; 660 size_t ena_wc_mem_map_size; 661 } ef10; 662 } en_arch; 663 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 664 }; 665 666 667 #define EFX_NIC_MAGIC 0x02121996 668 669 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 670 const efx_ev_callbacks_t *, void *); 671 672 typedef struct efx_evq_rxq_state_s { 673 unsigned int eers_rx_read_ptr; 674 unsigned int eers_rx_mask; 675 } efx_evq_rxq_state_t; 676 677 struct efx_evq_s { 678 uint32_t ee_magic; 679 efx_nic_t *ee_enp; 680 unsigned int ee_index; 681 unsigned int ee_mask; 682 efsys_mem_t *ee_esmp; 683 #if EFSYS_OPT_QSTATS 684 uint32_t ee_stat[EV_NQSTATS]; 685 #endif /* EFSYS_OPT_QSTATS */ 686 687 efx_ev_handler_t ee_rx; 688 efx_ev_handler_t ee_tx; 689 efx_ev_handler_t ee_driver; 690 efx_ev_handler_t ee_global; 691 efx_ev_handler_t ee_drv_gen; 692 #if EFSYS_OPT_MCDI 693 efx_ev_handler_t ee_mcdi; 694 #endif /* EFSYS_OPT_MCDI */ 695 696 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 697 }; 698 699 #define EFX_EVQ_MAGIC 0x08081997 700 701 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 702 703 struct efx_rxq_s { 704 uint32_t er_magic; 705 efx_nic_t *er_enp; 706 efx_evq_t *er_eep; 707 unsigned int er_index; 708 unsigned int er_label; 709 unsigned int er_mask; 710 efsys_mem_t *er_esmp; 711 }; 712 713 #define EFX_RXQ_MAGIC 0x15022005 714 715 struct efx_txq_s { 716 uint32_t et_magic; 717 efx_nic_t *et_enp; 718 unsigned int et_index; 719 unsigned int et_mask; 720 efsys_mem_t *et_esmp; 721 #if EFSYS_OPT_HUNTINGTON 722 uint32_t et_pio_bufnum; 723 uint32_t et_pio_blknum; 724 uint32_t et_pio_write_offset; 725 uint32_t et_pio_offset; 726 size_t et_pio_size; 727 #endif 728 #if EFSYS_OPT_QSTATS 729 uint32_t et_stat[TX_NQSTATS]; 730 #endif /* EFSYS_OPT_QSTATS */ 731 }; 732 733 #define EFX_TXQ_MAGIC 0x05092005 734 735 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 736 do { \ 737 (_dst)[0] = (_src)[0]; \ 738 (_dst)[1] = (_src)[1]; \ 739 (_dst)[2] = (_src)[2]; \ 740 (_dst)[3] = (_src)[3]; \ 741 (_dst)[4] = (_src)[4]; \ 742 (_dst)[5] = (_src)[5]; \ 743 _NOTE(CONSTANTCONDITION) \ 744 } while (B_FALSE) 745 746 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 747 do { \ 748 uint16_t *_d = (uint16_t *)(_dst); \ 749 _d[0] = 0xffff; \ 750 _d[1] = 0xffff; \ 751 _d[2] = 0xffff; \ 752 _NOTE(CONSTANTCONDITION) \ 753 } while (B_FALSE) 754 755 #if EFSYS_OPT_CHECK_REG 756 #define EFX_CHECK_REG(_enp, _reg) \ 757 do { \ 758 const char *name = #_reg; \ 759 char min = name[4]; \ 760 char max = name[5]; \ 761 char rev; \ 762 \ 763 switch ((_enp)->en_family) { \ 764 case EFX_FAMILY_SIENA: \ 765 rev = 'C'; \ 766 break; \ 767 \ 768 case EFX_FAMILY_HUNTINGTON: \ 769 rev = 'D'; \ 770 break; \ 771 \ 772 case EFX_FAMILY_MEDFORD: \ 773 rev = 'E'; \ 774 break; \ 775 \ 776 default: \ 777 rev = '?'; \ 778 break; \ 779 } \ 780 \ 781 EFSYS_ASSERT3S(rev, >=, min); \ 782 EFSYS_ASSERT3S(rev, <=, max); \ 783 \ 784 _NOTE(CONSTANTCONDITION) \ 785 } while (B_FALSE) 786 #else 787 #define EFX_CHECK_REG(_enp, _reg) do { \ 788 _NOTE(CONSTANTCONDITION) \ 789 } while(B_FALSE) 790 #endif 791 792 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 793 do { \ 794 EFX_CHECK_REG((_enp), (_reg)); \ 795 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 796 (_edp), (_lock)); \ 797 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 798 uint32_t, _reg ## _OFST, \ 799 uint32_t, (_edp)->ed_u32[0]); \ 800 _NOTE(CONSTANTCONDITION) \ 801 } while (B_FALSE) 802 803 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 804 do { \ 805 EFX_CHECK_REG((_enp), (_reg)); \ 806 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 807 uint32_t, _reg ## _OFST, \ 808 uint32_t, (_edp)->ed_u32[0]); \ 809 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 810 (_edp), (_lock)); \ 811 _NOTE(CONSTANTCONDITION) \ 812 } while (B_FALSE) 813 814 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 815 do { \ 816 EFX_CHECK_REG((_enp), (_reg)); \ 817 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 818 (_eqp)); \ 819 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 820 uint32_t, _reg ## _OFST, \ 821 uint32_t, (_eqp)->eq_u32[1], \ 822 uint32_t, (_eqp)->eq_u32[0]); \ 823 _NOTE(CONSTANTCONDITION) \ 824 } while (B_FALSE) 825 826 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 827 do { \ 828 EFX_CHECK_REG((_enp), (_reg)); \ 829 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 830 uint32_t, _reg ## _OFST, \ 831 uint32_t, (_eqp)->eq_u32[1], \ 832 uint32_t, (_eqp)->eq_u32[0]); \ 833 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 834 (_eqp)); \ 835 _NOTE(CONSTANTCONDITION) \ 836 } while (B_FALSE) 837 838 #define EFX_BAR_READO(_enp, _reg, _eop) \ 839 do { \ 840 EFX_CHECK_REG((_enp), (_reg)); \ 841 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 842 (_eop), B_TRUE); \ 843 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 844 uint32_t, _reg ## _OFST, \ 845 uint32_t, (_eop)->eo_u32[3], \ 846 uint32_t, (_eop)->eo_u32[2], \ 847 uint32_t, (_eop)->eo_u32[1], \ 848 uint32_t, (_eop)->eo_u32[0]); \ 849 _NOTE(CONSTANTCONDITION) \ 850 } while (B_FALSE) 851 852 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 853 do { \ 854 EFX_CHECK_REG((_enp), (_reg)); \ 855 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 856 uint32_t, _reg ## _OFST, \ 857 uint32_t, (_eop)->eo_u32[3], \ 858 uint32_t, (_eop)->eo_u32[2], \ 859 uint32_t, (_eop)->eo_u32[1], \ 860 uint32_t, (_eop)->eo_u32[0]); \ 861 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 862 (_eop), B_TRUE); \ 863 _NOTE(CONSTANTCONDITION) \ 864 } while (B_FALSE) 865 866 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 867 do { \ 868 EFX_CHECK_REG((_enp), (_reg)); \ 869 EFSYS_BAR_READD((_enp)->en_esbp, \ 870 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 871 (_edp), (_lock)); \ 872 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 873 uint32_t, (_index), \ 874 uint32_t, _reg ## _OFST, \ 875 uint32_t, (_edp)->ed_u32[0]); \ 876 _NOTE(CONSTANTCONDITION) \ 877 } while (B_FALSE) 878 879 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 880 do { \ 881 EFX_CHECK_REG((_enp), (_reg)); \ 882 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 883 uint32_t, (_index), \ 884 uint32_t, _reg ## _OFST, \ 885 uint32_t, (_edp)->ed_u32[0]); \ 886 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 887 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 888 (_edp), (_lock)); \ 889 _NOTE(CONSTANTCONDITION) \ 890 } while (B_FALSE) 891 892 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 893 do { \ 894 EFX_CHECK_REG((_enp), (_reg)); \ 895 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 896 uint32_t, (_index), \ 897 uint32_t, _reg ## _OFST, \ 898 uint32_t, (_edp)->ed_u32[0]); \ 899 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 900 (_reg ## _OFST + \ 901 (2 * sizeof (efx_dword_t)) + \ 902 ((_index) * _reg ## _STEP)), \ 903 (_edp), (_lock)); \ 904 _NOTE(CONSTANTCONDITION) \ 905 } while (B_FALSE) 906 907 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 908 do { \ 909 EFX_CHECK_REG((_enp), (_reg)); \ 910 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 911 uint32_t, (_index), \ 912 uint32_t, _reg ## _OFST, \ 913 uint32_t, (_edp)->ed_u32[0]); \ 914 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 915 (_reg ## _OFST + \ 916 (3 * sizeof (efx_dword_t)) + \ 917 ((_index) * _reg ## _STEP)), \ 918 (_edp), (_lock)); \ 919 _NOTE(CONSTANTCONDITION) \ 920 } while (B_FALSE) 921 922 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 923 do { \ 924 EFX_CHECK_REG((_enp), (_reg)); \ 925 EFSYS_BAR_READQ((_enp)->en_esbp, \ 926 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 927 (_eqp)); \ 928 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 929 uint32_t, (_index), \ 930 uint32_t, _reg ## _OFST, \ 931 uint32_t, (_eqp)->eq_u32[1], \ 932 uint32_t, (_eqp)->eq_u32[0]); \ 933 _NOTE(CONSTANTCONDITION) \ 934 } while (B_FALSE) 935 936 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 937 do { \ 938 EFX_CHECK_REG((_enp), (_reg)); \ 939 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 940 uint32_t, (_index), \ 941 uint32_t, _reg ## _OFST, \ 942 uint32_t, (_eqp)->eq_u32[1], \ 943 uint32_t, (_eqp)->eq_u32[0]); \ 944 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 945 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 946 (_eqp)); \ 947 _NOTE(CONSTANTCONDITION) \ 948 } while (B_FALSE) 949 950 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 951 do { \ 952 EFX_CHECK_REG((_enp), (_reg)); \ 953 EFSYS_BAR_READO((_enp)->en_esbp, \ 954 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 955 (_eop), (_lock)); \ 956 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 957 uint32_t, (_index), \ 958 uint32_t, _reg ## _OFST, \ 959 uint32_t, (_eop)->eo_u32[3], \ 960 uint32_t, (_eop)->eo_u32[2], \ 961 uint32_t, (_eop)->eo_u32[1], \ 962 uint32_t, (_eop)->eo_u32[0]); \ 963 _NOTE(CONSTANTCONDITION) \ 964 } while (B_FALSE) 965 966 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 967 do { \ 968 EFX_CHECK_REG((_enp), (_reg)); \ 969 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 970 uint32_t, (_index), \ 971 uint32_t, _reg ## _OFST, \ 972 uint32_t, (_eop)->eo_u32[3], \ 973 uint32_t, (_eop)->eo_u32[2], \ 974 uint32_t, (_eop)->eo_u32[1], \ 975 uint32_t, (_eop)->eo_u32[0]); \ 976 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 977 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 978 (_eop), (_lock)); \ 979 _NOTE(CONSTANTCONDITION) \ 980 } while (B_FALSE) 981 982 /* 983 * Allow drivers to perform optimised 128-bit doorbell writes. 984 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 985 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 986 * the need for locking in the host, and are the only ones known to be safe to 987 * use 128-bites write with. 988 */ 989 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 990 do { \ 991 EFX_CHECK_REG((_enp), (_reg)); \ 992 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 993 const char *, \ 994 #_reg, \ 995 uint32_t, (_index), \ 996 uint32_t, _reg ## _OFST, \ 997 uint32_t, (_eop)->eo_u32[3], \ 998 uint32_t, (_eop)->eo_u32[2], \ 999 uint32_t, (_eop)->eo_u32[1], \ 1000 uint32_t, (_eop)->eo_u32[0]); \ 1001 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1002 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1003 (_eop)); \ 1004 _NOTE(CONSTANTCONDITION) \ 1005 } while (B_FALSE) 1006 1007 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1008 do { \ 1009 unsigned int _new = (_wptr); \ 1010 unsigned int _old = (_owptr); \ 1011 \ 1012 if ((_new) >= (_old)) \ 1013 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1014 (_old) * sizeof (efx_desc_t), \ 1015 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1016 else \ 1017 /* \ 1018 * It is cheaper to sync entire map than sync \ 1019 * two parts especially when offset/size are \ 1020 * ignored and entire map is synced in any case.\ 1021 */ \ 1022 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1023 0, \ 1024 (_entries) * sizeof (efx_desc_t)); \ 1025 _NOTE(CONSTANTCONDITION) \ 1026 } while (B_FALSE) 1027 1028 extern __checkReturn efx_rc_t 1029 efx_nic_biu_test( 1030 __in efx_nic_t *enp); 1031 1032 extern __checkReturn efx_rc_t 1033 efx_mac_select( 1034 __in efx_nic_t *enp); 1035 1036 extern void 1037 efx_mac_multicast_hash_compute( 1038 __in_ecount(6*count) uint8_t const *addrs, 1039 __in int count, 1040 __out efx_oword_t *hash_low, 1041 __out efx_oword_t *hash_high); 1042 1043 extern __checkReturn efx_rc_t 1044 efx_phy_probe( 1045 __in efx_nic_t *enp); 1046 1047 extern void 1048 efx_phy_unprobe( 1049 __in efx_nic_t *enp); 1050 1051 #if EFSYS_OPT_VPD 1052 1053 /* VPD utility functions */ 1054 1055 extern __checkReturn efx_rc_t 1056 efx_vpd_hunk_length( 1057 __in_bcount(size) caddr_t data, 1058 __in size_t size, 1059 __out size_t *lengthp); 1060 1061 extern __checkReturn efx_rc_t 1062 efx_vpd_hunk_verify( 1063 __in_bcount(size) caddr_t data, 1064 __in size_t size, 1065 __out_opt boolean_t *cksummedp); 1066 1067 extern __checkReturn efx_rc_t 1068 efx_vpd_hunk_reinit( 1069 __in_bcount(size) caddr_t data, 1070 __in size_t size, 1071 __in boolean_t wantpid); 1072 1073 extern __checkReturn efx_rc_t 1074 efx_vpd_hunk_get( 1075 __in_bcount(size) caddr_t data, 1076 __in size_t size, 1077 __in efx_vpd_tag_t tag, 1078 __in efx_vpd_keyword_t keyword, 1079 __out unsigned int *payloadp, 1080 __out uint8_t *paylenp); 1081 1082 extern __checkReturn efx_rc_t 1083 efx_vpd_hunk_next( 1084 __in_bcount(size) caddr_t data, 1085 __in size_t size, 1086 __out efx_vpd_tag_t *tagp, 1087 __out efx_vpd_keyword_t *keyword, 1088 __out_opt unsigned int *payloadp, 1089 __out_opt uint8_t *paylenp, 1090 __inout unsigned int *contp); 1091 1092 extern __checkReturn efx_rc_t 1093 efx_vpd_hunk_set( 1094 __in_bcount(size) caddr_t data, 1095 __in size_t size, 1096 __in efx_vpd_value_t *evvp); 1097 1098 #endif /* EFSYS_OPT_VPD */ 1099 1100 #if EFSYS_OPT_DIAG 1101 1102 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1103 1104 typedef struct efx_register_set_s { 1105 unsigned int address; 1106 unsigned int step; 1107 unsigned int rows; 1108 efx_oword_t mask; 1109 } efx_register_set_t; 1110 1111 extern __checkReturn efx_rc_t 1112 efx_nic_test_registers( 1113 __in efx_nic_t *enp, 1114 __in efx_register_set_t *rsp, 1115 __in size_t count); 1116 1117 extern __checkReturn efx_rc_t 1118 efx_nic_test_tables( 1119 __in efx_nic_t *enp, 1120 __in efx_register_set_t *rsp, 1121 __in efx_pattern_type_t pattern, 1122 __in size_t count); 1123 1124 #endif /* EFSYS_OPT_DIAG */ 1125 1126 #if EFSYS_OPT_MCDI 1127 1128 extern __checkReturn efx_rc_t 1129 efx_mcdi_set_workaround( 1130 __in efx_nic_t *enp, 1131 __in uint32_t type, 1132 __in boolean_t enabled, 1133 __out_opt uint32_t *flagsp); 1134 1135 extern __checkReturn efx_rc_t 1136 efx_mcdi_get_workarounds( 1137 __in efx_nic_t *enp, 1138 __out_opt uint32_t *implementedp, 1139 __out_opt uint32_t *enabledp); 1140 1141 #endif /* EFSYS_OPT_MCDI */ 1142 1143 #ifdef __cplusplus 1144 } 1145 #endif 1146 1147 #endif /* _SYS_EFX_IMPL_H */ 1148