1 /*- 2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef _SYS_EFX_IMPL_H 27 #define _SYS_EFX_IMPL_H 28 29 #include "efsys.h" 30 #include "efx.h" 31 #include "efx_regs.h" 32 33 #if EFSYS_OPT_FALCON 34 #include "falcon_impl.h" 35 #endif /* EFSYS_OPT_FALCON */ 36 37 #if EFSYS_OPT_SIENA 38 #include "siena_impl.h" 39 #endif /* EFSYS_OPT_SIENA */ 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 #define EFX_MOD_MCDI 0x00000001 46 #define EFX_MOD_PROBE 0x00000002 47 #define EFX_MOD_NVRAM 0x00000004 48 #define EFX_MOD_VPD 0x00000008 49 #define EFX_MOD_NIC 0x00000010 50 #define EFX_MOD_INTR 0x00000020 51 #define EFX_MOD_EV 0x00000040 52 #define EFX_MOD_RX 0x00000080 53 #define EFX_MOD_TX 0x00000100 54 #define EFX_MOD_PORT 0x00000200 55 #define EFX_MOD_MON 0x00000400 56 #define EFX_MOD_WOL 0x00000800 57 #define EFX_MOD_FILTER 0x00001000 58 59 #define EFX_RESET_MAC 0x00000001 60 #define EFX_RESET_PHY 0x00000002 61 62 typedef enum efx_mac_type_e { 63 EFX_MAC_INVALID = 0, 64 EFX_MAC_FALCON_GMAC, 65 EFX_MAC_FALCON_XMAC, 66 EFX_MAC_SIENA, 67 EFX_MAC_NTYPES 68 } efx_mac_type_t; 69 70 typedef struct efx_mac_ops_s { 71 int (*emo_reset)(efx_nic_t *); /* optional */ 72 int (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 73 int (*emo_up)(efx_nic_t *, boolean_t *); 74 int (*emo_reconfigure)(efx_nic_t *); 75 #if EFSYS_OPT_LOOPBACK 76 int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 77 efx_loopback_type_t); 78 #endif /* EFSYS_OPT_LOOPBACK */ 79 #if EFSYS_OPT_MAC_STATS 80 int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 81 int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 82 uint16_t, boolean_t); 83 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 84 efsys_stat_t *, uint32_t *); 85 #endif /* EFSYS_OPT_MAC_STATS */ 86 } efx_mac_ops_t; 87 88 typedef struct efx_phy_ops_s { 89 int (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 90 int (*epo_reset)(efx_nic_t *); 91 int (*epo_reconfigure)(efx_nic_t *); 92 int (*epo_verify)(efx_nic_t *); 93 int (*epo_uplink_check)(efx_nic_t *, 94 boolean_t *); /* optional */ 95 int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, 96 unsigned int *, uint32_t *); 97 int (*epo_oui_get)(efx_nic_t *, uint32_t *); 98 #if EFSYS_OPT_PHY_STATS 99 int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 100 uint32_t *); 101 #endif /* EFSYS_OPT_PHY_STATS */ 102 #if EFSYS_OPT_PHY_PROPS 103 #if EFSYS_OPT_NAMES 104 const char __cs *(*epo_prop_name)(efx_nic_t *, unsigned int); 105 #endif /* EFSYS_OPT_PHY_PROPS */ 106 int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, 107 uint32_t *); 108 int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); 109 #endif /* EFSYS_OPT_PHY_PROPS */ 110 #if EFSYS_OPT_PHY_BIST 111 int (*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t); 112 int (*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t, 113 efx_phy_bist_result_t *, uint32_t *, 114 unsigned long *, size_t); 115 void (*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t); 116 #endif /* EFSYS_OPT_PHY_BIST */ 117 } efx_phy_ops_t; 118 119 typedef struct efx_port_s { 120 efx_mac_type_t ep_mac_type; 121 uint32_t ep_phy_type; 122 uint8_t ep_port; 123 uint32_t ep_mac_pdu; 124 uint8_t ep_mac_addr[6]; 125 efx_link_mode_t ep_link_mode; 126 boolean_t ep_unicst; 127 boolean_t ep_brdcst; 128 unsigned int ep_fcntl; 129 boolean_t ep_fcntl_autoneg; 130 efx_oword_t ep_multicst_hash[2]; 131 #if EFSYS_OPT_LOOPBACK 132 efx_loopback_type_t ep_loopback_type; 133 efx_link_mode_t ep_loopback_link_mode; 134 #endif /* EFSYS_OPT_LOOPBACK */ 135 #if EFSYS_OPT_PHY_FLAGS 136 uint32_t ep_phy_flags; 137 #endif /* EFSYS_OPT_PHY_FLAGS */ 138 #if EFSYS_OPT_PHY_LED_CONTROL 139 efx_phy_led_mode_t ep_phy_led_mode; 140 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 141 efx_phy_media_type_t ep_fixed_port_type; 142 efx_phy_media_type_t ep_module_type; 143 uint32_t ep_adv_cap_mask; 144 uint32_t ep_lp_cap_mask; 145 uint32_t ep_default_adv_cap_mask; 146 uint32_t ep_phy_cap_mask; 147 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C 148 union { 149 struct { 150 unsigned int bug10934_count; 151 } ep_txc43128; 152 struct { 153 unsigned int bug17190_count; 154 } ep_qt2025c; 155 }; 156 #endif 157 boolean_t ep_mac_poll_needed; /* falcon only */ 158 boolean_t ep_mac_up; /* falcon only */ 159 uint32_t ep_fwver; /* falcon only */ 160 boolean_t ep_mac_drain; 161 boolean_t ep_mac_stats_pending; 162 #if EFSYS_OPT_PHY_BIST 163 efx_phy_bist_type_t ep_current_bist; 164 #endif 165 efx_mac_ops_t *ep_emop; 166 efx_phy_ops_t *ep_epop; 167 } efx_port_t; 168 169 typedef struct efx_mon_ops_s { 170 int (*emo_reset)(efx_nic_t *); 171 int (*emo_reconfigure)(efx_nic_t *); 172 #if EFSYS_OPT_MON_STATS 173 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 174 efx_mon_stat_value_t *); 175 #endif /* EFSYS_OPT_MON_STATS */ 176 } efx_mon_ops_t; 177 178 typedef struct efx_mon_s { 179 efx_mon_type_t em_type; 180 efx_mon_ops_t *em_emop; 181 } efx_mon_t; 182 183 typedef struct efx_intr_s { 184 efx_intr_type_t ei_type; 185 efsys_mem_t *ei_esmp; 186 unsigned int ei_level; 187 } efx_intr_t; 188 189 typedef struct efx_nic_ops_s { 190 int (*eno_probe)(efx_nic_t *); 191 int (*eno_reset)(efx_nic_t *); 192 int (*eno_init)(efx_nic_t *); 193 #if EFSYS_OPT_DIAG 194 int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); 195 int (*eno_register_test)(efx_nic_t *); 196 #endif /* EFSYS_OPT_DIAG */ 197 void (*eno_fini)(efx_nic_t *); 198 void (*eno_unprobe)(efx_nic_t *); 199 } efx_nic_ops_t; 200 201 #define EFX_TXQ_LIMIT_TARGET 259 202 #define EFX_RXQ_LIMIT_TARGET 768 203 204 #if EFSYS_OPT_FILTER 205 206 typedef enum efx_filter_type_e { 207 EFX_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ 208 EFX_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ 209 EFX_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ 210 EFX_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ 211 212 #if EFSYS_OPT_SIENA 213 EFX_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 214 EFX_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 215 216 EFX_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 217 EFX_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 218 EFX_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 219 EFX_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ 220 221 EFX_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ 222 EFX_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ 223 #endif /* EFSYS_OPT_SIENA */ 224 225 EFX_FILTER_NTYPES 226 } efx_filter_type_t; 227 228 typedef enum efx_filter_tbl_id_e { 229 EFX_FILTER_TBL_RX_IP = 0, 230 EFX_FILTER_TBL_RX_MAC, 231 EFX_FILTER_TBL_TX_IP, 232 EFX_FILTER_TBL_TX_MAC, 233 EFX_FILTER_NTBLS 234 } efx_filter_tbl_id_t; 235 236 typedef struct efx_filter_tbl_s { 237 int eft_size; /* number of entries */ 238 int eft_used; /* active count */ 239 uint32_t *eft_bitmap; /* active bitmap */ 240 efx_filter_spec_t *eft_spec; /* array of saved specs */ 241 } efx_filter_tbl_t; 242 243 typedef struct efx_filter_s { 244 efx_filter_tbl_t ef_tbl[EFX_FILTER_NTBLS]; 245 unsigned int ef_depth[EFX_FILTER_NTYPES]; 246 } efx_filter_t; 247 248 249 extern __checkReturn int 250 efx_filter_insert_filter( 251 __in efx_nic_t *enp, 252 __in efx_filter_spec_t *spec, 253 __in boolean_t replace); 254 255 extern __checkReturn int 256 efx_filter_remove_filter( 257 __in efx_nic_t *enp, 258 __in efx_filter_spec_t *spec); 259 260 extern void 261 efx_filter_remove_index( 262 __inout efx_nic_t *enp, 263 __in efx_filter_type_t type, 264 __in int filter_idx); 265 266 extern void 267 efx_filter_redirect_index( 268 __inout efx_nic_t *enp, 269 __in efx_filter_type_t type, 270 __in int filter_index, 271 __in int rxq_index); 272 273 extern __checkReturn int 274 efx_filter_clear_tbl( 275 __in efx_nic_t *enp, 276 __in efx_filter_tbl_id_t tbl); 277 278 #endif /* EFSYS_OPT_FILTER */ 279 280 #if EFSYS_OPT_NVRAM 281 typedef struct efx_nvram_ops_s { 282 #if EFSYS_OPT_DIAG 283 int (*envo_test)(efx_nic_t *); 284 #endif /* EFSYS_OPT_DIAG */ 285 int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); 286 int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, 287 uint32_t *, uint16_t *); 288 int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); 289 int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, 290 unsigned int, caddr_t, size_t); 291 int (*envo_erase)(efx_nic_t *, efx_nvram_type_t); 292 int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, 293 unsigned int, caddr_t, size_t); 294 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); 295 int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *); 296 297 } efx_nvram_ops_t; 298 #endif /* EFSYS_OPT_NVRAM */ 299 300 #if EFSYS_OPT_VPD 301 typedef struct efx_vpd_ops_s { 302 int (*evpdo_init)(efx_nic_t *); 303 int (*evpdo_size)(efx_nic_t *, size_t *); 304 int (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 305 int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 306 int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 307 int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *); 308 int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *); 309 int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *, 310 unsigned int *); 311 int (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 312 void (*evpdo_fini)(efx_nic_t *); 313 } efx_vpd_ops_t; 314 #endif /* EFSYS_OPT_VPD */ 315 316 struct efx_nic_s { 317 uint32_t en_magic; 318 efx_family_t en_family; 319 uint32_t en_features; 320 efsys_identifier_t *en_esip; 321 efsys_lock_t *en_eslp; 322 efsys_bar_t *en_esbp; 323 unsigned int en_mod_flags; 324 unsigned int en_reset_flags; 325 efx_nic_cfg_t en_nic_cfg; 326 efx_port_t en_port; 327 efx_mon_t en_mon; 328 efx_intr_t en_intr; 329 uint32_t en_ev_qcount; 330 uint32_t en_rx_qcount; 331 uint32_t en_tx_qcount; 332 efx_nic_ops_t *en_enop; 333 #if EFSYS_OPT_FILTER 334 efx_filter_t en_filter; 335 #endif /* EFSYS_OPT_FILTER */ 336 #if EFSYS_OPT_NVRAM 337 efx_nvram_type_t en_nvram_locked; 338 efx_nvram_ops_t *en_envop; 339 #endif /* EFSYS_OPT_NVRAM */ 340 #if EFSYS_OPT_VPD 341 efx_vpd_ops_t *en_evpdop; 342 #endif /* EFSYS_OPT_VPD */ 343 union { 344 #if EFSYS_OPT_FALCON 345 struct { 346 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES]; 347 falcon_i2c_t enu_fip; 348 boolean_t enu_i2c_locked; 349 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 350 const uint8_t *enu_forced_cfg; 351 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ 352 uint8_t enu_mon_devid; 353 #if EFSYS_OPT_PCIE_TUNE 354 unsigned int enu_nlanes; 355 #endif /* EFSYS_OPT_PCIE_TUNE */ 356 uint16_t enu_board_rev; 357 boolean_t enu_internal_sram; 358 uint8_t enu_sram_num_bank; 359 uint8_t enu_sram_bank_size; 360 } falcon; 361 #endif /* EFSYS_OPT_FALCON */ 362 #if EFSYS_OPT_SIENA 363 struct { 364 #if EFSYS_OPT_MCDI 365 efx_mcdi_iface_t enu_mip; 366 #endif /* EFSYS_OPT_MCDI */ 367 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 368 unsigned int enu_partn_mask; 369 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 370 #if EFSYS_OPT_VPD 371 caddr_t enu_svpd; 372 size_t enu_svpd_length; 373 #endif /* EFSYS_OPT_VPD */ 374 } siena; 375 #endif /* EFSYS_OPT_SIENA */ 376 } en_u; 377 }; 378 379 380 #define EFX_NIC_MAGIC 0x02121996 381 382 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 383 const efx_ev_callbacks_t *, void *); 384 385 struct efx_evq_s { 386 uint32_t ee_magic; 387 efx_nic_t *ee_enp; 388 unsigned int ee_index; 389 unsigned int ee_mask; 390 efsys_mem_t *ee_esmp; 391 #if EFSYS_OPT_QSTATS 392 uint32_t ee_stat[EV_NQSTATS]; 393 #endif /* EFSYS_OPT_QSTATS */ 394 efx_ev_handler_t ee_handler[1 << FSF_AZ_EV_CODE_WIDTH]; 395 }; 396 397 #define EFX_EVQ_MAGIC 0x08081997 398 399 #define EFX_EV_TIMER_QUANTUM 5 400 401 struct efx_rxq_s { 402 uint32_t er_magic; 403 efx_nic_t *er_enp; 404 unsigned int er_index; 405 unsigned int er_mask; 406 efsys_mem_t *er_esmp; 407 }; 408 409 #define EFX_RXQ_MAGIC 0x15022005 410 411 struct efx_txq_s { 412 uint32_t et_magic; 413 efx_nic_t *et_enp; 414 unsigned int et_index; 415 unsigned int et_mask; 416 efsys_mem_t *et_esmp; 417 #if EFSYS_OPT_QSTATS 418 uint32_t et_stat[TX_NQSTATS]; 419 #endif /* EFSYS_OPT_QSTATS */ 420 }; 421 422 #define EFX_TXQ_MAGIC 0x05092005 423 424 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 425 do { \ 426 (_dst)[0] = (_src)[0]; \ 427 (_dst)[1] = (_src)[1]; \ 428 (_dst)[2] = (_src)[2]; \ 429 (_dst)[3] = (_src)[3]; \ 430 (_dst)[4] = (_src)[4]; \ 431 (_dst)[5] = (_src)[5]; \ 432 _NOTE(CONSTANTCONDITION) \ 433 } while (B_FALSE) 434 435 #if EFSYS_OPT_CHECK_REG 436 #define EFX_CHECK_REG(_enp, _reg) \ 437 do { \ 438 const char __cs *name = #_reg; \ 439 char min = name[4]; \ 440 char max = name[5]; \ 441 char rev; \ 442 \ 443 switch ((_enp)->en_family) { \ 444 case EFX_FAMILY_FALCON: \ 445 rev = 'B'; \ 446 break; \ 447 \ 448 case EFX_FAMILY_SIENA: \ 449 rev = 'C'; \ 450 break; \ 451 \ 452 default: \ 453 rev = '?'; \ 454 break; \ 455 } \ 456 \ 457 EFSYS_ASSERT3S(rev, >=, min); \ 458 EFSYS_ASSERT3S(rev, <=, max); \ 459 \ 460 _NOTE(CONSTANTCONDITION) \ 461 } while (B_FALSE) 462 #else 463 #define EFX_CHECK_REG(_enp, _reg) do { \ 464 _NOTE(CONSTANTCONDITION) \ 465 } while(B_FALSE) 466 #endif 467 468 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 469 do { \ 470 EFX_CHECK_REG((_enp), (_reg)); \ 471 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 472 (_edp), (_lock)); \ 473 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 474 uint32_t, _reg ## _OFST, \ 475 uint32_t, (_edp)->ed_u32[0]); \ 476 _NOTE(CONSTANTCONDITION) \ 477 } while (B_FALSE) 478 479 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 480 do { \ 481 EFX_CHECK_REG((_enp), (_reg)); \ 482 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 483 uint32_t, _reg ## _OFST, \ 484 uint32_t, (_edp)->ed_u32[0]); \ 485 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 486 (_edp), (_lock)); \ 487 _NOTE(CONSTANTCONDITION) \ 488 } while (B_FALSE) 489 490 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 491 do { \ 492 EFX_CHECK_REG((_enp), (_reg)); \ 493 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 494 (_eqp)); \ 495 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 496 uint32_t, _reg ## _OFST, \ 497 uint32_t, (_eqp)->eq_u32[1], \ 498 uint32_t, (_eqp)->eq_u32[0]); \ 499 _NOTE(CONSTANTCONDITION) \ 500 } while (B_FALSE) 501 502 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 503 do { \ 504 EFX_CHECK_REG((_enp), (_reg)); \ 505 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 506 uint32_t, _reg ## _OFST, \ 507 uint32_t, (_eqp)->eq_u32[1], \ 508 uint32_t, (_eqp)->eq_u32[0]); \ 509 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 510 (_eqp)); \ 511 _NOTE(CONSTANTCONDITION) \ 512 } while (B_FALSE) 513 514 #define EFX_BAR_READO(_enp, _reg, _eop) \ 515 do { \ 516 EFX_CHECK_REG((_enp), (_reg)); \ 517 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 518 (_eop), B_TRUE); \ 519 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 520 uint32_t, _reg ## _OFST, \ 521 uint32_t, (_eop)->eo_u32[3], \ 522 uint32_t, (_eop)->eo_u32[2], \ 523 uint32_t, (_eop)->eo_u32[1], \ 524 uint32_t, (_eop)->eo_u32[0]); \ 525 _NOTE(CONSTANTCONDITION) \ 526 } while (B_FALSE) 527 528 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 529 do { \ 530 EFX_CHECK_REG((_enp), (_reg)); \ 531 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 532 uint32_t, _reg ## _OFST, \ 533 uint32_t, (_eop)->eo_u32[3], \ 534 uint32_t, (_eop)->eo_u32[2], \ 535 uint32_t, (_eop)->eo_u32[1], \ 536 uint32_t, (_eop)->eo_u32[0]); \ 537 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 538 (_eop), B_TRUE); \ 539 _NOTE(CONSTANTCONDITION) \ 540 } while (B_FALSE) 541 542 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 543 do { \ 544 EFX_CHECK_REG((_enp), (_reg)); \ 545 EFSYS_BAR_READD((_enp)->en_esbp, \ 546 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 547 (_edp), (_lock)); \ 548 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 549 uint32_t, (_index), \ 550 uint32_t, _reg ## _OFST, \ 551 uint32_t, (_edp)->ed_u32[0]); \ 552 _NOTE(CONSTANTCONDITION) \ 553 } while (B_FALSE) 554 555 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 556 do { \ 557 EFX_CHECK_REG((_enp), (_reg)); \ 558 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 559 uint32_t, (_index), \ 560 uint32_t, _reg ## _OFST, \ 561 uint32_t, (_edp)->ed_u32[0]); \ 562 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 563 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 564 (_edp), (_lock)); \ 565 _NOTE(CONSTANTCONDITION) \ 566 } while (B_FALSE) 567 568 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 569 do { \ 570 EFX_CHECK_REG((_enp), (_reg)); \ 571 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 572 uint32_t, (_index), \ 573 uint32_t, _reg ## _OFST, \ 574 uint32_t, (_edp)->ed_u32[0]); \ 575 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 576 (_reg ## _OFST + \ 577 (3 * sizeof (efx_dword_t)) + \ 578 ((_index) * _reg ## _STEP)), \ 579 (_edp), (_lock)); \ 580 _NOTE(CONSTANTCONDITION) \ 581 } while (B_FALSE) 582 583 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 584 do { \ 585 EFX_CHECK_REG((_enp), (_reg)); \ 586 EFSYS_BAR_READQ((_enp)->en_esbp, \ 587 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 588 (_eqp)); \ 589 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 590 uint32_t, (_index), \ 591 uint32_t, _reg ## _OFST, \ 592 uint32_t, (_eqp)->eq_u32[1], \ 593 uint32_t, (_eqp)->eq_u32[0]); \ 594 _NOTE(CONSTANTCONDITION) \ 595 } while (B_FALSE) 596 597 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 598 do { \ 599 EFX_CHECK_REG((_enp), (_reg)); \ 600 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 601 uint32_t, (_index), \ 602 uint32_t, _reg ## _OFST, \ 603 uint32_t, (_eqp)->eq_u32[1], \ 604 uint32_t, (_eqp)->eq_u32[0]); \ 605 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 606 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 607 (_eqp)); \ 608 _NOTE(CONSTANTCONDITION) \ 609 } while (B_FALSE) 610 611 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop) \ 612 do { \ 613 EFX_CHECK_REG((_enp), (_reg)); \ 614 EFSYS_BAR_READO((_enp)->en_esbp, \ 615 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 616 (_eop), B_TRUE); \ 617 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 618 uint32_t, (_index), \ 619 uint32_t, _reg ## _OFST, \ 620 uint32_t, (_eop)->eo_u32[3], \ 621 uint32_t, (_eop)->eo_u32[2], \ 622 uint32_t, (_eop)->eo_u32[1], \ 623 uint32_t, (_eop)->eo_u32[0]); \ 624 _NOTE(CONSTANTCONDITION) \ 625 } while (B_FALSE) 626 627 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop) \ 628 do { \ 629 EFX_CHECK_REG((_enp), (_reg)); \ 630 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 631 uint32_t, (_index), \ 632 uint32_t, _reg ## _OFST, \ 633 uint32_t, (_eop)->eo_u32[3], \ 634 uint32_t, (_eop)->eo_u32[2], \ 635 uint32_t, (_eop)->eo_u32[1], \ 636 uint32_t, (_eop)->eo_u32[0]); \ 637 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 638 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 639 (_eop), B_TRUE); \ 640 _NOTE(CONSTANTCONDITION) \ 641 } while (B_FALSE) 642 643 extern __checkReturn int 644 efx_mac_select( 645 __in efx_nic_t *enp); 646 647 extern __checkReturn int 648 efx_phy_probe( 649 __in efx_nic_t *enp); 650 651 extern void 652 efx_phy_unprobe( 653 __in efx_nic_t *enp); 654 655 #if EFSYS_OPT_VPD 656 657 /* VPD utility functions */ 658 659 extern __checkReturn int 660 efx_vpd_hunk_length( 661 __in_bcount(size) caddr_t data, 662 __in size_t size, 663 __out size_t *lengthp); 664 665 extern __checkReturn int 666 efx_vpd_hunk_verify( 667 __in_bcount(size) caddr_t data, 668 __in size_t size, 669 __out_opt boolean_t *cksummedp); 670 671 extern __checkReturn int 672 efx_vpd_hunk_reinit( 673 __in caddr_t data, 674 __in size_t size, 675 __in boolean_t wantpid); 676 677 extern __checkReturn int 678 efx_vpd_hunk_get( 679 __in_bcount(size) caddr_t data, 680 __in size_t size, 681 __in efx_vpd_tag_t tag, 682 __in efx_vpd_keyword_t keyword, 683 __out unsigned int *payloadp, 684 __out uint8_t *paylenp); 685 686 extern __checkReturn int 687 efx_vpd_hunk_next( 688 __in_bcount(size) caddr_t data, 689 __in size_t size, 690 __out efx_vpd_tag_t *tagp, 691 __out efx_vpd_keyword_t *keyword, 692 __out_bcount_opt(*paylenp) unsigned int *payloadp, 693 __out_opt uint8_t *paylenp, 694 __inout unsigned int *contp); 695 696 extern __checkReturn int 697 efx_vpd_hunk_set( 698 __in_bcount(size) caddr_t data, 699 __in size_t size, 700 __in efx_vpd_value_t *evvp); 701 702 #endif /* EFSYS_OPT_VPD */ 703 704 #if EFSYS_OPT_DIAG 705 706 extern efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[]; 707 708 typedef struct efx_register_set_s { 709 unsigned int address; 710 unsigned int step; 711 unsigned int rows; 712 efx_oword_t mask; 713 } efx_register_set_t; 714 715 extern __checkReturn int 716 efx_nic_test_registers( 717 __in efx_nic_t *enp, 718 __in efx_register_set_t *rsp, 719 __in size_t count); 720 721 extern __checkReturn int 722 efx_nic_test_tables( 723 __in efx_nic_t *enp, 724 __in efx_register_set_t *rsp, 725 __in efx_pattern_type_t pattern, 726 __in size_t count); 727 728 #endif /* EFSYS_OPT_DIAG */ 729 730 #ifdef __cplusplus 731 } 732 #endif 733 734 #endif /* _SYS_EFX_IMPL_H */ 735