xref: /freebsd/sys/dev/sfxge/common/efx_impl.h (revision 9cb71b166c6a1f3fe8d36053975425dbea7ff55e)
1e948693eSPhilip Paeps /*-
23c838a9fSAndrew Rybchenko  * Copyright (c) 2007-2015 Solarflare Communications Inc.
33c838a9fSAndrew Rybchenko  * All rights reserved.
4e948693eSPhilip Paeps  *
5e948693eSPhilip Paeps  * Redistribution and use in source and binary forms, with or without
63c838a9fSAndrew Rybchenko  * modification, are permitted provided that the following conditions are met:
7e948693eSPhilip Paeps  *
83c838a9fSAndrew Rybchenko  * 1. Redistributions of source code must retain the above copyright notice,
93c838a9fSAndrew Rybchenko  *    this list of conditions and the following disclaimer.
103c838a9fSAndrew Rybchenko  * 2. Redistributions in binary form must reproduce the above copyright notice,
113c838a9fSAndrew Rybchenko  *    this list of conditions and the following disclaimer in the documentation
123c838a9fSAndrew Rybchenko  *    and/or other materials provided with the distribution.
133c838a9fSAndrew Rybchenko  *
143c838a9fSAndrew Rybchenko  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
153c838a9fSAndrew Rybchenko  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
163c838a9fSAndrew Rybchenko  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
173c838a9fSAndrew Rybchenko  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
183c838a9fSAndrew Rybchenko  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
193c838a9fSAndrew Rybchenko  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
203c838a9fSAndrew Rybchenko  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
213c838a9fSAndrew Rybchenko  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
223c838a9fSAndrew Rybchenko  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
233c838a9fSAndrew Rybchenko  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
243c838a9fSAndrew Rybchenko  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
253c838a9fSAndrew Rybchenko  *
263c838a9fSAndrew Rybchenko  * The views and conclusions contained in the software and documentation are
273c838a9fSAndrew Rybchenko  * those of the authors and should not be interpreted as representing official
283c838a9fSAndrew Rybchenko  * policies, either expressed or implied, of the FreeBSD Project.
295dee87d7SPhilip Paeps  *
305dee87d7SPhilip Paeps  * $FreeBSD$
31e948693eSPhilip Paeps  */
32e948693eSPhilip Paeps 
33e948693eSPhilip Paeps #ifndef	_SYS_EFX_IMPL_H
34e948693eSPhilip Paeps #define	_SYS_EFX_IMPL_H
35e948693eSPhilip Paeps 
36e948693eSPhilip Paeps #include "efsys.h"
37e948693eSPhilip Paeps #include "efx.h"
38e948693eSPhilip Paeps #include "efx_regs.h"
393c838a9fSAndrew Rybchenko #include "efx_regs_ef10.h"
403c838a9fSAndrew Rybchenko 
413c838a9fSAndrew Rybchenko /* FIXME: Add definition for driver generated software events */
423c838a9fSAndrew Rybchenko #ifndef	ESE_DZ_EV_CODE_DRV_GEN_EV
433c838a9fSAndrew Rybchenko #define	ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
443c838a9fSAndrew Rybchenko #endif
453c838a9fSAndrew Rybchenko 
463c838a9fSAndrew Rybchenko #include "efx_check.h"
473c838a9fSAndrew Rybchenko 
48e948693eSPhilip Paeps 
49e948693eSPhilip Paeps #if EFSYS_OPT_FALCON
50e948693eSPhilip Paeps #include "falcon_impl.h"
51e948693eSPhilip Paeps #endif	/* EFSYS_OPT_FALCON */
52e948693eSPhilip Paeps 
53e948693eSPhilip Paeps #if EFSYS_OPT_SIENA
54e948693eSPhilip Paeps #include "siena_impl.h"
55e948693eSPhilip Paeps #endif	/* EFSYS_OPT_SIENA */
56e948693eSPhilip Paeps 
573c838a9fSAndrew Rybchenko #if EFSYS_OPT_HUNTINGTON
583c838a9fSAndrew Rybchenko #include "hunt_impl.h"
593c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_HUNTINGTON */
603c838a9fSAndrew Rybchenko 
61e948693eSPhilip Paeps #ifdef	__cplusplus
62e948693eSPhilip Paeps extern "C" {
63e948693eSPhilip Paeps #endif
64e948693eSPhilip Paeps 
65e948693eSPhilip Paeps #define	EFX_MOD_MCDI		0x00000001
66e948693eSPhilip Paeps #define	EFX_MOD_PROBE		0x00000002
67e948693eSPhilip Paeps #define	EFX_MOD_NVRAM		0x00000004
68e948693eSPhilip Paeps #define	EFX_MOD_VPD		0x00000008
69e948693eSPhilip Paeps #define	EFX_MOD_NIC		0x00000010
70e948693eSPhilip Paeps #define	EFX_MOD_INTR		0x00000020
71e948693eSPhilip Paeps #define	EFX_MOD_EV		0x00000040
72e948693eSPhilip Paeps #define	EFX_MOD_RX		0x00000080
73e948693eSPhilip Paeps #define	EFX_MOD_TX		0x00000100
74e948693eSPhilip Paeps #define	EFX_MOD_PORT		0x00000200
75e948693eSPhilip Paeps #define	EFX_MOD_MON		0x00000400
76e948693eSPhilip Paeps #define	EFX_MOD_WOL		0x00000800
77e948693eSPhilip Paeps #define	EFX_MOD_FILTER		0x00001000
783c838a9fSAndrew Rybchenko #define	EFX_MOD_PKTFILTER	0x00002000
79e948693eSPhilip Paeps 
80e948693eSPhilip Paeps #define	EFX_RESET_MAC		0x00000001
81e948693eSPhilip Paeps #define	EFX_RESET_PHY		0x00000002
823c838a9fSAndrew Rybchenko #define	EFX_RESET_RXQ_ERR	0x00000004
833c838a9fSAndrew Rybchenko #define	EFX_RESET_TXQ_ERR	0x00000008
84e948693eSPhilip Paeps 
85e948693eSPhilip Paeps typedef enum efx_mac_type_e {
86e948693eSPhilip Paeps 	EFX_MAC_INVALID = 0,
87e948693eSPhilip Paeps 	EFX_MAC_FALCON_GMAC,
88e948693eSPhilip Paeps 	EFX_MAC_FALCON_XMAC,
89e948693eSPhilip Paeps 	EFX_MAC_SIENA,
903c838a9fSAndrew Rybchenko 	EFX_MAC_HUNTINGTON,
91e948693eSPhilip Paeps 	EFX_MAC_NTYPES
92e948693eSPhilip Paeps } efx_mac_type_t;
93e948693eSPhilip Paeps 
943c838a9fSAndrew Rybchenko typedef struct efx_ev_ops_s {
95460cb568SAndrew Rybchenko 	efx_rc_t	(*eevo_init)(efx_nic_t *);
963c838a9fSAndrew Rybchenko 	void		(*eevo_fini)(efx_nic_t *);
97460cb568SAndrew Rybchenko 	efx_rc_t	(*eevo_qcreate)(efx_nic_t *, unsigned int,
983c838a9fSAndrew Rybchenko 					  efsys_mem_t *, size_t, uint32_t,
993c838a9fSAndrew Rybchenko 					  efx_evq_t *);
1003c838a9fSAndrew Rybchenko 	void		(*eevo_qdestroy)(efx_evq_t *);
101460cb568SAndrew Rybchenko 	efx_rc_t	(*eevo_qprime)(efx_evq_t *, unsigned int);
1023c838a9fSAndrew Rybchenko 	void		(*eevo_qpost)(efx_evq_t *, uint16_t);
103460cb568SAndrew Rybchenko 	efx_rc_t	(*eevo_qmoderate)(efx_evq_t *, unsigned int);
1043c838a9fSAndrew Rybchenko #if EFSYS_OPT_QSTATS
1053c838a9fSAndrew Rybchenko 	void		(*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
1063c838a9fSAndrew Rybchenko #endif
1073c838a9fSAndrew Rybchenko } efx_ev_ops_t;
1083c838a9fSAndrew Rybchenko 
1093c838a9fSAndrew Rybchenko typedef struct efx_tx_ops_s {
110460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_init)(efx_nic_t *);
1113c838a9fSAndrew Rybchenko 	void		(*etxo_fini)(efx_nic_t *);
112460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qcreate)(efx_nic_t *,
1133c838a9fSAndrew Rybchenko 					unsigned int, unsigned int,
1143c838a9fSAndrew Rybchenko 					efsys_mem_t *, size_t,
1153c838a9fSAndrew Rybchenko 					uint32_t, uint16_t,
1163c838a9fSAndrew Rybchenko 					efx_evq_t *, efx_txq_t *,
1173c838a9fSAndrew Rybchenko 					unsigned int *);
1183c838a9fSAndrew Rybchenko 	void		(*etxo_qdestroy)(efx_txq_t *);
119460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
1203c838a9fSAndrew Rybchenko 				      unsigned int, unsigned int,
1213c838a9fSAndrew Rybchenko 				      unsigned int *);
1223c838a9fSAndrew Rybchenko 	void		(*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qpace)(efx_txq_t *, unsigned int);
124460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qflush)(efx_txq_t *);
1253c838a9fSAndrew Rybchenko 	void		(*etxo_qenable)(efx_txq_t *);
126460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qpio_enable)(efx_txq_t *);
1273c838a9fSAndrew Rybchenko 	void		(*etxo_qpio_disable)(efx_txq_t *);
128460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
1293c838a9fSAndrew Rybchenko 					   size_t);
130460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
1313c838a9fSAndrew Rybchenko 					   unsigned int *);
132460cb568SAndrew Rybchenko 	efx_rc_t	(*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
1333c838a9fSAndrew Rybchenko 				      unsigned int, unsigned int,
1343c838a9fSAndrew Rybchenko 				      unsigned int *);
1353c838a9fSAndrew Rybchenko 	void		(*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
1363c838a9fSAndrew Rybchenko 						size_t, boolean_t,
1373c838a9fSAndrew Rybchenko 						efx_desc_t *);
1383c838a9fSAndrew Rybchenko 	void		(*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
1393c838a9fSAndrew Rybchenko 						uint32_t, uint8_t,
1403c838a9fSAndrew Rybchenko 						efx_desc_t *);
1413c838a9fSAndrew Rybchenko 	void		(*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
1423c838a9fSAndrew Rybchenko 						efx_desc_t *);
1433c838a9fSAndrew Rybchenko #if EFSYS_OPT_QSTATS
1443c838a9fSAndrew Rybchenko 	void		(*etxo_qstats_update)(efx_txq_t *,
1453c838a9fSAndrew Rybchenko 					      efsys_stat_t *);
1463c838a9fSAndrew Rybchenko #endif
1473c838a9fSAndrew Rybchenko } efx_tx_ops_t;
1483c838a9fSAndrew Rybchenko 
1493c838a9fSAndrew Rybchenko typedef struct efx_rx_ops_s {
150460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_init)(efx_nic_t *);
1513c838a9fSAndrew Rybchenko 	void		(*erxo_fini)(efx_nic_t *);
1523c838a9fSAndrew Rybchenko #if EFSYS_OPT_RX_HDR_SPLIT
153460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
1543c838a9fSAndrew Rybchenko 						 unsigned int);
1553c838a9fSAndrew Rybchenko #endif
1563c838a9fSAndrew Rybchenko #if EFSYS_OPT_RX_SCATTER
157460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_scatter_enable)(efx_nic_t *, unsigned int);
1583c838a9fSAndrew Rybchenko #endif
1593c838a9fSAndrew Rybchenko #if EFSYS_OPT_RX_SCALE
160460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
1613c838a9fSAndrew Rybchenko 					       efx_rx_hash_type_t, boolean_t);
162460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
163460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
1643c838a9fSAndrew Rybchenko 					      size_t);
1653c838a9fSAndrew Rybchenko #endif
1663c838a9fSAndrew Rybchenko 	void		(*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
1673c838a9fSAndrew Rybchenko 				      unsigned int, unsigned int,
1683c838a9fSAndrew Rybchenko 				      unsigned int);
1693c838a9fSAndrew Rybchenko 	void		(*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_qflush)(efx_rxq_t *);
1713c838a9fSAndrew Rybchenko 	void		(*erxo_qenable)(efx_rxq_t *);
172460cb568SAndrew Rybchenko 	efx_rc_t	(*erxo_qcreate)(efx_nic_t *enp, unsigned int,
1733c838a9fSAndrew Rybchenko 					unsigned int, efx_rxq_type_t,
1743c838a9fSAndrew Rybchenko 					efsys_mem_t *, size_t, uint32_t,
1753c838a9fSAndrew Rybchenko 					efx_evq_t *, efx_rxq_t *);
1763c838a9fSAndrew Rybchenko 	void		(*erxo_qdestroy)(efx_rxq_t *);
1773c838a9fSAndrew Rybchenko } efx_rx_ops_t;
1783c838a9fSAndrew Rybchenko 
179e948693eSPhilip Paeps typedef struct efx_mac_ops_s {
180460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_reset)(efx_nic_t *); /* optional */
181460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_up)(efx_nic_t *, boolean_t *);
183460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_addr_set)(efx_nic_t *);
184460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_reconfigure)(efx_nic_t *);
185460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_multicast_list_set)(efx_nic_t *);
186460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_filter_default_rxq_set)(efx_nic_t *,
1873c838a9fSAndrew Rybchenko 						      efx_rxq_t *, boolean_t);
1883c838a9fSAndrew Rybchenko 	void		(*emo_filter_default_rxq_clear)(efx_nic_t *);
189e948693eSPhilip Paeps #if EFSYS_OPT_LOOPBACK
190460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191e948693eSPhilip Paeps 					    efx_loopback_type_t);
192e948693eSPhilip Paeps #endif	/* EFSYS_OPT_LOOPBACK */
193e948693eSPhilip Paeps #if EFSYS_OPT_MAC_STATS
194460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196e948693eSPhilip Paeps 					      uint16_t, boolean_t);
197460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198e948693eSPhilip Paeps 					    efsys_stat_t *, uint32_t *);
199e948693eSPhilip Paeps #endif	/* EFSYS_OPT_MAC_STATS */
200e948693eSPhilip Paeps } efx_mac_ops_t;
201e948693eSPhilip Paeps 
202e948693eSPhilip Paeps typedef struct efx_phy_ops_s {
203460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_power)(efx_nic_t *, boolean_t); /* optional */
204460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_reset)(efx_nic_t *);
205460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_reconfigure)(efx_nic_t *);
206460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_verify)(efx_nic_t *);
207460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_uplink_check)(efx_nic_t *,
208e948693eSPhilip Paeps 					    boolean_t *); /* optional */
209460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
210e948693eSPhilip Paeps 					      unsigned int *, uint32_t *);
211460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_oui_get)(efx_nic_t *, uint32_t *);
212e948693eSPhilip Paeps #if EFSYS_OPT_PHY_STATS
213460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
214e948693eSPhilip Paeps 					    uint32_t *);
215e948693eSPhilip Paeps #endif	/* EFSYS_OPT_PHY_STATS */
216e948693eSPhilip Paeps #if EFSYS_OPT_PHY_PROPS
217e948693eSPhilip Paeps #if EFSYS_OPT_NAMES
2183c838a9fSAndrew Rybchenko 	const char	*(*epo_prop_name)(efx_nic_t *, unsigned int);
219e948693eSPhilip Paeps #endif	/* EFSYS_OPT_PHY_PROPS */
220460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
221e948693eSPhilip Paeps 					uint32_t *);
222460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
223e948693eSPhilip Paeps #endif	/* EFSYS_OPT_PHY_PROPS */
2243c838a9fSAndrew Rybchenko #if EFSYS_OPT_BIST
225460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_bist_enable_offline)(efx_nic_t *);
226460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227460cb568SAndrew Rybchenko 	efx_rc_t	(*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
2283c838a9fSAndrew Rybchenko 					 efx_bist_result_t *, uint32_t *,
229e948693eSPhilip Paeps 					 unsigned long *, size_t);
2303c838a9fSAndrew Rybchenko 	void		(*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
2313c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_BIST */
232e948693eSPhilip Paeps } efx_phy_ops_t;
233e948693eSPhilip Paeps 
2343c838a9fSAndrew Rybchenko #if EFSYS_OPT_FILTER
2353c838a9fSAndrew Rybchenko typedef struct efx_filter_ops_s {
236460cb568SAndrew Rybchenko 	efx_rc_t	(*efo_init)(efx_nic_t *);
2373c838a9fSAndrew Rybchenko 	void		(*efo_fini)(efx_nic_t *);
238460cb568SAndrew Rybchenko 	efx_rc_t	(*efo_restore)(efx_nic_t *);
239460cb568SAndrew Rybchenko 	efx_rc_t	(*efo_add)(efx_nic_t *, efx_filter_spec_t *,
2403c838a9fSAndrew Rybchenko 				   boolean_t may_replace);
241460cb568SAndrew Rybchenko 	efx_rc_t	(*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242460cb568SAndrew Rybchenko 	efx_rc_t	(*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
243460cb568SAndrew Rybchenko 	efx_rc_t	(*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
2443c838a9fSAndrew Rybchenko 				   boolean_t, boolean_t, boolean_t,
2453c838a9fSAndrew Rybchenko 				   uint8_t const *, int);
2463c838a9fSAndrew Rybchenko } efx_filter_ops_t;
2473c838a9fSAndrew Rybchenko 
248460cb568SAndrew Rybchenko extern	__checkReturn	efx_rc_t
2493c838a9fSAndrew Rybchenko efx_filter_reconfigure(
2503c838a9fSAndrew Rybchenko 	__in				efx_nic_t *enp,
2513c838a9fSAndrew Rybchenko 	__in_ecount(6)			uint8_t const *mac_addr,
2523c838a9fSAndrew Rybchenko 	__in				boolean_t all_unicst,
2533c838a9fSAndrew Rybchenko 	__in				boolean_t mulcst,
2543c838a9fSAndrew Rybchenko 	__in				boolean_t all_mulcst,
2553c838a9fSAndrew Rybchenko 	__in				boolean_t brdcst,
2563c838a9fSAndrew Rybchenko 	__in_ecount(6*count)		uint8_t const *addrs,
2573c838a9fSAndrew Rybchenko 	__in				int count);
2583c838a9fSAndrew Rybchenko 
2593c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_FILTER */
2603c838a9fSAndrew Rybchenko 
2613c838a9fSAndrew Rybchenko typedef struct efx_pktfilter_ops_s {
262460cb568SAndrew Rybchenko 	efx_rc_t	(*epfo_set)(efx_nic_t *,
2633c838a9fSAndrew Rybchenko 				boolean_t unicst,
2643c838a9fSAndrew Rybchenko 				boolean_t brdcast);
2653c838a9fSAndrew Rybchenko #if EFSYS_OPT_MCAST_FILTER_LIST
266460cb568SAndrew Rybchenko 	efx_rc_t	(*epfo_mcast_list_set)(efx_nic_t *,
267460cb568SAndrew Rybchenko 				uint8_t const *addrs, int count);
2683c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
269460cb568SAndrew Rybchenko 	efx_rc_t	(*epfo_mcast_all)(efx_nic_t *);
2703c838a9fSAndrew Rybchenko } efx_pktfilter_ops_t;
2713c838a9fSAndrew Rybchenko 
272e948693eSPhilip Paeps typedef struct efx_port_s {
273e948693eSPhilip Paeps 	efx_mac_type_t		ep_mac_type;
274e948693eSPhilip Paeps 	uint32_t  		ep_phy_type;
275e948693eSPhilip Paeps 	uint8_t			ep_port;
276e948693eSPhilip Paeps 	uint32_t		ep_mac_pdu;
277e948693eSPhilip Paeps 	uint8_t			ep_mac_addr[6];
278e948693eSPhilip Paeps 	efx_link_mode_t		ep_link_mode;
2793c838a9fSAndrew Rybchenko 	boolean_t		ep_all_unicst;
2803c838a9fSAndrew Rybchenko 	boolean_t		ep_mulcst;
2813c838a9fSAndrew Rybchenko 	boolean_t		ep_all_mulcst;
282e948693eSPhilip Paeps 	boolean_t		ep_brdcst;
283e948693eSPhilip Paeps 	unsigned int		ep_fcntl;
284e948693eSPhilip Paeps 	boolean_t		ep_fcntl_autoneg;
285e948693eSPhilip Paeps 	efx_oword_t		ep_multicst_hash[2];
2863c838a9fSAndrew Rybchenko 	uint8_t			ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
2873c838a9fSAndrew Rybchenko 						    EFX_MAC_MULTICAST_LIST_MAX];
2883c838a9fSAndrew Rybchenko 	uint32_t		ep_mulcst_addr_count;
289e948693eSPhilip Paeps #if EFSYS_OPT_LOOPBACK
290e948693eSPhilip Paeps 	efx_loopback_type_t	ep_loopback_type;
291e948693eSPhilip Paeps 	efx_link_mode_t		ep_loopback_link_mode;
292e948693eSPhilip Paeps #endif	/* EFSYS_OPT_LOOPBACK */
293e948693eSPhilip Paeps #if EFSYS_OPT_PHY_FLAGS
294e948693eSPhilip Paeps 	uint32_t		ep_phy_flags;
295e948693eSPhilip Paeps #endif	/* EFSYS_OPT_PHY_FLAGS */
296e948693eSPhilip Paeps #if EFSYS_OPT_PHY_LED_CONTROL
297e948693eSPhilip Paeps 	efx_phy_led_mode_t	ep_phy_led_mode;
298e948693eSPhilip Paeps #endif	/* EFSYS_OPT_PHY_LED_CONTROL */
299e948693eSPhilip Paeps 	efx_phy_media_type_t	ep_fixed_port_type;
300e948693eSPhilip Paeps 	efx_phy_media_type_t	ep_module_type;
301e948693eSPhilip Paeps 	uint32_t		ep_adv_cap_mask;
302e948693eSPhilip Paeps 	uint32_t		ep_lp_cap_mask;
303e948693eSPhilip Paeps 	uint32_t		ep_default_adv_cap_mask;
304e948693eSPhilip Paeps 	uint32_t		ep_phy_cap_mask;
305e948693eSPhilip Paeps #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
306e948693eSPhilip Paeps 	union {
307e948693eSPhilip Paeps 		struct {
308e948693eSPhilip Paeps 			unsigned int	bug10934_count;
309e948693eSPhilip Paeps 		} ep_txc43128;
310e948693eSPhilip Paeps 		struct {
311e948693eSPhilip Paeps 			unsigned int	bug17190_count;
312e948693eSPhilip Paeps 		} ep_qt2025c;
313e948693eSPhilip Paeps 	};
314e948693eSPhilip Paeps #endif
315e948693eSPhilip Paeps 	boolean_t		ep_mac_poll_needed; /* falcon only */
316e948693eSPhilip Paeps 	boolean_t		ep_mac_up; /* falcon only */
317e948693eSPhilip Paeps 	uint32_t		ep_fwver; /* falcon only */
318e948693eSPhilip Paeps 	boolean_t		ep_mac_drain;
319e948693eSPhilip Paeps 	boolean_t		ep_mac_stats_pending;
3203c838a9fSAndrew Rybchenko #if EFSYS_OPT_BIST
3213c838a9fSAndrew Rybchenko 	efx_bist_type_t		ep_current_bist;
322e948693eSPhilip Paeps #endif
323e948693eSPhilip Paeps 	efx_mac_ops_t		*ep_emop;
324e948693eSPhilip Paeps 	efx_phy_ops_t		*ep_epop;
325e948693eSPhilip Paeps } efx_port_t;
326e948693eSPhilip Paeps 
327e948693eSPhilip Paeps typedef struct efx_mon_ops_s {
328460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_reset)(efx_nic_t *);
329460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_reconfigure)(efx_nic_t *);
330e948693eSPhilip Paeps #if EFSYS_OPT_MON_STATS
331460cb568SAndrew Rybchenko 	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
332e948693eSPhilip Paeps 					    efx_mon_stat_value_t *);
333e948693eSPhilip Paeps #endif	/* EFSYS_OPT_MON_STATS */
334e948693eSPhilip Paeps } efx_mon_ops_t;
335e948693eSPhilip Paeps 
336e948693eSPhilip Paeps typedef struct efx_mon_s {
337e948693eSPhilip Paeps 	efx_mon_type_t	em_type;
338e948693eSPhilip Paeps 	efx_mon_ops_t	*em_emop;
339e948693eSPhilip Paeps } efx_mon_t;
340e948693eSPhilip Paeps 
3413c838a9fSAndrew Rybchenko typedef struct efx_intr_ops_s {
342460cb568SAndrew Rybchenko 	efx_rc_t	(*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
3433c838a9fSAndrew Rybchenko 	void		(*eio_enable)(efx_nic_t *);
3443c838a9fSAndrew Rybchenko 	void		(*eio_disable)(efx_nic_t *);
3453c838a9fSAndrew Rybchenko 	void		(*eio_disable_unlocked)(efx_nic_t *);
346460cb568SAndrew Rybchenko 	efx_rc_t	(*eio_trigger)(efx_nic_t *, unsigned int);
3473c838a9fSAndrew Rybchenko 	void		(*eio_fini)(efx_nic_t *);
3483c838a9fSAndrew Rybchenko } efx_intr_ops_t;
3493c838a9fSAndrew Rybchenko 
350e948693eSPhilip Paeps typedef struct efx_intr_s {
3513c838a9fSAndrew Rybchenko 	efx_intr_ops_t	*ei_eiop;
352e948693eSPhilip Paeps 	efsys_mem_t	*ei_esmp;
3533c838a9fSAndrew Rybchenko 	efx_intr_type_t	ei_type;
354e948693eSPhilip Paeps 	unsigned int	ei_level;
355e948693eSPhilip Paeps } efx_intr_t;
356e948693eSPhilip Paeps 
357e948693eSPhilip Paeps typedef struct efx_nic_ops_s {
358460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_probe)(efx_nic_t *);
359460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_reset)(efx_nic_t *);
361460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_init)(efx_nic_t *);
362460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
3643c838a9fSAndrew Rybchenko 					uint32_t *, size_t *);
365e948693eSPhilip Paeps #if EFSYS_OPT_DIAG
366460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
367460cb568SAndrew Rybchenko 	efx_rc_t	(*eno_register_test)(efx_nic_t *);
368e948693eSPhilip Paeps #endif	/* EFSYS_OPT_DIAG */
369e948693eSPhilip Paeps 	void		(*eno_fini)(efx_nic_t *);
370e948693eSPhilip Paeps 	void		(*eno_unprobe)(efx_nic_t *);
371e948693eSPhilip Paeps } efx_nic_ops_t;
372e948693eSPhilip Paeps 
3739ab060a7SAndrew Rybchenko #ifndef EFX_TXQ_LIMIT_TARGET
374e948693eSPhilip Paeps #define	EFX_TXQ_LIMIT_TARGET 259
3759ab060a7SAndrew Rybchenko #endif
3769ab060a7SAndrew Rybchenko #ifndef EFX_RXQ_LIMIT_TARGET
37775ba9e1eSAndrew Rybchenko #define	EFX_RXQ_LIMIT_TARGET 512
3789ab060a7SAndrew Rybchenko #endif
3799ab060a7SAndrew Rybchenko #ifndef EFX_TXQ_DC_SIZE
3809ab060a7SAndrew Rybchenko #define	EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
3819ab060a7SAndrew Rybchenko #endif
3829ab060a7SAndrew Rybchenko #ifndef EFX_RXQ_DC_SIZE
3839ab060a7SAndrew Rybchenko #define	EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
3849ab060a7SAndrew Rybchenko #endif
385e948693eSPhilip Paeps 
386e948693eSPhilip Paeps #if EFSYS_OPT_FILTER
387e948693eSPhilip Paeps 
3883c838a9fSAndrew Rybchenko typedef struct falconsiena_filter_spec_s {
3893c838a9fSAndrew Rybchenko 	uint8_t		fsfs_type;
3903c838a9fSAndrew Rybchenko 	uint32_t	fsfs_flags;
3913c838a9fSAndrew Rybchenko 	uint32_t	fsfs_dmaq_id;
3923c838a9fSAndrew Rybchenko 	uint32_t	fsfs_dword[3];
3933c838a9fSAndrew Rybchenko } falconsiena_filter_spec_t;
3943c838a9fSAndrew Rybchenko 
3953c838a9fSAndrew Rybchenko typedef enum falconsiena_filter_type_e {
3963c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_RX_TCP_FULL,	/* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
3973c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_RX_TCP_WILD,	/* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
3983c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_RX_UDP_FULL,	/* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
3993c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_RX_UDP_WILD,	/* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
400e948693eSPhilip Paeps 
401e948693eSPhilip Paeps #if EFSYS_OPT_SIENA
4023c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_RX_MAC_FULL,	/* Ethernet {dMAC,VLAN} */
4033c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_RX_MAC_WILD,	/* Ethernet {dMAC,   -} */
404e948693eSPhilip Paeps 
4053c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TX_TCP_FULL,		/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
4063c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TX_TCP_WILD,		/* TCP/IPv4 {  -,   -,sIP,sTCP} */
4073c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TX_UDP_FULL,		/* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
4083c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TX_UDP_WILD,		/* UDP/IPv4 source (host, port) */
409e948693eSPhilip Paeps 
4103c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TX_MAC_FULL,		/* Ethernet source (MAC address, VLAN ID) */
4113c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TX_MAC_WILD,		/* Ethernet source (MAC address) */
412e948693eSPhilip Paeps #endif /* EFSYS_OPT_SIENA */
413e948693eSPhilip Paeps 
4143c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_NTYPES
4153c838a9fSAndrew Rybchenko } falconsiena_filter_type_t;
416e948693eSPhilip Paeps 
4173c838a9fSAndrew Rybchenko typedef enum falconsiena_filter_tbl_id_e {
4183c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TBL_RX_IP = 0,
4193c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TBL_RX_MAC,
4203c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TBL_TX_IP,
4213c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_TBL_TX_MAC,
4223c838a9fSAndrew Rybchenko 	EFX_FS_FILTER_NTBLS
4233c838a9fSAndrew Rybchenko } falconsiena_filter_tbl_id_t;
424e948693eSPhilip Paeps 
4253c838a9fSAndrew Rybchenko typedef struct falconsiena_filter_tbl_s {
4263c838a9fSAndrew Rybchenko 	int				fsft_size;	/* number of entries */
4273c838a9fSAndrew Rybchenko 	int				fsft_used;	/* active count */
4283c838a9fSAndrew Rybchenko 	uint32_t			*fsft_bitmap;	/* active bitmap */
4293c838a9fSAndrew Rybchenko 	falconsiena_filter_spec_t	*fsft_spec;	/* array of saved specs */
4303c838a9fSAndrew Rybchenko } falconsiena_filter_tbl_t;
4313c838a9fSAndrew Rybchenko 
4323c838a9fSAndrew Rybchenko typedef struct falconsiena_filter_s {
4333c838a9fSAndrew Rybchenko 	falconsiena_filter_tbl_t	fsf_tbl[EFX_FS_FILTER_NTBLS];
4343c838a9fSAndrew Rybchenko 	unsigned int			fsf_depth[EFX_FS_FILTER_NTYPES];
4353c838a9fSAndrew Rybchenko } falconsiena_filter_t;
436e948693eSPhilip Paeps 
437e948693eSPhilip Paeps typedef struct efx_filter_s {
4383c838a9fSAndrew Rybchenko #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
4393c838a9fSAndrew Rybchenko 	falconsiena_filter_t	*ef_falconsiena_filter;
4403c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
4413c838a9fSAndrew Rybchenko #if EFSYS_OPT_HUNTINGTON
4423c838a9fSAndrew Rybchenko 	hunt_filter_table_t	*ef_hunt_filter_table;
4433c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_HUNTINGTON */
444e948693eSPhilip Paeps } efx_filter_t;
445e948693eSPhilip Paeps 
446e948693eSPhilip Paeps extern			void
4473c838a9fSAndrew Rybchenko falconsiena_filter_tbl_clear(
448e948693eSPhilip Paeps 	__in		efx_nic_t *enp,
4493c838a9fSAndrew Rybchenko 	__in		falconsiena_filter_tbl_id_t tbl);
450e948693eSPhilip Paeps 
451e948693eSPhilip Paeps #endif	/* EFSYS_OPT_FILTER */
452e948693eSPhilip Paeps 
4533c838a9fSAndrew Rybchenko #if EFSYS_OPT_MCDI
4543c838a9fSAndrew Rybchenko 
4553c838a9fSAndrew Rybchenko typedef struct efx_mcdi_ops_s {
456460cb568SAndrew Rybchenko 	efx_rc_t	(*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
4573c838a9fSAndrew Rybchenko 	void		(*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
4583c838a9fSAndrew Rybchenko 					unsigned int, boolean_t, boolean_t);
4593c838a9fSAndrew Rybchenko 	boolean_t	(*emco_request_poll)(efx_nic_t *);
4603c838a9fSAndrew Rybchenko 	void		(*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
461460cb568SAndrew Rybchenko 	efx_rc_t	(*emco_poll_reboot)(efx_nic_t *);
4623c838a9fSAndrew Rybchenko 	void		(*emco_fini)(efx_nic_t *);
463460cb568SAndrew Rybchenko 	efx_rc_t	(*emco_fw_update_supported)(efx_nic_t *, boolean_t *);
464460cb568SAndrew Rybchenko 	efx_rc_t	(*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
465d486ce4bSAndrew Rybchenko 	efx_rc_t	(*emco_link_control_supported)(efx_nic_t *, boolean_t *);
4663c838a9fSAndrew Rybchenko } efx_mcdi_ops_t;
4673c838a9fSAndrew Rybchenko 
4683c838a9fSAndrew Rybchenko typedef struct efx_mcdi_s {
4693c838a9fSAndrew Rybchenko 	efx_mcdi_ops_t			*em_emcop;
4703c838a9fSAndrew Rybchenko 	const efx_mcdi_transport_t	*em_emtp;
4713c838a9fSAndrew Rybchenko 	efx_mcdi_iface_t		em_emip;
4723c838a9fSAndrew Rybchenko } efx_mcdi_t;
4733c838a9fSAndrew Rybchenko 
4743c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_MCDI */
4753c838a9fSAndrew Rybchenko 
476e948693eSPhilip Paeps #if EFSYS_OPT_NVRAM
477e948693eSPhilip Paeps typedef struct efx_nvram_ops_s {
478e948693eSPhilip Paeps #if EFSYS_OPT_DIAG
479460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_test)(efx_nic_t *);
480e948693eSPhilip Paeps #endif	/* EFSYS_OPT_DIAG */
481460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
482460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
483e948693eSPhilip Paeps 					    uint32_t *, uint16_t *);
484460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
485460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
486e948693eSPhilip Paeps 					    unsigned int, caddr_t, size_t);
487460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_erase)(efx_nic_t *, efx_nvram_type_t);
488460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
489e948693eSPhilip Paeps 					    unsigned int, caddr_t, size_t);
490e948693eSPhilip Paeps 	void		(*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
491460cb568SAndrew Rybchenko 	efx_rc_t	(*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
492460cb568SAndrew Rybchenko 					    uint16_t *);
493e948693eSPhilip Paeps 
494e948693eSPhilip Paeps } efx_nvram_ops_t;
495e948693eSPhilip Paeps #endif /* EFSYS_OPT_NVRAM */
496e948693eSPhilip Paeps 
497e948693eSPhilip Paeps #if EFSYS_OPT_VPD
498e948693eSPhilip Paeps typedef struct efx_vpd_ops_s {
499460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_init)(efx_nic_t *);
500460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_size)(efx_nic_t *, size_t *);
501460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_read)(efx_nic_t *, caddr_t, size_t);
502460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
503460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
504460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_get)(efx_nic_t *, caddr_t, size_t,
505460cb568SAndrew Rybchenko 					efx_vpd_value_t *);
506460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_set)(efx_nic_t *, caddr_t, size_t,
507460cb568SAndrew Rybchenko 					efx_vpd_value_t *);
508460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_next)(efx_nic_t *, caddr_t, size_t,
509460cb568SAndrew Rybchenko 					efx_vpd_value_t *, unsigned int *);
510460cb568SAndrew Rybchenko 	efx_rc_t	(*evpdo_write)(efx_nic_t *, caddr_t, size_t);
511e948693eSPhilip Paeps 	void		(*evpdo_fini)(efx_nic_t *);
512e948693eSPhilip Paeps } efx_vpd_ops_t;
513e948693eSPhilip Paeps #endif	/* EFSYS_OPT_VPD */
514e948693eSPhilip Paeps 
5153c838a9fSAndrew Rybchenko #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
5163c838a9fSAndrew Rybchenko 
517460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5183c838a9fSAndrew Rybchenko efx_mcdi_nvram_partitions(
5193c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5203c838a9fSAndrew Rybchenko 	__out_bcount(size)	caddr_t data,
5213c838a9fSAndrew Rybchenko 	__in			size_t size,
5223c838a9fSAndrew Rybchenko 	__out			unsigned int *npartnp);
5233c838a9fSAndrew Rybchenko 
524460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5253c838a9fSAndrew Rybchenko efx_mcdi_nvram_metadata(
5263c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5273c838a9fSAndrew Rybchenko 	__in			uint32_t partn,
5283c838a9fSAndrew Rybchenko 	__out			uint32_t *subtypep,
5293c838a9fSAndrew Rybchenko 	__out_ecount(4)		uint16_t version[4],
5303c838a9fSAndrew Rybchenko 	__out_bcount_opt(size)	char *descp,
5313c838a9fSAndrew Rybchenko 	__in			size_t size);
5323c838a9fSAndrew Rybchenko 
533460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5343c838a9fSAndrew Rybchenko efx_mcdi_nvram_info(
5353c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5363c838a9fSAndrew Rybchenko 	__in			uint32_t partn,
5373c838a9fSAndrew Rybchenko 	__out_opt		size_t *sizep,
5383c838a9fSAndrew Rybchenko 	__out_opt		uint32_t *addressp,
539*9cb71b16SAndrew Rybchenko 	__out_opt		uint32_t *erase_sizep,
540*9cb71b16SAndrew Rybchenko 	__out_opt		uint32_t *write_sizep);
5413c838a9fSAndrew Rybchenko 
542460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5433c838a9fSAndrew Rybchenko efx_mcdi_nvram_update_start(
5443c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5453c838a9fSAndrew Rybchenko 	__in			uint32_t partn);
5463c838a9fSAndrew Rybchenko 
547460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5483c838a9fSAndrew Rybchenko efx_mcdi_nvram_read(
5493c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5503c838a9fSAndrew Rybchenko 	__in			uint32_t partn,
5513c838a9fSAndrew Rybchenko 	__in			uint32_t offset,
5523c838a9fSAndrew Rybchenko 	__out_bcount(size)	caddr_t data,
5533c838a9fSAndrew Rybchenko 	__in			size_t size);
5543c838a9fSAndrew Rybchenko 
555460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5563c838a9fSAndrew Rybchenko efx_mcdi_nvram_erase(
5573c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5583c838a9fSAndrew Rybchenko 	__in			uint32_t partn,
5593c838a9fSAndrew Rybchenko 	__in			uint32_t offset,
5603c838a9fSAndrew Rybchenko 	__in			size_t size);
5613c838a9fSAndrew Rybchenko 
562460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5633c838a9fSAndrew Rybchenko efx_mcdi_nvram_write(
5643c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5653c838a9fSAndrew Rybchenko 	__in			uint32_t partn,
5663c838a9fSAndrew Rybchenko 	__in			uint32_t offset,
5673c838a9fSAndrew Rybchenko 	__out_bcount(size)	caddr_t data,
5683c838a9fSAndrew Rybchenko 	__in			size_t size);
5693c838a9fSAndrew Rybchenko 
570460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5713c838a9fSAndrew Rybchenko efx_mcdi_nvram_update_finish(
5723c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5733c838a9fSAndrew Rybchenko 	__in			uint32_t partn,
5743c838a9fSAndrew Rybchenko 	__in			boolean_t reboot);
5753c838a9fSAndrew Rybchenko 
5763c838a9fSAndrew Rybchenko #if EFSYS_OPT_DIAG
5773c838a9fSAndrew Rybchenko 
578460cb568SAndrew Rybchenko 	__checkReturn		efx_rc_t
5793c838a9fSAndrew Rybchenko efx_mcdi_nvram_test(
5803c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
5813c838a9fSAndrew Rybchenko 	__in			uint32_t partn);
5823c838a9fSAndrew Rybchenko 
5833c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_DIAG */
5843c838a9fSAndrew Rybchenko 
5853c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
5863c838a9fSAndrew Rybchenko 
5873c838a9fSAndrew Rybchenko typedef struct efx_drv_cfg_s {
5883c838a9fSAndrew Rybchenko 	uint32_t		edc_min_vi_count;
5893c838a9fSAndrew Rybchenko 	uint32_t		edc_max_vi_count;
5903c838a9fSAndrew Rybchenko 
5913c838a9fSAndrew Rybchenko 	uint32_t		edc_max_piobuf_count;
5923c838a9fSAndrew Rybchenko 	uint32_t		edc_pio_alloc_size;
5933c838a9fSAndrew Rybchenko } efx_drv_cfg_t;
5943c838a9fSAndrew Rybchenko 
595e948693eSPhilip Paeps struct efx_nic_s {
596e948693eSPhilip Paeps 	uint32_t		en_magic;
597e948693eSPhilip Paeps 	efx_family_t		en_family;
598e948693eSPhilip Paeps 	uint32_t		en_features;
599e948693eSPhilip Paeps 	efsys_identifier_t	*en_esip;
600e948693eSPhilip Paeps 	efsys_lock_t		*en_eslp;
601e948693eSPhilip Paeps 	efsys_bar_t 		*en_esbp;
602e948693eSPhilip Paeps 	unsigned int		en_mod_flags;
603e948693eSPhilip Paeps 	unsigned int		en_reset_flags;
604e948693eSPhilip Paeps 	efx_nic_cfg_t		en_nic_cfg;
6053c838a9fSAndrew Rybchenko 	efx_drv_cfg_t		en_drv_cfg;
606e948693eSPhilip Paeps 	efx_port_t		en_port;
607e948693eSPhilip Paeps 	efx_mon_t		en_mon;
608e948693eSPhilip Paeps 	efx_intr_t		en_intr;
609e948693eSPhilip Paeps 	uint32_t		en_ev_qcount;
610e948693eSPhilip Paeps 	uint32_t		en_rx_qcount;
611e948693eSPhilip Paeps 	uint32_t		en_tx_qcount;
612e948693eSPhilip Paeps 	efx_nic_ops_t		*en_enop;
6133c838a9fSAndrew Rybchenko 	efx_ev_ops_t		*en_eevop;
6143c838a9fSAndrew Rybchenko 	efx_tx_ops_t		*en_etxop;
6153c838a9fSAndrew Rybchenko 	efx_rx_ops_t		*en_erxop;
616e948693eSPhilip Paeps #if EFSYS_OPT_FILTER
617e948693eSPhilip Paeps 	efx_filter_t		en_filter;
6183c838a9fSAndrew Rybchenko 	efx_filter_ops_t	*en_efop;
619e948693eSPhilip Paeps #endif	/* EFSYS_OPT_FILTER */
6203c838a9fSAndrew Rybchenko 	efx_pktfilter_ops_t	*en_epfop;
6213c838a9fSAndrew Rybchenko #if EFSYS_OPT_MCDI
6223c838a9fSAndrew Rybchenko 	efx_mcdi_t		en_mcdi;
6233c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_MCDI */
624e948693eSPhilip Paeps #if EFSYS_OPT_NVRAM
625e948693eSPhilip Paeps 	efx_nvram_type_t	en_nvram_locked;
626e948693eSPhilip Paeps 	efx_nvram_ops_t		*en_envop;
627e948693eSPhilip Paeps #endif	/* EFSYS_OPT_NVRAM */
628e948693eSPhilip Paeps #if EFSYS_OPT_VPD
629e948693eSPhilip Paeps 	efx_vpd_ops_t		*en_evpdop;
630e948693eSPhilip Paeps #endif	/* EFSYS_OPT_VPD */
6313c838a9fSAndrew Rybchenko #if EFSYS_OPT_RX_SCALE
6323c838a9fSAndrew Rybchenko 	efx_rx_hash_support_t	en_hash_support;
6333c838a9fSAndrew Rybchenko 	efx_rx_scale_support_t	en_rss_support;
6343c838a9fSAndrew Rybchenko 	uint32_t		en_rss_context;
6353c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_RX_SCALE */
6363c838a9fSAndrew Rybchenko 	uint32_t		en_vport_id;
637e948693eSPhilip Paeps 	union {
638e948693eSPhilip Paeps #if EFSYS_OPT_FALCON
639e948693eSPhilip Paeps 		struct {
640e948693eSPhilip Paeps 			falcon_spi_dev_t	enu_fsd[FALCON_SPI_NTYPES];
641e948693eSPhilip Paeps 			falcon_i2c_t		enu_fip;
642e948693eSPhilip Paeps 			boolean_t		enu_i2c_locked;
643e948693eSPhilip Paeps #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
644e948693eSPhilip Paeps 			const uint8_t		*enu_forced_cfg;
645e948693eSPhilip Paeps #endif	/* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
646e948693eSPhilip Paeps 			uint8_t			enu_mon_devid;
647e948693eSPhilip Paeps #if EFSYS_OPT_PCIE_TUNE
648e948693eSPhilip Paeps 			unsigned int 		enu_nlanes;
649e948693eSPhilip Paeps #endif	/* EFSYS_OPT_PCIE_TUNE */
650e948693eSPhilip Paeps 			uint16_t		enu_board_rev;
651e948693eSPhilip Paeps 			boolean_t		enu_internal_sram;
652e948693eSPhilip Paeps 			uint8_t			enu_sram_num_bank;
653e948693eSPhilip Paeps 			uint8_t			enu_sram_bank_size;
654e948693eSPhilip Paeps 		} falcon;
655e948693eSPhilip Paeps #endif	/* EFSYS_OPT_FALCON */
656e948693eSPhilip Paeps #if EFSYS_OPT_SIENA
657e948693eSPhilip Paeps 		struct {
658e948693eSPhilip Paeps #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
659e948693eSPhilip Paeps 			unsigned int		enu_partn_mask;
660e948693eSPhilip Paeps #endif	/* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
661e948693eSPhilip Paeps #if EFSYS_OPT_VPD
662e948693eSPhilip Paeps 			caddr_t			enu_svpd;
663e948693eSPhilip Paeps 			size_t			enu_svpd_length;
664e948693eSPhilip Paeps #endif	/* EFSYS_OPT_VPD */
6653c838a9fSAndrew Rybchenko 			int			enu_unused;
666e948693eSPhilip Paeps 		} siena;
667e948693eSPhilip Paeps #endif	/* EFSYS_OPT_SIENA */
6683c838a9fSAndrew Rybchenko #if EFSYS_OPT_HUNTINGTON
6693c838a9fSAndrew Rybchenko 		struct {
6703c838a9fSAndrew Rybchenko 			int			enu_vi_base;
6713c838a9fSAndrew Rybchenko 			int			enu_vi_count;
6723c838a9fSAndrew Rybchenko #if EFSYS_OPT_VPD
6733c838a9fSAndrew Rybchenko 			caddr_t			enu_svpd;
6743c838a9fSAndrew Rybchenko 			size_t			enu_svpd_length;
6753c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_VPD */
6763c838a9fSAndrew Rybchenko 			efx_piobuf_handle_t	enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
6773c838a9fSAndrew Rybchenko 			uint32_t		enu_piobuf_count;
6783c838a9fSAndrew Rybchenko 			uint32_t		enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
6793c838a9fSAndrew Rybchenko 			uint32_t		enu_pio_write_vi_base;
6803c838a9fSAndrew Rybchenko 			/* Memory BAR mapping regions */
6813c838a9fSAndrew Rybchenko 			uint32_t		enu_uc_mem_map_offset;
6823c838a9fSAndrew Rybchenko 			size_t			enu_uc_mem_map_size;
6833c838a9fSAndrew Rybchenko 			uint32_t		enu_wc_mem_map_offset;
6843c838a9fSAndrew Rybchenko 			size_t			enu_wc_mem_map_size;
6853c838a9fSAndrew Rybchenko 		} hunt;
6863c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_HUNTINGTON */
687e948693eSPhilip Paeps 	} en_u;
688e948693eSPhilip Paeps };
689e948693eSPhilip Paeps 
690e948693eSPhilip Paeps 
691e948693eSPhilip Paeps #define	EFX_NIC_MAGIC	0x02121996
692e948693eSPhilip Paeps 
693e948693eSPhilip Paeps typedef	boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
694e948693eSPhilip Paeps     const efx_ev_callbacks_t *, void *);
695e948693eSPhilip Paeps 
6963c838a9fSAndrew Rybchenko typedef struct efx_evq_rxq_state_s {
6973c838a9fSAndrew Rybchenko 	unsigned int			eers_rx_read_ptr;
6983c838a9fSAndrew Rybchenko 	unsigned int			eers_rx_mask;
6993c838a9fSAndrew Rybchenko } efx_evq_rxq_state_t;
7003c838a9fSAndrew Rybchenko 
701e948693eSPhilip Paeps struct efx_evq_s {
702e948693eSPhilip Paeps 	uint32_t			ee_magic;
703e948693eSPhilip Paeps 	efx_nic_t			*ee_enp;
704e948693eSPhilip Paeps 	unsigned int			ee_index;
705e948693eSPhilip Paeps 	unsigned int			ee_mask;
706e948693eSPhilip Paeps 	efsys_mem_t			*ee_esmp;
707e948693eSPhilip Paeps #if EFSYS_OPT_QSTATS
708e948693eSPhilip Paeps 	uint32_t			ee_stat[EV_NQSTATS];
709e948693eSPhilip Paeps #endif	/* EFSYS_OPT_QSTATS */
7103c838a9fSAndrew Rybchenko 
7113c838a9fSAndrew Rybchenko 	efx_ev_handler_t		ee_rx;
7123c838a9fSAndrew Rybchenko 	efx_ev_handler_t		ee_tx;
7133c838a9fSAndrew Rybchenko 	efx_ev_handler_t		ee_driver;
7143c838a9fSAndrew Rybchenko 	efx_ev_handler_t		ee_global;
7153c838a9fSAndrew Rybchenko 	efx_ev_handler_t		ee_drv_gen;
7163c838a9fSAndrew Rybchenko #if EFSYS_OPT_MCDI
7173c838a9fSAndrew Rybchenko 	efx_ev_handler_t		ee_mcdi;
7183c838a9fSAndrew Rybchenko #endif	/* EFSYS_OPT_MCDI */
7193c838a9fSAndrew Rybchenko 
7203c838a9fSAndrew Rybchenko 	efx_evq_rxq_state_t		ee_rxq_state[EFX_EV_RX_NLABELS];
721e948693eSPhilip Paeps };
722e948693eSPhilip Paeps 
723e948693eSPhilip Paeps #define	EFX_EVQ_MAGIC	0x08081997
724e948693eSPhilip Paeps 
725af9078c3SAndrew Rybchenko #define	EFX_EVQ_FALCON_TIMER_QUANTUM_NS	4968 /* 621 cycles */
726af9078c3SAndrew Rybchenko #define	EFX_EVQ_SIENA_TIMER_QUANTUM_NS	6144 /* 768 cycles */
727e948693eSPhilip Paeps 
728e948693eSPhilip Paeps struct efx_rxq_s {
729e948693eSPhilip Paeps 	uint32_t			er_magic;
730e948693eSPhilip Paeps 	efx_nic_t			*er_enp;
7313c838a9fSAndrew Rybchenko 	efx_evq_t			*er_eep;
732e948693eSPhilip Paeps 	unsigned int			er_index;
7333c838a9fSAndrew Rybchenko 	unsigned int			er_label;
734e948693eSPhilip Paeps 	unsigned int			er_mask;
735e948693eSPhilip Paeps 	efsys_mem_t			*er_esmp;
736e948693eSPhilip Paeps };
737e948693eSPhilip Paeps 
738e948693eSPhilip Paeps #define	EFX_RXQ_MAGIC	0x15022005
739e948693eSPhilip Paeps 
740e948693eSPhilip Paeps struct efx_txq_s {
741e948693eSPhilip Paeps 	uint32_t			et_magic;
742e948693eSPhilip Paeps 	efx_nic_t			*et_enp;
743e948693eSPhilip Paeps 	unsigned int			et_index;
744e948693eSPhilip Paeps 	unsigned int			et_mask;
745e948693eSPhilip Paeps 	efsys_mem_t			*et_esmp;
7463c838a9fSAndrew Rybchenko #if EFSYS_OPT_HUNTINGTON
7473c838a9fSAndrew Rybchenko 	uint32_t			et_pio_bufnum;
7483c838a9fSAndrew Rybchenko 	uint32_t			et_pio_blknum;
7493c838a9fSAndrew Rybchenko 	uint32_t			et_pio_write_offset;
7503c838a9fSAndrew Rybchenko 	uint32_t			et_pio_offset;
7513c838a9fSAndrew Rybchenko 	size_t				et_pio_size;
7523c838a9fSAndrew Rybchenko #endif
753e948693eSPhilip Paeps #if EFSYS_OPT_QSTATS
754e948693eSPhilip Paeps 	uint32_t			et_stat[TX_NQSTATS];
755e948693eSPhilip Paeps #endif	/* EFSYS_OPT_QSTATS */
756e948693eSPhilip Paeps };
757e948693eSPhilip Paeps 
758e948693eSPhilip Paeps #define	EFX_TXQ_MAGIC	0x05092005
759e948693eSPhilip Paeps 
760e948693eSPhilip Paeps #define	EFX_MAC_ADDR_COPY(_dst, _src)					\
761e948693eSPhilip Paeps 	do {								\
762e948693eSPhilip Paeps 		(_dst)[0] = (_src)[0];					\
763e948693eSPhilip Paeps 		(_dst)[1] = (_src)[1];					\
764e948693eSPhilip Paeps 		(_dst)[2] = (_src)[2];					\
765e948693eSPhilip Paeps 		(_dst)[3] = (_src)[3];					\
766e948693eSPhilip Paeps 		(_dst)[4] = (_src)[4];					\
767e948693eSPhilip Paeps 		(_dst)[5] = (_src)[5];					\
768e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
769e948693eSPhilip Paeps 	} while (B_FALSE)
770e948693eSPhilip Paeps 
7713c838a9fSAndrew Rybchenko #define	EFX_MAC_BROADCAST_ADDR_SET(_dst)				\
7723c838a9fSAndrew Rybchenko 	do {								\
7733c838a9fSAndrew Rybchenko 		uint16_t *_d = (uint16_t *)(_dst);			\
7743c838a9fSAndrew Rybchenko 		_d[0] = 0xffff;						\
7753c838a9fSAndrew Rybchenko 		_d[1] = 0xffff;						\
7763c838a9fSAndrew Rybchenko 		_d[2] = 0xffff;						\
7773c838a9fSAndrew Rybchenko 	_NOTE(CONSTANTCONDITION)					\
7783c838a9fSAndrew Rybchenko 	} while (B_FALSE)
7793c838a9fSAndrew Rybchenko 
780e948693eSPhilip Paeps #if EFSYS_OPT_CHECK_REG
781e948693eSPhilip Paeps #define	EFX_CHECK_REG(_enp, _reg)					\
782e948693eSPhilip Paeps 	do {								\
7833c838a9fSAndrew Rybchenko 		const char *name = #_reg;				\
784e948693eSPhilip Paeps 		char min = name[4];					\
785e948693eSPhilip Paeps 		char max = name[5];					\
786e948693eSPhilip Paeps 		char rev;						\
787e948693eSPhilip Paeps 									\
788e948693eSPhilip Paeps 		switch ((_enp)->en_family) {				\
789e948693eSPhilip Paeps 		case EFX_FAMILY_FALCON:					\
790e948693eSPhilip Paeps 			rev = 'B';					\
791e948693eSPhilip Paeps 			break;						\
792e948693eSPhilip Paeps 									\
793e948693eSPhilip Paeps 		case EFX_FAMILY_SIENA:					\
794e948693eSPhilip Paeps 			rev = 'C';					\
795e948693eSPhilip Paeps 			break;						\
796e948693eSPhilip Paeps 									\
7973c838a9fSAndrew Rybchenko 		case EFX_FAMILY_HUNTINGTON:				\
7983c838a9fSAndrew Rybchenko 			rev = 'D';					\
7993c838a9fSAndrew Rybchenko 			break;						\
8003c838a9fSAndrew Rybchenko 									\
801e948693eSPhilip Paeps 		default:						\
802e948693eSPhilip Paeps 			rev = '?';					\
803e948693eSPhilip Paeps 			break;						\
804e948693eSPhilip Paeps 		}							\
805e948693eSPhilip Paeps 									\
806e948693eSPhilip Paeps 		EFSYS_ASSERT3S(rev, >=, min);				\
807e948693eSPhilip Paeps 		EFSYS_ASSERT3S(rev, <=, max);				\
808e948693eSPhilip Paeps 									\
809e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
810e948693eSPhilip Paeps 	} while (B_FALSE)
811e948693eSPhilip Paeps #else
812e948693eSPhilip Paeps #define	EFX_CHECK_REG(_enp, _reg) do {					\
813e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
814e948693eSPhilip Paeps 	} while(B_FALSE)
815e948693eSPhilip Paeps #endif
816e948693eSPhilip Paeps 
817e948693eSPhilip Paeps #define	EFX_BAR_READD(_enp, _reg, _edp, _lock)				\
818e948693eSPhilip Paeps 	do {								\
819e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
820e948693eSPhilip Paeps 		EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,		\
821e948693eSPhilip Paeps 		    (_edp), (_lock));					\
822e948693eSPhilip Paeps 		EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,	\
823e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
824e948693eSPhilip Paeps 		    uint32_t, (_edp)->ed_u32[0]);			\
825e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
826e948693eSPhilip Paeps 	} while (B_FALSE)
827e948693eSPhilip Paeps 
828e948693eSPhilip Paeps #define	EFX_BAR_WRITED(_enp, _reg, _edp, _lock)				\
829e948693eSPhilip Paeps 	do {								\
830e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
831e948693eSPhilip Paeps 		EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,	\
832e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
833e948693eSPhilip Paeps 		    uint32_t, (_edp)->ed_u32[0]);			\
834e948693eSPhilip Paeps 		EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,	\
835e948693eSPhilip Paeps 		    (_edp), (_lock));					\
836e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
837e948693eSPhilip Paeps 	} while (B_FALSE)
838e948693eSPhilip Paeps 
839e948693eSPhilip Paeps #define	EFX_BAR_READQ(_enp, _reg, _eqp)					\
840e948693eSPhilip Paeps 	do {								\
841e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
842e948693eSPhilip Paeps 		EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,		\
843e948693eSPhilip Paeps 		    (_eqp));						\
844e948693eSPhilip Paeps 		EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,	\
845e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
846e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[1],			\
847e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[0]);			\
848e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
849e948693eSPhilip Paeps 	} while (B_FALSE)
850e948693eSPhilip Paeps 
851e948693eSPhilip Paeps #define	EFX_BAR_WRITEQ(_enp, _reg, _eqp)				\
852e948693eSPhilip Paeps 	do {								\
853e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
854e948693eSPhilip Paeps 		EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,	\
855e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
856e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[1],			\
857e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[0]);			\
858e948693eSPhilip Paeps 		EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,	\
859e948693eSPhilip Paeps 		    (_eqp));						\
860e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
861e948693eSPhilip Paeps 	} while (B_FALSE)
862e948693eSPhilip Paeps 
863e948693eSPhilip Paeps #define	EFX_BAR_READO(_enp, _reg, _eop)					\
864e948693eSPhilip Paeps 	do {								\
865e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
866e948693eSPhilip Paeps 		EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,		\
867e948693eSPhilip Paeps 		    (_eop), B_TRUE);					\
868e948693eSPhilip Paeps 		EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,	\
869e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
870e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[3],			\
871e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[2],			\
872e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[1],			\
873e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[0]);			\
874e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
875e948693eSPhilip Paeps 	} while (B_FALSE)
876e948693eSPhilip Paeps 
877e948693eSPhilip Paeps #define	EFX_BAR_WRITEO(_enp, _reg, _eop)				\
878e948693eSPhilip Paeps 	do {								\
879e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
880e948693eSPhilip Paeps 		EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,	\
881e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
882e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[3],			\
883e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[2],			\
884e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[1],			\
885e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[0]);			\
886e948693eSPhilip Paeps 		EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,	\
887e948693eSPhilip Paeps 		    (_eop), B_TRUE);					\
888e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
889e948693eSPhilip Paeps 	} while (B_FALSE)
890e948693eSPhilip Paeps 
891e948693eSPhilip Paeps #define	EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)		\
892e948693eSPhilip Paeps 	do {								\
893e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
894e948693eSPhilip Paeps 		EFSYS_BAR_READD((_enp)->en_esbp,			\
895e948693eSPhilip Paeps 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
896e948693eSPhilip Paeps 		    (_edp), (_lock));					\
897e948693eSPhilip Paeps 		EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,	\
898e948693eSPhilip Paeps 		    uint32_t, (_index),					\
899e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
900e948693eSPhilip Paeps 		    uint32_t, (_edp)->ed_u32[0]);			\
901e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
902e948693eSPhilip Paeps 	} while (B_FALSE)
903e948693eSPhilip Paeps 
904e948693eSPhilip Paeps #define	EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)		\
905e948693eSPhilip Paeps 	do {								\
906e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
907e948693eSPhilip Paeps 		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
908e948693eSPhilip Paeps 		    uint32_t, (_index),					\
909e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
910e948693eSPhilip Paeps 		    uint32_t, (_edp)->ed_u32[0]);			\
911e948693eSPhilip Paeps 		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
912e948693eSPhilip Paeps 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
913e948693eSPhilip Paeps 		    (_edp), (_lock));					\
914e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
915e948693eSPhilip Paeps 	} while (B_FALSE)
916e948693eSPhilip Paeps 
9173c838a9fSAndrew Rybchenko #define	EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)		\
9183c838a9fSAndrew Rybchenko 	do {								\
9193c838a9fSAndrew Rybchenko 		EFX_CHECK_REG((_enp), (_reg));				\
9203c838a9fSAndrew Rybchenko 		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
9213c838a9fSAndrew Rybchenko 		    uint32_t, (_index),					\
9223c838a9fSAndrew Rybchenko 		    uint32_t, _reg ## _OFST,				\
9233c838a9fSAndrew Rybchenko 		    uint32_t, (_edp)->ed_u32[0]);			\
9243c838a9fSAndrew Rybchenko 		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
9253c838a9fSAndrew Rybchenko 		    (_reg ## _OFST +					\
9263c838a9fSAndrew Rybchenko 		    (2 * sizeof (efx_dword_t)) + 			\
9273c838a9fSAndrew Rybchenko 		    ((_index) * _reg ## _STEP)),			\
9283c838a9fSAndrew Rybchenko 		    (_edp), (_lock));					\
9293c838a9fSAndrew Rybchenko 	_NOTE(CONSTANTCONDITION)					\
9303c838a9fSAndrew Rybchenko 	} while (B_FALSE)
9313c838a9fSAndrew Rybchenko 
932e948693eSPhilip Paeps #define	EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)		\
933e948693eSPhilip Paeps 	do {								\
934e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
935e948693eSPhilip Paeps 		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
936e948693eSPhilip Paeps 		    uint32_t, (_index),					\
937e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
938e948693eSPhilip Paeps 		    uint32_t, (_edp)->ed_u32[0]);			\
939e948693eSPhilip Paeps 		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
940e948693eSPhilip Paeps 		    (_reg ## _OFST +					\
941e948693eSPhilip Paeps 		    (3 * sizeof (efx_dword_t)) + 			\
942e948693eSPhilip Paeps 		    ((_index) * _reg ## _STEP)),			\
943e948693eSPhilip Paeps 		    (_edp), (_lock));					\
944e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
945e948693eSPhilip Paeps 	} while (B_FALSE)
946e948693eSPhilip Paeps 
947e948693eSPhilip Paeps #define	EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)			\
948e948693eSPhilip Paeps 	do {								\
949e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
950e948693eSPhilip Paeps 		EFSYS_BAR_READQ((_enp)->en_esbp,			\
951e948693eSPhilip Paeps 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
952e948693eSPhilip Paeps 		    (_eqp));						\
953e948693eSPhilip Paeps 		EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,	\
954e948693eSPhilip Paeps 		    uint32_t, (_index),					\
955e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
956e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[1],			\
957e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[0]);			\
958e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
959e948693eSPhilip Paeps 	} while (B_FALSE)
960e948693eSPhilip Paeps 
961e948693eSPhilip Paeps #define	EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)			\
962e948693eSPhilip Paeps 	do {								\
963e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
964e948693eSPhilip Paeps 		EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,	\
965e948693eSPhilip Paeps 		    uint32_t, (_index),					\
966e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
967e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[1],			\
968e948693eSPhilip Paeps 		    uint32_t, (_eqp)->eq_u32[0]);			\
969e948693eSPhilip Paeps 		EFSYS_BAR_WRITEQ((_enp)->en_esbp,			\
970e948693eSPhilip Paeps 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
971e948693eSPhilip Paeps 		    (_eqp));						\
972e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
973e948693eSPhilip Paeps 	} while (B_FALSE)
974e948693eSPhilip Paeps 
9753c838a9fSAndrew Rybchenko #define	EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)		\
976e948693eSPhilip Paeps 	do {								\
977e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
978e948693eSPhilip Paeps 		EFSYS_BAR_READO((_enp)->en_esbp,			\
979e948693eSPhilip Paeps 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
9803c838a9fSAndrew Rybchenko 		    (_eop), (_lock));					\
981e948693eSPhilip Paeps 		EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,	\
982e948693eSPhilip Paeps 		    uint32_t, (_index),					\
983e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
984e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[3],			\
985e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[2],			\
986e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[1],			\
987e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[0]);			\
988e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
989e948693eSPhilip Paeps 	} while (B_FALSE)
990e948693eSPhilip Paeps 
9913c838a9fSAndrew Rybchenko #define	EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)		\
992e948693eSPhilip Paeps 	do {								\
993e948693eSPhilip Paeps 		EFX_CHECK_REG((_enp), (_reg));				\
994e948693eSPhilip Paeps 		EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,	\
995e948693eSPhilip Paeps 		    uint32_t, (_index),					\
996e948693eSPhilip Paeps 		    uint32_t, _reg ## _OFST,				\
997e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[3],			\
998e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[2],			\
999e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[1],			\
1000e948693eSPhilip Paeps 		    uint32_t, (_eop)->eo_u32[0]);			\
1001e948693eSPhilip Paeps 		EFSYS_BAR_WRITEO((_enp)->en_esbp,			\
1002e948693eSPhilip Paeps 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
10033c838a9fSAndrew Rybchenko 		    (_eop), (_lock));					\
10043c838a9fSAndrew Rybchenko 	_NOTE(CONSTANTCONDITION)					\
10053c838a9fSAndrew Rybchenko 	} while (B_FALSE)
10063c838a9fSAndrew Rybchenko 
10073c838a9fSAndrew Rybchenko /*
10083c838a9fSAndrew Rybchenko  * Allow drivers to perform optimised 128-bit doorbell writes.
10093c838a9fSAndrew Rybchenko  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
10103c838a9fSAndrew Rybchenko  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
10113c838a9fSAndrew Rybchenko  * the need for locking in the host, and are the only ones known to be safe to
10123c838a9fSAndrew Rybchenko  * use 128-bites write with.
10133c838a9fSAndrew Rybchenko  */
10143c838a9fSAndrew Rybchenko #define	EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)		\
10153c838a9fSAndrew Rybchenko 	do {								\
10163c838a9fSAndrew Rybchenko 		EFX_CHECK_REG((_enp), (_reg));				\
10173c838a9fSAndrew Rybchenko 		EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,		\
10183c838a9fSAndrew Rybchenko 		    const char *,					\
10193c838a9fSAndrew Rybchenko 		    #_reg,						\
10203c838a9fSAndrew Rybchenko 		    uint32_t, (_index),					\
10213c838a9fSAndrew Rybchenko 		    uint32_t, _reg ## _OFST,				\
10223c838a9fSAndrew Rybchenko 		    uint32_t, (_eop)->eo_u32[3],			\
10233c838a9fSAndrew Rybchenko 		    uint32_t, (_eop)->eo_u32[2],			\
10243c838a9fSAndrew Rybchenko 		    uint32_t, (_eop)->eo_u32[1],			\
10253c838a9fSAndrew Rybchenko 		    uint32_t, (_eop)->eo_u32[0]);			\
10263c838a9fSAndrew Rybchenko 		EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,		\
10273c838a9fSAndrew Rybchenko 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
10283c838a9fSAndrew Rybchenko 		    (_eop));						\
10293c838a9fSAndrew Rybchenko 	_NOTE(CONSTANTCONDITION)					\
10303c838a9fSAndrew Rybchenko 	} while (B_FALSE)
10313c838a9fSAndrew Rybchenko 
10323c838a9fSAndrew Rybchenko #define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)	\
10333c838a9fSAndrew Rybchenko 	do {								\
10343c838a9fSAndrew Rybchenko 		unsigned int _new = (_wptr);				\
10353c838a9fSAndrew Rybchenko 		unsigned int _old = (_owptr);				\
10363c838a9fSAndrew Rybchenko 									\
10373c838a9fSAndrew Rybchenko 		if ((_new) >= (_old))					\
10383c838a9fSAndrew Rybchenko 			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
10393c838a9fSAndrew Rybchenko 			    (_old) * sizeof (efx_desc_t),		\
10403c838a9fSAndrew Rybchenko 			    ((_new) - (_old)) * sizeof (efx_desc_t));	\
10413c838a9fSAndrew Rybchenko 		else							\
10423c838a9fSAndrew Rybchenko 			/*						\
10433c838a9fSAndrew Rybchenko 			 * It is cheaper to sync entire map than sync	\
10443c838a9fSAndrew Rybchenko 			 * two parts especially when offset/size are	\
10453c838a9fSAndrew Rybchenko 			 * ignored and entire map is synced in any case.\
10463c838a9fSAndrew Rybchenko 			 */						\
10473c838a9fSAndrew Rybchenko 			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
10483c838a9fSAndrew Rybchenko 			    0,						\
10493c838a9fSAndrew Rybchenko 			    (_entries) * sizeof (efx_desc_t));		\
1050e948693eSPhilip Paeps 	_NOTE(CONSTANTCONDITION)					\
1051e948693eSPhilip Paeps 	} while (B_FALSE)
1052e948693eSPhilip Paeps 
1053460cb568SAndrew Rybchenko extern	__checkReturn	efx_rc_t
10543c838a9fSAndrew Rybchenko efx_nic_biu_test(
10553c838a9fSAndrew Rybchenko 	__in		efx_nic_t *enp);
10563c838a9fSAndrew Rybchenko 
1057460cb568SAndrew Rybchenko extern	__checkReturn	efx_rc_t
1058e948693eSPhilip Paeps efx_mac_select(
1059e948693eSPhilip Paeps 	__in		efx_nic_t *enp);
1060e948693eSPhilip Paeps 
10613c838a9fSAndrew Rybchenko extern	void
10623c838a9fSAndrew Rybchenko efx_mac_multicast_hash_compute(
10633c838a9fSAndrew Rybchenko 	__in_ecount(6*count)		uint8_t const *addrs,
10643c838a9fSAndrew Rybchenko 	__in				int count,
10653c838a9fSAndrew Rybchenko 	__out				efx_oword_t *hash_low,
10663c838a9fSAndrew Rybchenko 	__out				efx_oword_t *hash_high);
10673c838a9fSAndrew Rybchenko 
1068460cb568SAndrew Rybchenko extern	__checkReturn	efx_rc_t
1069e948693eSPhilip Paeps efx_phy_probe(
1070e948693eSPhilip Paeps 	__in		efx_nic_t *enp);
1071e948693eSPhilip Paeps 
1072e948693eSPhilip Paeps extern			void
1073e948693eSPhilip Paeps efx_phy_unprobe(
1074e948693eSPhilip Paeps 	__in		efx_nic_t *enp);
1075e948693eSPhilip Paeps 
1076e948693eSPhilip Paeps #if EFSYS_OPT_VPD
1077e948693eSPhilip Paeps 
1078e948693eSPhilip Paeps /* VPD utility functions */
1079e948693eSPhilip Paeps 
1080460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
1081e948693eSPhilip Paeps efx_vpd_hunk_length(
1082e948693eSPhilip Paeps 	__in_bcount(size)	caddr_t data,
1083e948693eSPhilip Paeps 	__in			size_t size,
1084e948693eSPhilip Paeps 	__out			size_t *lengthp);
1085e948693eSPhilip Paeps 
1086460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
1087e948693eSPhilip Paeps efx_vpd_hunk_verify(
1088e948693eSPhilip Paeps 	__in_bcount(size)	caddr_t data,
1089e948693eSPhilip Paeps 	__in			size_t size,
1090e948693eSPhilip Paeps 	__out_opt		boolean_t *cksummedp);
1091e948693eSPhilip Paeps 
1092460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
1093e948693eSPhilip Paeps efx_vpd_hunk_reinit(
10943c838a9fSAndrew Rybchenko 	__in_bcount(size)	caddr_t data,
1095e948693eSPhilip Paeps 	__in			size_t size,
1096e948693eSPhilip Paeps 	__in			boolean_t wantpid);
1097e948693eSPhilip Paeps 
1098460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
1099e948693eSPhilip Paeps efx_vpd_hunk_get(
1100e948693eSPhilip Paeps 	__in_bcount(size)	caddr_t data,
1101e948693eSPhilip Paeps 	__in			size_t size,
1102e948693eSPhilip Paeps 	__in			efx_vpd_tag_t tag,
1103e948693eSPhilip Paeps 	__in			efx_vpd_keyword_t keyword,
1104e948693eSPhilip Paeps 	__out			unsigned int *payloadp,
1105e948693eSPhilip Paeps 	__out			uint8_t *paylenp);
1106e948693eSPhilip Paeps 
1107460cb568SAndrew Rybchenko extern	__checkReturn			efx_rc_t
1108e948693eSPhilip Paeps efx_vpd_hunk_next(
1109e948693eSPhilip Paeps 	__in_bcount(size)		caddr_t data,
1110e948693eSPhilip Paeps 	__in				size_t size,
1111e948693eSPhilip Paeps 	__out				efx_vpd_tag_t *tagp,
1112e948693eSPhilip Paeps 	__out				efx_vpd_keyword_t *keyword,
1113e948693eSPhilip Paeps 	__out_bcount_opt(*paylenp)	unsigned int *payloadp,
1114e948693eSPhilip Paeps 	__out_opt			uint8_t *paylenp,
1115e948693eSPhilip Paeps 	__inout				unsigned int *contp);
1116e948693eSPhilip Paeps 
1117460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
1118e948693eSPhilip Paeps efx_vpd_hunk_set(
1119e948693eSPhilip Paeps 	__in_bcount(size)	caddr_t data,
1120e948693eSPhilip Paeps 	__in			size_t size,
1121e948693eSPhilip Paeps 	__in			efx_vpd_value_t *evvp);
1122e948693eSPhilip Paeps 
1123e948693eSPhilip Paeps #endif	/* EFSYS_OPT_VPD */
1124e948693eSPhilip Paeps 
1125e948693eSPhilip Paeps #if EFSYS_OPT_DIAG
1126e948693eSPhilip Paeps 
11273c838a9fSAndrew Rybchenko extern	efx_sram_pattern_fn_t	__efx_sram_pattern_fns[];
1128e948693eSPhilip Paeps 
1129e948693eSPhilip Paeps typedef struct efx_register_set_s {
1130e948693eSPhilip Paeps 	unsigned int		address;
1131e948693eSPhilip Paeps 	unsigned int		step;
1132e948693eSPhilip Paeps 	unsigned int		rows;
1133e948693eSPhilip Paeps 	efx_oword_t		mask;
1134e948693eSPhilip Paeps } efx_register_set_t;
1135e948693eSPhilip Paeps 
1136460cb568SAndrew Rybchenko extern	__checkReturn	efx_rc_t
1137e948693eSPhilip Paeps efx_nic_test_registers(
1138e948693eSPhilip Paeps 	__in		efx_nic_t *enp,
1139e948693eSPhilip Paeps 	__in		efx_register_set_t *rsp,
1140e948693eSPhilip Paeps 	__in		size_t count);
1141e948693eSPhilip Paeps 
1142460cb568SAndrew Rybchenko extern	__checkReturn	efx_rc_t
1143e948693eSPhilip Paeps efx_nic_test_tables(
1144e948693eSPhilip Paeps 	__in		efx_nic_t *enp,
1145e948693eSPhilip Paeps 	__in		efx_register_set_t *rsp,
1146e948693eSPhilip Paeps 	__in		efx_pattern_type_t pattern,
1147e948693eSPhilip Paeps 	__in		size_t count);
1148e948693eSPhilip Paeps 
1149e948693eSPhilip Paeps #endif	/* EFSYS_OPT_DIAG */
1150e948693eSPhilip Paeps 
11513c838a9fSAndrew Rybchenko #if EFSYS_OPT_MCDI
11523c838a9fSAndrew Rybchenko 
1153460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
11543c838a9fSAndrew Rybchenko efx_mcdi_set_workaround(
11553c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
11563c838a9fSAndrew Rybchenko 	__in			uint32_t type,
11573c838a9fSAndrew Rybchenko 	__in			boolean_t enabled,
11583c838a9fSAndrew Rybchenko 	__out_opt		uint32_t *flagsp);
11593c838a9fSAndrew Rybchenko 
1160460cb568SAndrew Rybchenko extern	__checkReturn		efx_rc_t
11613c838a9fSAndrew Rybchenko efx_mcdi_get_workarounds(
11623c838a9fSAndrew Rybchenko 	__in			efx_nic_t *enp,
11633c838a9fSAndrew Rybchenko 	__out_opt		uint32_t *implementedp,
11643c838a9fSAndrew Rybchenko 	__out_opt		uint32_t *enabledp);
11653c838a9fSAndrew Rybchenko 
11663c838a9fSAndrew Rybchenko #endif /* EFSYS_OPT_MCDI */
11673c838a9fSAndrew Rybchenko 
1168e948693eSPhilip Paeps #ifdef	__cplusplus
1169e948693eSPhilip Paeps }
1170e948693eSPhilip Paeps #endif
1171e948693eSPhilip Paeps 
1172e948693eSPhilip Paeps #endif	/* _SYS_EFX_IMPL_H */
1173