1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 #include "efx.h" 35 #include "efx_impl.h" 36 #if EFSYS_OPT_MON_MCDI 37 #include "mcdi_mon.h" 38 #endif 39 40 #if EFSYS_OPT_QSTATS 41 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 42 do { \ 43 (_eep)->ee_stat[_stat]++; \ 44 _NOTE(CONSTANTCONDITION) \ 45 } while (B_FALSE) 46 #else 47 #define EFX_EV_QSTAT_INCR(_eep, _stat) 48 #endif 49 50 #define EFX_EV_PRESENT(_qword) \ 51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ 52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) 53 54 #if EFSYS_OPT_SIENA 55 56 static __checkReturn efx_rc_t 57 siena_ev_init( 58 __in efx_nic_t *enp); 59 60 static void 61 siena_ev_fini( 62 __in efx_nic_t *enp); 63 64 static __checkReturn efx_rc_t 65 siena_ev_qcreate( 66 __in efx_nic_t *enp, 67 __in unsigned int index, 68 __in efsys_mem_t *esmp, 69 __in size_t ndescs, 70 __in uint32_t id, 71 __in uint32_t us, 72 __in uint32_t flags, 73 __in efx_evq_t *eep); 74 75 static void 76 siena_ev_qdestroy( 77 __in efx_evq_t *eep); 78 79 static __checkReturn efx_rc_t 80 siena_ev_qprime( 81 __in efx_evq_t *eep, 82 __in unsigned int count); 83 84 static void 85 siena_ev_qpost( 86 __in efx_evq_t *eep, 87 __in uint16_t data); 88 89 static __checkReturn efx_rc_t 90 siena_ev_qmoderate( 91 __in efx_evq_t *eep, 92 __in unsigned int us); 93 94 #if EFSYS_OPT_QSTATS 95 static void 96 siena_ev_qstats_update( 97 __in efx_evq_t *eep, 98 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 99 100 #endif 101 102 #endif /* EFSYS_OPT_SIENA */ 103 104 #if EFSYS_OPT_SIENA 105 static const efx_ev_ops_t __efx_ev_siena_ops = { 106 siena_ev_init, /* eevo_init */ 107 siena_ev_fini, /* eevo_fini */ 108 siena_ev_qcreate, /* eevo_qcreate */ 109 siena_ev_qdestroy, /* eevo_qdestroy */ 110 siena_ev_qprime, /* eevo_qprime */ 111 siena_ev_qpost, /* eevo_qpost */ 112 siena_ev_qmoderate, /* eevo_qmoderate */ 113 #if EFSYS_OPT_QSTATS 114 siena_ev_qstats_update, /* eevo_qstats_update */ 115 #endif 116 }; 117 #endif /* EFSYS_OPT_SIENA */ 118 119 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 120 static const efx_ev_ops_t __efx_ev_ef10_ops = { 121 ef10_ev_init, /* eevo_init */ 122 ef10_ev_fini, /* eevo_fini */ 123 ef10_ev_qcreate, /* eevo_qcreate */ 124 ef10_ev_qdestroy, /* eevo_qdestroy */ 125 ef10_ev_qprime, /* eevo_qprime */ 126 ef10_ev_qpost, /* eevo_qpost */ 127 ef10_ev_qmoderate, /* eevo_qmoderate */ 128 #if EFSYS_OPT_QSTATS 129 ef10_ev_qstats_update, /* eevo_qstats_update */ 130 #endif 131 }; 132 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 133 134 __checkReturn efx_rc_t 135 efx_ev_init( 136 __in efx_nic_t *enp) 137 { 138 const efx_ev_ops_t *eevop; 139 efx_rc_t rc; 140 141 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 142 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 143 144 if (enp->en_mod_flags & EFX_MOD_EV) { 145 rc = EINVAL; 146 goto fail1; 147 } 148 149 switch (enp->en_family) { 150 #if EFSYS_OPT_SIENA 151 case EFX_FAMILY_SIENA: 152 eevop = &__efx_ev_siena_ops; 153 break; 154 #endif /* EFSYS_OPT_SIENA */ 155 156 #if EFSYS_OPT_HUNTINGTON 157 case EFX_FAMILY_HUNTINGTON: 158 eevop = &__efx_ev_ef10_ops; 159 break; 160 #endif /* EFSYS_OPT_HUNTINGTON */ 161 162 #if EFSYS_OPT_MEDFORD 163 case EFX_FAMILY_MEDFORD: 164 eevop = &__efx_ev_ef10_ops; 165 break; 166 #endif /* EFSYS_OPT_MEDFORD */ 167 168 #if EFSYS_OPT_MEDFORD2 169 case EFX_FAMILY_MEDFORD2: 170 eevop = &__efx_ev_ef10_ops; 171 break; 172 #endif /* EFSYS_OPT_MEDFORD2 */ 173 174 default: 175 EFSYS_ASSERT(0); 176 rc = ENOTSUP; 177 goto fail1; 178 } 179 180 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 181 182 if ((rc = eevop->eevo_init(enp)) != 0) 183 goto fail2; 184 185 enp->en_eevop = eevop; 186 enp->en_mod_flags |= EFX_MOD_EV; 187 return (0); 188 189 fail2: 190 EFSYS_PROBE(fail2); 191 192 fail1: 193 EFSYS_PROBE1(fail1, efx_rc_t, rc); 194 195 enp->en_eevop = NULL; 196 enp->en_mod_flags &= ~EFX_MOD_EV; 197 return (rc); 198 } 199 200 void 201 efx_ev_fini( 202 __in efx_nic_t *enp) 203 { 204 const efx_ev_ops_t *eevop = enp->en_eevop; 205 206 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 207 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 208 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 209 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 210 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 211 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); 212 213 eevop->eevo_fini(enp); 214 215 enp->en_eevop = NULL; 216 enp->en_mod_flags &= ~EFX_MOD_EV; 217 } 218 219 __checkReturn efx_rc_t 220 efx_ev_qcreate( 221 __in efx_nic_t *enp, 222 __in unsigned int index, 223 __in efsys_mem_t *esmp, 224 __in size_t ndescs, 225 __in uint32_t id, 226 __in uint32_t us, 227 __in uint32_t flags, 228 __deref_out efx_evq_t **eepp) 229 { 230 const efx_ev_ops_t *eevop = enp->en_eevop; 231 efx_evq_t *eep; 232 efx_rc_t rc; 233 234 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 235 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); 236 237 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, 238 enp->en_nic_cfg.enc_evq_limit); 239 240 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) { 241 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT: 242 break; 243 case EFX_EVQ_FLAGS_NOTIFY_DISABLED: 244 if (us != 0) { 245 rc = EINVAL; 246 goto fail1; 247 } 248 break; 249 default: 250 rc = EINVAL; 251 goto fail2; 252 } 253 254 /* Allocate an EVQ object */ 255 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep); 256 if (eep == NULL) { 257 rc = ENOMEM; 258 goto fail3; 259 } 260 261 eep->ee_magic = EFX_EVQ_MAGIC; 262 eep->ee_enp = enp; 263 eep->ee_index = index; 264 eep->ee_mask = ndescs - 1; 265 eep->ee_flags = flags; 266 eep->ee_esmp = esmp; 267 268 /* 269 * Set outputs before the queue is created because interrupts may be 270 * raised for events immediately after the queue is created, before the 271 * function call below returns. See bug58606. 272 * 273 * The eepp pointer passed in by the client must therefore point to data 274 * shared with the client's event processing context. 275 */ 276 enp->en_ev_qcount++; 277 *eepp = eep; 278 279 if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags, 280 eep)) != 0) 281 goto fail4; 282 283 return (0); 284 285 fail4: 286 EFSYS_PROBE(fail4); 287 288 *eepp = NULL; 289 enp->en_ev_qcount--; 290 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 291 fail3: 292 EFSYS_PROBE(fail3); 293 fail2: 294 EFSYS_PROBE(fail2); 295 fail1: 296 EFSYS_PROBE1(fail1, efx_rc_t, rc); 297 return (rc); 298 } 299 300 void 301 efx_ev_qdestroy( 302 __in efx_evq_t *eep) 303 { 304 efx_nic_t *enp = eep->ee_enp; 305 const efx_ev_ops_t *eevop = enp->en_eevop; 306 307 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 308 309 EFSYS_ASSERT(enp->en_ev_qcount != 0); 310 --enp->en_ev_qcount; 311 312 eevop->eevo_qdestroy(eep); 313 314 /* Free the EVQ object */ 315 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); 316 } 317 318 __checkReturn efx_rc_t 319 efx_ev_qprime( 320 __in efx_evq_t *eep, 321 __in unsigned int count) 322 { 323 efx_nic_t *enp = eep->ee_enp; 324 const efx_ev_ops_t *eevop = enp->en_eevop; 325 efx_rc_t rc; 326 327 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 328 329 if (!(enp->en_mod_flags & EFX_MOD_INTR)) { 330 rc = EINVAL; 331 goto fail1; 332 } 333 334 if ((rc = eevop->eevo_qprime(eep, count)) != 0) 335 goto fail2; 336 337 return (0); 338 339 fail2: 340 EFSYS_PROBE(fail2); 341 fail1: 342 EFSYS_PROBE1(fail1, efx_rc_t, rc); 343 return (rc); 344 } 345 346 __checkReturn boolean_t 347 efx_ev_qpending( 348 __in efx_evq_t *eep, 349 __in unsigned int count) 350 { 351 size_t offset; 352 efx_qword_t qword; 353 354 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 355 356 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 357 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword); 358 359 return (EFX_EV_PRESENT(qword)); 360 } 361 362 #if EFSYS_OPT_EV_PREFETCH 363 364 void 365 efx_ev_qprefetch( 366 __in efx_evq_t *eep, 367 __in unsigned int count) 368 { 369 unsigned int offset; 370 371 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 372 373 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 374 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 375 } 376 377 #endif /* EFSYS_OPT_EV_PREFETCH */ 378 379 #define EFX_EV_BATCH 8 380 381 void 382 efx_ev_qpoll( 383 __in efx_evq_t *eep, 384 __inout unsigned int *countp, 385 __in const efx_ev_callbacks_t *eecp, 386 __in_opt void *arg) 387 { 388 efx_qword_t ev[EFX_EV_BATCH]; 389 unsigned int batch; 390 unsigned int total; 391 unsigned int count; 392 unsigned int index; 393 size_t offset; 394 395 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */ 396 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN); 397 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH); 398 399 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV); 400 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV); 401 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV); 402 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV == 403 FSE_AZ_EV_CODE_DRV_GEN_EV); 404 #if EFSYS_OPT_MCDI 405 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV == 406 FSE_AZ_EV_CODE_MCDI_EVRESPONSE); 407 #endif 408 409 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 410 EFSYS_ASSERT(countp != NULL); 411 EFSYS_ASSERT(eecp != NULL); 412 413 count = *countp; 414 do { 415 /* Read up until the end of the batch period */ 416 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1)); 417 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 418 for (total = 0; total < batch; ++total) { 419 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total])); 420 421 if (!EFX_EV_PRESENT(ev[total])) 422 break; 423 424 EFSYS_PROBE3(event, unsigned int, eep->ee_index, 425 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1), 426 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0)); 427 428 offset += sizeof (efx_qword_t); 429 } 430 431 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1) 432 /* 433 * Prefetch the next batch when we get within PREFETCH_PERIOD 434 * of a completed batch. If the batch is smaller, then prefetch 435 * immediately. 436 */ 437 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD) 438 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 439 #endif /* EFSYS_OPT_EV_PREFETCH */ 440 441 /* Process the batch of events */ 442 for (index = 0; index < total; ++index) { 443 boolean_t should_abort; 444 uint32_t code; 445 446 #if EFSYS_OPT_EV_PREFETCH 447 /* Prefetch if we've now reached the batch period */ 448 if (total == batch && 449 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) { 450 offset = (count + batch) & eep->ee_mask; 451 offset *= sizeof (efx_qword_t); 452 453 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset); 454 } 455 #endif /* EFSYS_OPT_EV_PREFETCH */ 456 457 EFX_EV_QSTAT_INCR(eep, EV_ALL); 458 459 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE); 460 switch (code) { 461 case FSE_AZ_EV_CODE_RX_EV: 462 should_abort = eep->ee_rx(eep, 463 &(ev[index]), eecp, arg); 464 break; 465 case FSE_AZ_EV_CODE_TX_EV: 466 should_abort = eep->ee_tx(eep, 467 &(ev[index]), eecp, arg); 468 break; 469 case FSE_AZ_EV_CODE_DRIVER_EV: 470 should_abort = eep->ee_driver(eep, 471 &(ev[index]), eecp, arg); 472 break; 473 case FSE_AZ_EV_CODE_DRV_GEN_EV: 474 should_abort = eep->ee_drv_gen(eep, 475 &(ev[index]), eecp, arg); 476 break; 477 #if EFSYS_OPT_MCDI 478 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE: 479 should_abort = eep->ee_mcdi(eep, 480 &(ev[index]), eecp, arg); 481 break; 482 #endif 483 case FSE_AZ_EV_CODE_GLOBAL_EV: 484 if (eep->ee_global) { 485 should_abort = eep->ee_global(eep, 486 &(ev[index]), eecp, arg); 487 break; 488 } 489 /* else fallthrough */ 490 default: 491 EFSYS_PROBE3(bad_event, 492 unsigned int, eep->ee_index, 493 uint32_t, 494 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1), 495 uint32_t, 496 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0)); 497 498 EFSYS_ASSERT(eecp->eec_exception != NULL); 499 (void) eecp->eec_exception(arg, 500 EFX_EXCEPTION_EV_ERROR, code); 501 should_abort = B_TRUE; 502 } 503 if (should_abort) { 504 /* Ignore subsequent events */ 505 total = index + 1; 506 507 /* 508 * Poison batch to ensure the outer 509 * loop is broken out of. 510 */ 511 EFSYS_ASSERT(batch <= EFX_EV_BATCH); 512 batch += (EFX_EV_BATCH << 1); 513 EFSYS_ASSERT(total != batch); 514 break; 515 } 516 } 517 518 /* 519 * Now that the hardware has most likely moved onto dma'ing 520 * into the next cache line, clear the processed events. Take 521 * care to only clear out events that we've processed 522 */ 523 EFX_SET_QWORD(ev[0]); 524 offset = (count & eep->ee_mask) * sizeof (efx_qword_t); 525 for (index = 0; index < total; ++index) { 526 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0])); 527 offset += sizeof (efx_qword_t); 528 } 529 530 count += total; 531 532 } while (total == batch); 533 534 *countp = count; 535 } 536 537 void 538 efx_ev_qpost( 539 __in efx_evq_t *eep, 540 __in uint16_t data) 541 { 542 efx_nic_t *enp = eep->ee_enp; 543 const efx_ev_ops_t *eevop = enp->en_eevop; 544 545 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 546 547 EFSYS_ASSERT(eevop != NULL && 548 eevop->eevo_qpost != NULL); 549 550 eevop->eevo_qpost(eep, data); 551 } 552 553 __checkReturn efx_rc_t 554 efx_ev_usecs_to_ticks( 555 __in efx_nic_t *enp, 556 __in unsigned int us, 557 __out unsigned int *ticksp) 558 { 559 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 560 unsigned int ticks; 561 562 /* Convert microseconds to a timer tick count */ 563 if (us == 0) 564 ticks = 0; 565 else if (us * 1000 < encp->enc_evq_timer_quantum_ns) 566 ticks = 1; /* Never round down to zero */ 567 else 568 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns; 569 570 *ticksp = ticks; 571 return (0); 572 } 573 574 __checkReturn efx_rc_t 575 efx_ev_qmoderate( 576 __in efx_evq_t *eep, 577 __in unsigned int us) 578 { 579 efx_nic_t *enp = eep->ee_enp; 580 const efx_ev_ops_t *eevop = enp->en_eevop; 581 efx_rc_t rc; 582 583 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 584 585 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) == 586 EFX_EVQ_FLAGS_NOTIFY_DISABLED) { 587 rc = EINVAL; 588 goto fail1; 589 } 590 591 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0) 592 goto fail2; 593 594 return (0); 595 596 fail2: 597 EFSYS_PROBE(fail2); 598 fail1: 599 EFSYS_PROBE1(fail1, efx_rc_t, rc); 600 return (rc); 601 } 602 603 #if EFSYS_OPT_QSTATS 604 void 605 efx_ev_qstats_update( 606 __in efx_evq_t *eep, 607 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 608 609 { efx_nic_t *enp = eep->ee_enp; 610 const efx_ev_ops_t *eevop = enp->en_eevop; 611 612 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); 613 614 eevop->eevo_qstats_update(eep, stat); 615 } 616 617 #endif /* EFSYS_OPT_QSTATS */ 618 619 #if EFSYS_OPT_SIENA 620 621 static __checkReturn efx_rc_t 622 siena_ev_init( 623 __in efx_nic_t *enp) 624 { 625 efx_oword_t oword; 626 627 /* 628 * Program the event queue for receive and transmit queue 629 * flush events. 630 */ 631 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword); 632 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0); 633 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword); 634 635 return (0); 636 637 } 638 639 static __checkReturn boolean_t 640 siena_ev_rx_not_ok( 641 __in efx_evq_t *eep, 642 __in efx_qword_t *eqp, 643 __in uint32_t label, 644 __in uint32_t id, 645 __inout uint16_t *flagsp) 646 { 647 boolean_t ignore = B_FALSE; 648 649 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) { 650 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC); 651 EFSYS_PROBE(tobe_disc); 652 /* 653 * Assume this is a unicast address mismatch, unless below 654 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or 655 * EV_RX_PAUSE_FRM_ERR is set. 656 */ 657 (*flagsp) |= EFX_ADDR_MISMATCH; 658 } 659 660 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) { 661 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id); 662 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); 663 (*flagsp) |= EFX_DISCARD; 664 665 #if EFSYS_OPT_RX_SCATTER 666 /* 667 * Lookout for payload queue ran dry errors and ignore them. 668 * 669 * Sadly for the header/data split cases, the descriptor 670 * pointer in this event refers to the header queue and 671 * therefore cannot be easily detected as duplicate. 672 * So we drop these and rely on the receive processing seeing 673 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard 674 * the partially received packet. 675 */ 676 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) && 677 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && 678 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) 679 ignore = B_TRUE; 680 #endif /* EFSYS_OPT_RX_SCATTER */ 681 } 682 683 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { 684 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR); 685 EFSYS_PROBE(crc_err); 686 (*flagsp) &= ~EFX_ADDR_MISMATCH; 687 (*flagsp) |= EFX_DISCARD; 688 } 689 690 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) { 691 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR); 692 EFSYS_PROBE(pause_frm_err); 693 (*flagsp) &= ~EFX_ADDR_MISMATCH; 694 (*flagsp) |= EFX_DISCARD; 695 } 696 697 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) { 698 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR); 699 EFSYS_PROBE(owner_id_err); 700 (*flagsp) |= EFX_DISCARD; 701 } 702 703 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) { 704 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR); 705 EFSYS_PROBE(ipv4_err); 706 (*flagsp) &= ~EFX_CKSUM_IPV4; 707 } 708 709 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) { 710 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR); 711 EFSYS_PROBE(udp_chk_err); 712 (*flagsp) &= ~EFX_CKSUM_TCPUDP; 713 } 714 715 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) { 716 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR); 717 718 /* 719 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This 720 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error 721 * condition. 722 */ 723 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP); 724 } 725 726 return (ignore); 727 } 728 729 static __checkReturn boolean_t 730 siena_ev_rx( 731 __in efx_evq_t *eep, 732 __in efx_qword_t *eqp, 733 __in const efx_ev_callbacks_t *eecp, 734 __in_opt void *arg) 735 { 736 uint32_t id; 737 uint32_t size; 738 uint32_t label; 739 boolean_t ok; 740 #if EFSYS_OPT_RX_SCATTER 741 boolean_t sop; 742 boolean_t jumbo_cont; 743 #endif /* EFSYS_OPT_RX_SCATTER */ 744 uint32_t hdr_type; 745 boolean_t is_v6; 746 uint16_t flags; 747 boolean_t ignore; 748 boolean_t should_abort; 749 750 EFX_EV_QSTAT_INCR(eep, EV_RX); 751 752 /* Basic packet information */ 753 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR); 754 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT); 755 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); 756 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); 757 758 #if EFSYS_OPT_RX_SCATTER 759 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); 760 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); 761 #endif /* EFSYS_OPT_RX_SCATTER */ 762 763 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); 764 765 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0); 766 767 /* 768 * If packet is marked as OK and packet type is TCP/IP or 769 * UDP/IP or other IP, then we can rely on the hardware checksums. 770 */ 771 switch (hdr_type) { 772 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP: 773 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP; 774 if (is_v6) { 775 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6); 776 flags |= EFX_PKT_IPV6; 777 } else { 778 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4); 779 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 780 } 781 break; 782 783 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP: 784 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP; 785 if (is_v6) { 786 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6); 787 flags |= EFX_PKT_IPV6; 788 } else { 789 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4); 790 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 791 } 792 break; 793 794 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER: 795 if (is_v6) { 796 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6); 797 flags = EFX_PKT_IPV6; 798 } else { 799 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4); 800 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4; 801 } 802 break; 803 804 case FSE_AZ_RX_EV_HDR_TYPE_OTHER: 805 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP); 806 flags = 0; 807 break; 808 809 default: 810 EFSYS_ASSERT(B_FALSE); 811 flags = 0; 812 break; 813 } 814 815 #if EFSYS_OPT_RX_SCATTER 816 /* Report scatter and header/lookahead split buffer flags */ 817 if (sop) 818 flags |= EFX_PKT_START; 819 if (jumbo_cont) 820 flags |= EFX_PKT_CONT; 821 #endif /* EFSYS_OPT_RX_SCATTER */ 822 823 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ 824 if (!ok) { 825 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags); 826 if (ignore) { 827 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 828 uint32_t, size, uint16_t, flags); 829 830 return (B_FALSE); 831 } 832 } 833 834 /* If we're not discarding the packet then it is ok */ 835 if (~flags & EFX_DISCARD) 836 EFX_EV_QSTAT_INCR(eep, EV_RX_OK); 837 838 /* Detect multicast packets that didn't match the filter */ 839 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) { 840 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT); 841 842 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) { 843 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH); 844 } else { 845 EFSYS_PROBE(mcast_mismatch); 846 flags |= EFX_ADDR_MISMATCH; 847 } 848 } else { 849 flags |= EFX_PKT_UNICAST; 850 } 851 852 /* 853 * The packet parser in Siena can abort parsing packets under 854 * certain error conditions, setting the PKT_NOT_PARSED bit 855 * (which clears PKT_OK). If this is set, then don't trust 856 * the PKT_TYPE field. 857 */ 858 if (!ok) { 859 uint32_t parse_err; 860 861 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED); 862 if (parse_err != 0) 863 flags |= EFX_CHECK_VLAN; 864 } 865 866 if (~flags & EFX_CHECK_VLAN) { 867 uint32_t pkt_type; 868 869 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE); 870 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN) 871 flags |= EFX_PKT_VLAN_TAGGED; 872 } 873 874 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id, 875 uint32_t, size, uint16_t, flags); 876 877 EFSYS_ASSERT(eecp->eec_rx != NULL); 878 should_abort = eecp->eec_rx(arg, label, id, size, flags); 879 880 return (should_abort); 881 } 882 883 static __checkReturn boolean_t 884 siena_ev_tx( 885 __in efx_evq_t *eep, 886 __in efx_qword_t *eqp, 887 __in const efx_ev_callbacks_t *eecp, 888 __in_opt void *arg) 889 { 890 uint32_t id; 891 uint32_t label; 892 boolean_t should_abort; 893 894 EFX_EV_QSTAT_INCR(eep, EV_TX); 895 896 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 && 897 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && 898 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && 899 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { 900 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); 901 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); 902 903 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id); 904 905 EFSYS_ASSERT(eecp->eec_tx != NULL); 906 should_abort = eecp->eec_tx(arg, label, id); 907 908 return (should_abort); 909 } 910 911 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0) 912 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 913 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 914 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 915 916 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0) 917 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR); 918 919 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0) 920 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG); 921 922 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0) 923 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL); 924 925 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED); 926 return (B_FALSE); 927 } 928 929 static __checkReturn boolean_t 930 siena_ev_global( 931 __in efx_evq_t *eep, 932 __in efx_qword_t *eqp, 933 __in const efx_ev_callbacks_t *eecp, 934 __in_opt void *arg) 935 { 936 _NOTE(ARGUNUSED(eqp, eecp, arg)) 937 938 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL); 939 940 return (B_FALSE); 941 } 942 943 static __checkReturn boolean_t 944 siena_ev_driver( 945 __in efx_evq_t *eep, 946 __in efx_qword_t *eqp, 947 __in const efx_ev_callbacks_t *eecp, 948 __in_opt void *arg) 949 { 950 boolean_t should_abort; 951 952 EFX_EV_QSTAT_INCR(eep, EV_DRIVER); 953 should_abort = B_FALSE; 954 955 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) { 956 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: { 957 uint32_t txq_index; 958 959 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE); 960 961 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 962 963 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index); 964 965 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL); 966 should_abort = eecp->eec_txq_flush_done(arg, txq_index); 967 968 break; 969 } 970 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: { 971 uint32_t rxq_index; 972 uint32_t failed; 973 974 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); 975 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); 976 977 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL); 978 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL); 979 980 if (failed) { 981 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED); 982 983 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index); 984 985 should_abort = eecp->eec_rxq_flush_failed(arg, 986 rxq_index); 987 } else { 988 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE); 989 990 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index); 991 992 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index); 993 } 994 995 break; 996 } 997 case FSE_AZ_EVQ_INIT_DONE_EV: 998 EFSYS_ASSERT(eecp->eec_initialized != NULL); 999 should_abort = eecp->eec_initialized(arg); 1000 1001 break; 1002 1003 case FSE_AZ_EVQ_NOT_EN_EV: 1004 EFSYS_PROBE(evq_not_en); 1005 break; 1006 1007 case FSE_AZ_SRM_UPD_DONE_EV: { 1008 uint32_t code; 1009 1010 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE); 1011 1012 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 1013 1014 EFSYS_ASSERT(eecp->eec_sram != NULL); 1015 should_abort = eecp->eec_sram(arg, code); 1016 1017 break; 1018 } 1019 case FSE_AZ_WAKE_UP_EV: { 1020 uint32_t id; 1021 1022 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 1023 1024 EFSYS_ASSERT(eecp->eec_wake_up != NULL); 1025 should_abort = eecp->eec_wake_up(arg, id); 1026 1027 break; 1028 } 1029 case FSE_AZ_TX_PKT_NON_TCP_UDP: 1030 EFSYS_PROBE(tx_pkt_non_tcp_udp); 1031 break; 1032 1033 case FSE_AZ_TIMER_EV: { 1034 uint32_t id; 1035 1036 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA); 1037 1038 EFSYS_ASSERT(eecp->eec_timer != NULL); 1039 should_abort = eecp->eec_timer(arg, id); 1040 1041 break; 1042 } 1043 case FSE_AZ_RX_DSC_ERROR_EV: 1044 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR); 1045 1046 EFSYS_PROBE(rx_dsc_error); 1047 1048 EFSYS_ASSERT(eecp->eec_exception != NULL); 1049 should_abort = eecp->eec_exception(arg, 1050 EFX_EXCEPTION_RX_DSC_ERROR, 0); 1051 1052 break; 1053 1054 case FSE_AZ_TX_DSC_ERROR_EV: 1055 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR); 1056 1057 EFSYS_PROBE(tx_dsc_error); 1058 1059 EFSYS_ASSERT(eecp->eec_exception != NULL); 1060 should_abort = eecp->eec_exception(arg, 1061 EFX_EXCEPTION_TX_DSC_ERROR, 0); 1062 1063 break; 1064 1065 default: 1066 break; 1067 } 1068 1069 return (should_abort); 1070 } 1071 1072 static __checkReturn boolean_t 1073 siena_ev_drv_gen( 1074 __in efx_evq_t *eep, 1075 __in efx_qword_t *eqp, 1076 __in const efx_ev_callbacks_t *eecp, 1077 __in_opt void *arg) 1078 { 1079 uint32_t data; 1080 boolean_t should_abort; 1081 1082 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN); 1083 1084 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0); 1085 if (data >= ((uint32_t)1 << 16)) { 1086 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index, 1087 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1), 1088 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0)); 1089 return (B_TRUE); 1090 } 1091 1092 EFSYS_ASSERT(eecp->eec_software != NULL); 1093 should_abort = eecp->eec_software(arg, (uint16_t)data); 1094 1095 return (should_abort); 1096 } 1097 1098 #if EFSYS_OPT_MCDI 1099 1100 static __checkReturn boolean_t 1101 siena_ev_mcdi( 1102 __in efx_evq_t *eep, 1103 __in efx_qword_t *eqp, 1104 __in const efx_ev_callbacks_t *eecp, 1105 __in_opt void *arg) 1106 { 1107 efx_nic_t *enp = eep->ee_enp; 1108 unsigned int code; 1109 boolean_t should_abort = B_FALSE; 1110 1111 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); 1112 1113 if (enp->en_family != EFX_FAMILY_SIENA) 1114 goto out; 1115 1116 EFSYS_ASSERT(eecp->eec_link_change != NULL); 1117 EFSYS_ASSERT(eecp->eec_exception != NULL); 1118 #if EFSYS_OPT_MON_STATS 1119 EFSYS_ASSERT(eecp->eec_monitor != NULL); 1120 #endif 1121 1122 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE); 1123 1124 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE); 1125 switch (code) { 1126 case MCDI_EVENT_CODE_BADSSERT: 1127 efx_mcdi_ev_death(enp, EINTR); 1128 break; 1129 1130 case MCDI_EVENT_CODE_CMDDONE: 1131 efx_mcdi_ev_cpl(enp, 1132 MCDI_EV_FIELD(eqp, CMDDONE_SEQ), 1133 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN), 1134 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); 1135 break; 1136 1137 case MCDI_EVENT_CODE_LINKCHANGE: { 1138 efx_link_mode_t link_mode; 1139 1140 siena_phy_link_ev(enp, eqp, &link_mode); 1141 should_abort = eecp->eec_link_change(arg, link_mode); 1142 break; 1143 } 1144 case MCDI_EVENT_CODE_SENSOREVT: { 1145 #if EFSYS_OPT_MON_STATS 1146 efx_mon_stat_t id; 1147 efx_mon_stat_value_t value; 1148 efx_rc_t rc; 1149 1150 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) 1151 should_abort = eecp->eec_monitor(arg, id, value); 1152 else if (rc == ENOTSUP) { 1153 should_abort = eecp->eec_exception(arg, 1154 EFX_EXCEPTION_UNKNOWN_SENSOREVT, 1155 MCDI_EV_FIELD(eqp, DATA)); 1156 } else 1157 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */ 1158 #else 1159 should_abort = B_FALSE; 1160 #endif 1161 break; 1162 } 1163 case MCDI_EVENT_CODE_SCHEDERR: 1164 /* Informational only */ 1165 break; 1166 1167 case MCDI_EVENT_CODE_REBOOT: 1168 efx_mcdi_ev_death(enp, EIO); 1169 break; 1170 1171 case MCDI_EVENT_CODE_MAC_STATS_DMA: 1172 #if EFSYS_OPT_MAC_STATS 1173 if (eecp->eec_mac_stats != NULL) { 1174 eecp->eec_mac_stats(arg, 1175 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION)); 1176 } 1177 #endif 1178 break; 1179 1180 case MCDI_EVENT_CODE_FWALERT: { 1181 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON); 1182 1183 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS) 1184 should_abort = eecp->eec_exception(arg, 1185 EFX_EXCEPTION_FWALERT_SRAM, 1186 MCDI_EV_FIELD(eqp, FWALERT_DATA)); 1187 else 1188 should_abort = eecp->eec_exception(arg, 1189 EFX_EXCEPTION_UNKNOWN_FWALERT, 1190 MCDI_EV_FIELD(eqp, DATA)); 1191 break; 1192 } 1193 1194 default: 1195 EFSYS_PROBE1(mc_pcol_error, int, code); 1196 break; 1197 } 1198 1199 out: 1200 return (should_abort); 1201 } 1202 1203 #endif /* EFSYS_OPT_MCDI */ 1204 1205 static __checkReturn efx_rc_t 1206 siena_ev_qprime( 1207 __in efx_evq_t *eep, 1208 __in unsigned int count) 1209 { 1210 efx_nic_t *enp = eep->ee_enp; 1211 uint32_t rptr; 1212 efx_dword_t dword; 1213 1214 rptr = count & eep->ee_mask; 1215 1216 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr); 1217 1218 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index, 1219 &dword, B_FALSE); 1220 1221 return (0); 1222 } 1223 1224 static void 1225 siena_ev_qpost( 1226 __in efx_evq_t *eep, 1227 __in uint16_t data) 1228 { 1229 efx_nic_t *enp = eep->ee_enp; 1230 efx_qword_t ev; 1231 efx_oword_t oword; 1232 1233 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV, 1234 FSF_AZ_EV_DATA_DW0, (uint32_t)data); 1235 1236 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index, 1237 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0), 1238 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1)); 1239 1240 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); 1241 } 1242 1243 static __checkReturn efx_rc_t 1244 siena_ev_qmoderate( 1245 __in efx_evq_t *eep, 1246 __in unsigned int us) 1247 { 1248 efx_nic_t *enp = eep->ee_enp; 1249 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1250 unsigned int locked; 1251 efx_dword_t dword; 1252 efx_rc_t rc; 1253 1254 if (us > encp->enc_evq_timer_max_us) { 1255 rc = EINVAL; 1256 goto fail1; 1257 } 1258 1259 /* If the value is zero then disable the timer */ 1260 if (us == 0) { 1261 EFX_POPULATE_DWORD_2(dword, 1262 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS, 1263 FRF_CZ_TC_TIMER_VAL, 0); 1264 } else { 1265 unsigned int ticks; 1266 1267 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0) 1268 goto fail2; 1269 1270 EFSYS_ASSERT(ticks > 0); 1271 EFX_POPULATE_DWORD_2(dword, 1272 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF, 1273 FRF_CZ_TC_TIMER_VAL, ticks - 1); 1274 } 1275 1276 locked = (eep->ee_index == 0) ? 1 : 0; 1277 1278 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0, 1279 eep->ee_index, &dword, locked); 1280 1281 return (0); 1282 1283 fail2: 1284 EFSYS_PROBE(fail2); 1285 fail1: 1286 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1287 1288 return (rc); 1289 } 1290 1291 static __checkReturn efx_rc_t 1292 siena_ev_qcreate( 1293 __in efx_nic_t *enp, 1294 __in unsigned int index, 1295 __in efsys_mem_t *esmp, 1296 __in size_t ndescs, 1297 __in uint32_t id, 1298 __in uint32_t us, 1299 __in uint32_t flags, 1300 __in efx_evq_t *eep) 1301 { 1302 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 1303 uint32_t size; 1304 efx_oword_t oword; 1305 efx_rc_t rc; 1306 boolean_t notify_mode; 1307 1308 _NOTE(ARGUNUSED(esmp)) 1309 1310 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); 1311 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); 1312 1313 if (!ISP2(ndescs) || 1314 (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) { 1315 rc = EINVAL; 1316 goto fail1; 1317 } 1318 if (index >= encp->enc_evq_limit) { 1319 rc = EINVAL; 1320 goto fail2; 1321 } 1322 #if EFSYS_OPT_RX_SCALE 1323 if (enp->en_intr.ei_type == EFX_INTR_LINE && 1324 index >= EFX_MAXRSS_LEGACY) { 1325 rc = EINVAL; 1326 goto fail3; 1327 } 1328 #endif 1329 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS); 1330 size++) 1331 if ((1 << size) == (int)(ndescs / EFX_EVQ_MINNEVS)) 1332 break; 1333 if (id + (1 << size) >= encp->enc_buftbl_limit) { 1334 rc = EINVAL; 1335 goto fail4; 1336 } 1337 1338 /* Set up the handler table */ 1339 eep->ee_rx = siena_ev_rx; 1340 eep->ee_tx = siena_ev_tx; 1341 eep->ee_driver = siena_ev_driver; 1342 eep->ee_global = siena_ev_global; 1343 eep->ee_drv_gen = siena_ev_drv_gen; 1344 #if EFSYS_OPT_MCDI 1345 eep->ee_mcdi = siena_ev_mcdi; 1346 #endif /* EFSYS_OPT_MCDI */ 1347 1348 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) != 1349 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT); 1350 1351 /* Set up the new event queue */ 1352 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1, 1353 FRF_CZ_HOST_NOTIFY_MODE, notify_mode, 1354 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS); 1355 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE); 1356 1357 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size, 1358 FRF_AZ_EVQ_BUF_BASE_ID, id); 1359 1360 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE); 1361 1362 /* Set initial interrupt moderation */ 1363 siena_ev_qmoderate(eep, us); 1364 1365 return (0); 1366 1367 fail4: 1368 EFSYS_PROBE(fail4); 1369 #if EFSYS_OPT_RX_SCALE 1370 fail3: 1371 EFSYS_PROBE(fail3); 1372 #endif 1373 fail2: 1374 EFSYS_PROBE(fail2); 1375 fail1: 1376 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1377 1378 return (rc); 1379 } 1380 1381 #endif /* EFSYS_OPT_SIENA */ 1382 1383 #if EFSYS_OPT_QSTATS 1384 #if EFSYS_OPT_NAMES 1385 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */ 1386 static const char * const __efx_ev_qstat_name[] = { 1387 "all", 1388 "rx", 1389 "rx_ok", 1390 "rx_frm_trunc", 1391 "rx_tobe_disc", 1392 "rx_pause_frm_err", 1393 "rx_buf_owner_id_err", 1394 "rx_ipv4_hdr_chksum_err", 1395 "rx_tcp_udp_chksum_err", 1396 "rx_eth_crc_err", 1397 "rx_ip_frag_err", 1398 "rx_mcast_pkt", 1399 "rx_mcast_hash_match", 1400 "rx_tcp_ipv4", 1401 "rx_tcp_ipv6", 1402 "rx_udp_ipv4", 1403 "rx_udp_ipv6", 1404 "rx_other_ipv4", 1405 "rx_other_ipv6", 1406 "rx_non_ip", 1407 "rx_batch", 1408 "tx", 1409 "tx_wq_ff_full", 1410 "tx_pkt_err", 1411 "tx_pkt_too_big", 1412 "tx_unexpected", 1413 "global", 1414 "global_mnt", 1415 "driver", 1416 "driver_srm_upd_done", 1417 "driver_tx_descq_fls_done", 1418 "driver_rx_descq_fls_done", 1419 "driver_rx_descq_fls_failed", 1420 "driver_rx_dsc_error", 1421 "driver_tx_dsc_error", 1422 "drv_gen", 1423 "mcdi_response", 1424 }; 1425 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */ 1426 1427 const char * 1428 efx_ev_qstat_name( 1429 __in efx_nic_t *enp, 1430 __in unsigned int id) 1431 { 1432 _NOTE(ARGUNUSED(enp)) 1433 1434 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 1435 EFSYS_ASSERT3U(id, <, EV_NQSTATS); 1436 1437 return (__efx_ev_qstat_name[id]); 1438 } 1439 #endif /* EFSYS_OPT_NAMES */ 1440 #endif /* EFSYS_OPT_QSTATS */ 1441 1442 #if EFSYS_OPT_SIENA 1443 1444 #if EFSYS_OPT_QSTATS 1445 static void 1446 siena_ev_qstats_update( 1447 __in efx_evq_t *eep, 1448 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) 1449 { 1450 unsigned int id; 1451 1452 for (id = 0; id < EV_NQSTATS; id++) { 1453 efsys_stat_t *essp = &stat[id]; 1454 1455 EFSYS_STAT_INCR(essp, eep->ee_stat[id]); 1456 eep->ee_stat[id] = 0; 1457 } 1458 } 1459 #endif /* EFSYS_OPT_QSTATS */ 1460 1461 static void 1462 siena_ev_qdestroy( 1463 __in efx_evq_t *eep) 1464 { 1465 efx_nic_t *enp = eep->ee_enp; 1466 efx_oword_t oword; 1467 1468 /* Purge event queue */ 1469 EFX_ZERO_OWORD(oword); 1470 1471 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, 1472 eep->ee_index, &oword, B_TRUE); 1473 1474 EFX_ZERO_OWORD(oword); 1475 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE); 1476 } 1477 1478 static void 1479 siena_ev_fini( 1480 __in efx_nic_t *enp) 1481 { 1482 _NOTE(ARGUNUSED(enp)) 1483 } 1484 1485 #endif /* EFSYS_OPT_SIENA */ 1486