xref: /freebsd/sys/dev/sfxge/common/efx_ev.c (revision 7ef62cebc2f965b0f640263e179276928885e33d)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  *    this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  *    this list of conditions and the following disclaimer in the documentation
14  *    and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * The views and conclusions contained in the software and documentation are
29  * those of the authors and should not be interpreted as representing official
30  * policies, either expressed or implied, of the FreeBSD Project.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 #include "efx.h"
37 #include "efx_impl.h"
38 #if EFSYS_OPT_MON_MCDI
39 #include "mcdi_mon.h"
40 #endif
41 
42 #if EFSYS_OPT_QSTATS
43 #define	EFX_EV_QSTAT_INCR(_eep, _stat)					\
44 	do {								\
45 		(_eep)->ee_stat[_stat]++;				\
46 	_NOTE(CONSTANTCONDITION)					\
47 	} while (B_FALSE)
48 #else
49 #define	EFX_EV_QSTAT_INCR(_eep, _stat)
50 #endif
51 
52 #define	EFX_EV_PRESENT(_qword)						\
53 	(EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&	\
54 	EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
55 
56 #if EFSYS_OPT_SIENA
57 
58 static	__checkReturn	efx_rc_t
59 siena_ev_init(
60 	__in		efx_nic_t *enp);
61 
62 static			void
63 siena_ev_fini(
64 	__in		efx_nic_t *enp);
65 
66 static	__checkReturn	efx_rc_t
67 siena_ev_qcreate(
68 	__in		efx_nic_t *enp,
69 	__in		unsigned int index,
70 	__in		efsys_mem_t *esmp,
71 	__in		size_t ndescs,
72 	__in		uint32_t id,
73 	__in		uint32_t us,
74 	__in		uint32_t flags,
75 	__in		efx_evq_t *eep);
76 
77 static			void
78 siena_ev_qdestroy(
79 	__in		efx_evq_t *eep);
80 
81 static	__checkReturn	efx_rc_t
82 siena_ev_qprime(
83 	__in		efx_evq_t *eep,
84 	__in		unsigned int count);
85 
86 static			void
87 siena_ev_qpost(
88 	__in	efx_evq_t *eep,
89 	__in	uint16_t data);
90 
91 static	__checkReturn	efx_rc_t
92 siena_ev_qmoderate(
93 	__in		efx_evq_t *eep,
94 	__in		unsigned int us);
95 
96 #if EFSYS_OPT_QSTATS
97 static			void
98 siena_ev_qstats_update(
99 	__in				efx_evq_t *eep,
100 	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
101 
102 #endif
103 
104 #endif /* EFSYS_OPT_SIENA */
105 
106 #if EFSYS_OPT_SIENA
107 static const efx_ev_ops_t	__efx_ev_siena_ops = {
108 	siena_ev_init,				/* eevo_init */
109 	siena_ev_fini,				/* eevo_fini */
110 	siena_ev_qcreate,			/* eevo_qcreate */
111 	siena_ev_qdestroy,			/* eevo_qdestroy */
112 	siena_ev_qprime,			/* eevo_qprime */
113 	siena_ev_qpost,				/* eevo_qpost */
114 	siena_ev_qmoderate,			/* eevo_qmoderate */
115 #if EFSYS_OPT_QSTATS
116 	siena_ev_qstats_update,			/* eevo_qstats_update */
117 #endif
118 };
119 #endif /* EFSYS_OPT_SIENA */
120 
121 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
122 static const efx_ev_ops_t	__efx_ev_ef10_ops = {
123 	ef10_ev_init,				/* eevo_init */
124 	ef10_ev_fini,				/* eevo_fini */
125 	ef10_ev_qcreate,			/* eevo_qcreate */
126 	ef10_ev_qdestroy,			/* eevo_qdestroy */
127 	ef10_ev_qprime,				/* eevo_qprime */
128 	ef10_ev_qpost,				/* eevo_qpost */
129 	ef10_ev_qmoderate,			/* eevo_qmoderate */
130 #if EFSYS_OPT_QSTATS
131 	ef10_ev_qstats_update,			/* eevo_qstats_update */
132 #endif
133 };
134 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
135 
136 	__checkReturn	efx_rc_t
137 efx_ev_init(
138 	__in		efx_nic_t *enp)
139 {
140 	const efx_ev_ops_t *eevop;
141 	efx_rc_t rc;
142 
143 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
144 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
145 
146 	if (enp->en_mod_flags & EFX_MOD_EV) {
147 		rc = EINVAL;
148 		goto fail1;
149 	}
150 
151 	switch (enp->en_family) {
152 #if EFSYS_OPT_SIENA
153 	case EFX_FAMILY_SIENA:
154 		eevop = &__efx_ev_siena_ops;
155 		break;
156 #endif /* EFSYS_OPT_SIENA */
157 
158 #if EFSYS_OPT_HUNTINGTON
159 	case EFX_FAMILY_HUNTINGTON:
160 		eevop = &__efx_ev_ef10_ops;
161 		break;
162 #endif /* EFSYS_OPT_HUNTINGTON */
163 
164 #if EFSYS_OPT_MEDFORD
165 	case EFX_FAMILY_MEDFORD:
166 		eevop = &__efx_ev_ef10_ops;
167 		break;
168 #endif /* EFSYS_OPT_MEDFORD */
169 
170 #if EFSYS_OPT_MEDFORD2
171 	case EFX_FAMILY_MEDFORD2:
172 		eevop = &__efx_ev_ef10_ops;
173 		break;
174 #endif /* EFSYS_OPT_MEDFORD2 */
175 
176 	default:
177 		EFSYS_ASSERT(0);
178 		rc = ENOTSUP;
179 		goto fail1;
180 	}
181 
182 	EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
183 
184 	if ((rc = eevop->eevo_init(enp)) != 0)
185 		goto fail2;
186 
187 	enp->en_eevop = eevop;
188 	enp->en_mod_flags |= EFX_MOD_EV;
189 	return (0);
190 
191 fail2:
192 	EFSYS_PROBE(fail2);
193 
194 fail1:
195 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
196 
197 	enp->en_eevop = NULL;
198 	enp->en_mod_flags &= ~EFX_MOD_EV;
199 	return (rc);
200 }
201 
202 		void
203 efx_ev_fini(
204 	__in	efx_nic_t *enp)
205 {
206 	const efx_ev_ops_t *eevop = enp->en_eevop;
207 
208 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
209 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
210 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
211 	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
212 	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
213 	EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
214 
215 	eevop->eevo_fini(enp);
216 
217 	enp->en_eevop = NULL;
218 	enp->en_mod_flags &= ~EFX_MOD_EV;
219 }
220 
221 	__checkReturn	efx_rc_t
222 efx_ev_qcreate(
223 	__in		efx_nic_t *enp,
224 	__in		unsigned int index,
225 	__in		efsys_mem_t *esmp,
226 	__in		size_t ndescs,
227 	__in		uint32_t id,
228 	__in		uint32_t us,
229 	__in		uint32_t flags,
230 	__deref_out	efx_evq_t **eepp)
231 {
232 	const efx_ev_ops_t *eevop = enp->en_eevop;
233 	efx_evq_t *eep;
234 	efx_rc_t rc;
235 
236 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
237 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
238 
239 	EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
240 	    enp->en_nic_cfg.enc_evq_limit);
241 
242 	switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
243 	case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
244 		break;
245 	case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
246 		if (us != 0) {
247 			rc = EINVAL;
248 			goto fail1;
249 		}
250 		break;
251 	default:
252 		rc = EINVAL;
253 		goto fail2;
254 	}
255 
256 	/* Allocate an EVQ object */
257 	EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
258 	if (eep == NULL) {
259 		rc = ENOMEM;
260 		goto fail3;
261 	}
262 
263 	eep->ee_magic = EFX_EVQ_MAGIC;
264 	eep->ee_enp = enp;
265 	eep->ee_index = index;
266 	eep->ee_mask = ndescs - 1;
267 	eep->ee_flags = flags;
268 	eep->ee_esmp = esmp;
269 
270 	/*
271 	 * Set outputs before the queue is created because interrupts may be
272 	 * raised for events immediately after the queue is created, before the
273 	 * function call below returns. See bug58606.
274 	 *
275 	 * The eepp pointer passed in by the client must therefore point to data
276 	 * shared with the client's event processing context.
277 	 */
278 	enp->en_ev_qcount++;
279 	*eepp = eep;
280 
281 	if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
282 	    eep)) != 0)
283 		goto fail4;
284 
285 	return (0);
286 
287 fail4:
288 	EFSYS_PROBE(fail4);
289 
290 	*eepp = NULL;
291 	enp->en_ev_qcount--;
292 	EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
293 fail3:
294 	EFSYS_PROBE(fail3);
295 fail2:
296 	EFSYS_PROBE(fail2);
297 fail1:
298 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 	return (rc);
300 }
301 
302 		void
303 efx_ev_qdestroy(
304 	__in	efx_evq_t *eep)
305 {
306 	efx_nic_t *enp = eep->ee_enp;
307 	const efx_ev_ops_t *eevop = enp->en_eevop;
308 
309 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
310 
311 	EFSYS_ASSERT(enp->en_ev_qcount != 0);
312 	--enp->en_ev_qcount;
313 
314 	eevop->eevo_qdestroy(eep);
315 
316 	/* Free the EVQ object */
317 	EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
318 }
319 
320 	__checkReturn	efx_rc_t
321 efx_ev_qprime(
322 	__in		efx_evq_t *eep,
323 	__in		unsigned int count)
324 {
325 	efx_nic_t *enp = eep->ee_enp;
326 	const efx_ev_ops_t *eevop = enp->en_eevop;
327 	efx_rc_t rc;
328 
329 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
330 
331 	if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
332 		rc = EINVAL;
333 		goto fail1;
334 	}
335 
336 	if ((rc = eevop->eevo_qprime(eep, count)) != 0)
337 		goto fail2;
338 
339 	return (0);
340 
341 fail2:
342 	EFSYS_PROBE(fail2);
343 fail1:
344 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
345 	return (rc);
346 }
347 
348 	__checkReturn	boolean_t
349 efx_ev_qpending(
350 	__in		efx_evq_t *eep,
351 	__in		unsigned int count)
352 {
353 	size_t offset;
354 	efx_qword_t qword;
355 
356 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
357 
358 	offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
359 	EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
360 
361 	return (EFX_EV_PRESENT(qword));
362 }
363 
364 #if EFSYS_OPT_EV_PREFETCH
365 
366 			void
367 efx_ev_qprefetch(
368 	__in		efx_evq_t *eep,
369 	__in		unsigned int count)
370 {
371 	unsigned int offset;
372 
373 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
374 
375 	offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
376 	EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
377 }
378 
379 #endif	/* EFSYS_OPT_EV_PREFETCH */
380 
381 #define	EFX_EV_BATCH	8
382 
383 			void
384 efx_ev_qpoll(
385 	__in		efx_evq_t *eep,
386 	__inout		unsigned int *countp,
387 	__in		const efx_ev_callbacks_t *eecp,
388 	__in_opt	void *arg)
389 {
390 	efx_qword_t ev[EFX_EV_BATCH];
391 	unsigned int batch;
392 	unsigned int total;
393 	unsigned int count;
394 	unsigned int index;
395 	size_t offset;
396 
397 	/* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
398 	EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
399 	EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
400 
401 	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
402 	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
403 	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
404 	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
405 	    FSE_AZ_EV_CODE_DRV_GEN_EV);
406 #if EFSYS_OPT_MCDI
407 	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
408 	    FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
409 #endif
410 
411 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
412 	EFSYS_ASSERT(countp != NULL);
413 	EFSYS_ASSERT(eecp != NULL);
414 
415 	count = *countp;
416 	do {
417 		/* Read up until the end of the batch period */
418 		batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
419 		offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
420 		for (total = 0; total < batch; ++total) {
421 			EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
422 
423 			if (!EFX_EV_PRESENT(ev[total]))
424 				break;
425 
426 			EFSYS_PROBE3(event, unsigned int, eep->ee_index,
427 			    uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
428 			    uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
429 
430 			offset += sizeof (efx_qword_t);
431 		}
432 
433 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
434 		/*
435 		 * Prefetch the next batch when we get within PREFETCH_PERIOD
436 		 * of a completed batch. If the batch is smaller, then prefetch
437 		 * immediately.
438 		 */
439 		if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
440 			EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
441 #endif	/* EFSYS_OPT_EV_PREFETCH */
442 
443 		/* Process the batch of events */
444 		for (index = 0; index < total; ++index) {
445 			boolean_t should_abort;
446 			uint32_t code;
447 
448 #if EFSYS_OPT_EV_PREFETCH
449 			/* Prefetch if we've now reached the batch period */
450 			if (total == batch &&
451 			    index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
452 				offset = (count + batch) & eep->ee_mask;
453 				offset *= sizeof (efx_qword_t);
454 
455 				EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
456 			}
457 #endif	/* EFSYS_OPT_EV_PREFETCH */
458 
459 			EFX_EV_QSTAT_INCR(eep, EV_ALL);
460 
461 			code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
462 			switch (code) {
463 			case FSE_AZ_EV_CODE_RX_EV:
464 				should_abort = eep->ee_rx(eep,
465 				    &(ev[index]), eecp, arg);
466 				break;
467 			case FSE_AZ_EV_CODE_TX_EV:
468 				should_abort = eep->ee_tx(eep,
469 				    &(ev[index]), eecp, arg);
470 				break;
471 			case FSE_AZ_EV_CODE_DRIVER_EV:
472 				should_abort = eep->ee_driver(eep,
473 				    &(ev[index]), eecp, arg);
474 				break;
475 			case FSE_AZ_EV_CODE_DRV_GEN_EV:
476 				should_abort = eep->ee_drv_gen(eep,
477 				    &(ev[index]), eecp, arg);
478 				break;
479 #if EFSYS_OPT_MCDI
480 			case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
481 				should_abort = eep->ee_mcdi(eep,
482 				    &(ev[index]), eecp, arg);
483 				break;
484 #endif
485 			case FSE_AZ_EV_CODE_GLOBAL_EV:
486 				if (eep->ee_global) {
487 					should_abort = eep->ee_global(eep,
488 					    &(ev[index]), eecp, arg);
489 					break;
490 				}
491 				/* else fallthrough */
492 			default:
493 				EFSYS_PROBE3(bad_event,
494 				    unsigned int, eep->ee_index,
495 				    uint32_t,
496 				    EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
497 				    uint32_t,
498 				    EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
499 
500 				EFSYS_ASSERT(eecp->eec_exception != NULL);
501 				(void) eecp->eec_exception(arg,
502 					EFX_EXCEPTION_EV_ERROR, code);
503 				should_abort = B_TRUE;
504 			}
505 			if (should_abort) {
506 				/* Ignore subsequent events */
507 				total = index + 1;
508 
509 				/*
510 				 * Poison batch to ensure the outer
511 				 * loop is broken out of.
512 				 */
513 				EFSYS_ASSERT(batch <= EFX_EV_BATCH);
514 				batch += (EFX_EV_BATCH << 1);
515 				EFSYS_ASSERT(total != batch);
516 				break;
517 			}
518 		}
519 
520 		/*
521 		 * Now that the hardware has most likely moved onto dma'ing
522 		 * into the next cache line, clear the processed events. Take
523 		 * care to only clear out events that we've processed
524 		 */
525 		EFX_SET_QWORD(ev[0]);
526 		offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
527 		for (index = 0; index < total; ++index) {
528 			EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
529 			offset += sizeof (efx_qword_t);
530 		}
531 
532 		count += total;
533 
534 	} while (total == batch);
535 
536 	*countp = count;
537 }
538 
539 			void
540 efx_ev_qpost(
541 	__in	efx_evq_t *eep,
542 	__in	uint16_t data)
543 {
544 	efx_nic_t *enp = eep->ee_enp;
545 	const efx_ev_ops_t *eevop = enp->en_eevop;
546 
547 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
548 
549 	EFSYS_ASSERT(eevop != NULL &&
550 	    eevop->eevo_qpost != NULL);
551 
552 	eevop->eevo_qpost(eep, data);
553 }
554 
555 	__checkReturn	efx_rc_t
556 efx_ev_usecs_to_ticks(
557 	__in		efx_nic_t *enp,
558 	__in		unsigned int us,
559 	__out		unsigned int *ticksp)
560 {
561 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
562 	unsigned int ticks;
563 
564 	/* Convert microseconds to a timer tick count */
565 	if (us == 0)
566 		ticks = 0;
567 	else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
568 		ticks = 1;	/* Never round down to zero */
569 	else
570 		ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
571 
572 	*ticksp = ticks;
573 	return (0);
574 }
575 
576 	__checkReturn	efx_rc_t
577 efx_ev_qmoderate(
578 	__in		efx_evq_t *eep,
579 	__in		unsigned int us)
580 {
581 	efx_nic_t *enp = eep->ee_enp;
582 	const efx_ev_ops_t *eevop = enp->en_eevop;
583 	efx_rc_t rc;
584 
585 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
586 
587 	if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
588 	    EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
589 		rc = EINVAL;
590 		goto fail1;
591 	}
592 
593 	if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
594 		goto fail2;
595 
596 	return (0);
597 
598 fail2:
599 	EFSYS_PROBE(fail2);
600 fail1:
601 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
602 	return (rc);
603 }
604 
605 #if EFSYS_OPT_QSTATS
606 					void
607 efx_ev_qstats_update(
608 	__in				efx_evq_t *eep,
609 	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat)
610 
611 {	efx_nic_t *enp = eep->ee_enp;
612 	const efx_ev_ops_t *eevop = enp->en_eevop;
613 
614 	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
615 
616 	eevop->eevo_qstats_update(eep, stat);
617 }
618 
619 #endif	/* EFSYS_OPT_QSTATS */
620 
621 #if EFSYS_OPT_SIENA
622 
623 static	__checkReturn	efx_rc_t
624 siena_ev_init(
625 	__in		efx_nic_t *enp)
626 {
627 	efx_oword_t oword;
628 
629 	/*
630 	 * Program the event queue for receive and transmit queue
631 	 * flush events.
632 	 */
633 	EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
634 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
635 	EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
636 
637 	return (0);
638 
639 }
640 
641 static  __checkReturn   boolean_t
642 siena_ev_rx_not_ok(
643 	__in		efx_evq_t *eep,
644 	__in		efx_qword_t *eqp,
645 	__in		uint32_t label,
646 	__in		uint32_t id,
647 	__inout		uint16_t *flagsp)
648 {
649 	boolean_t ignore = B_FALSE;
650 
651 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
652 		EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
653 		EFSYS_PROBE(tobe_disc);
654 		/*
655 		 * Assume this is a unicast address mismatch, unless below
656 		 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
657 		 * EV_RX_PAUSE_FRM_ERR is set.
658 		 */
659 		(*flagsp) |= EFX_ADDR_MISMATCH;
660 	}
661 
662 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
663 		EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
664 		EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
665 		(*flagsp) |= EFX_DISCARD;
666 
667 #if EFSYS_OPT_RX_SCATTER
668 		/*
669 		 * Lookout for payload queue ran dry errors and ignore them.
670 		 *
671 		 * Sadly for the header/data split cases, the descriptor
672 		 * pointer in this event refers to the header queue and
673 		 * therefore cannot be easily detected as duplicate.
674 		 * So we drop these and rely on the receive processing seeing
675 		 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
676 		 * the partially received packet.
677 		 */
678 		if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
679 		    (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
680 		    (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
681 			ignore = B_TRUE;
682 #endif	/* EFSYS_OPT_RX_SCATTER */
683 	}
684 
685 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
686 		EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
687 		EFSYS_PROBE(crc_err);
688 		(*flagsp) &= ~EFX_ADDR_MISMATCH;
689 		(*flagsp) |= EFX_DISCARD;
690 	}
691 
692 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
693 		EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
694 		EFSYS_PROBE(pause_frm_err);
695 		(*flagsp) &= ~EFX_ADDR_MISMATCH;
696 		(*flagsp) |= EFX_DISCARD;
697 	}
698 
699 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
700 		EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
701 		EFSYS_PROBE(owner_id_err);
702 		(*flagsp) |= EFX_DISCARD;
703 	}
704 
705 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
706 		EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
707 		EFSYS_PROBE(ipv4_err);
708 		(*flagsp) &= ~EFX_CKSUM_IPV4;
709 	}
710 
711 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
712 		EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
713 		EFSYS_PROBE(udp_chk_err);
714 		(*flagsp) &= ~EFX_CKSUM_TCPUDP;
715 	}
716 
717 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
718 		EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
719 
720 		/*
721 		 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
722 		 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
723 		 * condition.
724 		 */
725 		(*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
726 	}
727 
728 	return (ignore);
729 }
730 
731 static	__checkReturn	boolean_t
732 siena_ev_rx(
733 	__in		efx_evq_t *eep,
734 	__in		efx_qword_t *eqp,
735 	__in		const efx_ev_callbacks_t *eecp,
736 	__in_opt	void *arg)
737 {
738 	uint32_t id;
739 	uint32_t size;
740 	uint32_t label;
741 	boolean_t ok;
742 #if EFSYS_OPT_RX_SCATTER
743 	boolean_t sop;
744 	boolean_t jumbo_cont;
745 #endif	/* EFSYS_OPT_RX_SCATTER */
746 	uint32_t hdr_type;
747 	boolean_t is_v6;
748 	uint16_t flags;
749 	boolean_t ignore;
750 	boolean_t should_abort;
751 
752 	EFX_EV_QSTAT_INCR(eep, EV_RX);
753 
754 	/* Basic packet information */
755 	id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
756 	size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
757 	label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
758 	ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
759 
760 #if EFSYS_OPT_RX_SCATTER
761 	sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
762 	jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
763 #endif	/* EFSYS_OPT_RX_SCATTER */
764 
765 	hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
766 
767 	is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
768 
769 	/*
770 	 * If packet is marked as OK and packet type is TCP/IP or
771 	 * UDP/IP or other IP, then we can rely on the hardware checksums.
772 	 */
773 	switch (hdr_type) {
774 	case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
775 		flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
776 		if (is_v6) {
777 			EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
778 			flags |= EFX_PKT_IPV6;
779 		} else {
780 			EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
781 			flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
782 		}
783 		break;
784 
785 	case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
786 		flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
787 		if (is_v6) {
788 			EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
789 			flags |= EFX_PKT_IPV6;
790 		} else {
791 			EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
792 			flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
793 		}
794 		break;
795 
796 	case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
797 		if (is_v6) {
798 			EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
799 			flags = EFX_PKT_IPV6;
800 		} else {
801 			EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
802 			flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
803 		}
804 		break;
805 
806 	case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
807 		EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
808 		flags = 0;
809 		break;
810 
811 	default:
812 		EFSYS_ASSERT(B_FALSE);
813 		flags = 0;
814 		break;
815 	}
816 
817 #if EFSYS_OPT_RX_SCATTER
818 	/* Report scatter and header/lookahead split buffer flags */
819 	if (sop)
820 		flags |= EFX_PKT_START;
821 	if (jumbo_cont)
822 		flags |= EFX_PKT_CONT;
823 #endif	/* EFSYS_OPT_RX_SCATTER */
824 
825 	/* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
826 	if (!ok) {
827 		ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
828 		if (ignore) {
829 			EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
830 			    uint32_t, size, uint16_t, flags);
831 
832 			return (B_FALSE);
833 		}
834 	}
835 
836 	/* If we're not discarding the packet then it is ok */
837 	if (~flags & EFX_DISCARD)
838 		EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
839 
840 	/* Detect multicast packets that didn't match the filter */
841 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
842 		EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
843 
844 		if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
845 			EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
846 		} else {
847 			EFSYS_PROBE(mcast_mismatch);
848 			flags |= EFX_ADDR_MISMATCH;
849 		}
850 	} else {
851 		flags |= EFX_PKT_UNICAST;
852 	}
853 
854 	/*
855 	 * The packet parser in Siena can abort parsing packets under
856 	 * certain error conditions, setting the PKT_NOT_PARSED bit
857 	 * (which clears PKT_OK). If this is set, then don't trust
858 	 * the PKT_TYPE field.
859 	 */
860 	if (!ok) {
861 		uint32_t parse_err;
862 
863 		parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
864 		if (parse_err != 0)
865 			flags |= EFX_CHECK_VLAN;
866 	}
867 
868 	if (~flags & EFX_CHECK_VLAN) {
869 		uint32_t pkt_type;
870 
871 		pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
872 		if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
873 			flags |= EFX_PKT_VLAN_TAGGED;
874 	}
875 
876 	EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
877 	    uint32_t, size, uint16_t, flags);
878 
879 	EFSYS_ASSERT(eecp->eec_rx != NULL);
880 	should_abort = eecp->eec_rx(arg, label, id, size, flags);
881 
882 	return (should_abort);
883 }
884 
885 static	__checkReturn	boolean_t
886 siena_ev_tx(
887 	__in		efx_evq_t *eep,
888 	__in		efx_qword_t *eqp,
889 	__in		const efx_ev_callbacks_t *eecp,
890 	__in_opt	void *arg)
891 {
892 	uint32_t id;
893 	uint32_t label;
894 	boolean_t should_abort;
895 
896 	EFX_EV_QSTAT_INCR(eep, EV_TX);
897 
898 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
899 	    EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
900 	    EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
901 	    EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
902 		id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
903 		label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
904 
905 		EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
906 
907 		EFSYS_ASSERT(eecp->eec_tx != NULL);
908 		should_abort = eecp->eec_tx(arg, label, id);
909 
910 		return (should_abort);
911 	}
912 
913 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
914 		EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
915 			    uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
916 			    uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
917 
918 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
919 		EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
920 
921 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
922 		EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
923 
924 	if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
925 		EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
926 
927 	EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
928 	return (B_FALSE);
929 }
930 
931 static	__checkReturn	boolean_t
932 siena_ev_global(
933 	__in		efx_evq_t *eep,
934 	__in		efx_qword_t *eqp,
935 	__in		const efx_ev_callbacks_t *eecp,
936 	__in_opt	void *arg)
937 {
938 	_NOTE(ARGUNUSED(eqp, eecp, arg))
939 
940 	EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
941 
942 	return (B_FALSE);
943 }
944 
945 static	__checkReturn	boolean_t
946 siena_ev_driver(
947 	__in		efx_evq_t *eep,
948 	__in		efx_qword_t *eqp,
949 	__in		const efx_ev_callbacks_t *eecp,
950 	__in_opt	void *arg)
951 {
952 	boolean_t should_abort;
953 
954 	EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
955 	should_abort = B_FALSE;
956 
957 	switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
958 	case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
959 		uint32_t txq_index;
960 
961 		EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
962 
963 		txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
964 
965 		EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
966 
967 		EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
968 		should_abort = eecp->eec_txq_flush_done(arg, txq_index);
969 
970 		break;
971 	}
972 	case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
973 		uint32_t rxq_index;
974 		uint32_t failed;
975 
976 		rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
977 		failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
978 
979 		EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
980 		EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
981 
982 		if (failed) {
983 			EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
984 
985 			EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
986 
987 			should_abort = eecp->eec_rxq_flush_failed(arg,
988 								    rxq_index);
989 		} else {
990 			EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
991 
992 			EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
993 
994 			should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
995 		}
996 
997 		break;
998 	}
999 	case FSE_AZ_EVQ_INIT_DONE_EV:
1000 		EFSYS_ASSERT(eecp->eec_initialized != NULL);
1001 		should_abort = eecp->eec_initialized(arg);
1002 
1003 		break;
1004 
1005 	case FSE_AZ_EVQ_NOT_EN_EV:
1006 		EFSYS_PROBE(evq_not_en);
1007 		break;
1008 
1009 	case FSE_AZ_SRM_UPD_DONE_EV: {
1010 		uint32_t code;
1011 
1012 		EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
1013 
1014 		code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1015 
1016 		EFSYS_ASSERT(eecp->eec_sram != NULL);
1017 		should_abort = eecp->eec_sram(arg, code);
1018 
1019 		break;
1020 	}
1021 	case FSE_AZ_WAKE_UP_EV: {
1022 		uint32_t id;
1023 
1024 		id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1025 
1026 		EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1027 		should_abort = eecp->eec_wake_up(arg, id);
1028 
1029 		break;
1030 	}
1031 	case FSE_AZ_TX_PKT_NON_TCP_UDP:
1032 		EFSYS_PROBE(tx_pkt_non_tcp_udp);
1033 		break;
1034 
1035 	case FSE_AZ_TIMER_EV: {
1036 		uint32_t id;
1037 
1038 		id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1039 
1040 		EFSYS_ASSERT(eecp->eec_timer != NULL);
1041 		should_abort = eecp->eec_timer(arg, id);
1042 
1043 		break;
1044 	}
1045 	case FSE_AZ_RX_DSC_ERROR_EV:
1046 		EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1047 
1048 		EFSYS_PROBE(rx_dsc_error);
1049 
1050 		EFSYS_ASSERT(eecp->eec_exception != NULL);
1051 		should_abort = eecp->eec_exception(arg,
1052 			EFX_EXCEPTION_RX_DSC_ERROR, 0);
1053 
1054 		break;
1055 
1056 	case FSE_AZ_TX_DSC_ERROR_EV:
1057 		EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1058 
1059 		EFSYS_PROBE(tx_dsc_error);
1060 
1061 		EFSYS_ASSERT(eecp->eec_exception != NULL);
1062 		should_abort = eecp->eec_exception(arg,
1063 			EFX_EXCEPTION_TX_DSC_ERROR, 0);
1064 
1065 		break;
1066 
1067 	default:
1068 		break;
1069 	}
1070 
1071 	return (should_abort);
1072 }
1073 
1074 static	__checkReturn	boolean_t
1075 siena_ev_drv_gen(
1076 	__in		efx_evq_t *eep,
1077 	__in		efx_qword_t *eqp,
1078 	__in		const efx_ev_callbacks_t *eecp,
1079 	__in_opt	void *arg)
1080 {
1081 	uint32_t data;
1082 	boolean_t should_abort;
1083 
1084 	EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1085 
1086 	data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1087 	if (data >= ((uint32_t)1 << 16)) {
1088 		EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1089 			    uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1090 			    uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1091 		return (B_TRUE);
1092 	}
1093 
1094 	EFSYS_ASSERT(eecp->eec_software != NULL);
1095 	should_abort = eecp->eec_software(arg, (uint16_t)data);
1096 
1097 	return (should_abort);
1098 }
1099 
1100 #if EFSYS_OPT_MCDI
1101 
1102 static	__checkReturn	boolean_t
1103 siena_ev_mcdi(
1104 	__in		efx_evq_t *eep,
1105 	__in		efx_qword_t *eqp,
1106 	__in		const efx_ev_callbacks_t *eecp,
1107 	__in_opt	void *arg)
1108 {
1109 	efx_nic_t *enp = eep->ee_enp;
1110 	unsigned int code;
1111 	boolean_t should_abort = B_FALSE;
1112 
1113 	EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1114 
1115 	if (enp->en_family != EFX_FAMILY_SIENA)
1116 		goto out;
1117 
1118 	EFSYS_ASSERT(eecp->eec_link_change != NULL);
1119 	EFSYS_ASSERT(eecp->eec_exception != NULL);
1120 #if EFSYS_OPT_MON_STATS
1121 	EFSYS_ASSERT(eecp->eec_monitor != NULL);
1122 #endif
1123 
1124 	EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1125 
1126 	code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1127 	switch (code) {
1128 	case MCDI_EVENT_CODE_BADSSERT:
1129 		efx_mcdi_ev_death(enp, EINTR);
1130 		break;
1131 
1132 	case MCDI_EVENT_CODE_CMDDONE:
1133 		efx_mcdi_ev_cpl(enp,
1134 		    MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1135 		    MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1136 		    MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1137 		break;
1138 
1139 	case MCDI_EVENT_CODE_LINKCHANGE: {
1140 		efx_link_mode_t link_mode;
1141 
1142 		siena_phy_link_ev(enp, eqp, &link_mode);
1143 		should_abort = eecp->eec_link_change(arg, link_mode);
1144 		break;
1145 	}
1146 	case MCDI_EVENT_CODE_SENSOREVT: {
1147 #if EFSYS_OPT_MON_STATS
1148 		efx_mon_stat_t id;
1149 		efx_mon_stat_value_t value;
1150 		efx_rc_t rc;
1151 
1152 		if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1153 			should_abort = eecp->eec_monitor(arg, id, value);
1154 		else if (rc == ENOTSUP) {
1155 			should_abort = eecp->eec_exception(arg,
1156 				EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1157 				MCDI_EV_FIELD(eqp, DATA));
1158 		} else
1159 			EFSYS_ASSERT(rc == ENODEV);	/* Wrong port */
1160 #else
1161 		should_abort = B_FALSE;
1162 #endif
1163 		break;
1164 	}
1165 	case MCDI_EVENT_CODE_SCHEDERR:
1166 		/* Informational only */
1167 		break;
1168 
1169 	case MCDI_EVENT_CODE_REBOOT:
1170 		efx_mcdi_ev_death(enp, EIO);
1171 		break;
1172 
1173 	case MCDI_EVENT_CODE_MAC_STATS_DMA:
1174 #if EFSYS_OPT_MAC_STATS
1175 		if (eecp->eec_mac_stats != NULL) {
1176 			eecp->eec_mac_stats(arg,
1177 			    MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1178 		}
1179 #endif
1180 		break;
1181 
1182 	case MCDI_EVENT_CODE_FWALERT: {
1183 		uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1184 
1185 		if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1186 			should_abort = eecp->eec_exception(arg,
1187 				EFX_EXCEPTION_FWALERT_SRAM,
1188 				MCDI_EV_FIELD(eqp, FWALERT_DATA));
1189 		else
1190 			should_abort = eecp->eec_exception(arg,
1191 				EFX_EXCEPTION_UNKNOWN_FWALERT,
1192 				MCDI_EV_FIELD(eqp, DATA));
1193 		break;
1194 	}
1195 
1196 	default:
1197 		EFSYS_PROBE1(mc_pcol_error, int, code);
1198 		break;
1199 	}
1200 
1201 out:
1202 	return (should_abort);
1203 }
1204 
1205 #endif	/* EFSYS_OPT_MCDI */
1206 
1207 static	__checkReturn	efx_rc_t
1208 siena_ev_qprime(
1209 	__in		efx_evq_t *eep,
1210 	__in		unsigned int count)
1211 {
1212 	efx_nic_t *enp = eep->ee_enp;
1213 	uint32_t rptr;
1214 	efx_dword_t dword;
1215 
1216 	rptr = count & eep->ee_mask;
1217 
1218 	EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1219 
1220 	EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1221 			    &dword, B_FALSE);
1222 
1223 	return (0);
1224 }
1225 
1226 static		void
1227 siena_ev_qpost(
1228 	__in	efx_evq_t *eep,
1229 	__in	uint16_t data)
1230 {
1231 	efx_nic_t *enp = eep->ee_enp;
1232 	efx_qword_t ev;
1233 	efx_oword_t oword;
1234 
1235 	EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1236 	    FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1237 
1238 	EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1239 	    EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1240 	    EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1241 
1242 	EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1243 }
1244 
1245 static	__checkReturn	efx_rc_t
1246 siena_ev_qmoderate(
1247 	__in		efx_evq_t *eep,
1248 	__in		unsigned int us)
1249 {
1250 	efx_nic_t *enp = eep->ee_enp;
1251 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1252 	unsigned int locked;
1253 	efx_dword_t dword;
1254 	efx_rc_t rc;
1255 
1256 	if (us > encp->enc_evq_timer_max_us) {
1257 		rc = EINVAL;
1258 		goto fail1;
1259 	}
1260 
1261 	/* If the value is zero then disable the timer */
1262 	if (us == 0) {
1263 		EFX_POPULATE_DWORD_2(dword,
1264 		    FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1265 		    FRF_CZ_TC_TIMER_VAL, 0);
1266 	} else {
1267 		unsigned int ticks;
1268 
1269 		if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1270 			goto fail2;
1271 
1272 		EFSYS_ASSERT(ticks > 0);
1273 		EFX_POPULATE_DWORD_2(dword,
1274 		    FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1275 		    FRF_CZ_TC_TIMER_VAL, ticks - 1);
1276 	}
1277 
1278 	locked = (eep->ee_index == 0) ? 1 : 0;
1279 
1280 	EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1281 	    eep->ee_index, &dword, locked);
1282 
1283 	return (0);
1284 
1285 fail2:
1286 	EFSYS_PROBE(fail2);
1287 fail1:
1288 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
1289 
1290 	return (rc);
1291 }
1292 
1293 static	__checkReturn	efx_rc_t
1294 siena_ev_qcreate(
1295 	__in		efx_nic_t *enp,
1296 	__in		unsigned int index,
1297 	__in		efsys_mem_t *esmp,
1298 	__in		size_t ndescs,
1299 	__in		uint32_t id,
1300 	__in		uint32_t us,
1301 	__in		uint32_t flags,
1302 	__in		efx_evq_t *eep)
1303 {
1304 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1305 	uint32_t size;
1306 	efx_oword_t oword;
1307 	efx_rc_t rc;
1308 	boolean_t notify_mode;
1309 
1310 	_NOTE(ARGUNUSED(esmp))
1311 
1312 	EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1313 	EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1314 
1315 	if (!ISP2(ndescs) ||
1316 	    (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
1317 		rc = EINVAL;
1318 		goto fail1;
1319 	}
1320 	if (index >= encp->enc_evq_limit) {
1321 		rc = EINVAL;
1322 		goto fail2;
1323 	}
1324 #if EFSYS_OPT_RX_SCALE
1325 	if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1326 	    index >= EFX_MAXRSS_LEGACY) {
1327 		rc = EINVAL;
1328 		goto fail3;
1329 	}
1330 #endif
1331 	for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1332 	    size++)
1333 		if ((1 << size) == (int)(ndescs / EFX_EVQ_MINNEVS))
1334 			break;
1335 	if (id + (1 << size) >= encp->enc_buftbl_limit) {
1336 		rc = EINVAL;
1337 		goto fail4;
1338 	}
1339 
1340 	/* Set up the handler table */
1341 	eep->ee_rx	= siena_ev_rx;
1342 	eep->ee_tx	= siena_ev_tx;
1343 	eep->ee_driver	= siena_ev_driver;
1344 	eep->ee_global	= siena_ev_global;
1345 	eep->ee_drv_gen	= siena_ev_drv_gen;
1346 #if EFSYS_OPT_MCDI
1347 	eep->ee_mcdi	= siena_ev_mcdi;
1348 #endif	/* EFSYS_OPT_MCDI */
1349 
1350 	notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1351 	    EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1352 
1353 	/* Set up the new event queue */
1354 	EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1355 	    FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1356 	    FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1357 	EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1358 
1359 	EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1360 	    FRF_AZ_EVQ_BUF_BASE_ID, id);
1361 
1362 	EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1363 
1364 	/* Set initial interrupt moderation */
1365 	siena_ev_qmoderate(eep, us);
1366 
1367 	return (0);
1368 
1369 fail4:
1370 	EFSYS_PROBE(fail4);
1371 #if EFSYS_OPT_RX_SCALE
1372 fail3:
1373 	EFSYS_PROBE(fail3);
1374 #endif
1375 fail2:
1376 	EFSYS_PROBE(fail2);
1377 fail1:
1378 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
1379 
1380 	return (rc);
1381 }
1382 
1383 #endif /* EFSYS_OPT_SIENA */
1384 
1385 #if EFSYS_OPT_QSTATS
1386 #if EFSYS_OPT_NAMES
1387 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1388 static const char * const __efx_ev_qstat_name[] = {
1389 	"all",
1390 	"rx",
1391 	"rx_ok",
1392 	"rx_frm_trunc",
1393 	"rx_tobe_disc",
1394 	"rx_pause_frm_err",
1395 	"rx_buf_owner_id_err",
1396 	"rx_ipv4_hdr_chksum_err",
1397 	"rx_tcp_udp_chksum_err",
1398 	"rx_eth_crc_err",
1399 	"rx_ip_frag_err",
1400 	"rx_mcast_pkt",
1401 	"rx_mcast_hash_match",
1402 	"rx_tcp_ipv4",
1403 	"rx_tcp_ipv6",
1404 	"rx_udp_ipv4",
1405 	"rx_udp_ipv6",
1406 	"rx_other_ipv4",
1407 	"rx_other_ipv6",
1408 	"rx_non_ip",
1409 	"rx_batch",
1410 	"tx",
1411 	"tx_wq_ff_full",
1412 	"tx_pkt_err",
1413 	"tx_pkt_too_big",
1414 	"tx_unexpected",
1415 	"global",
1416 	"global_mnt",
1417 	"driver",
1418 	"driver_srm_upd_done",
1419 	"driver_tx_descq_fls_done",
1420 	"driver_rx_descq_fls_done",
1421 	"driver_rx_descq_fls_failed",
1422 	"driver_rx_dsc_error",
1423 	"driver_tx_dsc_error",
1424 	"drv_gen",
1425 	"mcdi_response",
1426 };
1427 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1428 
1429 		const char *
1430 efx_ev_qstat_name(
1431 	__in	efx_nic_t *enp,
1432 	__in	unsigned int id)
1433 {
1434 	_NOTE(ARGUNUSED(enp))
1435 
1436 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1437 	EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1438 
1439 	return (__efx_ev_qstat_name[id]);
1440 }
1441 #endif	/* EFSYS_OPT_NAMES */
1442 #endif	/* EFSYS_OPT_QSTATS */
1443 
1444 #if EFSYS_OPT_SIENA
1445 
1446 #if EFSYS_OPT_QSTATS
1447 static					void
1448 siena_ev_qstats_update(
1449 	__in				efx_evq_t *eep,
1450 	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat)
1451 {
1452 	unsigned int id;
1453 
1454 	for (id = 0; id < EV_NQSTATS; id++) {
1455 		efsys_stat_t *essp = &stat[id];
1456 
1457 		EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1458 		eep->ee_stat[id] = 0;
1459 	}
1460 }
1461 #endif	/* EFSYS_OPT_QSTATS */
1462 
1463 static		void
1464 siena_ev_qdestroy(
1465 	__in	efx_evq_t *eep)
1466 {
1467 	efx_nic_t *enp = eep->ee_enp;
1468 	efx_oword_t oword;
1469 
1470 	/* Purge event queue */
1471 	EFX_ZERO_OWORD(oword);
1472 
1473 	EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1474 	    eep->ee_index, &oword, B_TRUE);
1475 
1476 	EFX_ZERO_OWORD(oword);
1477 	EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1478 }
1479 
1480 static		void
1481 siena_ev_fini(
1482 	__in	efx_nic_t *enp)
1483 {
1484 	_NOTE(ARGUNUSED(enp))
1485 }
1486 
1487 #endif /* EFSYS_OPT_SIENA */
1488