xref: /freebsd/sys/dev/sfxge/common/efx.h (revision fc7284da06408923f7850a0e4e954a903b8ee038)
1 /*-
2  * Copyright (c) 2006-2015 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  *
30  * $FreeBSD$
31  */
32 
33 #ifndef	_SYS_EFX_H
34 #define	_SYS_EFX_H
35 
36 #include "efsys.h"
37 #include "efx_phy_ids.h"
38 
39 #ifdef	__cplusplus
40 extern "C" {
41 #endif
42 
43 #define	EFX_STATIC_ASSERT(_cond)		\
44 	((void)sizeof(char[(_cond) ? 1 : -1]))
45 
46 #define	EFX_ARRAY_SIZE(_array)			\
47 	(sizeof(_array) / sizeof((_array)[0]))
48 
49 #define	EFX_FIELD_OFFSET(_type, _field)		\
50 	((size_t) &(((_type *)0)->_field))
51 
52 /* Return codes */
53 
54 typedef __success(return == 0) int efx_rc_t;
55 
56 
57 /* Chip families */
58 
59 typedef enum efx_family_e {
60 	EFX_FAMILY_INVALID,
61 	EFX_FAMILY_FALCON,
62 	EFX_FAMILY_SIENA,
63 	EFX_FAMILY_HUNTINGTON,
64 	EFX_FAMILY_NTYPES
65 } efx_family_t;
66 
67 extern	__checkReturn	efx_rc_t
68 efx_family(
69 	__in		uint16_t venid,
70 	__in		uint16_t devid,
71 	__out		efx_family_t *efp);
72 
73 extern	__checkReturn	efx_rc_t
74 efx_infer_family(
75 	__in		efsys_bar_t *esbp,
76 	__out		efx_family_t *efp);
77 
78 #define	EFX_PCI_VENID_SFC			0x1924
79 
80 #define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
81 
82 #define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
83 #define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
84 #define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
85 
86 #define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
87 #define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
88 #define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
89 
90 #define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
91 #define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
92 
93 
94 #define	EFX_MEM_BAR	2
95 
96 /* Error codes */
97 
98 enum {
99 	EFX_ERR_INVALID,
100 	EFX_ERR_SRAM_OOB,
101 	EFX_ERR_BUFID_DC_OOB,
102 	EFX_ERR_MEM_PERR,
103 	EFX_ERR_RBUF_OWN,
104 	EFX_ERR_TBUF_OWN,
105 	EFX_ERR_RDESQ_OWN,
106 	EFX_ERR_TDESQ_OWN,
107 	EFX_ERR_EVQ_OWN,
108 	EFX_ERR_EVFF_OFLO,
109 	EFX_ERR_ILL_ADDR,
110 	EFX_ERR_SRAM_PERR,
111 	EFX_ERR_NCODES
112 };
113 
114 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
115 extern	__checkReturn		uint32_t
116 efx_crc32_calculate(
117 	__in			uint32_t crc_init,
118 	__in_ecount(length)	uint8_t const *input,
119 	__in			int length);
120 
121 
122 /* Type prototypes */
123 
124 typedef struct efx_rxq_s	efx_rxq_t;
125 
126 /* NIC */
127 
128 typedef struct efx_nic_s	efx_nic_t;
129 
130 #define	EFX_NIC_FUNC_PRIMARY	0x00000001
131 #define	EFX_NIC_FUNC_LINKCTRL	0x00000002
132 #define	EFX_NIC_FUNC_TRUSTED	0x00000004
133 
134 
135 extern	__checkReturn	efx_rc_t
136 efx_nic_create(
137 	__in		efx_family_t family,
138 	__in		efsys_identifier_t *esip,
139 	__in		efsys_bar_t *esbp,
140 	__in		efsys_lock_t *eslp,
141 	__deref_out	efx_nic_t **enpp);
142 
143 extern	__checkReturn	efx_rc_t
144 efx_nic_probe(
145 	__in		efx_nic_t *enp);
146 
147 #if EFSYS_OPT_PCIE_TUNE
148 
149 extern	__checkReturn	efx_rc_t
150 efx_nic_pcie_tune(
151 	__in		efx_nic_t *enp,
152 	unsigned int	nlanes);
153 
154 extern	__checkReturn	efx_rc_t
155 efx_nic_pcie_extended_sync(
156 	__in		efx_nic_t *enp);
157 
158 #endif	/* EFSYS_OPT_PCIE_TUNE */
159 
160 extern	__checkReturn	efx_rc_t
161 efx_nic_init(
162 	__in		efx_nic_t *enp);
163 
164 extern	__checkReturn	efx_rc_t
165 efx_nic_reset(
166 	__in		efx_nic_t *enp);
167 
168 #if EFSYS_OPT_DIAG
169 
170 extern	__checkReturn	efx_rc_t
171 efx_nic_register_test(
172 	__in		efx_nic_t *enp);
173 
174 #endif	/* EFSYS_OPT_DIAG */
175 
176 extern		void
177 efx_nic_fini(
178 	__in		efx_nic_t *enp);
179 
180 extern		void
181 efx_nic_unprobe(
182 	__in		efx_nic_t *enp);
183 
184 extern 		void
185 efx_nic_destroy(
186 	__in	efx_nic_t *enp);
187 
188 #if EFSYS_OPT_MCDI
189 
190 #if EFSYS_OPT_HUNTINGTON
191 /* Huntington requires MCDIv2 commands */
192 #define	WITH_MCDI_V2 1
193 #endif
194 
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
196 
197 typedef enum efx_mcdi_exception_e {
198 	EFX_MCDI_EXCEPTION_MC_REBOOT,
199 	EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
201 
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e
204 {
205 	EFX_LOG_INVALID,
206 	EFX_LOG_MCDI_REQUEST,
207 	EFX_LOG_MCDI_RESPONSE,
208 } efx_log_msg_t;
209 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 
211 typedef struct efx_mcdi_transport_s {
212 	void		*emt_context;
213 	efsys_mem_t	*emt_dma_mem;
214 	void		(*emt_execute)(void *, efx_mcdi_req_t *);
215 	void		(*emt_ev_cpl)(void *);
216 	void		(*emt_exception)(void *, efx_mcdi_exception_t);
217 #if EFSYS_OPT_MCDI_LOGGING
218 	void		(*emt_logger)(void *, efx_log_msg_t,
219 					void *, size_t, void *, size_t);
220 #endif /* EFSYS_OPT_MCDI_LOGGING */
221 } efx_mcdi_transport_t;
222 
223 extern	__checkReturn	efx_rc_t
224 efx_mcdi_init(
225 	__in		efx_nic_t *enp,
226 	__in		const efx_mcdi_transport_t *mtp);
227 
228 extern	__checkReturn	efx_rc_t
229 efx_mcdi_reboot(
230 	__in		efx_nic_t *enp);
231 
232 			void
233 efx_mcdi_new_epoch(
234 	__in		efx_nic_t *enp);
235 
236 extern			void
237 efx_mcdi_request_start(
238 	__in		efx_nic_t *enp,
239 	__in		efx_mcdi_req_t *emrp,
240 	__in		boolean_t ev_cpl);
241 
242 extern	__checkReturn	boolean_t
243 efx_mcdi_request_poll(
244 	__in		efx_nic_t *enp);
245 
246 extern	__checkReturn	boolean_t
247 efx_mcdi_request_abort(
248 	__in		efx_nic_t *enp);
249 
250 extern			void
251 efx_mcdi_fini(
252 	__in		efx_nic_t *enp);
253 
254 #endif	/* EFSYS_OPT_MCDI */
255 
256 /* INTR */
257 
258 #define	EFX_NINTR_FALCON 64
259 #define	EFX_NINTR_SIENA 1024
260 
261 typedef enum efx_intr_type_e {
262 	EFX_INTR_INVALID = 0,
263 	EFX_INTR_LINE,
264 	EFX_INTR_MESSAGE,
265 	EFX_INTR_NTYPES
266 } efx_intr_type_t;
267 
268 #define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
269 
270 extern	__checkReturn	efx_rc_t
271 efx_intr_init(
272 	__in		efx_nic_t *enp,
273 	__in		efx_intr_type_t type,
274 	__in		efsys_mem_t *esmp);
275 
276 extern 			void
277 efx_intr_enable(
278 	__in		efx_nic_t *enp);
279 
280 extern 			void
281 efx_intr_disable(
282 	__in		efx_nic_t *enp);
283 
284 extern 			void
285 efx_intr_disable_unlocked(
286 	__in		efx_nic_t *enp);
287 
288 #define	EFX_INTR_NEVQS	32
289 
290 extern __checkReturn	efx_rc_t
291 efx_intr_trigger(
292 	__in		efx_nic_t *enp,
293 	__in		unsigned int level);
294 
295 extern			void
296 efx_intr_status_line(
297 	__in		efx_nic_t *enp,
298 	__out		boolean_t *fatalp,
299 	__out		uint32_t *maskp);
300 
301 extern			void
302 efx_intr_status_message(
303 	__in		efx_nic_t *enp,
304 	__in		unsigned int message,
305 	__out		boolean_t *fatalp);
306 
307 extern			void
308 efx_intr_fatal(
309 	__in		efx_nic_t *enp);
310 
311 extern			void
312 efx_intr_fini(
313 	__in		efx_nic_t *enp);
314 
315 /* MAC */
316 
317 #if EFSYS_OPT_MAC_STATS
318 
319 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
320 typedef enum efx_mac_stat_e {
321 	EFX_MAC_RX_OCTETS,
322 	EFX_MAC_RX_PKTS,
323 	EFX_MAC_RX_UNICST_PKTS,
324 	EFX_MAC_RX_MULTICST_PKTS,
325 	EFX_MAC_RX_BRDCST_PKTS,
326 	EFX_MAC_RX_PAUSE_PKTS,
327 	EFX_MAC_RX_LE_64_PKTS,
328 	EFX_MAC_RX_65_TO_127_PKTS,
329 	EFX_MAC_RX_128_TO_255_PKTS,
330 	EFX_MAC_RX_256_TO_511_PKTS,
331 	EFX_MAC_RX_512_TO_1023_PKTS,
332 	EFX_MAC_RX_1024_TO_15XX_PKTS,
333 	EFX_MAC_RX_GE_15XX_PKTS,
334 	EFX_MAC_RX_ERRORS,
335 	EFX_MAC_RX_FCS_ERRORS,
336 	EFX_MAC_RX_DROP_EVENTS,
337 	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
338 	EFX_MAC_RX_SYMBOL_ERRORS,
339 	EFX_MAC_RX_ALIGN_ERRORS,
340 	EFX_MAC_RX_INTERNAL_ERRORS,
341 	EFX_MAC_RX_JABBER_PKTS,
342 	EFX_MAC_RX_LANE0_CHAR_ERR,
343 	EFX_MAC_RX_LANE1_CHAR_ERR,
344 	EFX_MAC_RX_LANE2_CHAR_ERR,
345 	EFX_MAC_RX_LANE3_CHAR_ERR,
346 	EFX_MAC_RX_LANE0_DISP_ERR,
347 	EFX_MAC_RX_LANE1_DISP_ERR,
348 	EFX_MAC_RX_LANE2_DISP_ERR,
349 	EFX_MAC_RX_LANE3_DISP_ERR,
350 	EFX_MAC_RX_MATCH_FAULT,
351 	EFX_MAC_RX_NODESC_DROP_CNT,
352 	EFX_MAC_TX_OCTETS,
353 	EFX_MAC_TX_PKTS,
354 	EFX_MAC_TX_UNICST_PKTS,
355 	EFX_MAC_TX_MULTICST_PKTS,
356 	EFX_MAC_TX_BRDCST_PKTS,
357 	EFX_MAC_TX_PAUSE_PKTS,
358 	EFX_MAC_TX_LE_64_PKTS,
359 	EFX_MAC_TX_65_TO_127_PKTS,
360 	EFX_MAC_TX_128_TO_255_PKTS,
361 	EFX_MAC_TX_256_TO_511_PKTS,
362 	EFX_MAC_TX_512_TO_1023_PKTS,
363 	EFX_MAC_TX_1024_TO_15XX_PKTS,
364 	EFX_MAC_TX_GE_15XX_PKTS,
365 	EFX_MAC_TX_ERRORS,
366 	EFX_MAC_TX_SGL_COL_PKTS,
367 	EFX_MAC_TX_MULT_COL_PKTS,
368 	EFX_MAC_TX_EX_COL_PKTS,
369 	EFX_MAC_TX_LATE_COL_PKTS,
370 	EFX_MAC_TX_DEF_PKTS,
371 	EFX_MAC_TX_EX_DEF_PKTS,
372 	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
373 	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
374 	EFX_MAC_PM_TRUNC_VFIFO_FULL,
375 	EFX_MAC_PM_DISCARD_VFIFO_FULL,
376 	EFX_MAC_PM_TRUNC_QBB,
377 	EFX_MAC_PM_DISCARD_QBB,
378 	EFX_MAC_PM_DISCARD_MAPPING,
379 	EFX_MAC_RXDP_Q_DISABLED_PKTS,
380 	EFX_MAC_RXDP_DI_DROPPED_PKTS,
381 	EFX_MAC_RXDP_STREAMING_PKTS,
382 	EFX_MAC_RXDP_HLB_FETCH,
383 	EFX_MAC_RXDP_HLB_WAIT,
384 	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
385 	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
386 	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
387 	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
388 	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
389 	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
390 	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
391 	EFX_MAC_VADAPTER_RX_BAD_BYTES,
392 	EFX_MAC_VADAPTER_RX_OVERFLOW,
393 	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
394 	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
395 	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
396 	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
397 	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
398 	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
399 	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
400 	EFX_MAC_VADAPTER_TX_BAD_BYTES,
401 	EFX_MAC_VADAPTER_TX_OVERFLOW,
402 	EFX_MAC_NSTATS
403 } efx_mac_stat_t;
404 
405 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
406 
407 #endif	/* EFSYS_OPT_MAC_STATS */
408 
409 typedef enum efx_link_mode_e {
410 	EFX_LINK_UNKNOWN = 0,
411 	EFX_LINK_DOWN,
412 	EFX_LINK_10HDX,
413 	EFX_LINK_10FDX,
414 	EFX_LINK_100HDX,
415 	EFX_LINK_100FDX,
416 	EFX_LINK_1000HDX,
417 	EFX_LINK_1000FDX,
418 	EFX_LINK_10000FDX,
419 	EFX_LINK_40000FDX,
420 	EFX_LINK_NMODES
421 } efx_link_mode_t;
422 
423 #define	EFX_MAC_ADDR_LEN 6
424 
425 #define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
426 
427 #define	EFX_MAC_MULTICAST_LIST_MAX	256
428 
429 #define	EFX_MAC_SDU_MAX	9202
430 
431 #define	EFX_MAC_PDU(_sdu) 				\
432 	P2ROUNDUP(((_sdu)				\
433 		    + /* EtherII */ 14			\
434 		    + /* VLAN */ 4			\
435 		    + /* CRC */ 4			\
436 		    + /* bug16011 */ 16),		\
437 		    (1 << 3))
438 
439 #define	EFX_MAC_PDU_MIN	60
440 #define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
441 
442 extern	__checkReturn	efx_rc_t
443 efx_mac_pdu_set(
444 	__in		efx_nic_t *enp,
445 	__in		size_t pdu);
446 
447 extern	__checkReturn	efx_rc_t
448 efx_mac_addr_set(
449 	__in		efx_nic_t *enp,
450 	__in		uint8_t *addr);
451 
452 extern	__checkReturn			efx_rc_t
453 efx_mac_filter_set(
454 	__in				efx_nic_t *enp,
455 	__in				boolean_t all_unicst,
456 	__in				boolean_t mulcst,
457 	__in				boolean_t all_mulcst,
458 	__in				boolean_t brdcst);
459 
460 extern	__checkReturn	efx_rc_t
461 efx_mac_multicast_list_set(
462 	__in				efx_nic_t *enp,
463 	__in_ecount(6*count)		uint8_t const *addrs,
464 	__in				int count);
465 
466 extern	__checkReturn	efx_rc_t
467 efx_mac_filter_default_rxq_set(
468 	__in		efx_nic_t *enp,
469 	__in		efx_rxq_t *erp,
470 	__in		boolean_t using_rss);
471 
472 extern			void
473 efx_mac_filter_default_rxq_clear(
474 	__in		efx_nic_t *enp);
475 
476 extern	__checkReturn	efx_rc_t
477 efx_mac_drain(
478 	__in		efx_nic_t *enp,
479 	__in		boolean_t enabled);
480 
481 extern	__checkReturn	efx_rc_t
482 efx_mac_up(
483 	__in		efx_nic_t *enp,
484 	__out		boolean_t *mac_upp);
485 
486 #define	EFX_FCNTL_RESPOND	0x00000001
487 #define	EFX_FCNTL_GENERATE	0x00000002
488 
489 extern	__checkReturn	efx_rc_t
490 efx_mac_fcntl_set(
491 	__in		efx_nic_t *enp,
492 	__in		unsigned int fcntl,
493 	__in		boolean_t autoneg);
494 
495 extern			void
496 efx_mac_fcntl_get(
497 	__in		efx_nic_t *enp,
498 	__out		unsigned int *fcntl_wantedp,
499 	__out		unsigned int *fcntl_linkp);
500 
501 #define	EFX_MAC_HASH_BITS	(1 << 8)
502 
503 extern	__checkReturn			efx_rc_t
504 efx_pktfilter_init(
505 	__in				efx_nic_t *enp);
506 
507 extern					void
508 efx_pktfilter_fini(
509 	__in				efx_nic_t *enp);
510 
511 extern	__checkReturn			efx_rc_t
512 efx_pktfilter_set(
513 	__in		efx_nic_t *enp,
514 	__in		boolean_t unicst,
515 	__in		boolean_t brdcst);
516 
517 extern	__checkReturn			efx_rc_t
518 efx_mac_hash_set(
519 	__in				efx_nic_t *enp,
520 	__in_ecount(EFX_MAC_HASH_BITS)	unsigned int const *bucket);
521 
522 #if EFSYS_OPT_MCAST_FILTER_LIST
523 extern	__checkReturn			efx_rc_t
524 efx_pktfilter_mcast_list_set(
525 	__in				efx_nic_t *enp,
526 	__in				uint8_t const *addrs,
527 	__in				int count);
528 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
529 
530 extern	__checkReturn			efx_rc_t
531 efx_pktfilter_mcast_all(
532 	__in				efx_nic_t *enp);
533 
534 #if EFSYS_OPT_MAC_STATS
535 
536 #if EFSYS_OPT_NAMES
537 
538 extern	__checkReturn			const char *
539 efx_mac_stat_name(
540 	__in				efx_nic_t *enp,
541 	__in				unsigned int id);
542 
543 #endif	/* EFSYS_OPT_NAMES */
544 
545 #define	EFX_MAC_STATS_SIZE 0x400
546 
547 /*
548  * Upload mac statistics supported by the hardware into the given buffer.
549  *
550  * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
551  * and page aligned.
552  *
553  * The hardware will only DMA statistics that it understands (of course).
554  * Drivers should not make any assumptions about which statistics are
555  * supported, especially when the statistics are generated by firmware.
556  *
557  * Thus, drivers should zero this buffer before use, so that not-understood
558  * statistics read back as zero.
559  */
560 extern	__checkReturn			efx_rc_t
561 efx_mac_stats_upload(
562 	__in				efx_nic_t *enp,
563 	__in				efsys_mem_t *esmp);
564 
565 extern	__checkReturn			efx_rc_t
566 efx_mac_stats_periodic(
567 	__in				efx_nic_t *enp,
568 	__in				efsys_mem_t *esmp,
569 	__in				uint16_t period_ms,
570 	__in				boolean_t events);
571 
572 extern	__checkReturn			efx_rc_t
573 efx_mac_stats_update(
574 	__in				efx_nic_t *enp,
575 	__in				efsys_mem_t *esmp,
576 	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
577 	__inout_opt			uint32_t *generationp);
578 
579 #endif	/* EFSYS_OPT_MAC_STATS */
580 
581 /* MON */
582 
583 typedef enum efx_mon_type_e {
584 	EFX_MON_INVALID = 0,
585 	EFX_MON_NULL,
586 	EFX_MON_LM87,
587 	EFX_MON_MAX6647,
588 	EFX_MON_SFC90X0,
589 	EFX_MON_SFC91X0,
590 	EFX_MON_NTYPES
591 } efx_mon_type_t;
592 
593 #if EFSYS_OPT_NAMES
594 
595 extern		const char *
596 efx_mon_name(
597 	__in	efx_nic_t *enp);
598 
599 #endif	/* EFSYS_OPT_NAMES */
600 
601 extern	__checkReturn	efx_rc_t
602 efx_mon_init(
603 	__in		efx_nic_t *enp);
604 
605 #if EFSYS_OPT_MON_STATS
606 
607 #define	EFX_MON_STATS_PAGE_SIZE 0x100
608 #define	EFX_MON_MASK_ELEMENT_SIZE 32
609 
610 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */
611 typedef enum efx_mon_stat_e {
612 	EFX_MON_STAT_2_5V,
613 	EFX_MON_STAT_VCCP1,
614 	EFX_MON_STAT_VCC,
615 	EFX_MON_STAT_5V,
616 	EFX_MON_STAT_12V,
617 	EFX_MON_STAT_VCCP2,
618 	EFX_MON_STAT_EXT_TEMP,
619 	EFX_MON_STAT_INT_TEMP,
620 	EFX_MON_STAT_AIN1,
621 	EFX_MON_STAT_AIN2,
622 	EFX_MON_STAT_INT_COOLING,
623 	EFX_MON_STAT_EXT_COOLING,
624 	EFX_MON_STAT_1V,
625 	EFX_MON_STAT_1_2V,
626 	EFX_MON_STAT_1_8V,
627 	EFX_MON_STAT_3_3V,
628 	EFX_MON_STAT_1_2VA,
629 	EFX_MON_STAT_VREF,
630 	EFX_MON_STAT_VAOE,
631 	EFX_MON_STAT_AOE_TEMP,
632 	EFX_MON_STAT_PSU_AOE_TEMP,
633 	EFX_MON_STAT_PSU_TEMP,
634 	EFX_MON_STAT_FAN0,
635 	EFX_MON_STAT_FAN1,
636 	EFX_MON_STAT_FAN2,
637 	EFX_MON_STAT_FAN3,
638 	EFX_MON_STAT_FAN4,
639 	EFX_MON_STAT_VAOE_IN,
640 	EFX_MON_STAT_IAOE,
641 	EFX_MON_STAT_IAOE_IN,
642 	EFX_MON_STAT_NIC_POWER,
643 	EFX_MON_STAT_0_9V,
644 	EFX_MON_STAT_I0_9V,
645 	EFX_MON_STAT_I1_2V,
646 	EFX_MON_STAT_0_9V_ADC,
647 	EFX_MON_STAT_INT_TEMP2,
648 	EFX_MON_STAT_VREG_TEMP,
649 	EFX_MON_STAT_VREG_0_9V_TEMP,
650 	EFX_MON_STAT_VREG_1_2V_TEMP,
651 	EFX_MON_STAT_INT_VPTAT,
652 	EFX_MON_STAT_INT_ADC_TEMP,
653 	EFX_MON_STAT_EXT_VPTAT,
654 	EFX_MON_STAT_EXT_ADC_TEMP,
655 	EFX_MON_STAT_AMBIENT_TEMP,
656 	EFX_MON_STAT_AIRFLOW,
657 	EFX_MON_STAT_VDD08D_VSS08D_CSR,
658 	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
659 	EFX_MON_STAT_HOTPOINT_TEMP,
660 	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
661 	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
662 	EFX_MON_STAT_MUM_VCC,
663 	EFX_MON_STAT_0V9_A,
664 	EFX_MON_STAT_I0V9_A,
665 	EFX_MON_STAT_0V9_A_TEMP,
666 	EFX_MON_STAT_0V9_B,
667 	EFX_MON_STAT_I0V9_B,
668 	EFX_MON_STAT_0V9_B_TEMP,
669 	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
670 	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
671 	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
672 	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
673 	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
674 	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
675 	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
676 	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
677 	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
678 	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
679 	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
680 	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
681 	EFX_MON_NSTATS
682 } efx_mon_stat_t;
683 
684 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
685 
686 typedef enum efx_mon_stat_state_e {
687 	EFX_MON_STAT_STATE_OK = 0,
688 	EFX_MON_STAT_STATE_WARNING = 1,
689 	EFX_MON_STAT_STATE_FATAL = 2,
690 	EFX_MON_STAT_STATE_BROKEN = 3,
691 	EFX_MON_STAT_STATE_NO_READING = 4,
692 } efx_mon_stat_state_t;
693 
694 typedef struct efx_mon_stat_value_s {
695 	uint16_t	emsv_value;
696 	uint16_t	emsv_state;
697 } efx_mon_stat_value_t;
698 
699 #if EFSYS_OPT_NAMES
700 
701 extern					const char *
702 efx_mon_stat_name(
703 	__in				efx_nic_t *enp,
704 	__in				efx_mon_stat_t id);
705 
706 #endif	/* EFSYS_OPT_NAMES */
707 
708 extern	__checkReturn			efx_rc_t
709 efx_mon_stats_update(
710 	__in				efx_nic_t *enp,
711 	__in				efsys_mem_t *esmp,
712 	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
713 
714 #endif	/* EFSYS_OPT_MON_STATS */
715 
716 extern		void
717 efx_mon_fini(
718 	__in	efx_nic_t *enp);
719 
720 /* PHY */
721 
722 #define	PMA_PMD_MMD	1
723 #define	PCS_MMD		3
724 #define	PHY_XS_MMD	4
725 #define	DTE_XS_MMD	5
726 #define	AN_MMD		7
727 #define	CL22EXT_MMD	29
728 
729 #define	MAXMMD		((1 << 5) - 1)
730 
731 extern	__checkReturn	efx_rc_t
732 efx_phy_verify(
733 	__in		efx_nic_t *enp);
734 
735 #if EFSYS_OPT_PHY_LED_CONTROL
736 
737 typedef enum efx_phy_led_mode_e {
738 	EFX_PHY_LED_DEFAULT = 0,
739 	EFX_PHY_LED_OFF,
740 	EFX_PHY_LED_ON,
741 	EFX_PHY_LED_FLASH,
742 	EFX_PHY_LED_NMODES
743 } efx_phy_led_mode_t;
744 
745 extern	__checkReturn	efx_rc_t
746 efx_phy_led_set(
747 	__in	efx_nic_t *enp,
748 	__in	efx_phy_led_mode_t mode);
749 
750 #endif	/* EFSYS_OPT_PHY_LED_CONTROL */
751 
752 extern	__checkReturn	efx_rc_t
753 efx_port_init(
754 	__in		efx_nic_t *enp);
755 
756 #if EFSYS_OPT_LOOPBACK
757 
758 typedef enum efx_loopback_type_e {
759 	EFX_LOOPBACK_OFF = 0,
760 	EFX_LOOPBACK_DATA = 1,
761 	EFX_LOOPBACK_GMAC = 2,
762 	EFX_LOOPBACK_XGMII = 3,
763 	EFX_LOOPBACK_XGXS = 4,
764 	EFX_LOOPBACK_XAUI = 5,
765 	EFX_LOOPBACK_GMII = 6,
766 	EFX_LOOPBACK_SGMII = 7,
767 	EFX_LOOPBACK_XGBR = 8,
768 	EFX_LOOPBACK_XFI = 9,
769 	EFX_LOOPBACK_XAUI_FAR = 10,
770 	EFX_LOOPBACK_GMII_FAR = 11,
771 	EFX_LOOPBACK_SGMII_FAR = 12,
772 	EFX_LOOPBACK_XFI_FAR = 13,
773 	EFX_LOOPBACK_GPHY = 14,
774 	EFX_LOOPBACK_PHY_XS = 15,
775 	EFX_LOOPBACK_PCS = 16,
776 	EFX_LOOPBACK_PMA_PMD = 17,
777 	EFX_LOOPBACK_XPORT = 18,
778 	EFX_LOOPBACK_XGMII_WS = 19,
779 	EFX_LOOPBACK_XAUI_WS = 20,
780 	EFX_LOOPBACK_XAUI_WS_FAR = 21,
781 	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
782 	EFX_LOOPBACK_GMII_WS = 23,
783 	EFX_LOOPBACK_XFI_WS = 24,
784 	EFX_LOOPBACK_XFI_WS_FAR = 25,
785 	EFX_LOOPBACK_PHYXS_WS = 26,
786 	EFX_LOOPBACK_PMA_INT = 27,
787 	EFX_LOOPBACK_SD_NEAR = 28,
788 	EFX_LOOPBACK_SD_FAR = 29,
789 	EFX_LOOPBACK_PMA_INT_WS = 30,
790 	EFX_LOOPBACK_SD_FEP2_WS = 31,
791 	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
792 	EFX_LOOPBACK_SD_FEP_WS = 33,
793 	EFX_LOOPBACK_SD_FES_WS = 34,
794 	EFX_LOOPBACK_NTYPES
795 } efx_loopback_type_t;
796 
797 typedef enum efx_loopback_kind_e {
798 	EFX_LOOPBACK_KIND_OFF = 0,
799 	EFX_LOOPBACK_KIND_ALL,
800 	EFX_LOOPBACK_KIND_MAC,
801 	EFX_LOOPBACK_KIND_PHY,
802 	EFX_LOOPBACK_NKINDS
803 } efx_loopback_kind_t;
804 
805 extern			void
806 efx_loopback_mask(
807 	__in	efx_loopback_kind_t loopback_kind,
808 	__out	efx_qword_t *maskp);
809 
810 extern	__checkReturn	efx_rc_t
811 efx_port_loopback_set(
812 	__in	efx_nic_t *enp,
813 	__in	efx_link_mode_t link_mode,
814 	__in	efx_loopback_type_t type);
815 
816 #if EFSYS_OPT_NAMES
817 
818 extern	__checkReturn	const char *
819 efx_loopback_type_name(
820 	__in		efx_nic_t *enp,
821 	__in		efx_loopback_type_t type);
822 
823 #endif	/* EFSYS_OPT_NAMES */
824 
825 #endif	/* EFSYS_OPT_LOOPBACK */
826 
827 extern	__checkReturn	efx_rc_t
828 efx_port_poll(
829 	__in		efx_nic_t *enp,
830 	__out_opt	efx_link_mode_t	*link_modep);
831 
832 extern 		void
833 efx_port_fini(
834 	__in	efx_nic_t *enp);
835 
836 typedef enum efx_phy_cap_type_e {
837 	EFX_PHY_CAP_INVALID = 0,
838 	EFX_PHY_CAP_10HDX,
839 	EFX_PHY_CAP_10FDX,
840 	EFX_PHY_CAP_100HDX,
841 	EFX_PHY_CAP_100FDX,
842 	EFX_PHY_CAP_1000HDX,
843 	EFX_PHY_CAP_1000FDX,
844 	EFX_PHY_CAP_10000FDX,
845 	EFX_PHY_CAP_PAUSE,
846 	EFX_PHY_CAP_ASYM,
847 	EFX_PHY_CAP_AN,
848 	EFX_PHY_CAP_40000FDX,
849 	EFX_PHY_CAP_NTYPES
850 } efx_phy_cap_type_t;
851 
852 
853 #define	EFX_PHY_CAP_CURRENT	0x00000000
854 #define	EFX_PHY_CAP_DEFAULT	0x00000001
855 #define	EFX_PHY_CAP_PERM	0x00000002
856 
857 extern		void
858 efx_phy_adv_cap_get(
859 	__in		efx_nic_t *enp,
860 	__in            uint32_t flag,
861 	__out		uint32_t *maskp);
862 
863 extern	__checkReturn	efx_rc_t
864 efx_phy_adv_cap_set(
865 	__in		efx_nic_t *enp,
866 	__in		uint32_t mask);
867 
868 extern			void
869 efx_phy_lp_cap_get(
870 	__in		efx_nic_t *enp,
871 	__out		uint32_t *maskp);
872 
873 extern	__checkReturn	efx_rc_t
874 efx_phy_oui_get(
875 	__in		efx_nic_t *enp,
876 	__out		uint32_t *ouip);
877 
878 typedef enum efx_phy_media_type_e {
879 	EFX_PHY_MEDIA_INVALID = 0,
880 	EFX_PHY_MEDIA_XAUI,
881 	EFX_PHY_MEDIA_CX4,
882 	EFX_PHY_MEDIA_KX4,
883 	EFX_PHY_MEDIA_XFP,
884 	EFX_PHY_MEDIA_SFP_PLUS,
885 	EFX_PHY_MEDIA_BASE_T,
886 	EFX_PHY_MEDIA_QSFP_PLUS,
887 	EFX_PHY_MEDIA_NTYPES
888 } efx_phy_media_type_t;
889 
890 /* Get the type of medium currently used.  If the board has ports for
891  * modules, a module is present, and we recognise the media type of
892  * the module, then this will be the media type of the module.
893  * Otherwise it will be the media type of the port.
894  */
895 extern			void
896 efx_phy_media_type_get(
897 	__in		efx_nic_t *enp,
898 	__out		efx_phy_media_type_t *typep);
899 
900 #if EFSYS_OPT_PHY_STATS
901 
902 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
903 typedef enum efx_phy_stat_e {
904 	EFX_PHY_STAT_OUI,
905 	EFX_PHY_STAT_PMA_PMD_LINK_UP,
906 	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
907 	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
908 	EFX_PHY_STAT_PMA_PMD_REV_A,
909 	EFX_PHY_STAT_PMA_PMD_REV_B,
910 	EFX_PHY_STAT_PMA_PMD_REV_C,
911 	EFX_PHY_STAT_PMA_PMD_REV_D,
912 	EFX_PHY_STAT_PCS_LINK_UP,
913 	EFX_PHY_STAT_PCS_RX_FAULT,
914 	EFX_PHY_STAT_PCS_TX_FAULT,
915 	EFX_PHY_STAT_PCS_BER,
916 	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
917 	EFX_PHY_STAT_PHY_XS_LINK_UP,
918 	EFX_PHY_STAT_PHY_XS_RX_FAULT,
919 	EFX_PHY_STAT_PHY_XS_TX_FAULT,
920 	EFX_PHY_STAT_PHY_XS_ALIGN,
921 	EFX_PHY_STAT_PHY_XS_SYNC_A,
922 	EFX_PHY_STAT_PHY_XS_SYNC_B,
923 	EFX_PHY_STAT_PHY_XS_SYNC_C,
924 	EFX_PHY_STAT_PHY_XS_SYNC_D,
925 	EFX_PHY_STAT_AN_LINK_UP,
926 	EFX_PHY_STAT_AN_MASTER,
927 	EFX_PHY_STAT_AN_LOCAL_RX_OK,
928 	EFX_PHY_STAT_AN_REMOTE_RX_OK,
929 	EFX_PHY_STAT_CL22EXT_LINK_UP,
930 	EFX_PHY_STAT_SNR_A,
931 	EFX_PHY_STAT_SNR_B,
932 	EFX_PHY_STAT_SNR_C,
933 	EFX_PHY_STAT_SNR_D,
934 	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
935 	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
936 	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
937 	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
938 	EFX_PHY_STAT_AN_COMPLETE,
939 	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
940 	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
941 	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
942 	EFX_PHY_STAT_PCS_FW_VERSION_0,
943 	EFX_PHY_STAT_PCS_FW_VERSION_1,
944 	EFX_PHY_STAT_PCS_FW_VERSION_2,
945 	EFX_PHY_STAT_PCS_FW_VERSION_3,
946 	EFX_PHY_STAT_PCS_FW_BUILD_YY,
947 	EFX_PHY_STAT_PCS_FW_BUILD_MM,
948 	EFX_PHY_STAT_PCS_FW_BUILD_DD,
949 	EFX_PHY_STAT_PCS_OP_MODE,
950 	EFX_PHY_NSTATS
951 } efx_phy_stat_t;
952 
953 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
954 
955 #if EFSYS_OPT_NAMES
956 
957 extern					const char *
958 efx_phy_stat_name(
959 	__in				efx_nic_t *enp,
960 	__in				efx_phy_stat_t stat);
961 
962 #endif	/* EFSYS_OPT_NAMES */
963 
964 #define	EFX_PHY_STATS_SIZE 0x100
965 
966 extern	__checkReturn			efx_rc_t
967 efx_phy_stats_update(
968 	__in				efx_nic_t *enp,
969 	__in				efsys_mem_t *esmp,
970 	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
971 
972 #endif	/* EFSYS_OPT_PHY_STATS */
973 
974 #if EFSYS_OPT_PHY_PROPS
975 
976 #if EFSYS_OPT_NAMES
977 
978 extern		const char *
979 efx_phy_prop_name(
980 	__in	efx_nic_t *enp,
981 	__in	unsigned int id);
982 
983 #endif	/* EFSYS_OPT_NAMES */
984 
985 #define	EFX_PHY_PROP_DEFAULT	0x00000001
986 
987 extern	__checkReturn	efx_rc_t
988 efx_phy_prop_get(
989 	__in		efx_nic_t *enp,
990 	__in		unsigned int id,
991 	__in		uint32_t flags,
992 	__out		uint32_t *valp);
993 
994 extern	__checkReturn	efx_rc_t
995 efx_phy_prop_set(
996 	__in		efx_nic_t *enp,
997 	__in		unsigned int id,
998 	__in		uint32_t val);
999 
1000 #endif	/* EFSYS_OPT_PHY_PROPS */
1001 
1002 #if EFSYS_OPT_BIST
1003 
1004 typedef enum efx_bist_type_e {
1005 	EFX_BIST_TYPE_UNKNOWN,
1006 	EFX_BIST_TYPE_PHY_NORMAL,
1007 	EFX_BIST_TYPE_PHY_CABLE_SHORT,
1008 	EFX_BIST_TYPE_PHY_CABLE_LONG,
1009 	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1010 	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1011 	EFX_BIST_TYPE_REG,	/* Test the register memories */
1012 	EFX_BIST_TYPE_NTYPES,
1013 } efx_bist_type_t;
1014 
1015 typedef enum efx_bist_result_e {
1016 	EFX_BIST_RESULT_UNKNOWN,
1017 	EFX_BIST_RESULT_RUNNING,
1018 	EFX_BIST_RESULT_PASSED,
1019 	EFX_BIST_RESULT_FAILED,
1020 } efx_bist_result_t;
1021 
1022 typedef enum efx_phy_cable_status_e {
1023 	EFX_PHY_CABLE_STATUS_OK,
1024 	EFX_PHY_CABLE_STATUS_INVALID,
1025 	EFX_PHY_CABLE_STATUS_OPEN,
1026 	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1027 	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1028 	EFX_PHY_CABLE_STATUS_BUSY,
1029 } efx_phy_cable_status_t;
1030 
1031 typedef enum efx_bist_value_e {
1032 	EFX_BIST_PHY_CABLE_LENGTH_A,
1033 	EFX_BIST_PHY_CABLE_LENGTH_B,
1034 	EFX_BIST_PHY_CABLE_LENGTH_C,
1035 	EFX_BIST_PHY_CABLE_LENGTH_D,
1036 	EFX_BIST_PHY_CABLE_STATUS_A,
1037 	EFX_BIST_PHY_CABLE_STATUS_B,
1038 	EFX_BIST_PHY_CABLE_STATUS_C,
1039 	EFX_BIST_PHY_CABLE_STATUS_D,
1040 	EFX_BIST_FAULT_CODE,
1041 	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1042 	 * response. */
1043 	EFX_BIST_MEM_TEST,
1044 	EFX_BIST_MEM_ADDR,
1045 	EFX_BIST_MEM_BUS,
1046 	EFX_BIST_MEM_EXPECT,
1047 	EFX_BIST_MEM_ACTUAL,
1048 	EFX_BIST_MEM_ECC,
1049 	EFX_BIST_MEM_ECC_PARITY,
1050 	EFX_BIST_MEM_ECC_FATAL,
1051 	EFX_BIST_NVALUES,
1052 } efx_bist_value_t;
1053 
1054 extern	__checkReturn		efx_rc_t
1055 efx_bist_enable_offline(
1056 	__in			efx_nic_t *enp);
1057 
1058 extern	__checkReturn		efx_rc_t
1059 efx_bist_start(
1060 	__in			efx_nic_t *enp,
1061 	__in			efx_bist_type_t type);
1062 
1063 extern	__checkReturn		efx_rc_t
1064 efx_bist_poll(
1065 	__in			efx_nic_t *enp,
1066 	__in			efx_bist_type_t type,
1067 	__out			efx_bist_result_t *resultp,
1068 	__out_opt		uint32_t *value_maskp,
1069 	__out_ecount_opt(count)	unsigned long *valuesp,
1070 	__in			size_t count);
1071 
1072 extern				void
1073 efx_bist_stop(
1074 	__in			efx_nic_t *enp,
1075 	__in			efx_bist_type_t type);
1076 
1077 #endif	/* EFSYS_OPT_BIST */
1078 
1079 #define	EFX_FEATURE_IPV6		0x00000001
1080 #define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1081 #define	EFX_FEATURE_LINK_EVENTS		0x00000004
1082 #define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1083 #define	EFX_FEATURE_WOL			0x00000010
1084 #define	EFX_FEATURE_MCDI		0x00000020
1085 #define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1086 #define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1087 #define	EFX_FEATURE_TURBO		0x00000100
1088 #define	EFX_FEATURE_MCDI_DMA		0x00000200
1089 #define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1090 #define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1091 #define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1092 
1093 typedef struct efx_nic_cfg_s {
1094 	uint32_t		enc_board_type;
1095 	uint32_t		enc_phy_type;
1096 #if EFSYS_OPT_NAMES
1097 	char			enc_phy_name[21];
1098 #endif
1099 	char			enc_phy_revision[21];
1100 	efx_mon_type_t		enc_mon_type;
1101 #if EFSYS_OPT_MON_STATS
1102 	uint32_t		enc_mon_stat_dma_buf_size;
1103 	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1104 #endif
1105 	unsigned int		enc_features;
1106 	uint8_t			enc_mac_addr[6];
1107 	uint8_t			enc_port;	/* PHY port number */
1108 	uint32_t		enc_func_flags;
1109 	uint32_t		enc_intr_vec_base;
1110 	uint32_t		enc_intr_limit;
1111 	uint32_t		enc_evq_limit;
1112 	uint32_t		enc_txq_limit;
1113 	uint32_t		enc_rxq_limit;
1114 	uint32_t		enc_buftbl_limit;
1115 	uint32_t		enc_piobuf_limit;
1116 	uint32_t		enc_piobuf_size;
1117 	uint32_t		enc_evq_timer_quantum_ns;
1118 	uint32_t		enc_evq_timer_max_us;
1119 	uint32_t		enc_clk_mult;
1120 	uint32_t		enc_rx_prefix_size;
1121 	uint32_t		enc_rx_buf_align_start;
1122 	uint32_t		enc_rx_buf_align_end;
1123 #if EFSYS_OPT_LOOPBACK
1124 	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1125 #endif	/* EFSYS_OPT_LOOPBACK */
1126 #if EFSYS_OPT_PHY_FLAGS
1127 	uint32_t		enc_phy_flags_mask;
1128 #endif	/* EFSYS_OPT_PHY_FLAGS */
1129 #if EFSYS_OPT_PHY_LED_CONTROL
1130 	uint32_t		enc_led_mask;
1131 #endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1132 #if EFSYS_OPT_PHY_STATS
1133 	uint64_t		enc_phy_stat_mask;
1134 #endif	/* EFSYS_OPT_PHY_STATS */
1135 #if EFSYS_OPT_PHY_PROPS
1136 	unsigned int		enc_phy_nprops;
1137 #endif	/* EFSYS_OPT_PHY_PROPS */
1138 #if EFSYS_OPT_SIENA
1139 	uint8_t			enc_mcdi_mdio_channel;
1140 #if EFSYS_OPT_PHY_STATS
1141 	uint32_t		enc_mcdi_phy_stat_mask;
1142 #endif	/* EFSYS_OPT_PHY_STATS */
1143 #endif /* EFSYS_OPT_SIENA */
1144 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
1145 #if EFSYS_OPT_MON_STATS
1146 	uint32_t		*enc_mcdi_sensor_maskp;
1147 	uint32_t		enc_mcdi_sensor_mask_size;
1148 #endif	/* EFSYS_OPT_MON_STATS */
1149 #endif	/* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */
1150 #if EFSYS_OPT_BIST
1151 	uint32_t		enc_bist_mask;
1152 #endif	/* EFSYS_OPT_BIST */
1153 #if EFSYS_OPT_HUNTINGTON
1154 	uint32_t		enc_pf;
1155 	uint32_t		enc_vf;
1156 	uint32_t		enc_privilege_mask;
1157 #endif /* EFSYS_OPT_HUNTINGTON */
1158 	boolean_t		enc_bug26807_workaround;
1159 	boolean_t		enc_bug35388_workaround;
1160 	boolean_t		enc_bug41750_workaround;
1161 	boolean_t		enc_rx_batching_enabled;
1162 	/* Maximum number of descriptors completed in an rx event. */
1163 	uint32_t		enc_rx_batch_max;
1164         /* Number of rx descriptors the hardware requires for a push. */
1165         uint32_t		enc_rx_push_align;
1166 	/*
1167 	 * Maximum number of bytes into the packet the TCP header can start for
1168 	 * the hardware to apply TSO packet edits.
1169 	 */
1170 	uint32_t                enc_tx_tso_tcp_header_offset_limit;
1171 	boolean_t               enc_fw_assisted_tso_enabled;
1172 	boolean_t               enc_hw_tx_insert_vlan_enabled;
1173 	/* Datapath firmware vadapter/vport/vswitch support */
1174 	boolean_t		enc_datapath_cap_evb;
1175 	boolean_t               enc_rx_disable_scatter_supported;
1176 	boolean_t               enc_allow_set_mac_with_installed_filters;
1177 	/* External port identifier */
1178 	uint8_t			enc_external_port;
1179 	uint32_t		enc_mcdi_max_payload_length;
1180 } efx_nic_cfg_t;
1181 
1182 #define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1183 #define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1184 
1185 #define	EFX_PCI_FUNCTION(_encp)	\
1186 	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1187 
1188 #define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1189 
1190 extern			const efx_nic_cfg_t *
1191 efx_nic_cfg_get(
1192 	__in		efx_nic_t *enp);
1193 
1194 /* Driver resource limits (minimum required/maximum usable). */
1195 typedef struct efx_drv_limits_s
1196 {
1197 	uint32_t	edl_min_evq_count;
1198 	uint32_t	edl_max_evq_count;
1199 
1200 	uint32_t	edl_min_rxq_count;
1201 	uint32_t	edl_max_rxq_count;
1202 
1203 	uint32_t	edl_min_txq_count;
1204 	uint32_t	edl_max_txq_count;
1205 
1206 	/* PIO blocks (sub-allocated from piobuf) */
1207 	uint32_t	edl_min_pio_alloc_size;
1208 	uint32_t	edl_max_pio_alloc_count;
1209 } efx_drv_limits_t;
1210 
1211 extern	__checkReturn	efx_rc_t
1212 efx_nic_set_drv_limits(
1213 	__inout		efx_nic_t *enp,
1214 	__in		efx_drv_limits_t *edlp);
1215 
1216 typedef enum efx_nic_region_e {
1217 	EFX_REGION_VI,			/* Memory BAR UC mapping */
1218 	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1219 } efx_nic_region_t;
1220 
1221 extern	__checkReturn	efx_rc_t
1222 efx_nic_get_bar_region(
1223 	__in		efx_nic_t *enp,
1224 	__in		efx_nic_region_t region,
1225 	__out		uint32_t *offsetp,
1226 	__out		size_t *sizep);
1227 
1228 extern	__checkReturn	efx_rc_t
1229 efx_nic_get_vi_pool(
1230 	__in		efx_nic_t *enp,
1231 	__out		uint32_t *evq_countp,
1232 	__out		uint32_t *rxq_countp,
1233 	__out		uint32_t *txq_countp);
1234 
1235 
1236 #if EFSYS_OPT_VPD
1237 
1238 typedef enum efx_vpd_tag_e {
1239 	EFX_VPD_ID = 0x02,
1240 	EFX_VPD_END = 0x0f,
1241 	EFX_VPD_RO = 0x10,
1242 	EFX_VPD_RW = 0x11,
1243 } efx_vpd_tag_t;
1244 
1245 typedef uint16_t efx_vpd_keyword_t;
1246 
1247 typedef struct efx_vpd_value_s {
1248 	efx_vpd_tag_t		evv_tag;
1249 	efx_vpd_keyword_t	evv_keyword;
1250 	uint8_t			evv_length;
1251 	uint8_t			evv_value[0x100];
1252 } efx_vpd_value_t;
1253 
1254 
1255 #define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1256 
1257 extern	__checkReturn		efx_rc_t
1258 efx_vpd_init(
1259 	__in			efx_nic_t *enp);
1260 
1261 extern	__checkReturn		efx_rc_t
1262 efx_vpd_size(
1263 	__in			efx_nic_t *enp,
1264 	__out			size_t *sizep);
1265 
1266 extern	__checkReturn		efx_rc_t
1267 efx_vpd_read(
1268 	__in			efx_nic_t *enp,
1269 	__out_bcount(size)	caddr_t data,
1270 	__in			size_t size);
1271 
1272 extern	__checkReturn		efx_rc_t
1273 efx_vpd_verify(
1274 	__in			efx_nic_t *enp,
1275 	__in_bcount(size)	caddr_t data,
1276 	__in			size_t size);
1277 
1278 extern  __checkReturn		efx_rc_t
1279 efx_vpd_reinit(
1280 	__in			efx_nic_t *enp,
1281 	__in_bcount(size)	caddr_t data,
1282 	__in			size_t size);
1283 
1284 extern	__checkReturn		efx_rc_t
1285 efx_vpd_get(
1286 	__in			efx_nic_t *enp,
1287 	__in_bcount(size)	caddr_t data,
1288 	__in			size_t size,
1289 	__inout			efx_vpd_value_t *evvp);
1290 
1291 extern	__checkReturn		efx_rc_t
1292 efx_vpd_set(
1293 	__in			efx_nic_t *enp,
1294 	__inout_bcount(size)	caddr_t data,
1295 	__in			size_t size,
1296 	__in			efx_vpd_value_t *evvp);
1297 
1298 extern	__checkReturn		efx_rc_t
1299 efx_vpd_next(
1300 	__in			efx_nic_t *enp,
1301 	__inout_bcount(size)	caddr_t data,
1302 	__in			size_t size,
1303 	__out			efx_vpd_value_t *evvp,
1304 	__inout			unsigned int *contp);
1305 
1306 extern __checkReturn		efx_rc_t
1307 efx_vpd_write(
1308 	__in			efx_nic_t *enp,
1309 	__in_bcount(size)	caddr_t data,
1310 	__in			size_t size);
1311 
1312 extern				void
1313 efx_vpd_fini(
1314 	__in			efx_nic_t *enp);
1315 
1316 #endif	/* EFSYS_OPT_VPD */
1317 
1318 /* NVRAM */
1319 
1320 #if EFSYS_OPT_NVRAM
1321 
1322 typedef enum efx_nvram_type_e {
1323 	EFX_NVRAM_INVALID = 0,
1324 	EFX_NVRAM_BOOTROM,
1325 	EFX_NVRAM_BOOTROM_CFG,
1326 	EFX_NVRAM_MC_FIRMWARE,
1327 	EFX_NVRAM_MC_GOLDEN,
1328 	EFX_NVRAM_PHY,
1329 	EFX_NVRAM_NULLPHY,
1330 	EFX_NVRAM_FPGA,
1331 	EFX_NVRAM_FCFW,
1332 	EFX_NVRAM_CPLD,
1333 	EFX_NVRAM_FPGA_BACKUP,
1334 	EFX_NVRAM_DYNAMIC_CFG,
1335 	EFX_NVRAM_NTYPES,
1336 } efx_nvram_type_t;
1337 
1338 extern	__checkReturn		efx_rc_t
1339 efx_nvram_init(
1340 	__in			efx_nic_t *enp);
1341 
1342 #if EFSYS_OPT_DIAG
1343 
1344 extern	__checkReturn		efx_rc_t
1345 efx_nvram_test(
1346 	__in			efx_nic_t *enp);
1347 
1348 #endif	/* EFSYS_OPT_DIAG */
1349 
1350 extern	__checkReturn		efx_rc_t
1351 efx_nvram_size(
1352 	__in			efx_nic_t *enp,
1353 	__in			efx_nvram_type_t type,
1354 	__out			size_t *sizep);
1355 
1356 extern	__checkReturn		efx_rc_t
1357 efx_nvram_rw_start(
1358 	__in			efx_nic_t *enp,
1359 	__in			efx_nvram_type_t type,
1360 	__out_opt		size_t *pref_chunkp);
1361 
1362 extern				void
1363 efx_nvram_rw_finish(
1364 	__in			efx_nic_t *enp,
1365 	__in			efx_nvram_type_t type);
1366 
1367 extern	__checkReturn		efx_rc_t
1368 efx_nvram_get_version(
1369 	__in			efx_nic_t *enp,
1370 	__in			efx_nvram_type_t type,
1371 	__out			uint32_t *subtypep,
1372 	__out_ecount(4)		uint16_t version[4]);
1373 
1374 extern	__checkReturn		efx_rc_t
1375 efx_nvram_read_chunk(
1376 	__in			efx_nic_t *enp,
1377 	__in			efx_nvram_type_t type,
1378 	__in			unsigned int offset,
1379 	__out_bcount(size)	caddr_t data,
1380 	__in			size_t size);
1381 
1382 extern	__checkReturn		efx_rc_t
1383 efx_nvram_set_version(
1384 	__in			efx_nic_t *enp,
1385 	__in			efx_nvram_type_t type,
1386 	__in_ecount(4)		uint16_t version[4]);
1387 
1388 /* Validate contents of TLV formatted partition */
1389 extern	__checkReturn		efx_rc_t
1390 efx_nvram_tlv_validate(
1391 	__in			efx_nic_t *enp,
1392 	__in			uint32_t partn,
1393 	__in_bcount(partn_size)	caddr_t partn_data,
1394 	__in			size_t partn_size);
1395 
1396 extern	 __checkReturn		efx_rc_t
1397 efx_nvram_erase(
1398 	__in			efx_nic_t *enp,
1399 	__in			efx_nvram_type_t type);
1400 
1401 extern	__checkReturn		efx_rc_t
1402 efx_nvram_write_chunk(
1403 	__in			efx_nic_t *enp,
1404 	__in			efx_nvram_type_t type,
1405 	__in			unsigned int offset,
1406 	__in_bcount(size)	caddr_t data,
1407 	__in			size_t size);
1408 
1409 extern				void
1410 efx_nvram_fini(
1411 	__in			efx_nic_t *enp);
1412 
1413 #endif	/* EFSYS_OPT_NVRAM */
1414 
1415 #if EFSYS_OPT_BOOTCFG
1416 
1417 extern				efx_rc_t
1418 efx_bootcfg_read(
1419 	__in			efx_nic_t *enp,
1420 	__out_bcount(size)	caddr_t data,
1421 	__in			size_t size);
1422 
1423 extern				efx_rc_t
1424 efx_bootcfg_write(
1425 	__in			efx_nic_t *enp,
1426 	__in_bcount(size)	caddr_t data,
1427 	__in			size_t size);
1428 
1429 #endif	/* EFSYS_OPT_BOOTCFG */
1430 
1431 #if EFSYS_OPT_WOL
1432 
1433 typedef enum efx_wol_type_e {
1434 	EFX_WOL_TYPE_INVALID,
1435 	EFX_WOL_TYPE_MAGIC,
1436 	EFX_WOL_TYPE_BITMAP,
1437 	EFX_WOL_TYPE_LINK,
1438 	EFX_WOL_NTYPES,
1439 } efx_wol_type_t;
1440 
1441 typedef enum efx_lightsout_offload_type_e {
1442 	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1443 	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1444 	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1445 } efx_lightsout_offload_type_t;
1446 
1447 #define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1448 #define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1449 
1450 typedef union efx_wol_param_u {
1451 	struct {
1452 		uint8_t mac_addr[6];
1453 	} ewp_magic;
1454 	struct {
1455 		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1456 		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1457 		uint8_t value_len;
1458 	} ewp_bitmap;
1459 } efx_wol_param_t;
1460 
1461 typedef union efx_lightsout_offload_param_u {
1462 	struct {
1463 		uint8_t mac_addr[6];
1464 		uint32_t ip;
1465 	} elop_arp;
1466 	struct {
1467 		uint8_t mac_addr[6];
1468 		uint32_t solicited_node[4];
1469 		uint32_t ip[4];
1470 	} elop_ns;
1471 } efx_lightsout_offload_param_t;
1472 
1473 extern	__checkReturn	efx_rc_t
1474 efx_wol_init(
1475 	__in		efx_nic_t *enp);
1476 
1477 extern	__checkReturn	efx_rc_t
1478 efx_wol_filter_clear(
1479 	__in		efx_nic_t *enp);
1480 
1481 extern	__checkReturn	efx_rc_t
1482 efx_wol_filter_add(
1483 	__in		efx_nic_t *enp,
1484 	__in		efx_wol_type_t type,
1485 	__in		efx_wol_param_t *paramp,
1486 	__out		uint32_t *filter_idp);
1487 
1488 extern	__checkReturn	efx_rc_t
1489 efx_wol_filter_remove(
1490 	__in		efx_nic_t *enp,
1491 	__in		uint32_t filter_id);
1492 
1493 extern	__checkReturn	efx_rc_t
1494 efx_lightsout_offload_add(
1495 	__in		efx_nic_t *enp,
1496 	__in		efx_lightsout_offload_type_t type,
1497 	__in		efx_lightsout_offload_param_t *paramp,
1498 	__out		uint32_t *filter_idp);
1499 
1500 extern	__checkReturn	efx_rc_t
1501 efx_lightsout_offload_remove(
1502 	__in		efx_nic_t *enp,
1503 	__in		efx_lightsout_offload_type_t type,
1504 	__in		uint32_t filter_id);
1505 
1506 extern			void
1507 efx_wol_fini(
1508 	__in		efx_nic_t *enp);
1509 
1510 #endif	/* EFSYS_OPT_WOL */
1511 
1512 #if EFSYS_OPT_DIAG
1513 
1514 typedef enum efx_pattern_type_t {
1515 	EFX_PATTERN_BYTE_INCREMENT = 0,
1516 	EFX_PATTERN_ALL_THE_SAME,
1517 	EFX_PATTERN_BIT_ALTERNATE,
1518 	EFX_PATTERN_BYTE_ALTERNATE,
1519 	EFX_PATTERN_BYTE_CHANGING,
1520 	EFX_PATTERN_BIT_SWEEP,
1521 	EFX_PATTERN_NTYPES
1522 } efx_pattern_type_t;
1523 
1524 typedef 		void
1525 (*efx_sram_pattern_fn_t)(
1526 	__in		size_t row,
1527 	__in		boolean_t negate,
1528 	__out		efx_qword_t *eqp);
1529 
1530 extern	__checkReturn	efx_rc_t
1531 efx_sram_test(
1532 	__in		efx_nic_t *enp,
1533 	__in		efx_pattern_type_t type);
1534 
1535 #endif	/* EFSYS_OPT_DIAG */
1536 
1537 extern	__checkReturn	efx_rc_t
1538 efx_sram_buf_tbl_set(
1539 	__in		efx_nic_t *enp,
1540 	__in		uint32_t id,
1541 	__in		efsys_mem_t *esmp,
1542 	__in		size_t n);
1543 
1544 extern		void
1545 efx_sram_buf_tbl_clear(
1546 	__in	efx_nic_t *enp,
1547 	__in	uint32_t id,
1548 	__in	size_t n);
1549 
1550 #define	EFX_BUF_TBL_SIZE	0x20000
1551 
1552 #define	EFX_BUF_SIZE		4096
1553 
1554 /* EV */
1555 
1556 typedef struct efx_evq_s	efx_evq_t;
1557 
1558 #if EFSYS_OPT_QSTATS
1559 
1560 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1561 typedef enum efx_ev_qstat_e {
1562 	EV_ALL,
1563 	EV_RX,
1564 	EV_RX_OK,
1565 	EV_RX_FRM_TRUNC,
1566 	EV_RX_TOBE_DISC,
1567 	EV_RX_PAUSE_FRM_ERR,
1568 	EV_RX_BUF_OWNER_ID_ERR,
1569 	EV_RX_IPV4_HDR_CHKSUM_ERR,
1570 	EV_RX_TCP_UDP_CHKSUM_ERR,
1571 	EV_RX_ETH_CRC_ERR,
1572 	EV_RX_IP_FRAG_ERR,
1573 	EV_RX_MCAST_PKT,
1574 	EV_RX_MCAST_HASH_MATCH,
1575 	EV_RX_TCP_IPV4,
1576 	EV_RX_TCP_IPV6,
1577 	EV_RX_UDP_IPV4,
1578 	EV_RX_UDP_IPV6,
1579 	EV_RX_OTHER_IPV4,
1580 	EV_RX_OTHER_IPV6,
1581 	EV_RX_NON_IP,
1582 	EV_RX_BATCH,
1583 	EV_TX,
1584 	EV_TX_WQ_FF_FULL,
1585 	EV_TX_PKT_ERR,
1586 	EV_TX_PKT_TOO_BIG,
1587 	EV_TX_UNEXPECTED,
1588 	EV_GLOBAL,
1589 	EV_GLOBAL_MNT,
1590 	EV_DRIVER,
1591 	EV_DRIVER_SRM_UPD_DONE,
1592 	EV_DRIVER_TX_DESCQ_FLS_DONE,
1593 	EV_DRIVER_RX_DESCQ_FLS_DONE,
1594 	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1595 	EV_DRIVER_RX_DSC_ERROR,
1596 	EV_DRIVER_TX_DSC_ERROR,
1597 	EV_DRV_GEN,
1598 	EV_MCDI_RESPONSE,
1599 	EV_NQSTATS
1600 } efx_ev_qstat_t;
1601 
1602 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1603 
1604 #endif	/* EFSYS_OPT_QSTATS */
1605 
1606 extern	__checkReturn	efx_rc_t
1607 efx_ev_init(
1608 	__in		efx_nic_t *enp);
1609 
1610 extern		void
1611 efx_ev_fini(
1612 	__in		efx_nic_t *enp);
1613 
1614 #define	EFX_EVQ_MAXNEVS		32768
1615 #define	EFX_EVQ_MINNEVS		512
1616 
1617 #define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1618 #define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1619 
1620 extern	__checkReturn	efx_rc_t
1621 efx_ev_qcreate(
1622 	__in		efx_nic_t *enp,
1623 	__in		unsigned int index,
1624 	__in		efsys_mem_t *esmp,
1625 	__in		size_t n,
1626 	__in		uint32_t id,
1627 	__deref_out	efx_evq_t **eepp);
1628 
1629 extern		void
1630 efx_ev_qpost(
1631 	__in		efx_evq_t *eep,
1632 	__in		uint16_t data);
1633 
1634 typedef __checkReturn	boolean_t
1635 (*efx_initialized_ev_t)(
1636 	__in_opt	void *arg);
1637 
1638 #define	EFX_PKT_UNICAST		0x0004
1639 #define	EFX_PKT_START		0x0008
1640 
1641 #define	EFX_PKT_VLAN_TAGGED	0x0010
1642 #define	EFX_CKSUM_TCPUDP	0x0020
1643 #define	EFX_CKSUM_IPV4		0x0040
1644 #define	EFX_PKT_CONT		0x0080
1645 
1646 #define	EFX_CHECK_VLAN		0x0100
1647 #define	EFX_PKT_TCP		0x0200
1648 #define	EFX_PKT_UDP		0x0400
1649 #define	EFX_PKT_IPV4		0x0800
1650 
1651 #define	EFX_PKT_IPV6		0x1000
1652 #define	EFX_PKT_PREFIX_LEN	0x2000
1653 #define	EFX_ADDR_MISMATCH	0x4000
1654 #define	EFX_DISCARD		0x8000
1655 
1656 #define	EFX_EV_RX_NLABELS	32
1657 #define	EFX_EV_TX_NLABELS	32
1658 
1659 typedef	__checkReturn	boolean_t
1660 (*efx_rx_ev_t)(
1661 	__in_opt	void *arg,
1662 	__in		uint32_t label,
1663 	__in		uint32_t id,
1664 	__in		uint32_t size,
1665 	__in		uint16_t flags);
1666 
1667 typedef	__checkReturn	boolean_t
1668 (*efx_tx_ev_t)(
1669 	__in_opt	void *arg,
1670 	__in		uint32_t label,
1671 	__in		uint32_t id);
1672 
1673 #define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1674 #define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1675 #define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1676 #define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1677 #define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1678 #define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1679 #define	EFX_EXCEPTION_RX_ERROR		0x00000007
1680 #define	EFX_EXCEPTION_TX_ERROR		0x00000008
1681 #define	EFX_EXCEPTION_EV_ERROR		0x00000009
1682 
1683 typedef	__checkReturn	boolean_t
1684 (*efx_exception_ev_t)(
1685 	__in_opt	void *arg,
1686 	__in		uint32_t label,
1687 	__in		uint32_t data);
1688 
1689 typedef	__checkReturn	boolean_t
1690 (*efx_rxq_flush_done_ev_t)(
1691 	__in_opt	void *arg,
1692 	__in		uint32_t rxq_index);
1693 
1694 typedef	__checkReturn	boolean_t
1695 (*efx_rxq_flush_failed_ev_t)(
1696 	__in_opt	void *arg,
1697 	__in		uint32_t rxq_index);
1698 
1699 typedef	__checkReturn	boolean_t
1700 (*efx_txq_flush_done_ev_t)(
1701 	__in_opt	void *arg,
1702 	__in		uint32_t txq_index);
1703 
1704 typedef	__checkReturn	boolean_t
1705 (*efx_software_ev_t)(
1706 	__in_opt	void *arg,
1707 	__in		uint16_t magic);
1708 
1709 typedef	__checkReturn	boolean_t
1710 (*efx_sram_ev_t)(
1711 	__in_opt	void *arg,
1712 	__in		uint32_t code);
1713 
1714 #define	EFX_SRAM_CLEAR		0
1715 #define	EFX_SRAM_UPDATE		1
1716 #define	EFX_SRAM_ILLEGAL_CLEAR	2
1717 
1718 typedef	__checkReturn	boolean_t
1719 (*efx_wake_up_ev_t)(
1720 	__in_opt	void *arg,
1721 	__in		uint32_t label);
1722 
1723 typedef	__checkReturn	boolean_t
1724 (*efx_timer_ev_t)(
1725 	__in_opt	void *arg,
1726 	__in		uint32_t label);
1727 
1728 typedef __checkReturn	boolean_t
1729 (*efx_link_change_ev_t)(
1730 	__in_opt	void *arg,
1731 	__in		efx_link_mode_t	link_mode);
1732 
1733 #if EFSYS_OPT_MON_STATS
1734 
1735 typedef __checkReturn	boolean_t
1736 (*efx_monitor_ev_t)(
1737 	__in_opt	void *arg,
1738 	__in		efx_mon_stat_t id,
1739 	__in		efx_mon_stat_value_t value);
1740 
1741 #endif	/* EFSYS_OPT_MON_STATS */
1742 
1743 #if EFSYS_OPT_MAC_STATS
1744 
1745 typedef __checkReturn	boolean_t
1746 (*efx_mac_stats_ev_t)(
1747 	__in_opt	void *arg,
1748 	__in		uint32_t generation
1749 	);
1750 
1751 #endif	/* EFSYS_OPT_MAC_STATS */
1752 
1753 typedef struct efx_ev_callbacks_s {
1754 	efx_initialized_ev_t		eec_initialized;
1755 	efx_rx_ev_t			eec_rx;
1756 	efx_tx_ev_t			eec_tx;
1757 	efx_exception_ev_t		eec_exception;
1758 	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1759 	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1760 	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1761 	efx_software_ev_t		eec_software;
1762 	efx_sram_ev_t			eec_sram;
1763 	efx_wake_up_ev_t		eec_wake_up;
1764 	efx_timer_ev_t			eec_timer;
1765 	efx_link_change_ev_t		eec_link_change;
1766 #if EFSYS_OPT_MON_STATS
1767 	efx_monitor_ev_t		eec_monitor;
1768 #endif	/* EFSYS_OPT_MON_STATS */
1769 #if EFSYS_OPT_MAC_STATS
1770 	efx_mac_stats_ev_t		eec_mac_stats;
1771 #endif	/* EFSYS_OPT_MAC_STATS */
1772 } efx_ev_callbacks_t;
1773 
1774 extern	__checkReturn	boolean_t
1775 efx_ev_qpending(
1776 	__in		efx_evq_t *eep,
1777 	__in		unsigned int count);
1778 
1779 #if EFSYS_OPT_EV_PREFETCH
1780 
1781 extern			void
1782 efx_ev_qprefetch(
1783 	__in		efx_evq_t *eep,
1784 	__in		unsigned int count);
1785 
1786 #endif	/* EFSYS_OPT_EV_PREFETCH */
1787 
1788 extern			void
1789 efx_ev_qpoll(
1790 	__in		efx_evq_t *eep,
1791 	__inout		unsigned int *countp,
1792 	__in		const efx_ev_callbacks_t *eecp,
1793 	__in_opt	void *arg);
1794 
1795 extern	__checkReturn	efx_rc_t
1796 efx_ev_qmoderate(
1797 	__in		efx_evq_t *eep,
1798 	__in		unsigned int us);
1799 
1800 extern	__checkReturn	efx_rc_t
1801 efx_ev_qprime(
1802 	__in		efx_evq_t *eep,
1803 	__in		unsigned int count);
1804 
1805 #if EFSYS_OPT_QSTATS
1806 
1807 #if EFSYS_OPT_NAMES
1808 
1809 extern		const char *
1810 efx_ev_qstat_name(
1811 	__in	efx_nic_t *enp,
1812 	__in	unsigned int id);
1813 
1814 #endif	/* EFSYS_OPT_NAMES */
1815 
1816 extern					void
1817 efx_ev_qstats_update(
1818 	__in				efx_evq_t *eep,
1819 	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1820 
1821 #endif	/* EFSYS_OPT_QSTATS */
1822 
1823 extern		void
1824 efx_ev_qdestroy(
1825 	__in	efx_evq_t *eep);
1826 
1827 /* RX */
1828 
1829 extern	__checkReturn	efx_rc_t
1830 efx_rx_init(
1831 	__inout		efx_nic_t *enp);
1832 
1833 extern		void
1834 efx_rx_fini(
1835 	__in		efx_nic_t *enp);
1836 
1837 #if EFSYS_OPT_RX_HDR_SPLIT
1838 	__checkReturn	efx_rc_t
1839 efx_rx_hdr_split_enable(
1840 	__in		efx_nic_t *enp,
1841 	__in		unsigned int hdr_buf_size,
1842 	__in		unsigned int pld_buf_size);
1843 
1844 #endif	/* EFSYS_OPT_RX_HDR_SPLIT */
1845 
1846 #if EFSYS_OPT_RX_SCATTER
1847 	__checkReturn	efx_rc_t
1848 efx_rx_scatter_enable(
1849 	__in		efx_nic_t *enp,
1850 	__in		unsigned int buf_size);
1851 #endif	/* EFSYS_OPT_RX_SCATTER */
1852 
1853 #if EFSYS_OPT_RX_SCALE
1854 
1855 typedef enum efx_rx_hash_alg_e {
1856 	EFX_RX_HASHALG_LFSR = 0,
1857 	EFX_RX_HASHALG_TOEPLITZ
1858 } efx_rx_hash_alg_t;
1859 
1860 typedef enum efx_rx_hash_type_e {
1861 	EFX_RX_HASH_IPV4 = 0,
1862 	EFX_RX_HASH_TCPIPV4,
1863 	EFX_RX_HASH_IPV6,
1864 	EFX_RX_HASH_TCPIPV6,
1865 } efx_rx_hash_type_t;
1866 
1867 typedef enum efx_rx_hash_support_e {
1868 	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1869 	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1870 } efx_rx_hash_support_t;
1871 
1872 #define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1873 #define	EFX_MAXRSS	    	64	/* RX indirection entry range */
1874 #define	EFX_MAXRSS_LEGACY   	16 	/* See bug16611 and bug17213 */
1875 
1876 typedef enum efx_rx_scale_support_e {
1877 	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1878 	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1879 	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1880 } efx_rx_scale_support_t;
1881 
1882 extern	__checkReturn	efx_rc_t
1883 efx_rx_hash_support_get(
1884 	__in		efx_nic_t *enp,
1885 	__out		efx_rx_hash_support_t *supportp);
1886 
1887 
1888 extern	__checkReturn	efx_rc_t
1889 efx_rx_scale_support_get(
1890 	__in		efx_nic_t *enp,
1891 	__out		efx_rx_scale_support_t *supportp);
1892 
1893 extern	__checkReturn	efx_rc_t
1894 efx_rx_scale_mode_set(
1895 	__in	efx_nic_t *enp,
1896 	__in	efx_rx_hash_alg_t alg,
1897 	__in	efx_rx_hash_type_t type,
1898 	__in	boolean_t insert);
1899 
1900 extern	__checkReturn	efx_rc_t
1901 efx_rx_scale_tbl_set(
1902 	__in		efx_nic_t *enp,
1903 	__in_ecount(n)	unsigned int *table,
1904 	__in		size_t n);
1905 
1906 extern	__checkReturn	efx_rc_t
1907 efx_rx_scale_key_set(
1908 	__in		efx_nic_t *enp,
1909 	__in_ecount(n)	uint8_t *key,
1910 	__in		size_t n);
1911 
1912 extern uint32_t
1913 efx_psuedo_hdr_hash_get(
1914 	__in		efx_nic_t *enp,
1915 	__in		efx_rx_hash_alg_t func,
1916 	__in		uint8_t *buffer);
1917 
1918 #endif	/* EFSYS_OPT_RX_SCALE */
1919 
1920 extern	__checkReturn	efx_rc_t
1921 efx_psuedo_hdr_pkt_length_get(
1922 	__in		efx_nic_t *enp,
1923 	__in		uint8_t *buffer,
1924 	__out		uint16_t *pkt_lengthp);
1925 
1926 #define	EFX_RXQ_MAXNDESCS		4096
1927 #define	EFX_RXQ_MINNDESCS		512
1928 
1929 #define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1930 #define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1931 #define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1932 #define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1933 
1934 typedef enum efx_rxq_type_e {
1935 	EFX_RXQ_TYPE_DEFAULT,
1936 	EFX_RXQ_TYPE_SPLIT_HEADER,
1937 	EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1938 	EFX_RXQ_TYPE_SCATTER,
1939 	EFX_RXQ_NTYPES
1940 } efx_rxq_type_t;
1941 
1942 extern	__checkReturn	efx_rc_t
1943 efx_rx_qcreate(
1944 	__in		efx_nic_t *enp,
1945 	__in		unsigned int index,
1946 	__in		unsigned int label,
1947 	__in		efx_rxq_type_t type,
1948 	__in		efsys_mem_t *esmp,
1949 	__in		size_t n,
1950 	__in		uint32_t id,
1951 	__in		efx_evq_t *eep,
1952 	__deref_out	efx_rxq_t **erpp);
1953 
1954 typedef struct efx_buffer_s {
1955 	efsys_dma_addr_t	eb_addr;
1956 	size_t			eb_size;
1957 	boolean_t		eb_eop;
1958 } efx_buffer_t;
1959 
1960 typedef struct efx_desc_s {
1961 	efx_qword_t ed_eq;
1962 } efx_desc_t;
1963 
1964 extern			void
1965 efx_rx_qpost(
1966 	__in		efx_rxq_t *erp,
1967 	__in_ecount(n)	efsys_dma_addr_t *addrp,
1968 	__in		size_t size,
1969 	__in		unsigned int n,
1970 	__in		unsigned int completed,
1971 	__in		unsigned int added);
1972 
1973 extern		void
1974 efx_rx_qpush(
1975 	__in	efx_rxq_t *erp,
1976 	__in	unsigned int added,
1977 	__inout	unsigned int *pushedp);
1978 
1979 extern	__checkReturn	efx_rc_t
1980 efx_rx_qflush(
1981 	__in	efx_rxq_t *erp);
1982 
1983 extern		void
1984 efx_rx_qenable(
1985 	__in	efx_rxq_t *erp);
1986 
1987 extern		void
1988 efx_rx_qdestroy(
1989 	__in	efx_rxq_t *erp);
1990 
1991 /* TX */
1992 
1993 typedef struct efx_txq_s	efx_txq_t;
1994 
1995 #if EFSYS_OPT_QSTATS
1996 
1997 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1998 typedef enum efx_tx_qstat_e {
1999 	TX_POST,
2000 	TX_POST_PIO,
2001 	TX_NQSTATS
2002 } efx_tx_qstat_t;
2003 
2004 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2005 
2006 #endif	/* EFSYS_OPT_QSTATS */
2007 
2008 extern	__checkReturn	efx_rc_t
2009 efx_tx_init(
2010 	__in		efx_nic_t *enp);
2011 
2012 extern		void
2013 efx_tx_fini(
2014 	__in	efx_nic_t *enp);
2015 
2016 #define	EFX_BUG35388_WORKAROUND(_encp)					\
2017 	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2018 
2019 #define	EFX_TXQ_MAXNDESCS(_encp)					\
2020 	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2021 
2022 #define	EFX_TXQ_MINNDESCS		512
2023 
2024 #define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2025 #define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2026 #define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2027 #define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2028 
2029 #define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2030 
2031 #define	EFX_TXQ_CKSUM_IPV4	0x0001
2032 #define	EFX_TXQ_CKSUM_TCPUDP	0x0002
2033 
2034 extern	__checkReturn	efx_rc_t
2035 efx_tx_qcreate(
2036 	__in		efx_nic_t *enp,
2037 	__in		unsigned int index,
2038 	__in		unsigned int label,
2039 	__in		efsys_mem_t *esmp,
2040 	__in		size_t n,
2041 	__in		uint32_t id,
2042 	__in		uint16_t flags,
2043 	__in		efx_evq_t *eep,
2044 	__deref_out	efx_txq_t **etpp,
2045 	__out		unsigned int *addedp);
2046 
2047 extern	__checkReturn	efx_rc_t
2048 efx_tx_qpost(
2049 	__in		efx_txq_t *etp,
2050 	__in_ecount(n)	efx_buffer_t *eb,
2051 	__in		unsigned int n,
2052 	__in		unsigned int completed,
2053 	__inout		unsigned int *addedp);
2054 
2055 extern	__checkReturn	efx_rc_t
2056 efx_tx_qpace(
2057 	__in		efx_txq_t *etp,
2058 	__in		unsigned int ns);
2059 
2060 extern			void
2061 efx_tx_qpush(
2062 	__in		efx_txq_t *etp,
2063 	__in		unsigned int added,
2064 	__in		unsigned int pushed);
2065 
2066 extern	__checkReturn	efx_rc_t
2067 efx_tx_qflush(
2068 	__in		efx_txq_t *etp);
2069 
2070 extern			void
2071 efx_tx_qenable(
2072 	__in		efx_txq_t *etp);
2073 
2074 extern	__checkReturn	efx_rc_t
2075 efx_tx_qpio_enable(
2076 	__in		efx_txq_t *etp);
2077 
2078 extern			void
2079 efx_tx_qpio_disable(
2080 	__in		efx_txq_t *etp);
2081 
2082 extern	__checkReturn	efx_rc_t
2083 efx_tx_qpio_write(
2084 	__in			efx_txq_t *etp,
2085 	__in_ecount(buf_length)	uint8_t *buffer,
2086 	__in			size_t buf_length,
2087 	__in                    size_t pio_buf_offset);
2088 
2089 extern	__checkReturn	efx_rc_t
2090 efx_tx_qpio_post(
2091 	__in			efx_txq_t *etp,
2092 	__in			size_t pkt_length,
2093 	__in			unsigned int completed,
2094 	__inout			unsigned int *addedp);
2095 
2096 extern	__checkReturn	efx_rc_t
2097 efx_tx_qdesc_post(
2098 	__in		efx_txq_t *etp,
2099 	__in_ecount(n)	efx_desc_t *ed,
2100 	__in		unsigned int n,
2101 	__in		unsigned int completed,
2102 	__inout		unsigned int *addedp);
2103 
2104 extern	void
2105 efx_tx_qdesc_dma_create(
2106 	__in	efx_txq_t *etp,
2107 	__in	efsys_dma_addr_t addr,
2108 	__in	size_t size,
2109 	__in	boolean_t eop,
2110 	__out	efx_desc_t *edp);
2111 
2112 extern	void
2113 efx_tx_qdesc_tso_create(
2114 	__in	efx_txq_t *etp,
2115 	__in	uint16_t ipv4_id,
2116 	__in	uint32_t tcp_seq,
2117 	__in	uint8_t  tcp_flags,
2118 	__out	efx_desc_t *edp);
2119 
2120 extern	void
2121 efx_tx_qdesc_vlantci_create(
2122 	__in	efx_txq_t *etp,
2123 	__in	uint16_t tci,
2124 	__out	efx_desc_t *edp);
2125 
2126 #if EFSYS_OPT_QSTATS
2127 
2128 #if EFSYS_OPT_NAMES
2129 
2130 extern		const char *
2131 efx_tx_qstat_name(
2132 	__in	efx_nic_t *etp,
2133 	__in	unsigned int id);
2134 
2135 #endif	/* EFSYS_OPT_NAMES */
2136 
2137 extern					void
2138 efx_tx_qstats_update(
2139 	__in				efx_txq_t *etp,
2140 	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2141 
2142 #endif	/* EFSYS_OPT_QSTATS */
2143 
2144 extern		void
2145 efx_tx_qdestroy(
2146 	__in	efx_txq_t *etp);
2147 
2148 
2149 /* FILTER */
2150 
2151 #if EFSYS_OPT_FILTER
2152 
2153 #define	EFX_ETHER_TYPE_IPV4 0x0800
2154 #define	EFX_ETHER_TYPE_IPV6 0x86DD
2155 
2156 #define	EFX_IPPROTO_TCP 6
2157 #define	EFX_IPPROTO_UDP 17
2158 
2159 typedef enum efx_filter_flag_e {
2160 	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
2161 						 * multiple queues */
2162 	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
2163 	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
2164 						 * (priority EFX_FILTER_PRI_AUTO).
2165 						 * May only be set by the filter
2166 						 * implementation for each type.
2167 						 * A removal request will
2168 						 * restore the automatic filter
2169 						 * in its place. */
2170 	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
2171 	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
2172 } efx_filter_flag_t;
2173 
2174 typedef enum efx_filter_match_flags_e {
2175 	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2176 						 * address */
2177 	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2178 						 * address */
2179 	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2180 	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2181 	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2182 	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2183 	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2184 	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2185 	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2186 	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2187 						 * protocol */
2188 	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2189 						 * I/G bit. Used for RX default
2190 						 * unicast and multicast/
2191 						 * broadcast filters. */
2192 } efx_filter_match_flags_t;
2193 
2194 typedef enum efx_filter_priority_s {
2195 	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2196 	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2197 					 * address list or hardware
2198 					 * requirements. This may only be used
2199 					 * by the filter implementation for
2200 					 * each NIC type. */
2201 	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2202 	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2203 					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2204 					 */
2205 } efx_filter_priority_t;
2206 
2207 /*
2208  * FIXME: All these fields are assumed to be in little-endian byte order.
2209  * It may be better for some to be big-endian. See bug42804.
2210  */
2211 
2212 typedef struct efx_filter_spec_s {
2213 	uint32_t	efs_match_flags:12;
2214 	uint32_t	efs_priority:2;
2215 	uint32_t	efs_flags:6;
2216 	uint32_t	efs_dmaq_id:12;
2217 	uint32_t	efs_rss_context;
2218 	uint16_t	efs_outer_vid;
2219 	uint16_t	efs_inner_vid;
2220 	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2221 	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2222 	uint16_t	efs_ether_type;
2223 	uint8_t		efs_ip_proto;
2224 	uint16_t	efs_loc_port;
2225 	uint16_t	efs_rem_port;
2226 	efx_oword_t	efs_rem_host;
2227 	efx_oword_t	efs_loc_host;
2228 } efx_filter_spec_t;
2229 
2230 
2231 /* Default values for use in filter specifications */
2232 #define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2233 #define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2234 #define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2235 
2236 extern	__checkReturn	efx_rc_t
2237 efx_filter_init(
2238 	__in		efx_nic_t *enp);
2239 
2240 extern			void
2241 efx_filter_fini(
2242 	__in		efx_nic_t *enp);
2243 
2244 extern	__checkReturn	efx_rc_t
2245 efx_filter_insert(
2246 	__in		efx_nic_t *enp,
2247 	__inout		efx_filter_spec_t *spec);
2248 
2249 extern	__checkReturn	efx_rc_t
2250 efx_filter_remove(
2251 	__in		efx_nic_t *enp,
2252 	__inout		efx_filter_spec_t *spec);
2253 
2254 extern	__checkReturn	efx_rc_t
2255 efx_filter_restore(
2256 	__in		efx_nic_t *enp);
2257 
2258 extern	__checkReturn	efx_rc_t
2259 efx_filter_supported_filters(
2260 	__in		efx_nic_t *enp,
2261 	__out		uint32_t *list,
2262 	__out		size_t *length);
2263 
2264 extern			void
2265 efx_filter_spec_init_rx(
2266 	__inout		efx_filter_spec_t *spec,
2267 	__in		efx_filter_priority_t priority,
2268 	__in		efx_filter_flag_t flags,
2269 	__in		efx_rxq_t *erp);
2270 
2271 extern			void
2272 efx_filter_spec_init_tx(
2273 	__inout		efx_filter_spec_t *spec,
2274 	__in		efx_txq_t *etp);
2275 
2276 extern	__checkReturn	efx_rc_t
2277 efx_filter_spec_set_ipv4_local(
2278 	__inout		efx_filter_spec_t *spec,
2279 	__in		uint8_t proto,
2280 	__in		uint32_t host,
2281 	__in		uint16_t port);
2282 
2283 extern	__checkReturn	efx_rc_t
2284 efx_filter_spec_set_ipv4_full(
2285 	__inout		efx_filter_spec_t *spec,
2286 	__in		uint8_t proto,
2287 	__in		uint32_t lhost,
2288 	__in		uint16_t lport,
2289 	__in		uint32_t rhost,
2290 	__in		uint16_t rport);
2291 
2292 extern	__checkReturn	efx_rc_t
2293 efx_filter_spec_set_eth_local(
2294 	__inout		efx_filter_spec_t *spec,
2295 	__in		uint16_t vid,
2296 	__in		const uint8_t *addr);
2297 
2298 extern	__checkReturn	efx_rc_t
2299 efx_filter_spec_set_uc_def(
2300 	__inout		efx_filter_spec_t *spec);
2301 
2302 extern	__checkReturn	efx_rc_t
2303 efx_filter_spec_set_mc_def(
2304 	__inout		efx_filter_spec_t *spec);
2305 
2306 #endif	/* EFSYS_OPT_FILTER */
2307 
2308 /* HASH */
2309 
2310 extern	__checkReturn		uint32_t
2311 efx_hash_dwords(
2312 	__in_ecount(count)	uint32_t const *input,
2313 	__in			size_t count,
2314 	__in			uint32_t init);
2315 
2316 extern	__checkReturn		uint32_t
2317 efx_hash_bytes(
2318 	__in_ecount(length)	uint8_t const *input,
2319 	__in			size_t length,
2320 	__in			uint32_t init);
2321 
2322 
2323 #ifdef	__cplusplus
2324 }
2325 #endif
2326 
2327 #endif	/* _SYS_EFX_H */
2328