1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_H 36 #define _SYS_EFX_H 37 38 #include "efsys.h" 39 #include "efx_check.h" 40 #include "efx_phy_ids.h" 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define EFX_STATIC_ASSERT(_cond) \ 47 ((void)sizeof(char[(_cond) ? 1 : -1])) 48 49 #define EFX_ARRAY_SIZE(_array) \ 50 (sizeof(_array) / sizeof((_array)[0])) 51 52 #define EFX_FIELD_OFFSET(_type, _field) \ 53 ((size_t) &(((_type *)0)->_field)) 54 55 /* Return codes */ 56 57 typedef __success(return == 0) int efx_rc_t; 58 59 60 /* Chip families */ 61 62 typedef enum efx_family_e { 63 EFX_FAMILY_INVALID, 64 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 65 EFX_FAMILY_SIENA, 66 EFX_FAMILY_HUNTINGTON, 67 EFX_FAMILY_MEDFORD, 68 EFX_FAMILY_NTYPES 69 } efx_family_t; 70 71 extern __checkReturn efx_rc_t 72 efx_family( 73 __in uint16_t venid, 74 __in uint16_t devid, 75 __out efx_family_t *efp); 76 77 78 #define EFX_PCI_VENID_SFC 0x1924 79 80 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 81 82 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 83 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 84 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 85 86 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 87 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 88 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 89 90 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 91 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 92 93 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 94 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 95 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 96 97 #define EFX_MEM_BAR 2 98 99 /* Error codes */ 100 101 enum { 102 EFX_ERR_INVALID, 103 EFX_ERR_SRAM_OOB, 104 EFX_ERR_BUFID_DC_OOB, 105 EFX_ERR_MEM_PERR, 106 EFX_ERR_RBUF_OWN, 107 EFX_ERR_TBUF_OWN, 108 EFX_ERR_RDESQ_OWN, 109 EFX_ERR_TDESQ_OWN, 110 EFX_ERR_EVQ_OWN, 111 EFX_ERR_EVFF_OFLO, 112 EFX_ERR_ILL_ADDR, 113 EFX_ERR_SRAM_PERR, 114 EFX_ERR_NCODES 115 }; 116 117 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 118 extern __checkReturn uint32_t 119 efx_crc32_calculate( 120 __in uint32_t crc_init, 121 __in_ecount(length) uint8_t const *input, 122 __in int length); 123 124 125 /* Type prototypes */ 126 127 typedef struct efx_rxq_s efx_rxq_t; 128 129 /* NIC */ 130 131 typedef struct efx_nic_s efx_nic_t; 132 133 extern __checkReturn efx_rc_t 134 efx_nic_create( 135 __in efx_family_t family, 136 __in efsys_identifier_t *esip, 137 __in efsys_bar_t *esbp, 138 __in efsys_lock_t *eslp, 139 __deref_out efx_nic_t **enpp); 140 141 extern __checkReturn efx_rc_t 142 efx_nic_probe( 143 __in efx_nic_t *enp); 144 145 extern __checkReturn efx_rc_t 146 efx_nic_init( 147 __in efx_nic_t *enp); 148 149 extern __checkReturn efx_rc_t 150 efx_nic_reset( 151 __in efx_nic_t *enp); 152 153 #if EFSYS_OPT_DIAG 154 155 extern __checkReturn efx_rc_t 156 efx_nic_register_test( 157 __in efx_nic_t *enp); 158 159 #endif /* EFSYS_OPT_DIAG */ 160 161 extern void 162 efx_nic_fini( 163 __in efx_nic_t *enp); 164 165 extern void 166 efx_nic_unprobe( 167 __in efx_nic_t *enp); 168 169 extern void 170 efx_nic_destroy( 171 __in efx_nic_t *enp); 172 173 #define EFX_PCIE_LINK_SPEED_GEN1 1 174 #define EFX_PCIE_LINK_SPEED_GEN2 2 175 #define EFX_PCIE_LINK_SPEED_GEN3 3 176 177 typedef enum efx_pcie_link_performance_e { 178 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 179 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 180 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 181 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 182 } efx_pcie_link_performance_t; 183 184 extern __checkReturn efx_rc_t 185 efx_nic_calculate_pcie_link_bandwidth( 186 __in uint32_t pcie_link_width, 187 __in uint32_t pcie_link_gen, 188 __out uint32_t *bandwidth_mbpsp); 189 190 extern __checkReturn efx_rc_t 191 efx_nic_check_pcie_link_speed( 192 __in efx_nic_t *enp, 193 __in uint32_t pcie_link_width, 194 __in uint32_t pcie_link_gen, 195 __out efx_pcie_link_performance_t *resultp); 196 197 #if EFSYS_OPT_MCDI 198 199 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 200 /* Huntington and Medford require MCDIv2 commands */ 201 #define WITH_MCDI_V2 1 202 #endif 203 204 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 205 206 typedef enum efx_mcdi_exception_e { 207 EFX_MCDI_EXCEPTION_MC_REBOOT, 208 EFX_MCDI_EXCEPTION_MC_BADASSERT, 209 } efx_mcdi_exception_t; 210 211 #if EFSYS_OPT_MCDI_LOGGING 212 typedef enum efx_log_msg_e { 213 EFX_LOG_INVALID, 214 EFX_LOG_MCDI_REQUEST, 215 EFX_LOG_MCDI_RESPONSE, 216 } efx_log_msg_t; 217 #endif /* EFSYS_OPT_MCDI_LOGGING */ 218 219 typedef struct efx_mcdi_transport_s { 220 void *emt_context; 221 efsys_mem_t *emt_dma_mem; 222 void (*emt_execute)(void *, efx_mcdi_req_t *); 223 void (*emt_ev_cpl)(void *); 224 void (*emt_exception)(void *, efx_mcdi_exception_t); 225 #if EFSYS_OPT_MCDI_LOGGING 226 void (*emt_logger)(void *, efx_log_msg_t, 227 void *, size_t, void *, size_t); 228 #endif /* EFSYS_OPT_MCDI_LOGGING */ 229 #if EFSYS_OPT_MCDI_PROXY_AUTH 230 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 231 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 232 } efx_mcdi_transport_t; 233 234 extern __checkReturn efx_rc_t 235 efx_mcdi_init( 236 __in efx_nic_t *enp, 237 __in const efx_mcdi_transport_t *mtp); 238 239 extern __checkReturn efx_rc_t 240 efx_mcdi_reboot( 241 __in efx_nic_t *enp); 242 243 void 244 efx_mcdi_new_epoch( 245 __in efx_nic_t *enp); 246 247 extern void 248 efx_mcdi_get_timeout( 249 __in efx_nic_t *enp, 250 __in efx_mcdi_req_t *emrp, 251 __out uint32_t *usec_timeoutp); 252 253 extern void 254 efx_mcdi_request_start( 255 __in efx_nic_t *enp, 256 __in efx_mcdi_req_t *emrp, 257 __in boolean_t ev_cpl); 258 259 extern __checkReturn boolean_t 260 efx_mcdi_request_poll( 261 __in efx_nic_t *enp); 262 263 extern __checkReturn boolean_t 264 efx_mcdi_request_abort( 265 __in efx_nic_t *enp); 266 267 extern void 268 efx_mcdi_fini( 269 __in efx_nic_t *enp); 270 271 #endif /* EFSYS_OPT_MCDI */ 272 273 /* INTR */ 274 275 #define EFX_NINTR_SIENA 1024 276 277 typedef enum efx_intr_type_e { 278 EFX_INTR_INVALID = 0, 279 EFX_INTR_LINE, 280 EFX_INTR_MESSAGE, 281 EFX_INTR_NTYPES 282 } efx_intr_type_t; 283 284 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 285 286 extern __checkReturn efx_rc_t 287 efx_intr_init( 288 __in efx_nic_t *enp, 289 __in efx_intr_type_t type, 290 __in efsys_mem_t *esmp); 291 292 extern void 293 efx_intr_enable( 294 __in efx_nic_t *enp); 295 296 extern void 297 efx_intr_disable( 298 __in efx_nic_t *enp); 299 300 extern void 301 efx_intr_disable_unlocked( 302 __in efx_nic_t *enp); 303 304 #define EFX_INTR_NEVQS 32 305 306 extern __checkReturn efx_rc_t 307 efx_intr_trigger( 308 __in efx_nic_t *enp, 309 __in unsigned int level); 310 311 extern void 312 efx_intr_status_line( 313 __in efx_nic_t *enp, 314 __out boolean_t *fatalp, 315 __out uint32_t *maskp); 316 317 extern void 318 efx_intr_status_message( 319 __in efx_nic_t *enp, 320 __in unsigned int message, 321 __out boolean_t *fatalp); 322 323 extern void 324 efx_intr_fatal( 325 __in efx_nic_t *enp); 326 327 extern void 328 efx_intr_fini( 329 __in efx_nic_t *enp); 330 331 /* MAC */ 332 333 #if EFSYS_OPT_MAC_STATS 334 335 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 336 typedef enum efx_mac_stat_e { 337 EFX_MAC_RX_OCTETS, 338 EFX_MAC_RX_PKTS, 339 EFX_MAC_RX_UNICST_PKTS, 340 EFX_MAC_RX_MULTICST_PKTS, 341 EFX_MAC_RX_BRDCST_PKTS, 342 EFX_MAC_RX_PAUSE_PKTS, 343 EFX_MAC_RX_LE_64_PKTS, 344 EFX_MAC_RX_65_TO_127_PKTS, 345 EFX_MAC_RX_128_TO_255_PKTS, 346 EFX_MAC_RX_256_TO_511_PKTS, 347 EFX_MAC_RX_512_TO_1023_PKTS, 348 EFX_MAC_RX_1024_TO_15XX_PKTS, 349 EFX_MAC_RX_GE_15XX_PKTS, 350 EFX_MAC_RX_ERRORS, 351 EFX_MAC_RX_FCS_ERRORS, 352 EFX_MAC_RX_DROP_EVENTS, 353 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 354 EFX_MAC_RX_SYMBOL_ERRORS, 355 EFX_MAC_RX_ALIGN_ERRORS, 356 EFX_MAC_RX_INTERNAL_ERRORS, 357 EFX_MAC_RX_JABBER_PKTS, 358 EFX_MAC_RX_LANE0_CHAR_ERR, 359 EFX_MAC_RX_LANE1_CHAR_ERR, 360 EFX_MAC_RX_LANE2_CHAR_ERR, 361 EFX_MAC_RX_LANE3_CHAR_ERR, 362 EFX_MAC_RX_LANE0_DISP_ERR, 363 EFX_MAC_RX_LANE1_DISP_ERR, 364 EFX_MAC_RX_LANE2_DISP_ERR, 365 EFX_MAC_RX_LANE3_DISP_ERR, 366 EFX_MAC_RX_MATCH_FAULT, 367 EFX_MAC_RX_NODESC_DROP_CNT, 368 EFX_MAC_TX_OCTETS, 369 EFX_MAC_TX_PKTS, 370 EFX_MAC_TX_UNICST_PKTS, 371 EFX_MAC_TX_MULTICST_PKTS, 372 EFX_MAC_TX_BRDCST_PKTS, 373 EFX_MAC_TX_PAUSE_PKTS, 374 EFX_MAC_TX_LE_64_PKTS, 375 EFX_MAC_TX_65_TO_127_PKTS, 376 EFX_MAC_TX_128_TO_255_PKTS, 377 EFX_MAC_TX_256_TO_511_PKTS, 378 EFX_MAC_TX_512_TO_1023_PKTS, 379 EFX_MAC_TX_1024_TO_15XX_PKTS, 380 EFX_MAC_TX_GE_15XX_PKTS, 381 EFX_MAC_TX_ERRORS, 382 EFX_MAC_TX_SGL_COL_PKTS, 383 EFX_MAC_TX_MULT_COL_PKTS, 384 EFX_MAC_TX_EX_COL_PKTS, 385 EFX_MAC_TX_LATE_COL_PKTS, 386 EFX_MAC_TX_DEF_PKTS, 387 EFX_MAC_TX_EX_DEF_PKTS, 388 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 389 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 390 EFX_MAC_PM_TRUNC_VFIFO_FULL, 391 EFX_MAC_PM_DISCARD_VFIFO_FULL, 392 EFX_MAC_PM_TRUNC_QBB, 393 EFX_MAC_PM_DISCARD_QBB, 394 EFX_MAC_PM_DISCARD_MAPPING, 395 EFX_MAC_RXDP_Q_DISABLED_PKTS, 396 EFX_MAC_RXDP_DI_DROPPED_PKTS, 397 EFX_MAC_RXDP_STREAMING_PKTS, 398 EFX_MAC_RXDP_HLB_FETCH, 399 EFX_MAC_RXDP_HLB_WAIT, 400 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 401 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 402 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 403 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 404 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 405 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 406 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 407 EFX_MAC_VADAPTER_RX_BAD_BYTES, 408 EFX_MAC_VADAPTER_RX_OVERFLOW, 409 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 410 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 411 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 412 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 413 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 414 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 415 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 416 EFX_MAC_VADAPTER_TX_BAD_BYTES, 417 EFX_MAC_VADAPTER_TX_OVERFLOW, 418 EFX_MAC_NSTATS 419 } efx_mac_stat_t; 420 421 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 422 423 #endif /* EFSYS_OPT_MAC_STATS */ 424 425 typedef enum efx_link_mode_e { 426 EFX_LINK_UNKNOWN = 0, 427 EFX_LINK_DOWN, 428 EFX_LINK_10HDX, 429 EFX_LINK_10FDX, 430 EFX_LINK_100HDX, 431 EFX_LINK_100FDX, 432 EFX_LINK_1000HDX, 433 EFX_LINK_1000FDX, 434 EFX_LINK_10000FDX, 435 EFX_LINK_40000FDX, 436 EFX_LINK_NMODES 437 } efx_link_mode_t; 438 439 #define EFX_MAC_ADDR_LEN 6 440 441 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 442 443 #define EFX_MAC_MULTICAST_LIST_MAX 256 444 445 #define EFX_MAC_SDU_MAX 9202 446 447 #define EFX_MAC_PDU_ADJUSTMENT \ 448 (/* EtherII */ 14 \ 449 + /* VLAN */ 4 \ 450 + /* CRC */ 4 \ 451 + /* bug16011 */ 16) \ 452 453 #define EFX_MAC_PDU(_sdu) \ 454 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 455 456 /* 457 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 458 * the SDU rounded up slightly. 459 */ 460 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 461 462 #define EFX_MAC_PDU_MIN 60 463 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 464 465 extern __checkReturn efx_rc_t 466 efx_mac_pdu_get( 467 __in efx_nic_t *enp, 468 __out size_t *pdu); 469 470 extern __checkReturn efx_rc_t 471 efx_mac_pdu_set( 472 __in efx_nic_t *enp, 473 __in size_t pdu); 474 475 extern __checkReturn efx_rc_t 476 efx_mac_addr_set( 477 __in efx_nic_t *enp, 478 __in uint8_t *addr); 479 480 extern __checkReturn efx_rc_t 481 efx_mac_filter_set( 482 __in efx_nic_t *enp, 483 __in boolean_t all_unicst, 484 __in boolean_t mulcst, 485 __in boolean_t all_mulcst, 486 __in boolean_t brdcst); 487 488 extern __checkReturn efx_rc_t 489 efx_mac_multicast_list_set( 490 __in efx_nic_t *enp, 491 __in_ecount(6*count) uint8_t const *addrs, 492 __in int count); 493 494 extern __checkReturn efx_rc_t 495 efx_mac_filter_default_rxq_set( 496 __in efx_nic_t *enp, 497 __in efx_rxq_t *erp, 498 __in boolean_t using_rss); 499 500 extern void 501 efx_mac_filter_default_rxq_clear( 502 __in efx_nic_t *enp); 503 504 extern __checkReturn efx_rc_t 505 efx_mac_drain( 506 __in efx_nic_t *enp, 507 __in boolean_t enabled); 508 509 extern __checkReturn efx_rc_t 510 efx_mac_up( 511 __in efx_nic_t *enp, 512 __out boolean_t *mac_upp); 513 514 #define EFX_FCNTL_RESPOND 0x00000001 515 #define EFX_FCNTL_GENERATE 0x00000002 516 517 extern __checkReturn efx_rc_t 518 efx_mac_fcntl_set( 519 __in efx_nic_t *enp, 520 __in unsigned int fcntl, 521 __in boolean_t autoneg); 522 523 extern void 524 efx_mac_fcntl_get( 525 __in efx_nic_t *enp, 526 __out unsigned int *fcntl_wantedp, 527 __out unsigned int *fcntl_linkp); 528 529 530 #if EFSYS_OPT_MAC_STATS 531 532 #if EFSYS_OPT_NAMES 533 534 extern __checkReturn const char * 535 efx_mac_stat_name( 536 __in efx_nic_t *enp, 537 __in unsigned int id); 538 539 #endif /* EFSYS_OPT_NAMES */ 540 541 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 542 543 #define EFX_MAC_STATS_MASK_NPAGES \ 544 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 545 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 546 547 /* 548 * Get mask of MAC statistics supported by the hardware. 549 * 550 * If mask_size is insufficient to return the mask, EINVAL error is 551 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 552 * (which is sizeof (uint32_t)) is sufficient. 553 */ 554 extern __checkReturn efx_rc_t 555 efx_mac_stats_get_mask( 556 __in efx_nic_t *enp, 557 __out_bcount(mask_size) uint32_t *maskp, 558 __in size_t mask_size); 559 560 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 561 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 562 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 563 564 #define EFX_MAC_STATS_SIZE 0x400 565 566 /* 567 * Upload mac statistics supported by the hardware into the given buffer. 568 * 569 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 570 * and page aligned. 571 * 572 * The hardware will only DMA statistics that it understands (of course). 573 * Drivers should not make any assumptions about which statistics are 574 * supported, especially when the statistics are generated by firmware. 575 * 576 * Thus, drivers should zero this buffer before use, so that not-understood 577 * statistics read back as zero. 578 */ 579 extern __checkReturn efx_rc_t 580 efx_mac_stats_upload( 581 __in efx_nic_t *enp, 582 __in efsys_mem_t *esmp); 583 584 extern __checkReturn efx_rc_t 585 efx_mac_stats_periodic( 586 __in efx_nic_t *enp, 587 __in efsys_mem_t *esmp, 588 __in uint16_t period_ms, 589 __in boolean_t events); 590 591 extern __checkReturn efx_rc_t 592 efx_mac_stats_update( 593 __in efx_nic_t *enp, 594 __in efsys_mem_t *esmp, 595 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 596 __inout_opt uint32_t *generationp); 597 598 #endif /* EFSYS_OPT_MAC_STATS */ 599 600 /* MON */ 601 602 typedef enum efx_mon_type_e { 603 EFX_MON_INVALID = 0, 604 EFX_MON_SFC90X0, 605 EFX_MON_SFC91X0, 606 EFX_MON_SFC92X0, 607 EFX_MON_NTYPES 608 } efx_mon_type_t; 609 610 #if EFSYS_OPT_NAMES 611 612 extern const char * 613 efx_mon_name( 614 __in efx_nic_t *enp); 615 616 #endif /* EFSYS_OPT_NAMES */ 617 618 extern __checkReturn efx_rc_t 619 efx_mon_init( 620 __in efx_nic_t *enp); 621 622 #if EFSYS_OPT_MON_STATS 623 624 #define EFX_MON_STATS_PAGE_SIZE 0x100 625 #define EFX_MON_MASK_ELEMENT_SIZE 32 626 627 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */ 628 typedef enum efx_mon_stat_e { 629 EFX_MON_STAT_2_5V, 630 EFX_MON_STAT_VCCP1, 631 EFX_MON_STAT_VCC, 632 EFX_MON_STAT_5V, 633 EFX_MON_STAT_12V, 634 EFX_MON_STAT_VCCP2, 635 EFX_MON_STAT_EXT_TEMP, 636 EFX_MON_STAT_INT_TEMP, 637 EFX_MON_STAT_AIN1, 638 EFX_MON_STAT_AIN2, 639 EFX_MON_STAT_INT_COOLING, 640 EFX_MON_STAT_EXT_COOLING, 641 EFX_MON_STAT_1V, 642 EFX_MON_STAT_1_2V, 643 EFX_MON_STAT_1_8V, 644 EFX_MON_STAT_3_3V, 645 EFX_MON_STAT_1_2VA, 646 EFX_MON_STAT_VREF, 647 EFX_MON_STAT_VAOE, 648 EFX_MON_STAT_AOE_TEMP, 649 EFX_MON_STAT_PSU_AOE_TEMP, 650 EFX_MON_STAT_PSU_TEMP, 651 EFX_MON_STAT_FAN0, 652 EFX_MON_STAT_FAN1, 653 EFX_MON_STAT_FAN2, 654 EFX_MON_STAT_FAN3, 655 EFX_MON_STAT_FAN4, 656 EFX_MON_STAT_VAOE_IN, 657 EFX_MON_STAT_IAOE, 658 EFX_MON_STAT_IAOE_IN, 659 EFX_MON_STAT_NIC_POWER, 660 EFX_MON_STAT_0_9V, 661 EFX_MON_STAT_I0_9V, 662 EFX_MON_STAT_I1_2V, 663 EFX_MON_STAT_0_9V_ADC, 664 EFX_MON_STAT_INT_TEMP2, 665 EFX_MON_STAT_VREG_TEMP, 666 EFX_MON_STAT_VREG_0_9V_TEMP, 667 EFX_MON_STAT_VREG_1_2V_TEMP, 668 EFX_MON_STAT_INT_VPTAT, 669 EFX_MON_STAT_INT_ADC_TEMP, 670 EFX_MON_STAT_EXT_VPTAT, 671 EFX_MON_STAT_EXT_ADC_TEMP, 672 EFX_MON_STAT_AMBIENT_TEMP, 673 EFX_MON_STAT_AIRFLOW, 674 EFX_MON_STAT_VDD08D_VSS08D_CSR, 675 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 676 EFX_MON_STAT_HOTPOINT_TEMP, 677 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 678 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 679 EFX_MON_STAT_MUM_VCC, 680 EFX_MON_STAT_0V9_A, 681 EFX_MON_STAT_I0V9_A, 682 EFX_MON_STAT_0V9_A_TEMP, 683 EFX_MON_STAT_0V9_B, 684 EFX_MON_STAT_I0V9_B, 685 EFX_MON_STAT_0V9_B_TEMP, 686 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 687 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 688 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 689 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 690 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 691 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 692 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 693 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 694 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 695 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 696 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 697 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 698 EFX_MON_STAT_SODIMM_VOUT, 699 EFX_MON_STAT_SODIMM_0_TEMP, 700 EFX_MON_STAT_SODIMM_1_TEMP, 701 EFX_MON_STAT_PHY0_VCC, 702 EFX_MON_STAT_PHY1_VCC, 703 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 704 EFX_MON_STAT_BOARD_FRONT_TEMP, 705 EFX_MON_STAT_BOARD_BACK_TEMP, 706 EFX_MON_NSTATS 707 } efx_mon_stat_t; 708 709 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 710 711 typedef enum efx_mon_stat_state_e { 712 EFX_MON_STAT_STATE_OK = 0, 713 EFX_MON_STAT_STATE_WARNING = 1, 714 EFX_MON_STAT_STATE_FATAL = 2, 715 EFX_MON_STAT_STATE_BROKEN = 3, 716 EFX_MON_STAT_STATE_NO_READING = 4, 717 } efx_mon_stat_state_t; 718 719 typedef struct efx_mon_stat_value_s { 720 uint16_t emsv_value; 721 uint16_t emsv_state; 722 } efx_mon_stat_value_t; 723 724 #if EFSYS_OPT_NAMES 725 726 extern const char * 727 efx_mon_stat_name( 728 __in efx_nic_t *enp, 729 __in efx_mon_stat_t id); 730 731 #endif /* EFSYS_OPT_NAMES */ 732 733 extern __checkReturn efx_rc_t 734 efx_mon_stats_update( 735 __in efx_nic_t *enp, 736 __in efsys_mem_t *esmp, 737 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 738 739 #endif /* EFSYS_OPT_MON_STATS */ 740 741 extern void 742 efx_mon_fini( 743 __in efx_nic_t *enp); 744 745 /* PHY */ 746 747 extern __checkReturn efx_rc_t 748 efx_phy_verify( 749 __in efx_nic_t *enp); 750 751 #if EFSYS_OPT_PHY_LED_CONTROL 752 753 typedef enum efx_phy_led_mode_e { 754 EFX_PHY_LED_DEFAULT = 0, 755 EFX_PHY_LED_OFF, 756 EFX_PHY_LED_ON, 757 EFX_PHY_LED_FLASH, 758 EFX_PHY_LED_NMODES 759 } efx_phy_led_mode_t; 760 761 extern __checkReturn efx_rc_t 762 efx_phy_led_set( 763 __in efx_nic_t *enp, 764 __in efx_phy_led_mode_t mode); 765 766 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 767 768 extern __checkReturn efx_rc_t 769 efx_port_init( 770 __in efx_nic_t *enp); 771 772 #if EFSYS_OPT_LOOPBACK 773 774 typedef enum efx_loopback_type_e { 775 EFX_LOOPBACK_OFF = 0, 776 EFX_LOOPBACK_DATA = 1, 777 EFX_LOOPBACK_GMAC = 2, 778 EFX_LOOPBACK_XGMII = 3, 779 EFX_LOOPBACK_XGXS = 4, 780 EFX_LOOPBACK_XAUI = 5, 781 EFX_LOOPBACK_GMII = 6, 782 EFX_LOOPBACK_SGMII = 7, 783 EFX_LOOPBACK_XGBR = 8, 784 EFX_LOOPBACK_XFI = 9, 785 EFX_LOOPBACK_XAUI_FAR = 10, 786 EFX_LOOPBACK_GMII_FAR = 11, 787 EFX_LOOPBACK_SGMII_FAR = 12, 788 EFX_LOOPBACK_XFI_FAR = 13, 789 EFX_LOOPBACK_GPHY = 14, 790 EFX_LOOPBACK_PHY_XS = 15, 791 EFX_LOOPBACK_PCS = 16, 792 EFX_LOOPBACK_PMA_PMD = 17, 793 EFX_LOOPBACK_XPORT = 18, 794 EFX_LOOPBACK_XGMII_WS = 19, 795 EFX_LOOPBACK_XAUI_WS = 20, 796 EFX_LOOPBACK_XAUI_WS_FAR = 21, 797 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 798 EFX_LOOPBACK_GMII_WS = 23, 799 EFX_LOOPBACK_XFI_WS = 24, 800 EFX_LOOPBACK_XFI_WS_FAR = 25, 801 EFX_LOOPBACK_PHYXS_WS = 26, 802 EFX_LOOPBACK_PMA_INT = 27, 803 EFX_LOOPBACK_SD_NEAR = 28, 804 EFX_LOOPBACK_SD_FAR = 29, 805 EFX_LOOPBACK_PMA_INT_WS = 30, 806 EFX_LOOPBACK_SD_FEP2_WS = 31, 807 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 808 EFX_LOOPBACK_SD_FEP_WS = 33, 809 EFX_LOOPBACK_SD_FES_WS = 34, 810 EFX_LOOPBACK_NTYPES 811 } efx_loopback_type_t; 812 813 typedef enum efx_loopback_kind_e { 814 EFX_LOOPBACK_KIND_OFF = 0, 815 EFX_LOOPBACK_KIND_ALL, 816 EFX_LOOPBACK_KIND_MAC, 817 EFX_LOOPBACK_KIND_PHY, 818 EFX_LOOPBACK_NKINDS 819 } efx_loopback_kind_t; 820 821 extern void 822 efx_loopback_mask( 823 __in efx_loopback_kind_t loopback_kind, 824 __out efx_qword_t *maskp); 825 826 extern __checkReturn efx_rc_t 827 efx_port_loopback_set( 828 __in efx_nic_t *enp, 829 __in efx_link_mode_t link_mode, 830 __in efx_loopback_type_t type); 831 832 #if EFSYS_OPT_NAMES 833 834 extern __checkReturn const char * 835 efx_loopback_type_name( 836 __in efx_nic_t *enp, 837 __in efx_loopback_type_t type); 838 839 #endif /* EFSYS_OPT_NAMES */ 840 841 #endif /* EFSYS_OPT_LOOPBACK */ 842 843 extern __checkReturn efx_rc_t 844 efx_port_poll( 845 __in efx_nic_t *enp, 846 __out_opt efx_link_mode_t *link_modep); 847 848 extern void 849 efx_port_fini( 850 __in efx_nic_t *enp); 851 852 typedef enum efx_phy_cap_type_e { 853 EFX_PHY_CAP_INVALID = 0, 854 EFX_PHY_CAP_10HDX, 855 EFX_PHY_CAP_10FDX, 856 EFX_PHY_CAP_100HDX, 857 EFX_PHY_CAP_100FDX, 858 EFX_PHY_CAP_1000HDX, 859 EFX_PHY_CAP_1000FDX, 860 EFX_PHY_CAP_10000FDX, 861 EFX_PHY_CAP_PAUSE, 862 EFX_PHY_CAP_ASYM, 863 EFX_PHY_CAP_AN, 864 EFX_PHY_CAP_40000FDX, 865 EFX_PHY_CAP_NTYPES 866 } efx_phy_cap_type_t; 867 868 869 #define EFX_PHY_CAP_CURRENT 0x00000000 870 #define EFX_PHY_CAP_DEFAULT 0x00000001 871 #define EFX_PHY_CAP_PERM 0x00000002 872 873 extern void 874 efx_phy_adv_cap_get( 875 __in efx_nic_t *enp, 876 __in uint32_t flag, 877 __out uint32_t *maskp); 878 879 extern __checkReturn efx_rc_t 880 efx_phy_adv_cap_set( 881 __in efx_nic_t *enp, 882 __in uint32_t mask); 883 884 extern void 885 efx_phy_lp_cap_get( 886 __in efx_nic_t *enp, 887 __out uint32_t *maskp); 888 889 extern __checkReturn efx_rc_t 890 efx_phy_oui_get( 891 __in efx_nic_t *enp, 892 __out uint32_t *ouip); 893 894 typedef enum efx_phy_media_type_e { 895 EFX_PHY_MEDIA_INVALID = 0, 896 EFX_PHY_MEDIA_XAUI, 897 EFX_PHY_MEDIA_CX4, 898 EFX_PHY_MEDIA_KX4, 899 EFX_PHY_MEDIA_XFP, 900 EFX_PHY_MEDIA_SFP_PLUS, 901 EFX_PHY_MEDIA_BASE_T, 902 EFX_PHY_MEDIA_QSFP_PLUS, 903 EFX_PHY_MEDIA_NTYPES 904 } efx_phy_media_type_t; 905 906 /* Get the type of medium currently used. If the board has ports for 907 * modules, a module is present, and we recognise the media type of 908 * the module, then this will be the media type of the module. 909 * Otherwise it will be the media type of the port. 910 */ 911 extern void 912 efx_phy_media_type_get( 913 __in efx_nic_t *enp, 914 __out efx_phy_media_type_t *typep); 915 916 extern efx_rc_t 917 efx_phy_module_get_info( 918 __in efx_nic_t *enp, 919 __in uint8_t dev_addr, 920 __in uint8_t offset, 921 __in uint8_t len, 922 __out_bcount(len) uint8_t *data); 923 924 #if EFSYS_OPT_PHY_STATS 925 926 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 927 typedef enum efx_phy_stat_e { 928 EFX_PHY_STAT_OUI, 929 EFX_PHY_STAT_PMA_PMD_LINK_UP, 930 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 931 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 932 EFX_PHY_STAT_PMA_PMD_REV_A, 933 EFX_PHY_STAT_PMA_PMD_REV_B, 934 EFX_PHY_STAT_PMA_PMD_REV_C, 935 EFX_PHY_STAT_PMA_PMD_REV_D, 936 EFX_PHY_STAT_PCS_LINK_UP, 937 EFX_PHY_STAT_PCS_RX_FAULT, 938 EFX_PHY_STAT_PCS_TX_FAULT, 939 EFX_PHY_STAT_PCS_BER, 940 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 941 EFX_PHY_STAT_PHY_XS_LINK_UP, 942 EFX_PHY_STAT_PHY_XS_RX_FAULT, 943 EFX_PHY_STAT_PHY_XS_TX_FAULT, 944 EFX_PHY_STAT_PHY_XS_ALIGN, 945 EFX_PHY_STAT_PHY_XS_SYNC_A, 946 EFX_PHY_STAT_PHY_XS_SYNC_B, 947 EFX_PHY_STAT_PHY_XS_SYNC_C, 948 EFX_PHY_STAT_PHY_XS_SYNC_D, 949 EFX_PHY_STAT_AN_LINK_UP, 950 EFX_PHY_STAT_AN_MASTER, 951 EFX_PHY_STAT_AN_LOCAL_RX_OK, 952 EFX_PHY_STAT_AN_REMOTE_RX_OK, 953 EFX_PHY_STAT_CL22EXT_LINK_UP, 954 EFX_PHY_STAT_SNR_A, 955 EFX_PHY_STAT_SNR_B, 956 EFX_PHY_STAT_SNR_C, 957 EFX_PHY_STAT_SNR_D, 958 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 959 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 960 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 961 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 962 EFX_PHY_STAT_AN_COMPLETE, 963 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 964 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 965 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 966 EFX_PHY_STAT_PCS_FW_VERSION_0, 967 EFX_PHY_STAT_PCS_FW_VERSION_1, 968 EFX_PHY_STAT_PCS_FW_VERSION_2, 969 EFX_PHY_STAT_PCS_FW_VERSION_3, 970 EFX_PHY_STAT_PCS_FW_BUILD_YY, 971 EFX_PHY_STAT_PCS_FW_BUILD_MM, 972 EFX_PHY_STAT_PCS_FW_BUILD_DD, 973 EFX_PHY_STAT_PCS_OP_MODE, 974 EFX_PHY_NSTATS 975 } efx_phy_stat_t; 976 977 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 978 979 #if EFSYS_OPT_NAMES 980 981 extern const char * 982 efx_phy_stat_name( 983 __in efx_nic_t *enp, 984 __in efx_phy_stat_t stat); 985 986 #endif /* EFSYS_OPT_NAMES */ 987 988 #define EFX_PHY_STATS_SIZE 0x100 989 990 extern __checkReturn efx_rc_t 991 efx_phy_stats_update( 992 __in efx_nic_t *enp, 993 __in efsys_mem_t *esmp, 994 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 995 996 #endif /* EFSYS_OPT_PHY_STATS */ 997 998 999 #if EFSYS_OPT_BIST 1000 1001 typedef enum efx_bist_type_e { 1002 EFX_BIST_TYPE_UNKNOWN, 1003 EFX_BIST_TYPE_PHY_NORMAL, 1004 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1005 EFX_BIST_TYPE_PHY_CABLE_LONG, 1006 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1007 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 1008 EFX_BIST_TYPE_REG, /* Test the register memories */ 1009 EFX_BIST_TYPE_NTYPES, 1010 } efx_bist_type_t; 1011 1012 typedef enum efx_bist_result_e { 1013 EFX_BIST_RESULT_UNKNOWN, 1014 EFX_BIST_RESULT_RUNNING, 1015 EFX_BIST_RESULT_PASSED, 1016 EFX_BIST_RESULT_FAILED, 1017 } efx_bist_result_t; 1018 1019 typedef enum efx_phy_cable_status_e { 1020 EFX_PHY_CABLE_STATUS_OK, 1021 EFX_PHY_CABLE_STATUS_INVALID, 1022 EFX_PHY_CABLE_STATUS_OPEN, 1023 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1024 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1025 EFX_PHY_CABLE_STATUS_BUSY, 1026 } efx_phy_cable_status_t; 1027 1028 typedef enum efx_bist_value_e { 1029 EFX_BIST_PHY_CABLE_LENGTH_A, 1030 EFX_BIST_PHY_CABLE_LENGTH_B, 1031 EFX_BIST_PHY_CABLE_LENGTH_C, 1032 EFX_BIST_PHY_CABLE_LENGTH_D, 1033 EFX_BIST_PHY_CABLE_STATUS_A, 1034 EFX_BIST_PHY_CABLE_STATUS_B, 1035 EFX_BIST_PHY_CABLE_STATUS_C, 1036 EFX_BIST_PHY_CABLE_STATUS_D, 1037 EFX_BIST_FAULT_CODE, 1038 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1039 * response. */ 1040 EFX_BIST_MEM_TEST, 1041 EFX_BIST_MEM_ADDR, 1042 EFX_BIST_MEM_BUS, 1043 EFX_BIST_MEM_EXPECT, 1044 EFX_BIST_MEM_ACTUAL, 1045 EFX_BIST_MEM_ECC, 1046 EFX_BIST_MEM_ECC_PARITY, 1047 EFX_BIST_MEM_ECC_FATAL, 1048 EFX_BIST_NVALUES, 1049 } efx_bist_value_t; 1050 1051 extern __checkReturn efx_rc_t 1052 efx_bist_enable_offline( 1053 __in efx_nic_t *enp); 1054 1055 extern __checkReturn efx_rc_t 1056 efx_bist_start( 1057 __in efx_nic_t *enp, 1058 __in efx_bist_type_t type); 1059 1060 extern __checkReturn efx_rc_t 1061 efx_bist_poll( 1062 __in efx_nic_t *enp, 1063 __in efx_bist_type_t type, 1064 __out efx_bist_result_t *resultp, 1065 __out_opt uint32_t *value_maskp, 1066 __out_ecount_opt(count) unsigned long *valuesp, 1067 __in size_t count); 1068 1069 extern void 1070 efx_bist_stop( 1071 __in efx_nic_t *enp, 1072 __in efx_bist_type_t type); 1073 1074 #endif /* EFSYS_OPT_BIST */ 1075 1076 #define EFX_FEATURE_IPV6 0x00000001 1077 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1078 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1079 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1080 #define EFX_FEATURE_MCDI 0x00000020 1081 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1082 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1083 #define EFX_FEATURE_TURBO 0x00000100 1084 #define EFX_FEATURE_MCDI_DMA 0x00000200 1085 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1086 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1087 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1088 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1089 1090 typedef struct efx_nic_cfg_s { 1091 uint32_t enc_board_type; 1092 uint32_t enc_phy_type; 1093 #if EFSYS_OPT_NAMES 1094 char enc_phy_name[21]; 1095 #endif 1096 char enc_phy_revision[21]; 1097 efx_mon_type_t enc_mon_type; 1098 #if EFSYS_OPT_MON_STATS 1099 uint32_t enc_mon_stat_dma_buf_size; 1100 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1101 #endif 1102 unsigned int enc_features; 1103 uint8_t enc_mac_addr[6]; 1104 uint8_t enc_port; /* PHY port number */ 1105 uint32_t enc_intr_vec_base; 1106 uint32_t enc_intr_limit; 1107 uint32_t enc_evq_limit; 1108 uint32_t enc_txq_limit; 1109 uint32_t enc_rxq_limit; 1110 uint32_t enc_buftbl_limit; 1111 uint32_t enc_piobuf_limit; 1112 uint32_t enc_piobuf_size; 1113 uint32_t enc_piobuf_min_alloc_size; 1114 uint32_t enc_evq_timer_quantum_ns; 1115 uint32_t enc_evq_timer_max_us; 1116 uint32_t enc_clk_mult; 1117 uint32_t enc_rx_prefix_size; 1118 uint32_t enc_rx_buf_align_start; 1119 uint32_t enc_rx_buf_align_end; 1120 #if EFSYS_OPT_LOOPBACK 1121 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1122 #endif /* EFSYS_OPT_LOOPBACK */ 1123 #if EFSYS_OPT_PHY_FLAGS 1124 uint32_t enc_phy_flags_mask; 1125 #endif /* EFSYS_OPT_PHY_FLAGS */ 1126 #if EFSYS_OPT_PHY_LED_CONTROL 1127 uint32_t enc_led_mask; 1128 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1129 #if EFSYS_OPT_PHY_STATS 1130 uint64_t enc_phy_stat_mask; 1131 #endif /* EFSYS_OPT_PHY_STATS */ 1132 #if EFSYS_OPT_MCDI 1133 uint8_t enc_mcdi_mdio_channel; 1134 #if EFSYS_OPT_PHY_STATS 1135 uint32_t enc_mcdi_phy_stat_mask; 1136 #endif /* EFSYS_OPT_PHY_STATS */ 1137 #if EFSYS_OPT_MON_STATS 1138 uint32_t *enc_mcdi_sensor_maskp; 1139 uint32_t enc_mcdi_sensor_mask_size; 1140 #endif /* EFSYS_OPT_MON_STATS */ 1141 #endif /* EFSYS_OPT_MCDI */ 1142 #if EFSYS_OPT_BIST 1143 uint32_t enc_bist_mask; 1144 #endif /* EFSYS_OPT_BIST */ 1145 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1146 uint32_t enc_pf; 1147 uint32_t enc_vf; 1148 uint32_t enc_privilege_mask; 1149 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1150 boolean_t enc_bug26807_workaround; 1151 boolean_t enc_bug35388_workaround; 1152 boolean_t enc_bug41750_workaround; 1153 boolean_t enc_bug61265_workaround; 1154 boolean_t enc_rx_batching_enabled; 1155 /* Maximum number of descriptors completed in an rx event. */ 1156 uint32_t enc_rx_batch_max; 1157 /* Number of rx descriptors the hardware requires for a push. */ 1158 uint32_t enc_rx_push_align; 1159 /* Maximum amount of data in DMA descriptor */ 1160 uint32_t enc_tx_dma_desc_size_max; 1161 /* 1162 * Boundary which DMA descriptor data must not cross or 0 if no 1163 * limitation. 1164 */ 1165 uint32_t enc_tx_dma_desc_boundary; 1166 /* 1167 * Maximum number of bytes into the packet the TCP header can start for 1168 * the hardware to apply TSO packet edits. 1169 */ 1170 uint32_t enc_tx_tso_tcp_header_offset_limit; 1171 boolean_t enc_fw_assisted_tso_enabled; 1172 boolean_t enc_fw_assisted_tso_v2_enabled; 1173 /* Number of TSO contexts on the NIC (FATSOv2) */ 1174 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1175 boolean_t enc_hw_tx_insert_vlan_enabled; 1176 /* Number of PFs on the NIC */ 1177 uint32_t enc_hw_pf_count; 1178 /* Datapath firmware vadapter/vport/vswitch support */ 1179 boolean_t enc_datapath_cap_evb; 1180 boolean_t enc_rx_disable_scatter_supported; 1181 boolean_t enc_allow_set_mac_with_installed_filters; 1182 boolean_t enc_enhanced_set_mac_supported; 1183 boolean_t enc_init_evq_v2_supported; 1184 boolean_t enc_pm_and_rxdp_counters; 1185 boolean_t enc_mac_stats_40g_tx_size_bins; 1186 /* External port identifier */ 1187 uint8_t enc_external_port; 1188 uint32_t enc_mcdi_max_payload_length; 1189 /* VPD may be per-PF or global */ 1190 boolean_t enc_vpd_is_global; 1191 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1192 uint32_t enc_required_pcie_bandwidth_mbps; 1193 uint32_t enc_max_pcie_link_gen; 1194 /* Firmware verifies integrity of NVRAM updates */ 1195 uint32_t enc_fw_verified_nvram_update_required; 1196 } efx_nic_cfg_t; 1197 1198 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1199 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1200 1201 #define EFX_PCI_FUNCTION(_encp) \ 1202 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1203 1204 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1205 1206 extern const efx_nic_cfg_t * 1207 efx_nic_cfg_get( 1208 __in efx_nic_t *enp); 1209 1210 /* Driver resource limits (minimum required/maximum usable). */ 1211 typedef struct efx_drv_limits_s { 1212 uint32_t edl_min_evq_count; 1213 uint32_t edl_max_evq_count; 1214 1215 uint32_t edl_min_rxq_count; 1216 uint32_t edl_max_rxq_count; 1217 1218 uint32_t edl_min_txq_count; 1219 uint32_t edl_max_txq_count; 1220 1221 /* PIO blocks (sub-allocated from piobuf) */ 1222 uint32_t edl_min_pio_alloc_size; 1223 uint32_t edl_max_pio_alloc_count; 1224 } efx_drv_limits_t; 1225 1226 extern __checkReturn efx_rc_t 1227 efx_nic_set_drv_limits( 1228 __inout efx_nic_t *enp, 1229 __in efx_drv_limits_t *edlp); 1230 1231 typedef enum efx_nic_region_e { 1232 EFX_REGION_VI, /* Memory BAR UC mapping */ 1233 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1234 } efx_nic_region_t; 1235 1236 extern __checkReturn efx_rc_t 1237 efx_nic_get_bar_region( 1238 __in efx_nic_t *enp, 1239 __in efx_nic_region_t region, 1240 __out uint32_t *offsetp, 1241 __out size_t *sizep); 1242 1243 extern __checkReturn efx_rc_t 1244 efx_nic_get_vi_pool( 1245 __in efx_nic_t *enp, 1246 __out uint32_t *evq_countp, 1247 __out uint32_t *rxq_countp, 1248 __out uint32_t *txq_countp); 1249 1250 1251 #if EFSYS_OPT_VPD 1252 1253 typedef enum efx_vpd_tag_e { 1254 EFX_VPD_ID = 0x02, 1255 EFX_VPD_END = 0x0f, 1256 EFX_VPD_RO = 0x10, 1257 EFX_VPD_RW = 0x11, 1258 } efx_vpd_tag_t; 1259 1260 typedef uint16_t efx_vpd_keyword_t; 1261 1262 typedef struct efx_vpd_value_s { 1263 efx_vpd_tag_t evv_tag; 1264 efx_vpd_keyword_t evv_keyword; 1265 uint8_t evv_length; 1266 uint8_t evv_value[0x100]; 1267 } efx_vpd_value_t; 1268 1269 1270 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1271 1272 extern __checkReturn efx_rc_t 1273 efx_vpd_init( 1274 __in efx_nic_t *enp); 1275 1276 extern __checkReturn efx_rc_t 1277 efx_vpd_size( 1278 __in efx_nic_t *enp, 1279 __out size_t *sizep); 1280 1281 extern __checkReturn efx_rc_t 1282 efx_vpd_read( 1283 __in efx_nic_t *enp, 1284 __out_bcount(size) caddr_t data, 1285 __in size_t size); 1286 1287 extern __checkReturn efx_rc_t 1288 efx_vpd_verify( 1289 __in efx_nic_t *enp, 1290 __in_bcount(size) caddr_t data, 1291 __in size_t size); 1292 1293 extern __checkReturn efx_rc_t 1294 efx_vpd_reinit( 1295 __in efx_nic_t *enp, 1296 __in_bcount(size) caddr_t data, 1297 __in size_t size); 1298 1299 extern __checkReturn efx_rc_t 1300 efx_vpd_get( 1301 __in efx_nic_t *enp, 1302 __in_bcount(size) caddr_t data, 1303 __in size_t size, 1304 __inout efx_vpd_value_t *evvp); 1305 1306 extern __checkReturn efx_rc_t 1307 efx_vpd_set( 1308 __in efx_nic_t *enp, 1309 __inout_bcount(size) caddr_t data, 1310 __in size_t size, 1311 __in efx_vpd_value_t *evvp); 1312 1313 extern __checkReturn efx_rc_t 1314 efx_vpd_next( 1315 __in efx_nic_t *enp, 1316 __inout_bcount(size) caddr_t data, 1317 __in size_t size, 1318 __out efx_vpd_value_t *evvp, 1319 __inout unsigned int *contp); 1320 1321 extern __checkReturn efx_rc_t 1322 efx_vpd_write( 1323 __in efx_nic_t *enp, 1324 __in_bcount(size) caddr_t data, 1325 __in size_t size); 1326 1327 extern void 1328 efx_vpd_fini( 1329 __in efx_nic_t *enp); 1330 1331 #endif /* EFSYS_OPT_VPD */ 1332 1333 /* NVRAM */ 1334 1335 #if EFSYS_OPT_NVRAM 1336 1337 typedef enum efx_nvram_type_e { 1338 EFX_NVRAM_INVALID = 0, 1339 EFX_NVRAM_BOOTROM, 1340 EFX_NVRAM_BOOTROM_CFG, 1341 EFX_NVRAM_MC_FIRMWARE, 1342 EFX_NVRAM_MC_GOLDEN, 1343 EFX_NVRAM_PHY, 1344 EFX_NVRAM_NULLPHY, 1345 EFX_NVRAM_FPGA, 1346 EFX_NVRAM_FCFW, 1347 EFX_NVRAM_CPLD, 1348 EFX_NVRAM_FPGA_BACKUP, 1349 EFX_NVRAM_DYNAMIC_CFG, 1350 EFX_NVRAM_LICENSE, 1351 EFX_NVRAM_UEFIROM, 1352 EFX_NVRAM_NTYPES, 1353 } efx_nvram_type_t; 1354 1355 extern __checkReturn efx_rc_t 1356 efx_nvram_init( 1357 __in efx_nic_t *enp); 1358 1359 #if EFSYS_OPT_DIAG 1360 1361 extern __checkReturn efx_rc_t 1362 efx_nvram_test( 1363 __in efx_nic_t *enp); 1364 1365 #endif /* EFSYS_OPT_DIAG */ 1366 1367 extern __checkReturn efx_rc_t 1368 efx_nvram_size( 1369 __in efx_nic_t *enp, 1370 __in efx_nvram_type_t type, 1371 __out size_t *sizep); 1372 1373 extern __checkReturn efx_rc_t 1374 efx_nvram_rw_start( 1375 __in efx_nic_t *enp, 1376 __in efx_nvram_type_t type, 1377 __out_opt size_t *pref_chunkp); 1378 1379 extern __checkReturn efx_rc_t 1380 efx_nvram_rw_finish( 1381 __in efx_nic_t *enp, 1382 __in efx_nvram_type_t type); 1383 1384 extern __checkReturn efx_rc_t 1385 efx_nvram_get_version( 1386 __in efx_nic_t *enp, 1387 __in efx_nvram_type_t type, 1388 __out uint32_t *subtypep, 1389 __out_ecount(4) uint16_t version[4]); 1390 1391 extern __checkReturn efx_rc_t 1392 efx_nvram_read_chunk( 1393 __in efx_nic_t *enp, 1394 __in efx_nvram_type_t type, 1395 __in unsigned int offset, 1396 __out_bcount(size) caddr_t data, 1397 __in size_t size); 1398 1399 extern __checkReturn efx_rc_t 1400 efx_nvram_set_version( 1401 __in efx_nic_t *enp, 1402 __in efx_nvram_type_t type, 1403 __in_ecount(4) uint16_t version[4]); 1404 1405 extern __checkReturn efx_rc_t 1406 efx_nvram_validate( 1407 __in efx_nic_t *enp, 1408 __in efx_nvram_type_t type, 1409 __in_bcount(partn_size) caddr_t partn_data, 1410 __in size_t partn_size); 1411 1412 extern __checkReturn efx_rc_t 1413 efx_nvram_erase( 1414 __in efx_nic_t *enp, 1415 __in efx_nvram_type_t type); 1416 1417 extern __checkReturn efx_rc_t 1418 efx_nvram_write_chunk( 1419 __in efx_nic_t *enp, 1420 __in efx_nvram_type_t type, 1421 __in unsigned int offset, 1422 __in_bcount(size) caddr_t data, 1423 __in size_t size); 1424 1425 extern void 1426 efx_nvram_fini( 1427 __in efx_nic_t *enp); 1428 1429 #endif /* EFSYS_OPT_NVRAM */ 1430 1431 #if EFSYS_OPT_BOOTCFG 1432 1433 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1434 extern __checkReturn efx_rc_t 1435 efx_bootcfg_sector_info( 1436 __in efx_nic_t *enp, 1437 __in uint32_t pf, 1438 __out_opt uint32_t *sector_countp, 1439 __out size_t *offsetp, 1440 __out size_t *max_sizep); 1441 1442 /* 1443 * Copy bootcfg sector data to a target buffer which may differ in size. 1444 * Optionally corrects format errors in source buffer. 1445 */ 1446 extern efx_rc_t 1447 efx_bootcfg_copy_sector( 1448 __in efx_nic_t *enp, 1449 __inout_bcount(sector_length) 1450 uint8_t *sector, 1451 __in size_t sector_length, 1452 __out_bcount(data_size) uint8_t *data, 1453 __in size_t data_size, 1454 __in boolean_t handle_format_errors); 1455 1456 extern efx_rc_t 1457 efx_bootcfg_read( 1458 __in efx_nic_t *enp, 1459 __out_bcount(size) caddr_t data, 1460 __in size_t size); 1461 1462 extern efx_rc_t 1463 efx_bootcfg_write( 1464 __in efx_nic_t *enp, 1465 __in_bcount(size) caddr_t data, 1466 __in size_t size); 1467 1468 #endif /* EFSYS_OPT_BOOTCFG */ 1469 1470 #if EFSYS_OPT_DIAG 1471 1472 typedef enum efx_pattern_type_t { 1473 EFX_PATTERN_BYTE_INCREMENT = 0, 1474 EFX_PATTERN_ALL_THE_SAME, 1475 EFX_PATTERN_BIT_ALTERNATE, 1476 EFX_PATTERN_BYTE_ALTERNATE, 1477 EFX_PATTERN_BYTE_CHANGING, 1478 EFX_PATTERN_BIT_SWEEP, 1479 EFX_PATTERN_NTYPES 1480 } efx_pattern_type_t; 1481 1482 typedef void 1483 (*efx_sram_pattern_fn_t)( 1484 __in size_t row, 1485 __in boolean_t negate, 1486 __out efx_qword_t *eqp); 1487 1488 extern __checkReturn efx_rc_t 1489 efx_sram_test( 1490 __in efx_nic_t *enp, 1491 __in efx_pattern_type_t type); 1492 1493 #endif /* EFSYS_OPT_DIAG */ 1494 1495 extern __checkReturn efx_rc_t 1496 efx_sram_buf_tbl_set( 1497 __in efx_nic_t *enp, 1498 __in uint32_t id, 1499 __in efsys_mem_t *esmp, 1500 __in size_t n); 1501 1502 extern void 1503 efx_sram_buf_tbl_clear( 1504 __in efx_nic_t *enp, 1505 __in uint32_t id, 1506 __in size_t n); 1507 1508 #define EFX_BUF_TBL_SIZE 0x20000 1509 1510 #define EFX_BUF_SIZE 4096 1511 1512 /* EV */ 1513 1514 typedef struct efx_evq_s efx_evq_t; 1515 1516 #if EFSYS_OPT_QSTATS 1517 1518 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1519 typedef enum efx_ev_qstat_e { 1520 EV_ALL, 1521 EV_RX, 1522 EV_RX_OK, 1523 EV_RX_FRM_TRUNC, 1524 EV_RX_TOBE_DISC, 1525 EV_RX_PAUSE_FRM_ERR, 1526 EV_RX_BUF_OWNER_ID_ERR, 1527 EV_RX_IPV4_HDR_CHKSUM_ERR, 1528 EV_RX_TCP_UDP_CHKSUM_ERR, 1529 EV_RX_ETH_CRC_ERR, 1530 EV_RX_IP_FRAG_ERR, 1531 EV_RX_MCAST_PKT, 1532 EV_RX_MCAST_HASH_MATCH, 1533 EV_RX_TCP_IPV4, 1534 EV_RX_TCP_IPV6, 1535 EV_RX_UDP_IPV4, 1536 EV_RX_UDP_IPV6, 1537 EV_RX_OTHER_IPV4, 1538 EV_RX_OTHER_IPV6, 1539 EV_RX_NON_IP, 1540 EV_RX_BATCH, 1541 EV_TX, 1542 EV_TX_WQ_FF_FULL, 1543 EV_TX_PKT_ERR, 1544 EV_TX_PKT_TOO_BIG, 1545 EV_TX_UNEXPECTED, 1546 EV_GLOBAL, 1547 EV_GLOBAL_MNT, 1548 EV_DRIVER, 1549 EV_DRIVER_SRM_UPD_DONE, 1550 EV_DRIVER_TX_DESCQ_FLS_DONE, 1551 EV_DRIVER_RX_DESCQ_FLS_DONE, 1552 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1553 EV_DRIVER_RX_DSC_ERROR, 1554 EV_DRIVER_TX_DSC_ERROR, 1555 EV_DRV_GEN, 1556 EV_MCDI_RESPONSE, 1557 EV_NQSTATS 1558 } efx_ev_qstat_t; 1559 1560 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1561 1562 #endif /* EFSYS_OPT_QSTATS */ 1563 1564 extern __checkReturn efx_rc_t 1565 efx_ev_init( 1566 __in efx_nic_t *enp); 1567 1568 extern void 1569 efx_ev_fini( 1570 __in efx_nic_t *enp); 1571 1572 #define EFX_EVQ_MAXNEVS 32768 1573 #define EFX_EVQ_MINNEVS 512 1574 1575 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1576 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1577 1578 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 1579 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 1580 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 1581 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 1582 1583 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 1584 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 1585 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 1586 1587 extern __checkReturn efx_rc_t 1588 efx_ev_qcreate( 1589 __in efx_nic_t *enp, 1590 __in unsigned int index, 1591 __in efsys_mem_t *esmp, 1592 __in size_t n, 1593 __in uint32_t id, 1594 __in uint32_t us, 1595 __in uint32_t flags, 1596 __deref_out efx_evq_t **eepp); 1597 1598 extern void 1599 efx_ev_qpost( 1600 __in efx_evq_t *eep, 1601 __in uint16_t data); 1602 1603 typedef __checkReturn boolean_t 1604 (*efx_initialized_ev_t)( 1605 __in_opt void *arg); 1606 1607 #define EFX_PKT_UNICAST 0x0004 1608 #define EFX_PKT_START 0x0008 1609 1610 #define EFX_PKT_VLAN_TAGGED 0x0010 1611 #define EFX_CKSUM_TCPUDP 0x0020 1612 #define EFX_CKSUM_IPV4 0x0040 1613 #define EFX_PKT_CONT 0x0080 1614 1615 #define EFX_CHECK_VLAN 0x0100 1616 #define EFX_PKT_TCP 0x0200 1617 #define EFX_PKT_UDP 0x0400 1618 #define EFX_PKT_IPV4 0x0800 1619 1620 #define EFX_PKT_IPV6 0x1000 1621 #define EFX_PKT_PREFIX_LEN 0x2000 1622 #define EFX_ADDR_MISMATCH 0x4000 1623 #define EFX_DISCARD 0x8000 1624 1625 #define EFX_EV_RX_NLABELS 32 1626 #define EFX_EV_TX_NLABELS 32 1627 1628 typedef __checkReturn boolean_t 1629 (*efx_rx_ev_t)( 1630 __in_opt void *arg, 1631 __in uint32_t label, 1632 __in uint32_t id, 1633 __in uint32_t size, 1634 __in uint16_t flags); 1635 1636 typedef __checkReturn boolean_t 1637 (*efx_tx_ev_t)( 1638 __in_opt void *arg, 1639 __in uint32_t label, 1640 __in uint32_t id); 1641 1642 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1643 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1644 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1645 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1646 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1647 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1648 #define EFX_EXCEPTION_RX_ERROR 0x00000007 1649 #define EFX_EXCEPTION_TX_ERROR 0x00000008 1650 #define EFX_EXCEPTION_EV_ERROR 0x00000009 1651 1652 typedef __checkReturn boolean_t 1653 (*efx_exception_ev_t)( 1654 __in_opt void *arg, 1655 __in uint32_t label, 1656 __in uint32_t data); 1657 1658 typedef __checkReturn boolean_t 1659 (*efx_rxq_flush_done_ev_t)( 1660 __in_opt void *arg, 1661 __in uint32_t rxq_index); 1662 1663 typedef __checkReturn boolean_t 1664 (*efx_rxq_flush_failed_ev_t)( 1665 __in_opt void *arg, 1666 __in uint32_t rxq_index); 1667 1668 typedef __checkReturn boolean_t 1669 (*efx_txq_flush_done_ev_t)( 1670 __in_opt void *arg, 1671 __in uint32_t txq_index); 1672 1673 typedef __checkReturn boolean_t 1674 (*efx_software_ev_t)( 1675 __in_opt void *arg, 1676 __in uint16_t magic); 1677 1678 typedef __checkReturn boolean_t 1679 (*efx_sram_ev_t)( 1680 __in_opt void *arg, 1681 __in uint32_t code); 1682 1683 #define EFX_SRAM_CLEAR 0 1684 #define EFX_SRAM_UPDATE 1 1685 #define EFX_SRAM_ILLEGAL_CLEAR 2 1686 1687 typedef __checkReturn boolean_t 1688 (*efx_wake_up_ev_t)( 1689 __in_opt void *arg, 1690 __in uint32_t label); 1691 1692 typedef __checkReturn boolean_t 1693 (*efx_timer_ev_t)( 1694 __in_opt void *arg, 1695 __in uint32_t label); 1696 1697 typedef __checkReturn boolean_t 1698 (*efx_link_change_ev_t)( 1699 __in_opt void *arg, 1700 __in efx_link_mode_t link_mode); 1701 1702 #if EFSYS_OPT_MON_STATS 1703 1704 typedef __checkReturn boolean_t 1705 (*efx_monitor_ev_t)( 1706 __in_opt void *arg, 1707 __in efx_mon_stat_t id, 1708 __in efx_mon_stat_value_t value); 1709 1710 #endif /* EFSYS_OPT_MON_STATS */ 1711 1712 #if EFSYS_OPT_MAC_STATS 1713 1714 typedef __checkReturn boolean_t 1715 (*efx_mac_stats_ev_t)( 1716 __in_opt void *arg, 1717 __in uint32_t generation 1718 ); 1719 1720 #endif /* EFSYS_OPT_MAC_STATS */ 1721 1722 typedef struct efx_ev_callbacks_s { 1723 efx_initialized_ev_t eec_initialized; 1724 efx_rx_ev_t eec_rx; 1725 efx_tx_ev_t eec_tx; 1726 efx_exception_ev_t eec_exception; 1727 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1728 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1729 efx_txq_flush_done_ev_t eec_txq_flush_done; 1730 efx_software_ev_t eec_software; 1731 efx_sram_ev_t eec_sram; 1732 efx_wake_up_ev_t eec_wake_up; 1733 efx_timer_ev_t eec_timer; 1734 efx_link_change_ev_t eec_link_change; 1735 #if EFSYS_OPT_MON_STATS 1736 efx_monitor_ev_t eec_monitor; 1737 #endif /* EFSYS_OPT_MON_STATS */ 1738 #if EFSYS_OPT_MAC_STATS 1739 efx_mac_stats_ev_t eec_mac_stats; 1740 #endif /* EFSYS_OPT_MAC_STATS */ 1741 } efx_ev_callbacks_t; 1742 1743 extern __checkReturn boolean_t 1744 efx_ev_qpending( 1745 __in efx_evq_t *eep, 1746 __in unsigned int count); 1747 1748 #if EFSYS_OPT_EV_PREFETCH 1749 1750 extern void 1751 efx_ev_qprefetch( 1752 __in efx_evq_t *eep, 1753 __in unsigned int count); 1754 1755 #endif /* EFSYS_OPT_EV_PREFETCH */ 1756 1757 extern void 1758 efx_ev_qpoll( 1759 __in efx_evq_t *eep, 1760 __inout unsigned int *countp, 1761 __in const efx_ev_callbacks_t *eecp, 1762 __in_opt void *arg); 1763 1764 extern __checkReturn efx_rc_t 1765 efx_ev_usecs_to_ticks( 1766 __in efx_nic_t *enp, 1767 __in unsigned int usecs, 1768 __out unsigned int *ticksp); 1769 1770 extern __checkReturn efx_rc_t 1771 efx_ev_qmoderate( 1772 __in efx_evq_t *eep, 1773 __in unsigned int us); 1774 1775 extern __checkReturn efx_rc_t 1776 efx_ev_qprime( 1777 __in efx_evq_t *eep, 1778 __in unsigned int count); 1779 1780 #if EFSYS_OPT_QSTATS 1781 1782 #if EFSYS_OPT_NAMES 1783 1784 extern const char * 1785 efx_ev_qstat_name( 1786 __in efx_nic_t *enp, 1787 __in unsigned int id); 1788 1789 #endif /* EFSYS_OPT_NAMES */ 1790 1791 extern void 1792 efx_ev_qstats_update( 1793 __in efx_evq_t *eep, 1794 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1795 1796 #endif /* EFSYS_OPT_QSTATS */ 1797 1798 extern void 1799 efx_ev_qdestroy( 1800 __in efx_evq_t *eep); 1801 1802 /* RX */ 1803 1804 extern __checkReturn efx_rc_t 1805 efx_rx_init( 1806 __inout efx_nic_t *enp); 1807 1808 extern void 1809 efx_rx_fini( 1810 __in efx_nic_t *enp); 1811 1812 #if EFSYS_OPT_RX_SCATTER 1813 __checkReturn efx_rc_t 1814 efx_rx_scatter_enable( 1815 __in efx_nic_t *enp, 1816 __in unsigned int buf_size); 1817 #endif /* EFSYS_OPT_RX_SCATTER */ 1818 1819 #if EFSYS_OPT_RX_SCALE 1820 1821 typedef enum efx_rx_hash_alg_e { 1822 EFX_RX_HASHALG_LFSR = 0, 1823 EFX_RX_HASHALG_TOEPLITZ 1824 } efx_rx_hash_alg_t; 1825 1826 #define EFX_RX_HASH_IPV4 (1U << 0) 1827 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 1828 #define EFX_RX_HASH_IPV6 (1U << 2) 1829 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 1830 1831 typedef unsigned int efx_rx_hash_type_t; 1832 1833 typedef enum efx_rx_hash_support_e { 1834 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1835 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1836 } efx_rx_hash_support_t; 1837 1838 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1839 #define EFX_MAXRSS 64 /* RX indirection entry range */ 1840 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1841 1842 typedef enum efx_rx_scale_support_e { 1843 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1844 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1845 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1846 } efx_rx_scale_support_t; 1847 1848 extern __checkReturn efx_rc_t 1849 efx_rx_hash_support_get( 1850 __in efx_nic_t *enp, 1851 __out efx_rx_hash_support_t *supportp); 1852 1853 1854 extern __checkReturn efx_rc_t 1855 efx_rx_scale_support_get( 1856 __in efx_nic_t *enp, 1857 __out efx_rx_scale_support_t *supportp); 1858 1859 extern __checkReturn efx_rc_t 1860 efx_rx_scale_mode_set( 1861 __in efx_nic_t *enp, 1862 __in efx_rx_hash_alg_t alg, 1863 __in efx_rx_hash_type_t type, 1864 __in boolean_t insert); 1865 1866 extern __checkReturn efx_rc_t 1867 efx_rx_scale_tbl_set( 1868 __in efx_nic_t *enp, 1869 __in_ecount(n) unsigned int *table, 1870 __in size_t n); 1871 1872 extern __checkReturn efx_rc_t 1873 efx_rx_scale_key_set( 1874 __in efx_nic_t *enp, 1875 __in_ecount(n) uint8_t *key, 1876 __in size_t n); 1877 1878 extern __checkReturn uint32_t 1879 efx_pseudo_hdr_hash_get( 1880 __in efx_rxq_t *erp, 1881 __in efx_rx_hash_alg_t func, 1882 __in uint8_t *buffer); 1883 1884 #endif /* EFSYS_OPT_RX_SCALE */ 1885 1886 extern __checkReturn efx_rc_t 1887 efx_pseudo_hdr_pkt_length_get( 1888 __in efx_rxq_t *erp, 1889 __in uint8_t *buffer, 1890 __out uint16_t *pkt_lengthp); 1891 1892 #define EFX_RXQ_MAXNDESCS 4096 1893 #define EFX_RXQ_MINNDESCS 512 1894 1895 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1896 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1897 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1898 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1899 1900 typedef enum efx_rxq_type_e { 1901 EFX_RXQ_TYPE_DEFAULT, 1902 EFX_RXQ_TYPE_SCATTER, 1903 EFX_RXQ_NTYPES 1904 } efx_rxq_type_t; 1905 1906 extern __checkReturn efx_rc_t 1907 efx_rx_qcreate( 1908 __in efx_nic_t *enp, 1909 __in unsigned int index, 1910 __in unsigned int label, 1911 __in efx_rxq_type_t type, 1912 __in efsys_mem_t *esmp, 1913 __in size_t n, 1914 __in uint32_t id, 1915 __in efx_evq_t *eep, 1916 __deref_out efx_rxq_t **erpp); 1917 1918 typedef struct efx_buffer_s { 1919 efsys_dma_addr_t eb_addr; 1920 size_t eb_size; 1921 boolean_t eb_eop; 1922 } efx_buffer_t; 1923 1924 typedef struct efx_desc_s { 1925 efx_qword_t ed_eq; 1926 } efx_desc_t; 1927 1928 extern void 1929 efx_rx_qpost( 1930 __in efx_rxq_t *erp, 1931 __in_ecount(n) efsys_dma_addr_t *addrp, 1932 __in size_t size, 1933 __in unsigned int n, 1934 __in unsigned int completed, 1935 __in unsigned int added); 1936 1937 extern void 1938 efx_rx_qpush( 1939 __in efx_rxq_t *erp, 1940 __in unsigned int added, 1941 __inout unsigned int *pushedp); 1942 1943 extern __checkReturn efx_rc_t 1944 efx_rx_qflush( 1945 __in efx_rxq_t *erp); 1946 1947 extern void 1948 efx_rx_qenable( 1949 __in efx_rxq_t *erp); 1950 1951 extern void 1952 efx_rx_qdestroy( 1953 __in efx_rxq_t *erp); 1954 1955 /* TX */ 1956 1957 typedef struct efx_txq_s efx_txq_t; 1958 1959 #if EFSYS_OPT_QSTATS 1960 1961 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 1962 typedef enum efx_tx_qstat_e { 1963 TX_POST, 1964 TX_POST_PIO, 1965 TX_NQSTATS 1966 } efx_tx_qstat_t; 1967 1968 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 1969 1970 #endif /* EFSYS_OPT_QSTATS */ 1971 1972 extern __checkReturn efx_rc_t 1973 efx_tx_init( 1974 __in efx_nic_t *enp); 1975 1976 extern void 1977 efx_tx_fini( 1978 __in efx_nic_t *enp); 1979 1980 #define EFX_BUG35388_WORKAROUND(_encp) \ 1981 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 1982 1983 #define EFX_TXQ_MAXNDESCS(_encp) \ 1984 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 1985 1986 #define EFX_TXQ_MINNDESCS 512 1987 1988 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1989 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1990 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1991 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1992 1993 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 1994 1995 #define EFX_TXQ_CKSUM_IPV4 0x0001 1996 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 1997 #define EFX_TXQ_FATSOV2 0x0004 1998 1999 extern __checkReturn efx_rc_t 2000 efx_tx_qcreate( 2001 __in efx_nic_t *enp, 2002 __in unsigned int index, 2003 __in unsigned int label, 2004 __in efsys_mem_t *esmp, 2005 __in size_t n, 2006 __in uint32_t id, 2007 __in uint16_t flags, 2008 __in efx_evq_t *eep, 2009 __deref_out efx_txq_t **etpp, 2010 __out unsigned int *addedp); 2011 2012 extern __checkReturn efx_rc_t 2013 efx_tx_qpost( 2014 __in efx_txq_t *etp, 2015 __in_ecount(n) efx_buffer_t *eb, 2016 __in unsigned int n, 2017 __in unsigned int completed, 2018 __inout unsigned int *addedp); 2019 2020 extern __checkReturn efx_rc_t 2021 efx_tx_qpace( 2022 __in efx_txq_t *etp, 2023 __in unsigned int ns); 2024 2025 extern void 2026 efx_tx_qpush( 2027 __in efx_txq_t *etp, 2028 __in unsigned int added, 2029 __in unsigned int pushed); 2030 2031 extern __checkReturn efx_rc_t 2032 efx_tx_qflush( 2033 __in efx_txq_t *etp); 2034 2035 extern void 2036 efx_tx_qenable( 2037 __in efx_txq_t *etp); 2038 2039 extern __checkReturn efx_rc_t 2040 efx_tx_qpio_enable( 2041 __in efx_txq_t *etp); 2042 2043 extern void 2044 efx_tx_qpio_disable( 2045 __in efx_txq_t *etp); 2046 2047 extern __checkReturn efx_rc_t 2048 efx_tx_qpio_write( 2049 __in efx_txq_t *etp, 2050 __in_ecount(buf_length) uint8_t *buffer, 2051 __in size_t buf_length, 2052 __in size_t pio_buf_offset); 2053 2054 extern __checkReturn efx_rc_t 2055 efx_tx_qpio_post( 2056 __in efx_txq_t *etp, 2057 __in size_t pkt_length, 2058 __in unsigned int completed, 2059 __inout unsigned int *addedp); 2060 2061 extern __checkReturn efx_rc_t 2062 efx_tx_qdesc_post( 2063 __in efx_txq_t *etp, 2064 __in_ecount(n) efx_desc_t *ed, 2065 __in unsigned int n, 2066 __in unsigned int completed, 2067 __inout unsigned int *addedp); 2068 2069 extern void 2070 efx_tx_qdesc_dma_create( 2071 __in efx_txq_t *etp, 2072 __in efsys_dma_addr_t addr, 2073 __in size_t size, 2074 __in boolean_t eop, 2075 __out efx_desc_t *edp); 2076 2077 extern void 2078 efx_tx_qdesc_tso_create( 2079 __in efx_txq_t *etp, 2080 __in uint16_t ipv4_id, 2081 __in uint32_t tcp_seq, 2082 __in uint8_t tcp_flags, 2083 __out efx_desc_t *edp); 2084 2085 /* Number of FATSOv2 option descriptors */ 2086 #define EFX_TX_FATSOV2_OPT_NDESCS 2 2087 2088 /* Maximum number of DMA segments per TSO packet (not superframe) */ 2089 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2090 2091 extern void 2092 efx_tx_qdesc_tso2_create( 2093 __in efx_txq_t *etp, 2094 __in uint16_t ipv4_id, 2095 __in uint32_t tcp_seq, 2096 __in uint16_t tcp_mss, 2097 __out_ecount(count) efx_desc_t *edp, 2098 __in int count); 2099 2100 extern void 2101 efx_tx_qdesc_vlantci_create( 2102 __in efx_txq_t *etp, 2103 __in uint16_t tci, 2104 __out efx_desc_t *edp); 2105 2106 #if EFSYS_OPT_QSTATS 2107 2108 #if EFSYS_OPT_NAMES 2109 2110 extern const char * 2111 efx_tx_qstat_name( 2112 __in efx_nic_t *etp, 2113 __in unsigned int id); 2114 2115 #endif /* EFSYS_OPT_NAMES */ 2116 2117 extern void 2118 efx_tx_qstats_update( 2119 __in efx_txq_t *etp, 2120 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2121 2122 #endif /* EFSYS_OPT_QSTATS */ 2123 2124 extern void 2125 efx_tx_qdestroy( 2126 __in efx_txq_t *etp); 2127 2128 2129 /* FILTER */ 2130 2131 #if EFSYS_OPT_FILTER 2132 2133 #define EFX_ETHER_TYPE_IPV4 0x0800 2134 #define EFX_ETHER_TYPE_IPV6 0x86DD 2135 2136 #define EFX_IPPROTO_TCP 6 2137 #define EFX_IPPROTO_UDP 17 2138 2139 /* Use RSS to spread across multiple queues */ 2140 #define EFX_FILTER_FLAG_RX_RSS 0x01 2141 /* Enable RX scatter */ 2142 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 2143 /* 2144 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2145 * May only be set by the filter implementation for each type. 2146 * A removal request will restore the automatic filter in its place. 2147 */ 2148 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2149 /* Filter is for RX */ 2150 #define EFX_FILTER_FLAG_RX 0x08 2151 /* Filter is for TX */ 2152 #define EFX_FILTER_FLAG_TX 0x10 2153 2154 typedef unsigned int efx_filter_flags_t; 2155 2156 typedef enum efx_filter_match_flags_e { 2157 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2158 * address */ 2159 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2160 * address */ 2161 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2162 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2163 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2164 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2165 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2166 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2167 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2168 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2169 * protocol */ 2170 /* Match otherwise-unmatched multicast and broadcast packets */ 2171 EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000, 2172 /* Match otherwise-unmatched unicast packets */ 2173 EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000, 2174 } efx_filter_match_flags_t; 2175 2176 typedef enum efx_filter_priority_s { 2177 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2178 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2179 * address list or hardware 2180 * requirements. This may only be used 2181 * by the filter implementation for 2182 * each NIC type. */ 2183 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2184 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2185 * client (e.g. SR-IOV, HyperV VMQ etc.) 2186 */ 2187 } efx_filter_priority_t; 2188 2189 /* 2190 * FIXME: All these fields are assumed to be in little-endian byte order. 2191 * It may be better for some to be big-endian. See bug42804. 2192 */ 2193 2194 typedef struct efx_filter_spec_s { 2195 uint32_t efs_match_flags; 2196 uint32_t efs_priority:2; 2197 uint32_t efs_flags:6; 2198 uint32_t efs_dmaq_id:12; 2199 uint32_t efs_rss_context; 2200 uint16_t efs_outer_vid; 2201 uint16_t efs_inner_vid; 2202 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2203 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2204 uint16_t efs_ether_type; 2205 uint8_t efs_ip_proto; 2206 uint16_t efs_loc_port; 2207 uint16_t efs_rem_port; 2208 efx_oword_t efs_rem_host; 2209 efx_oword_t efs_loc_host; 2210 } efx_filter_spec_t; 2211 2212 2213 /* Default values for use in filter specifications */ 2214 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2215 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2216 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2217 2218 extern __checkReturn efx_rc_t 2219 efx_filter_init( 2220 __in efx_nic_t *enp); 2221 2222 extern void 2223 efx_filter_fini( 2224 __in efx_nic_t *enp); 2225 2226 extern __checkReturn efx_rc_t 2227 efx_filter_insert( 2228 __in efx_nic_t *enp, 2229 __inout efx_filter_spec_t *spec); 2230 2231 extern __checkReturn efx_rc_t 2232 efx_filter_remove( 2233 __in efx_nic_t *enp, 2234 __inout efx_filter_spec_t *spec); 2235 2236 extern __checkReturn efx_rc_t 2237 efx_filter_restore( 2238 __in efx_nic_t *enp); 2239 2240 extern __checkReturn efx_rc_t 2241 efx_filter_supported_filters( 2242 __in efx_nic_t *enp, 2243 __out_ecount(buffer_length) uint32_t *buffer, 2244 __in size_t buffer_length, 2245 __out size_t *list_lengthp); 2246 2247 extern void 2248 efx_filter_spec_init_rx( 2249 __out efx_filter_spec_t *spec, 2250 __in efx_filter_priority_t priority, 2251 __in efx_filter_flags_t flags, 2252 __in efx_rxq_t *erp); 2253 2254 extern void 2255 efx_filter_spec_init_tx( 2256 __out efx_filter_spec_t *spec, 2257 __in efx_txq_t *etp); 2258 2259 extern __checkReturn efx_rc_t 2260 efx_filter_spec_set_ipv4_local( 2261 __inout efx_filter_spec_t *spec, 2262 __in uint8_t proto, 2263 __in uint32_t host, 2264 __in uint16_t port); 2265 2266 extern __checkReturn efx_rc_t 2267 efx_filter_spec_set_ipv4_full( 2268 __inout efx_filter_spec_t *spec, 2269 __in uint8_t proto, 2270 __in uint32_t lhost, 2271 __in uint16_t lport, 2272 __in uint32_t rhost, 2273 __in uint16_t rport); 2274 2275 extern __checkReturn efx_rc_t 2276 efx_filter_spec_set_eth_local( 2277 __inout efx_filter_spec_t *spec, 2278 __in uint16_t vid, 2279 __in const uint8_t *addr); 2280 2281 extern __checkReturn efx_rc_t 2282 efx_filter_spec_set_uc_def( 2283 __inout efx_filter_spec_t *spec); 2284 2285 extern __checkReturn efx_rc_t 2286 efx_filter_spec_set_mc_def( 2287 __inout efx_filter_spec_t *spec); 2288 2289 #endif /* EFSYS_OPT_FILTER */ 2290 2291 /* HASH */ 2292 2293 extern __checkReturn uint32_t 2294 efx_hash_dwords( 2295 __in_ecount(count) uint32_t const *input, 2296 __in size_t count, 2297 __in uint32_t init); 2298 2299 extern __checkReturn uint32_t 2300 efx_hash_bytes( 2301 __in_ecount(length) uint8_t const *input, 2302 __in size_t length, 2303 __in uint32_t init); 2304 2305 #if EFSYS_OPT_LICENSING 2306 2307 /* LICENSING */ 2308 2309 typedef struct efx_key_stats_s { 2310 uint32_t eks_valid; 2311 uint32_t eks_invalid; 2312 uint32_t eks_blacklisted; 2313 uint32_t eks_unverifiable; 2314 uint32_t eks_wrong_node; 2315 uint32_t eks_licensed_apps_lo; 2316 uint32_t eks_licensed_apps_hi; 2317 uint32_t eks_licensed_features_lo; 2318 uint32_t eks_licensed_features_hi; 2319 } efx_key_stats_t; 2320 2321 extern __checkReturn efx_rc_t 2322 efx_lic_init( 2323 __in efx_nic_t *enp); 2324 2325 extern void 2326 efx_lic_fini( 2327 __in efx_nic_t *enp); 2328 2329 extern __checkReturn boolean_t 2330 efx_lic_check_support( 2331 __in efx_nic_t *enp); 2332 2333 extern __checkReturn efx_rc_t 2334 efx_lic_update_licenses( 2335 __in efx_nic_t *enp); 2336 2337 extern __checkReturn efx_rc_t 2338 efx_lic_get_key_stats( 2339 __in efx_nic_t *enp, 2340 __out efx_key_stats_t *ksp); 2341 2342 extern __checkReturn efx_rc_t 2343 efx_lic_app_state( 2344 __in efx_nic_t *enp, 2345 __in uint64_t app_id, 2346 __out boolean_t *licensedp); 2347 2348 extern __checkReturn efx_rc_t 2349 efx_lic_get_id( 2350 __in efx_nic_t *enp, 2351 __in size_t buffer_size, 2352 __out uint32_t *typep, 2353 __out size_t *lengthp, 2354 __out_opt uint8_t *bufferp); 2355 2356 2357 extern __checkReturn efx_rc_t 2358 efx_lic_find_start( 2359 __in efx_nic_t *enp, 2360 __in_bcount(buffer_size) 2361 caddr_t bufferp, 2362 __in size_t buffer_size, 2363 __out uint32_t *startp 2364 ); 2365 2366 extern __checkReturn efx_rc_t 2367 efx_lic_find_end( 2368 __in efx_nic_t *enp, 2369 __in_bcount(buffer_size) 2370 caddr_t bufferp, 2371 __in size_t buffer_size, 2372 __in uint32_t offset, 2373 __out uint32_t *endp 2374 ); 2375 2376 extern __checkReturn __success(return != B_FALSE) boolean_t 2377 efx_lic_find_key( 2378 __in efx_nic_t *enp, 2379 __in_bcount(buffer_size) 2380 caddr_t bufferp, 2381 __in size_t buffer_size, 2382 __in uint32_t offset, 2383 __out uint32_t *startp, 2384 __out uint32_t *lengthp 2385 ); 2386 2387 extern __checkReturn __success(return != B_FALSE) boolean_t 2388 efx_lic_validate_key( 2389 __in efx_nic_t *enp, 2390 __in_bcount(length) caddr_t keyp, 2391 __in uint32_t length 2392 ); 2393 2394 extern __checkReturn efx_rc_t 2395 efx_lic_read_key( 2396 __in efx_nic_t *enp, 2397 __in_bcount(buffer_size) 2398 caddr_t bufferp, 2399 __in size_t buffer_size, 2400 __in uint32_t offset, 2401 __in uint32_t length, 2402 __out_bcount_part(key_max_size, *lengthp) 2403 caddr_t keyp, 2404 __in size_t key_max_size, 2405 __out uint32_t *lengthp 2406 ); 2407 2408 extern __checkReturn efx_rc_t 2409 efx_lic_write_key( 2410 __in efx_nic_t *enp, 2411 __in_bcount(buffer_size) 2412 caddr_t bufferp, 2413 __in size_t buffer_size, 2414 __in uint32_t offset, 2415 __in_bcount(length) caddr_t keyp, 2416 __in uint32_t length, 2417 __out uint32_t *lengthp 2418 ); 2419 2420 __checkReturn efx_rc_t 2421 efx_lic_delete_key( 2422 __in efx_nic_t *enp, 2423 __in_bcount(buffer_size) 2424 caddr_t bufferp, 2425 __in size_t buffer_size, 2426 __in uint32_t offset, 2427 __in uint32_t length, 2428 __in uint32_t end, 2429 __out uint32_t *deltap 2430 ); 2431 2432 extern __checkReturn efx_rc_t 2433 efx_lic_create_partition( 2434 __in efx_nic_t *enp, 2435 __in_bcount(buffer_size) 2436 caddr_t bufferp, 2437 __in size_t buffer_size 2438 ); 2439 2440 extern __checkReturn efx_rc_t 2441 efx_lic_finish_partition( 2442 __in efx_nic_t *enp, 2443 __in_bcount(buffer_size) 2444 caddr_t bufferp, 2445 __in size_t buffer_size 2446 ); 2447 2448 #endif /* EFSYS_OPT_LICENSING */ 2449 2450 2451 2452 #ifdef __cplusplus 2453 } 2454 #endif 2455 2456 #endif /* _SYS_EFX_H */ 2457