1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_H 36 #define _SYS_EFX_H 37 38 #include "efx_annote.h" 39 #include "efsys.h" 40 #include "efx_check.h" 41 #include "efx_phy_ids.h" 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #define EFX_STATIC_ASSERT(_cond) \ 48 ((void)sizeof (char[(_cond) ? 1 : -1])) 49 50 #define EFX_ARRAY_SIZE(_array) \ 51 (sizeof (_array) / sizeof ((_array)[0])) 52 53 #define EFX_FIELD_OFFSET(_type, _field) \ 54 ((size_t)&(((_type *)0)->_field)) 55 56 /* The macro expands divider twice */ 57 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 58 59 /* Return codes */ 60 61 typedef __success(return == 0) int efx_rc_t; 62 63 64 /* Chip families */ 65 66 typedef enum efx_family_e { 67 EFX_FAMILY_INVALID, 68 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 69 EFX_FAMILY_SIENA, 70 EFX_FAMILY_HUNTINGTON, 71 EFX_FAMILY_MEDFORD, 72 EFX_FAMILY_MEDFORD2, 73 EFX_FAMILY_NTYPES 74 } efx_family_t; 75 76 extern __checkReturn efx_rc_t 77 efx_family( 78 __in uint16_t venid, 79 __in uint16_t devid, 80 __out efx_family_t *efp, 81 __out unsigned int *membarp); 82 83 84 #define EFX_PCI_VENID_SFC 0x1924 85 86 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 87 88 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 89 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 90 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 91 92 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 93 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 94 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 95 96 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 97 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 98 99 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 100 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 101 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 102 103 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 104 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 105 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 106 107 108 #define EFX_MEM_BAR_SIENA 2 109 110 #define EFX_MEM_BAR_HUNTINGTON_PF 2 111 #define EFX_MEM_BAR_HUNTINGTON_VF 0 112 113 #define EFX_MEM_BAR_MEDFORD_PF 2 114 #define EFX_MEM_BAR_MEDFORD_VF 0 115 116 #define EFX_MEM_BAR_MEDFORD2 0 117 118 119 /* Error codes */ 120 121 enum { 122 EFX_ERR_INVALID, 123 EFX_ERR_SRAM_OOB, 124 EFX_ERR_BUFID_DC_OOB, 125 EFX_ERR_MEM_PERR, 126 EFX_ERR_RBUF_OWN, 127 EFX_ERR_TBUF_OWN, 128 EFX_ERR_RDESQ_OWN, 129 EFX_ERR_TDESQ_OWN, 130 EFX_ERR_EVQ_OWN, 131 EFX_ERR_EVFF_OFLO, 132 EFX_ERR_ILL_ADDR, 133 EFX_ERR_SRAM_PERR, 134 EFX_ERR_NCODES 135 }; 136 137 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 138 extern __checkReturn uint32_t 139 efx_crc32_calculate( 140 __in uint32_t crc_init, 141 __in_ecount(length) uint8_t const *input, 142 __in int length); 143 144 145 /* Type prototypes */ 146 147 typedef struct efx_rxq_s efx_rxq_t; 148 149 /* NIC */ 150 151 typedef struct efx_nic_s efx_nic_t; 152 153 extern __checkReturn efx_rc_t 154 efx_nic_create( 155 __in efx_family_t family, 156 __in efsys_identifier_t *esip, 157 __in efsys_bar_t *esbp, 158 __in efsys_lock_t *eslp, 159 __deref_out efx_nic_t **enpp); 160 161 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 162 typedef enum efx_fw_variant_e { 163 EFX_FW_VARIANT_FULL_FEATURED, 164 EFX_FW_VARIANT_LOW_LATENCY, 165 EFX_FW_VARIANT_PACKED_STREAM, 166 EFX_FW_VARIANT_HIGH_TX_RATE, 167 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 168 EFX_FW_VARIANT_RULES_ENGINE, 169 EFX_FW_VARIANT_DPDK, 170 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 171 } efx_fw_variant_t; 172 173 extern __checkReturn efx_rc_t 174 efx_nic_probe( 175 __in efx_nic_t *enp, 176 __in efx_fw_variant_t efv); 177 178 extern __checkReturn efx_rc_t 179 efx_nic_init( 180 __in efx_nic_t *enp); 181 182 extern __checkReturn efx_rc_t 183 efx_nic_reset( 184 __in efx_nic_t *enp); 185 186 extern __checkReturn boolean_t 187 efx_nic_hw_unavailable( 188 __in efx_nic_t *enp); 189 190 extern void 191 efx_nic_set_hw_unavailable( 192 __in efx_nic_t *enp); 193 194 #if EFSYS_OPT_DIAG 195 196 extern __checkReturn efx_rc_t 197 efx_nic_register_test( 198 __in efx_nic_t *enp); 199 200 #endif /* EFSYS_OPT_DIAG */ 201 202 extern void 203 efx_nic_fini( 204 __in efx_nic_t *enp); 205 206 extern void 207 efx_nic_unprobe( 208 __in efx_nic_t *enp); 209 210 extern void 211 efx_nic_destroy( 212 __in efx_nic_t *enp); 213 214 #define EFX_PCIE_LINK_SPEED_GEN1 1 215 #define EFX_PCIE_LINK_SPEED_GEN2 2 216 #define EFX_PCIE_LINK_SPEED_GEN3 3 217 218 typedef enum efx_pcie_link_performance_e { 219 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 220 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 221 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 222 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 223 } efx_pcie_link_performance_t; 224 225 extern __checkReturn efx_rc_t 226 efx_nic_calculate_pcie_link_bandwidth( 227 __in uint32_t pcie_link_width, 228 __in uint32_t pcie_link_gen, 229 __out uint32_t *bandwidth_mbpsp); 230 231 extern __checkReturn efx_rc_t 232 efx_nic_check_pcie_link_speed( 233 __in efx_nic_t *enp, 234 __in uint32_t pcie_link_width, 235 __in uint32_t pcie_link_gen, 236 __out efx_pcie_link_performance_t *resultp); 237 238 #if EFSYS_OPT_MCDI 239 240 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 241 /* Huntington and Medford require MCDIv2 commands */ 242 #define WITH_MCDI_V2 1 243 #endif 244 245 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 246 247 typedef enum efx_mcdi_exception_e { 248 EFX_MCDI_EXCEPTION_MC_REBOOT, 249 EFX_MCDI_EXCEPTION_MC_BADASSERT, 250 } efx_mcdi_exception_t; 251 252 #if EFSYS_OPT_MCDI_LOGGING 253 typedef enum efx_log_msg_e { 254 EFX_LOG_INVALID, 255 EFX_LOG_MCDI_REQUEST, 256 EFX_LOG_MCDI_RESPONSE, 257 } efx_log_msg_t; 258 #endif /* EFSYS_OPT_MCDI_LOGGING */ 259 260 typedef struct efx_mcdi_transport_s { 261 void *emt_context; 262 efsys_mem_t *emt_dma_mem; 263 void (*emt_execute)(void *, efx_mcdi_req_t *); 264 void (*emt_ev_cpl)(void *); 265 void (*emt_exception)(void *, efx_mcdi_exception_t); 266 #if EFSYS_OPT_MCDI_LOGGING 267 void (*emt_logger)(void *, efx_log_msg_t, 268 void *, size_t, void *, size_t); 269 #endif /* EFSYS_OPT_MCDI_LOGGING */ 270 #if EFSYS_OPT_MCDI_PROXY_AUTH 271 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 272 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 273 } efx_mcdi_transport_t; 274 275 extern __checkReturn efx_rc_t 276 efx_mcdi_init( 277 __in efx_nic_t *enp, 278 __in const efx_mcdi_transport_t *mtp); 279 280 extern __checkReturn efx_rc_t 281 efx_mcdi_reboot( 282 __in efx_nic_t *enp); 283 284 void 285 efx_mcdi_new_epoch( 286 __in efx_nic_t *enp); 287 288 extern void 289 efx_mcdi_get_timeout( 290 __in efx_nic_t *enp, 291 __in efx_mcdi_req_t *emrp, 292 __out uint32_t *usec_timeoutp); 293 294 extern void 295 efx_mcdi_request_start( 296 __in efx_nic_t *enp, 297 __in efx_mcdi_req_t *emrp, 298 __in boolean_t ev_cpl); 299 300 extern __checkReturn boolean_t 301 efx_mcdi_request_poll( 302 __in efx_nic_t *enp); 303 304 extern __checkReturn boolean_t 305 efx_mcdi_request_abort( 306 __in efx_nic_t *enp); 307 308 extern void 309 efx_mcdi_fini( 310 __in efx_nic_t *enp); 311 312 #endif /* EFSYS_OPT_MCDI */ 313 314 /* INTR */ 315 316 #define EFX_NINTR_SIENA 1024 317 318 typedef enum efx_intr_type_e { 319 EFX_INTR_INVALID = 0, 320 EFX_INTR_LINE, 321 EFX_INTR_MESSAGE, 322 EFX_INTR_NTYPES 323 } efx_intr_type_t; 324 325 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 326 327 extern __checkReturn efx_rc_t 328 efx_intr_init( 329 __in efx_nic_t *enp, 330 __in efx_intr_type_t type, 331 __in_opt efsys_mem_t *esmp); 332 333 extern void 334 efx_intr_enable( 335 __in efx_nic_t *enp); 336 337 extern void 338 efx_intr_disable( 339 __in efx_nic_t *enp); 340 341 extern void 342 efx_intr_disable_unlocked( 343 __in efx_nic_t *enp); 344 345 #define EFX_INTR_NEVQS 32 346 347 extern __checkReturn efx_rc_t 348 efx_intr_trigger( 349 __in efx_nic_t *enp, 350 __in unsigned int level); 351 352 extern void 353 efx_intr_status_line( 354 __in efx_nic_t *enp, 355 __out boolean_t *fatalp, 356 __out uint32_t *maskp); 357 358 extern void 359 efx_intr_status_message( 360 __in efx_nic_t *enp, 361 __in unsigned int message, 362 __out boolean_t *fatalp); 363 364 extern void 365 efx_intr_fatal( 366 __in efx_nic_t *enp); 367 368 extern void 369 efx_intr_fini( 370 __in efx_nic_t *enp); 371 372 /* MAC */ 373 374 #if EFSYS_OPT_MAC_STATS 375 376 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 377 typedef enum efx_mac_stat_e { 378 EFX_MAC_RX_OCTETS, 379 EFX_MAC_RX_PKTS, 380 EFX_MAC_RX_UNICST_PKTS, 381 EFX_MAC_RX_MULTICST_PKTS, 382 EFX_MAC_RX_BRDCST_PKTS, 383 EFX_MAC_RX_PAUSE_PKTS, 384 EFX_MAC_RX_LE_64_PKTS, 385 EFX_MAC_RX_65_TO_127_PKTS, 386 EFX_MAC_RX_128_TO_255_PKTS, 387 EFX_MAC_RX_256_TO_511_PKTS, 388 EFX_MAC_RX_512_TO_1023_PKTS, 389 EFX_MAC_RX_1024_TO_15XX_PKTS, 390 EFX_MAC_RX_GE_15XX_PKTS, 391 EFX_MAC_RX_ERRORS, 392 EFX_MAC_RX_FCS_ERRORS, 393 EFX_MAC_RX_DROP_EVENTS, 394 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 395 EFX_MAC_RX_SYMBOL_ERRORS, 396 EFX_MAC_RX_ALIGN_ERRORS, 397 EFX_MAC_RX_INTERNAL_ERRORS, 398 EFX_MAC_RX_JABBER_PKTS, 399 EFX_MAC_RX_LANE0_CHAR_ERR, 400 EFX_MAC_RX_LANE1_CHAR_ERR, 401 EFX_MAC_RX_LANE2_CHAR_ERR, 402 EFX_MAC_RX_LANE3_CHAR_ERR, 403 EFX_MAC_RX_LANE0_DISP_ERR, 404 EFX_MAC_RX_LANE1_DISP_ERR, 405 EFX_MAC_RX_LANE2_DISP_ERR, 406 EFX_MAC_RX_LANE3_DISP_ERR, 407 EFX_MAC_RX_MATCH_FAULT, 408 EFX_MAC_RX_NODESC_DROP_CNT, 409 EFX_MAC_TX_OCTETS, 410 EFX_MAC_TX_PKTS, 411 EFX_MAC_TX_UNICST_PKTS, 412 EFX_MAC_TX_MULTICST_PKTS, 413 EFX_MAC_TX_BRDCST_PKTS, 414 EFX_MAC_TX_PAUSE_PKTS, 415 EFX_MAC_TX_LE_64_PKTS, 416 EFX_MAC_TX_65_TO_127_PKTS, 417 EFX_MAC_TX_128_TO_255_PKTS, 418 EFX_MAC_TX_256_TO_511_PKTS, 419 EFX_MAC_TX_512_TO_1023_PKTS, 420 EFX_MAC_TX_1024_TO_15XX_PKTS, 421 EFX_MAC_TX_GE_15XX_PKTS, 422 EFX_MAC_TX_ERRORS, 423 EFX_MAC_TX_SGL_COL_PKTS, 424 EFX_MAC_TX_MULT_COL_PKTS, 425 EFX_MAC_TX_EX_COL_PKTS, 426 EFX_MAC_TX_LATE_COL_PKTS, 427 EFX_MAC_TX_DEF_PKTS, 428 EFX_MAC_TX_EX_DEF_PKTS, 429 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 430 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 431 EFX_MAC_PM_TRUNC_VFIFO_FULL, 432 EFX_MAC_PM_DISCARD_VFIFO_FULL, 433 EFX_MAC_PM_TRUNC_QBB, 434 EFX_MAC_PM_DISCARD_QBB, 435 EFX_MAC_PM_DISCARD_MAPPING, 436 EFX_MAC_RXDP_Q_DISABLED_PKTS, 437 EFX_MAC_RXDP_DI_DROPPED_PKTS, 438 EFX_MAC_RXDP_STREAMING_PKTS, 439 EFX_MAC_RXDP_HLB_FETCH, 440 EFX_MAC_RXDP_HLB_WAIT, 441 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 442 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 443 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 444 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 445 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 446 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 447 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 448 EFX_MAC_VADAPTER_RX_BAD_BYTES, 449 EFX_MAC_VADAPTER_RX_OVERFLOW, 450 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 451 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 452 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 453 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 454 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 455 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 456 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 457 EFX_MAC_VADAPTER_TX_BAD_BYTES, 458 EFX_MAC_VADAPTER_TX_OVERFLOW, 459 EFX_MAC_FEC_UNCORRECTED_ERRORS, 460 EFX_MAC_FEC_CORRECTED_ERRORS, 461 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 462 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 463 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 464 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 465 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 466 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 467 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 468 EFX_MAC_CTPIO_OVERFLOW_FAIL, 469 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 470 EFX_MAC_CTPIO_TIMEOUT_FAIL, 471 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 472 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 473 EFX_MAC_CTPIO_INVALID_WR_FAIL, 474 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 475 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 476 EFX_MAC_CTPIO_RUNT_FALLBACK, 477 EFX_MAC_CTPIO_SUCCESS, 478 EFX_MAC_CTPIO_FALLBACK, 479 EFX_MAC_CTPIO_POISON, 480 EFX_MAC_CTPIO_ERASE, 481 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 482 EFX_MAC_RXDP_HLB_IDLE, 483 EFX_MAC_RXDP_HLB_TIMEOUT, 484 EFX_MAC_NSTATS 485 } efx_mac_stat_t; 486 487 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 488 489 #endif /* EFSYS_OPT_MAC_STATS */ 490 491 typedef enum efx_link_mode_e { 492 EFX_LINK_UNKNOWN = 0, 493 EFX_LINK_DOWN, 494 EFX_LINK_10HDX, 495 EFX_LINK_10FDX, 496 EFX_LINK_100HDX, 497 EFX_LINK_100FDX, 498 EFX_LINK_1000HDX, 499 EFX_LINK_1000FDX, 500 EFX_LINK_10000FDX, 501 EFX_LINK_40000FDX, 502 EFX_LINK_25000FDX, 503 EFX_LINK_50000FDX, 504 EFX_LINK_100000FDX, 505 EFX_LINK_NMODES 506 } efx_link_mode_t; 507 508 #define EFX_MAC_ADDR_LEN 6 509 510 #define EFX_VNI_OR_VSID_LEN 3 511 512 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 513 514 #define EFX_MAC_MULTICAST_LIST_MAX 256 515 516 #define EFX_MAC_SDU_MAX 9202 517 518 #define EFX_MAC_PDU_ADJUSTMENT \ 519 (/* EtherII */ 14 \ 520 + /* VLAN */ 4 \ 521 + /* CRC */ 4 \ 522 + /* bug16011 */ 16) \ 523 524 #define EFX_MAC_PDU(_sdu) \ 525 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 526 527 /* 528 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 529 * the SDU rounded up slightly. 530 */ 531 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 532 533 #define EFX_MAC_PDU_MIN 60 534 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 535 536 extern __checkReturn efx_rc_t 537 efx_mac_pdu_get( 538 __in efx_nic_t *enp, 539 __out size_t *pdu); 540 541 extern __checkReturn efx_rc_t 542 efx_mac_pdu_set( 543 __in efx_nic_t *enp, 544 __in size_t pdu); 545 546 extern __checkReturn efx_rc_t 547 efx_mac_addr_set( 548 __in efx_nic_t *enp, 549 __in uint8_t *addr); 550 551 extern __checkReturn efx_rc_t 552 efx_mac_filter_set( 553 __in efx_nic_t *enp, 554 __in boolean_t all_unicst, 555 __in boolean_t mulcst, 556 __in boolean_t all_mulcst, 557 __in boolean_t brdcst); 558 559 extern __checkReturn efx_rc_t 560 efx_mac_multicast_list_set( 561 __in efx_nic_t *enp, 562 __in_ecount(6*count) uint8_t const *addrs, 563 __in int count); 564 565 extern __checkReturn efx_rc_t 566 efx_mac_filter_default_rxq_set( 567 __in efx_nic_t *enp, 568 __in efx_rxq_t *erp, 569 __in boolean_t using_rss); 570 571 extern void 572 efx_mac_filter_default_rxq_clear( 573 __in efx_nic_t *enp); 574 575 extern __checkReturn efx_rc_t 576 efx_mac_drain( 577 __in efx_nic_t *enp, 578 __in boolean_t enabled); 579 580 extern __checkReturn efx_rc_t 581 efx_mac_up( 582 __in efx_nic_t *enp, 583 __out boolean_t *mac_upp); 584 585 #define EFX_FCNTL_RESPOND 0x00000001 586 #define EFX_FCNTL_GENERATE 0x00000002 587 588 extern __checkReturn efx_rc_t 589 efx_mac_fcntl_set( 590 __in efx_nic_t *enp, 591 __in unsigned int fcntl, 592 __in boolean_t autoneg); 593 594 extern void 595 efx_mac_fcntl_get( 596 __in efx_nic_t *enp, 597 __out unsigned int *fcntl_wantedp, 598 __out unsigned int *fcntl_linkp); 599 600 601 #if EFSYS_OPT_MAC_STATS 602 603 #if EFSYS_OPT_NAMES 604 605 extern __checkReturn const char * 606 efx_mac_stat_name( 607 __in efx_nic_t *enp, 608 __in unsigned int id); 609 610 #endif /* EFSYS_OPT_NAMES */ 611 612 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 613 614 #define EFX_MAC_STATS_MASK_NPAGES \ 615 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 616 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 617 618 /* 619 * Get mask of MAC statistics supported by the hardware. 620 * 621 * If mask_size is insufficient to return the mask, EINVAL error is 622 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 623 * (which is sizeof (uint32_t)) is sufficient. 624 */ 625 extern __checkReturn efx_rc_t 626 efx_mac_stats_get_mask( 627 __in efx_nic_t *enp, 628 __out_bcount(mask_size) uint32_t *maskp, 629 __in size_t mask_size); 630 631 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 632 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 633 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 634 635 636 extern __checkReturn efx_rc_t 637 efx_mac_stats_clear( 638 __in efx_nic_t *enp); 639 640 /* 641 * Upload mac statistics supported by the hardware into the given buffer. 642 * 643 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 644 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 645 * 646 * The hardware will only DMA statistics that it understands (of course). 647 * Drivers should not make any assumptions about which statistics are 648 * supported, especially when the statistics are generated by firmware. 649 * 650 * Thus, drivers should zero this buffer before use, so that not-understood 651 * statistics read back as zero. 652 */ 653 extern __checkReturn efx_rc_t 654 efx_mac_stats_upload( 655 __in efx_nic_t *enp, 656 __in efsys_mem_t *esmp); 657 658 extern __checkReturn efx_rc_t 659 efx_mac_stats_periodic( 660 __in efx_nic_t *enp, 661 __in efsys_mem_t *esmp, 662 __in uint16_t period_ms, 663 __in boolean_t events); 664 665 extern __checkReturn efx_rc_t 666 efx_mac_stats_update( 667 __in efx_nic_t *enp, 668 __in efsys_mem_t *esmp, 669 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 670 __inout_opt uint32_t *generationp); 671 672 #endif /* EFSYS_OPT_MAC_STATS */ 673 674 /* MON */ 675 676 typedef enum efx_mon_type_e { 677 EFX_MON_INVALID = 0, 678 EFX_MON_SFC90X0, 679 EFX_MON_SFC91X0, 680 EFX_MON_SFC92X0, 681 EFX_MON_NTYPES 682 } efx_mon_type_t; 683 684 #if EFSYS_OPT_NAMES 685 686 extern const char * 687 efx_mon_name( 688 __in efx_nic_t *enp); 689 690 #endif /* EFSYS_OPT_NAMES */ 691 692 extern __checkReturn efx_rc_t 693 efx_mon_init( 694 __in efx_nic_t *enp); 695 696 #if EFSYS_OPT_MON_STATS 697 698 #define EFX_MON_STATS_PAGE_SIZE 0x100 699 #define EFX_MON_MASK_ELEMENT_SIZE 32 700 701 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 702 typedef enum efx_mon_stat_e { 703 EFX_MON_STAT_CONTROLLER_TEMP, 704 EFX_MON_STAT_PHY_COMMON_TEMP, 705 EFX_MON_STAT_CONTROLLER_COOLING, 706 EFX_MON_STAT_PHY0_TEMP, 707 EFX_MON_STAT_PHY0_COOLING, 708 EFX_MON_STAT_PHY1_TEMP, 709 EFX_MON_STAT_PHY1_COOLING, 710 EFX_MON_STAT_IN_1V0, 711 EFX_MON_STAT_IN_1V2, 712 EFX_MON_STAT_IN_1V8, 713 EFX_MON_STAT_IN_2V5, 714 EFX_MON_STAT_IN_3V3, 715 EFX_MON_STAT_IN_12V0, 716 EFX_MON_STAT_IN_1V2A, 717 EFX_MON_STAT_IN_VREF, 718 EFX_MON_STAT_OUT_VAOE, 719 EFX_MON_STAT_AOE_TEMP, 720 EFX_MON_STAT_PSU_AOE_TEMP, 721 EFX_MON_STAT_PSU_TEMP, 722 EFX_MON_STAT_FAN_0, 723 EFX_MON_STAT_FAN_1, 724 EFX_MON_STAT_FAN_2, 725 EFX_MON_STAT_FAN_3, 726 EFX_MON_STAT_FAN_4, 727 EFX_MON_STAT_IN_VAOE, 728 EFX_MON_STAT_OUT_IAOE, 729 EFX_MON_STAT_IN_IAOE, 730 EFX_MON_STAT_NIC_POWER, 731 EFX_MON_STAT_IN_0V9, 732 EFX_MON_STAT_IN_I0V9, 733 EFX_MON_STAT_IN_I1V2, 734 EFX_MON_STAT_IN_0V9_ADC, 735 EFX_MON_STAT_CONTROLLER_2_TEMP, 736 EFX_MON_STAT_VREG_INTERNAL_TEMP, 737 EFX_MON_STAT_VREG_0V9_TEMP, 738 EFX_MON_STAT_VREG_1V2_TEMP, 739 EFX_MON_STAT_CONTROLLER_VPTAT, 740 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 741 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 742 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 743 EFX_MON_STAT_AMBIENT_TEMP, 744 EFX_MON_STAT_AIRFLOW, 745 EFX_MON_STAT_VDD08D_VSS08D_CSR, 746 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 747 EFX_MON_STAT_HOTPOINT_TEMP, 748 EFX_MON_STAT_PHY_POWER_PORT0, 749 EFX_MON_STAT_PHY_POWER_PORT1, 750 EFX_MON_STAT_MUM_VCC, 751 EFX_MON_STAT_IN_0V9_A, 752 EFX_MON_STAT_IN_I0V9_A, 753 EFX_MON_STAT_VREG_0V9_A_TEMP, 754 EFX_MON_STAT_IN_0V9_B, 755 EFX_MON_STAT_IN_I0V9_B, 756 EFX_MON_STAT_VREG_0V9_B_TEMP, 757 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 758 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 759 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 760 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 761 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 762 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 763 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 764 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 765 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 766 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 767 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 768 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 769 EFX_MON_STAT_SODIMM_VOUT, 770 EFX_MON_STAT_SODIMM_0_TEMP, 771 EFX_MON_STAT_SODIMM_1_TEMP, 772 EFX_MON_STAT_PHY0_VCC, 773 EFX_MON_STAT_PHY1_VCC, 774 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 775 EFX_MON_STAT_BOARD_FRONT_TEMP, 776 EFX_MON_STAT_BOARD_BACK_TEMP, 777 EFX_MON_STAT_IN_I1V8, 778 EFX_MON_STAT_IN_I2V5, 779 EFX_MON_STAT_IN_I3V3, 780 EFX_MON_STAT_IN_I12V0, 781 EFX_MON_STAT_IN_1V3, 782 EFX_MON_STAT_IN_I1V3, 783 EFX_MON_NSTATS 784 } efx_mon_stat_t; 785 786 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 787 788 typedef enum efx_mon_stat_state_e { 789 EFX_MON_STAT_STATE_OK = 0, 790 EFX_MON_STAT_STATE_WARNING = 1, 791 EFX_MON_STAT_STATE_FATAL = 2, 792 EFX_MON_STAT_STATE_BROKEN = 3, 793 EFX_MON_STAT_STATE_NO_READING = 4, 794 } efx_mon_stat_state_t; 795 796 typedef enum efx_mon_stat_unit_e { 797 EFX_MON_STAT_UNIT_UNKNOWN = 0, 798 EFX_MON_STAT_UNIT_BOOL, 799 EFX_MON_STAT_UNIT_TEMP_C, 800 EFX_MON_STAT_UNIT_VOLTAGE_MV, 801 EFX_MON_STAT_UNIT_CURRENT_MA, 802 EFX_MON_STAT_UNIT_POWER_W, 803 EFX_MON_STAT_UNIT_RPM, 804 EFX_MON_NUNITS 805 } efx_mon_stat_unit_t; 806 807 typedef struct efx_mon_stat_value_s { 808 uint16_t emsv_value; 809 efx_mon_stat_state_t emsv_state; 810 efx_mon_stat_unit_t emsv_unit; 811 } efx_mon_stat_value_t; 812 813 typedef struct efx_mon_limit_value_s { 814 uint16_t emlv_warning_min; 815 uint16_t emlv_warning_max; 816 uint16_t emlv_fatal_min; 817 uint16_t emlv_fatal_max; 818 } efx_mon_stat_limits_t; 819 820 typedef enum efx_mon_stat_portmask_e { 821 EFX_MON_STAT_PORTMAP_NONE = 0, 822 EFX_MON_STAT_PORTMAP_PORT0 = 1, 823 EFX_MON_STAT_PORTMAP_PORT1 = 2, 824 EFX_MON_STAT_PORTMAP_PORT2 = 3, 825 EFX_MON_STAT_PORTMAP_PORT3 = 4, 826 EFX_MON_STAT_PORTMAP_ALL = (-1), 827 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 828 } efx_mon_stat_portmask_t; 829 830 #if EFSYS_OPT_NAMES 831 832 extern const char * 833 efx_mon_stat_name( 834 __in efx_nic_t *enp, 835 __in efx_mon_stat_t id); 836 837 extern const char * 838 efx_mon_stat_description( 839 __in efx_nic_t *enp, 840 __in efx_mon_stat_t id); 841 842 #endif /* EFSYS_OPT_NAMES */ 843 844 extern __checkReturn boolean_t 845 efx_mon_mcdi_to_efx_stat( 846 __in int mcdi_index, 847 __out efx_mon_stat_t *statp); 848 849 extern __checkReturn boolean_t 850 efx_mon_get_stat_unit( 851 __in efx_mon_stat_t stat, 852 __out efx_mon_stat_unit_t *unitp); 853 854 extern __checkReturn boolean_t 855 efx_mon_get_stat_portmap( 856 __in efx_mon_stat_t stat, 857 __out efx_mon_stat_portmask_t *maskp); 858 859 extern __checkReturn efx_rc_t 860 efx_mon_stats_update( 861 __in efx_nic_t *enp, 862 __in efsys_mem_t *esmp, 863 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 864 865 extern __checkReturn efx_rc_t 866 efx_mon_limits_update( 867 __in efx_nic_t *enp, 868 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 869 870 #endif /* EFSYS_OPT_MON_STATS */ 871 872 extern void 873 efx_mon_fini( 874 __in efx_nic_t *enp); 875 876 /* PHY */ 877 878 extern __checkReturn efx_rc_t 879 efx_phy_verify( 880 __in efx_nic_t *enp); 881 882 #if EFSYS_OPT_PHY_LED_CONTROL 883 884 typedef enum efx_phy_led_mode_e { 885 EFX_PHY_LED_DEFAULT = 0, 886 EFX_PHY_LED_OFF, 887 EFX_PHY_LED_ON, 888 EFX_PHY_LED_FLASH, 889 EFX_PHY_LED_NMODES 890 } efx_phy_led_mode_t; 891 892 extern __checkReturn efx_rc_t 893 efx_phy_led_set( 894 __in efx_nic_t *enp, 895 __in efx_phy_led_mode_t mode); 896 897 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 898 899 extern __checkReturn efx_rc_t 900 efx_port_init( 901 __in efx_nic_t *enp); 902 903 #if EFSYS_OPT_LOOPBACK 904 905 typedef enum efx_loopback_type_e { 906 EFX_LOOPBACK_OFF = 0, 907 EFX_LOOPBACK_DATA = 1, 908 EFX_LOOPBACK_GMAC = 2, 909 EFX_LOOPBACK_XGMII = 3, 910 EFX_LOOPBACK_XGXS = 4, 911 EFX_LOOPBACK_XAUI = 5, 912 EFX_LOOPBACK_GMII = 6, 913 EFX_LOOPBACK_SGMII = 7, 914 EFX_LOOPBACK_XGBR = 8, 915 EFX_LOOPBACK_XFI = 9, 916 EFX_LOOPBACK_XAUI_FAR = 10, 917 EFX_LOOPBACK_GMII_FAR = 11, 918 EFX_LOOPBACK_SGMII_FAR = 12, 919 EFX_LOOPBACK_XFI_FAR = 13, 920 EFX_LOOPBACK_GPHY = 14, 921 EFX_LOOPBACK_PHY_XS = 15, 922 EFX_LOOPBACK_PCS = 16, 923 EFX_LOOPBACK_PMA_PMD = 17, 924 EFX_LOOPBACK_XPORT = 18, 925 EFX_LOOPBACK_XGMII_WS = 19, 926 EFX_LOOPBACK_XAUI_WS = 20, 927 EFX_LOOPBACK_XAUI_WS_FAR = 21, 928 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 929 EFX_LOOPBACK_GMII_WS = 23, 930 EFX_LOOPBACK_XFI_WS = 24, 931 EFX_LOOPBACK_XFI_WS_FAR = 25, 932 EFX_LOOPBACK_PHYXS_WS = 26, 933 EFX_LOOPBACK_PMA_INT = 27, 934 EFX_LOOPBACK_SD_NEAR = 28, 935 EFX_LOOPBACK_SD_FAR = 29, 936 EFX_LOOPBACK_PMA_INT_WS = 30, 937 EFX_LOOPBACK_SD_FEP2_WS = 31, 938 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 939 EFX_LOOPBACK_SD_FEP_WS = 33, 940 EFX_LOOPBACK_SD_FES_WS = 34, 941 EFX_LOOPBACK_AOE_INT_NEAR = 35, 942 EFX_LOOPBACK_DATA_WS = 36, 943 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 944 EFX_LOOPBACK_NTYPES 945 } efx_loopback_type_t; 946 947 typedef enum efx_loopback_kind_e { 948 EFX_LOOPBACK_KIND_OFF = 0, 949 EFX_LOOPBACK_KIND_ALL, 950 EFX_LOOPBACK_KIND_MAC, 951 EFX_LOOPBACK_KIND_PHY, 952 EFX_LOOPBACK_NKINDS 953 } efx_loopback_kind_t; 954 955 extern void 956 efx_loopback_mask( 957 __in efx_loopback_kind_t loopback_kind, 958 __out efx_qword_t *maskp); 959 960 extern __checkReturn efx_rc_t 961 efx_port_loopback_set( 962 __in efx_nic_t *enp, 963 __in efx_link_mode_t link_mode, 964 __in efx_loopback_type_t type); 965 966 #if EFSYS_OPT_NAMES 967 968 extern __checkReturn const char * 969 efx_loopback_type_name( 970 __in efx_nic_t *enp, 971 __in efx_loopback_type_t type); 972 973 #endif /* EFSYS_OPT_NAMES */ 974 975 #endif /* EFSYS_OPT_LOOPBACK */ 976 977 extern __checkReturn efx_rc_t 978 efx_port_poll( 979 __in efx_nic_t *enp, 980 __out_opt efx_link_mode_t *link_modep); 981 982 extern void 983 efx_port_fini( 984 __in efx_nic_t *enp); 985 986 typedef enum efx_phy_cap_type_e { 987 EFX_PHY_CAP_INVALID = 0, 988 EFX_PHY_CAP_10HDX, 989 EFX_PHY_CAP_10FDX, 990 EFX_PHY_CAP_100HDX, 991 EFX_PHY_CAP_100FDX, 992 EFX_PHY_CAP_1000HDX, 993 EFX_PHY_CAP_1000FDX, 994 EFX_PHY_CAP_10000FDX, 995 EFX_PHY_CAP_PAUSE, 996 EFX_PHY_CAP_ASYM, 997 EFX_PHY_CAP_AN, 998 EFX_PHY_CAP_40000FDX, 999 EFX_PHY_CAP_DDM, 1000 EFX_PHY_CAP_100000FDX, 1001 EFX_PHY_CAP_25000FDX, 1002 EFX_PHY_CAP_50000FDX, 1003 EFX_PHY_CAP_BASER_FEC, 1004 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1005 EFX_PHY_CAP_RS_FEC, 1006 EFX_PHY_CAP_RS_FEC_REQUESTED, 1007 EFX_PHY_CAP_25G_BASER_FEC, 1008 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1009 EFX_PHY_CAP_NTYPES 1010 } efx_phy_cap_type_t; 1011 1012 1013 #define EFX_PHY_CAP_CURRENT 0x00000000 1014 #define EFX_PHY_CAP_DEFAULT 0x00000001 1015 #define EFX_PHY_CAP_PERM 0x00000002 1016 1017 extern void 1018 efx_phy_adv_cap_get( 1019 __in efx_nic_t *enp, 1020 __in uint32_t flag, 1021 __out uint32_t *maskp); 1022 1023 extern __checkReturn efx_rc_t 1024 efx_phy_adv_cap_set( 1025 __in efx_nic_t *enp, 1026 __in uint32_t mask); 1027 1028 extern void 1029 efx_phy_lp_cap_get( 1030 __in efx_nic_t *enp, 1031 __out uint32_t *maskp); 1032 1033 extern __checkReturn efx_rc_t 1034 efx_phy_oui_get( 1035 __in efx_nic_t *enp, 1036 __out uint32_t *ouip); 1037 1038 typedef enum efx_phy_media_type_e { 1039 EFX_PHY_MEDIA_INVALID = 0, 1040 EFX_PHY_MEDIA_XAUI, 1041 EFX_PHY_MEDIA_CX4, 1042 EFX_PHY_MEDIA_KX4, 1043 EFX_PHY_MEDIA_XFP, 1044 EFX_PHY_MEDIA_SFP_PLUS, 1045 EFX_PHY_MEDIA_BASE_T, 1046 EFX_PHY_MEDIA_QSFP_PLUS, 1047 EFX_PHY_MEDIA_NTYPES 1048 } efx_phy_media_type_t; 1049 1050 /* 1051 * Get the type of medium currently used. If the board has ports for 1052 * modules, a module is present, and we recognise the media type of 1053 * the module, then this will be the media type of the module. 1054 * Otherwise it will be the media type of the port. 1055 */ 1056 extern void 1057 efx_phy_media_type_get( 1058 __in efx_nic_t *enp, 1059 __out efx_phy_media_type_t *typep); 1060 1061 /* 1062 * 2-wire device address of the base information in accordance with SFF-8472 1063 * Diagnostic Monitoring Interface for Optical Transceivers section 1064 * 4 Memory Organization. 1065 */ 1066 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1067 1068 /* 1069 * 2-wire device address of the digital diagnostics monitoring interface 1070 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1071 * Transceivers section 4 Memory Organization. 1072 */ 1073 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1074 1075 /* 1076 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1077 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1078 * Operation. 1079 */ 1080 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1081 1082 /* 1083 * Maximum accessible data offset for PHY module information. 1084 */ 1085 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1086 1087 1088 extern __checkReturn efx_rc_t 1089 efx_phy_module_get_info( 1090 __in efx_nic_t *enp, 1091 __in uint8_t dev_addr, 1092 __in size_t offset, 1093 __in size_t len, 1094 __out_bcount(len) uint8_t *data); 1095 1096 #if EFSYS_OPT_PHY_STATS 1097 1098 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1099 typedef enum efx_phy_stat_e { 1100 EFX_PHY_STAT_OUI, 1101 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1102 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1103 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1104 EFX_PHY_STAT_PMA_PMD_REV_A, 1105 EFX_PHY_STAT_PMA_PMD_REV_B, 1106 EFX_PHY_STAT_PMA_PMD_REV_C, 1107 EFX_PHY_STAT_PMA_PMD_REV_D, 1108 EFX_PHY_STAT_PCS_LINK_UP, 1109 EFX_PHY_STAT_PCS_RX_FAULT, 1110 EFX_PHY_STAT_PCS_TX_FAULT, 1111 EFX_PHY_STAT_PCS_BER, 1112 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1113 EFX_PHY_STAT_PHY_XS_LINK_UP, 1114 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1115 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1116 EFX_PHY_STAT_PHY_XS_ALIGN, 1117 EFX_PHY_STAT_PHY_XS_SYNC_A, 1118 EFX_PHY_STAT_PHY_XS_SYNC_B, 1119 EFX_PHY_STAT_PHY_XS_SYNC_C, 1120 EFX_PHY_STAT_PHY_XS_SYNC_D, 1121 EFX_PHY_STAT_AN_LINK_UP, 1122 EFX_PHY_STAT_AN_MASTER, 1123 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1124 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1125 EFX_PHY_STAT_CL22EXT_LINK_UP, 1126 EFX_PHY_STAT_SNR_A, 1127 EFX_PHY_STAT_SNR_B, 1128 EFX_PHY_STAT_SNR_C, 1129 EFX_PHY_STAT_SNR_D, 1130 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1131 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1132 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1133 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1134 EFX_PHY_STAT_AN_COMPLETE, 1135 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1136 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1137 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1138 EFX_PHY_STAT_PCS_FW_VERSION_0, 1139 EFX_PHY_STAT_PCS_FW_VERSION_1, 1140 EFX_PHY_STAT_PCS_FW_VERSION_2, 1141 EFX_PHY_STAT_PCS_FW_VERSION_3, 1142 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1143 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1144 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1145 EFX_PHY_STAT_PCS_OP_MODE, 1146 EFX_PHY_NSTATS 1147 } efx_phy_stat_t; 1148 1149 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1150 1151 #if EFSYS_OPT_NAMES 1152 1153 extern const char * 1154 efx_phy_stat_name( 1155 __in efx_nic_t *enp, 1156 __in efx_phy_stat_t stat); 1157 1158 #endif /* EFSYS_OPT_NAMES */ 1159 1160 #define EFX_PHY_STATS_SIZE 0x100 1161 1162 extern __checkReturn efx_rc_t 1163 efx_phy_stats_update( 1164 __in efx_nic_t *enp, 1165 __in efsys_mem_t *esmp, 1166 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1167 1168 #endif /* EFSYS_OPT_PHY_STATS */ 1169 1170 1171 #if EFSYS_OPT_BIST 1172 1173 typedef enum efx_bist_type_e { 1174 EFX_BIST_TYPE_UNKNOWN, 1175 EFX_BIST_TYPE_PHY_NORMAL, 1176 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1177 EFX_BIST_TYPE_PHY_CABLE_LONG, 1178 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1179 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1180 EFX_BIST_TYPE_REG, /* Test the register memories */ 1181 EFX_BIST_TYPE_NTYPES, 1182 } efx_bist_type_t; 1183 1184 typedef enum efx_bist_result_e { 1185 EFX_BIST_RESULT_UNKNOWN, 1186 EFX_BIST_RESULT_RUNNING, 1187 EFX_BIST_RESULT_PASSED, 1188 EFX_BIST_RESULT_FAILED, 1189 } efx_bist_result_t; 1190 1191 typedef enum efx_phy_cable_status_e { 1192 EFX_PHY_CABLE_STATUS_OK, 1193 EFX_PHY_CABLE_STATUS_INVALID, 1194 EFX_PHY_CABLE_STATUS_OPEN, 1195 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1196 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1197 EFX_PHY_CABLE_STATUS_BUSY, 1198 } efx_phy_cable_status_t; 1199 1200 typedef enum efx_bist_value_e { 1201 EFX_BIST_PHY_CABLE_LENGTH_A, 1202 EFX_BIST_PHY_CABLE_LENGTH_B, 1203 EFX_BIST_PHY_CABLE_LENGTH_C, 1204 EFX_BIST_PHY_CABLE_LENGTH_D, 1205 EFX_BIST_PHY_CABLE_STATUS_A, 1206 EFX_BIST_PHY_CABLE_STATUS_B, 1207 EFX_BIST_PHY_CABLE_STATUS_C, 1208 EFX_BIST_PHY_CABLE_STATUS_D, 1209 EFX_BIST_FAULT_CODE, 1210 /* 1211 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1212 * response. 1213 */ 1214 EFX_BIST_MEM_TEST, 1215 EFX_BIST_MEM_ADDR, 1216 EFX_BIST_MEM_BUS, 1217 EFX_BIST_MEM_EXPECT, 1218 EFX_BIST_MEM_ACTUAL, 1219 EFX_BIST_MEM_ECC, 1220 EFX_BIST_MEM_ECC_PARITY, 1221 EFX_BIST_MEM_ECC_FATAL, 1222 EFX_BIST_NVALUES, 1223 } efx_bist_value_t; 1224 1225 extern __checkReturn efx_rc_t 1226 efx_bist_enable_offline( 1227 __in efx_nic_t *enp); 1228 1229 extern __checkReturn efx_rc_t 1230 efx_bist_start( 1231 __in efx_nic_t *enp, 1232 __in efx_bist_type_t type); 1233 1234 extern __checkReturn efx_rc_t 1235 efx_bist_poll( 1236 __in efx_nic_t *enp, 1237 __in efx_bist_type_t type, 1238 __out efx_bist_result_t *resultp, 1239 __out_opt uint32_t *value_maskp, 1240 __out_ecount_opt(count) unsigned long *valuesp, 1241 __in size_t count); 1242 1243 extern void 1244 efx_bist_stop( 1245 __in efx_nic_t *enp, 1246 __in efx_bist_type_t type); 1247 1248 #endif /* EFSYS_OPT_BIST */ 1249 1250 #define EFX_FEATURE_IPV6 0x00000001 1251 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1252 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1253 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1254 #define EFX_FEATURE_MCDI 0x00000020 1255 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1256 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1257 #define EFX_FEATURE_TURBO 0x00000100 1258 #define EFX_FEATURE_MCDI_DMA 0x00000200 1259 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1260 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1261 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1262 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1263 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1264 1265 typedef enum efx_tunnel_protocol_e { 1266 EFX_TUNNEL_PROTOCOL_NONE = 0, 1267 EFX_TUNNEL_PROTOCOL_VXLAN, 1268 EFX_TUNNEL_PROTOCOL_GENEVE, 1269 EFX_TUNNEL_PROTOCOL_NVGRE, 1270 EFX_TUNNEL_NPROTOS 1271 } efx_tunnel_protocol_t; 1272 1273 typedef enum efx_vi_window_shift_e { 1274 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1275 EFX_VI_WINDOW_SHIFT_8K = 13, 1276 EFX_VI_WINDOW_SHIFT_16K = 14, 1277 EFX_VI_WINDOW_SHIFT_64K = 16, 1278 } efx_vi_window_shift_t; 1279 1280 typedef struct efx_nic_cfg_s { 1281 uint32_t enc_board_type; 1282 uint32_t enc_phy_type; 1283 #if EFSYS_OPT_NAMES 1284 char enc_phy_name[21]; 1285 #endif 1286 char enc_phy_revision[21]; 1287 efx_mon_type_t enc_mon_type; 1288 #if EFSYS_OPT_MON_STATS 1289 uint32_t enc_mon_stat_dma_buf_size; 1290 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1291 #endif 1292 unsigned int enc_features; 1293 efx_vi_window_shift_t enc_vi_window_shift; 1294 uint8_t enc_mac_addr[6]; 1295 uint8_t enc_port; /* PHY port number */ 1296 uint32_t enc_intr_vec_base; 1297 uint32_t enc_intr_limit; 1298 uint32_t enc_evq_limit; 1299 uint32_t enc_txq_limit; 1300 uint32_t enc_rxq_limit; 1301 uint32_t enc_txq_max_ndescs; 1302 uint32_t enc_buftbl_limit; 1303 uint32_t enc_piobuf_limit; 1304 uint32_t enc_piobuf_size; 1305 uint32_t enc_piobuf_min_alloc_size; 1306 uint32_t enc_evq_timer_quantum_ns; 1307 uint32_t enc_evq_timer_max_us; 1308 uint32_t enc_clk_mult; 1309 uint32_t enc_rx_prefix_size; 1310 uint32_t enc_rx_buf_align_start; 1311 uint32_t enc_rx_buf_align_end; 1312 #if EFSYS_OPT_RX_SCALE 1313 uint32_t enc_rx_scale_max_exclusive_contexts; 1314 /* 1315 * Mask of supported hash algorithms. 1316 * Hash algorithm types are used as the bit indices. 1317 */ 1318 uint32_t enc_rx_scale_hash_alg_mask; 1319 /* 1320 * Indicates whether port numbers can be included to the 1321 * input data for hash computation. 1322 */ 1323 boolean_t enc_rx_scale_l4_hash_supported; 1324 boolean_t enc_rx_scale_additional_modes_supported; 1325 #endif /* EFSYS_OPT_RX_SCALE */ 1326 #if EFSYS_OPT_LOOPBACK 1327 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1328 #endif /* EFSYS_OPT_LOOPBACK */ 1329 #if EFSYS_OPT_PHY_FLAGS 1330 uint32_t enc_phy_flags_mask; 1331 #endif /* EFSYS_OPT_PHY_FLAGS */ 1332 #if EFSYS_OPT_PHY_LED_CONTROL 1333 uint32_t enc_led_mask; 1334 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1335 #if EFSYS_OPT_PHY_STATS 1336 uint64_t enc_phy_stat_mask; 1337 #endif /* EFSYS_OPT_PHY_STATS */ 1338 #if EFSYS_OPT_MCDI 1339 uint8_t enc_mcdi_mdio_channel; 1340 #if EFSYS_OPT_PHY_STATS 1341 uint32_t enc_mcdi_phy_stat_mask; 1342 #endif /* EFSYS_OPT_PHY_STATS */ 1343 #if EFSYS_OPT_MON_STATS 1344 uint32_t *enc_mcdi_sensor_maskp; 1345 uint32_t enc_mcdi_sensor_mask_size; 1346 #endif /* EFSYS_OPT_MON_STATS */ 1347 #endif /* EFSYS_OPT_MCDI */ 1348 #if EFSYS_OPT_BIST 1349 uint32_t enc_bist_mask; 1350 #endif /* EFSYS_OPT_BIST */ 1351 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 1352 uint32_t enc_pf; 1353 uint32_t enc_vf; 1354 uint32_t enc_privilege_mask; 1355 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 1356 boolean_t enc_bug26807_workaround; 1357 boolean_t enc_bug35388_workaround; 1358 boolean_t enc_bug41750_workaround; 1359 boolean_t enc_bug61265_workaround; 1360 boolean_t enc_bug61297_workaround; 1361 boolean_t enc_rx_batching_enabled; 1362 /* Maximum number of descriptors completed in an rx event. */ 1363 uint32_t enc_rx_batch_max; 1364 /* Number of rx descriptors the hardware requires for a push. */ 1365 uint32_t enc_rx_push_align; 1366 /* Maximum amount of data in DMA descriptor */ 1367 uint32_t enc_tx_dma_desc_size_max; 1368 /* 1369 * Boundary which DMA descriptor data must not cross or 0 if no 1370 * limitation. 1371 */ 1372 uint32_t enc_tx_dma_desc_boundary; 1373 /* 1374 * Maximum number of bytes into the packet the TCP header can start for 1375 * the hardware to apply TSO packet edits. 1376 */ 1377 uint32_t enc_tx_tso_tcp_header_offset_limit; 1378 boolean_t enc_fw_assisted_tso_enabled; 1379 boolean_t enc_fw_assisted_tso_v2_enabled; 1380 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1381 /* Number of TSO contexts on the NIC (FATSOv2) */ 1382 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1383 boolean_t enc_hw_tx_insert_vlan_enabled; 1384 /* Number of PFs on the NIC */ 1385 uint32_t enc_hw_pf_count; 1386 /* Datapath firmware vadapter/vport/vswitch support */ 1387 boolean_t enc_datapath_cap_evb; 1388 boolean_t enc_rx_disable_scatter_supported; 1389 boolean_t enc_allow_set_mac_with_installed_filters; 1390 boolean_t enc_enhanced_set_mac_supported; 1391 boolean_t enc_init_evq_v2_supported; 1392 boolean_t enc_rx_packed_stream_supported; 1393 boolean_t enc_rx_var_packed_stream_supported; 1394 boolean_t enc_rx_es_super_buffer_supported; 1395 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1396 boolean_t enc_pm_and_rxdp_counters; 1397 boolean_t enc_mac_stats_40g_tx_size_bins; 1398 uint32_t enc_tunnel_encapsulations_supported; 1399 /* 1400 * NIC global maximum for unique UDP tunnel ports shared by all 1401 * functions. 1402 */ 1403 uint32_t enc_tunnel_config_udp_entries_max; 1404 /* External port identifier */ 1405 uint8_t enc_external_port; 1406 uint32_t enc_mcdi_max_payload_length; 1407 /* VPD may be per-PF or global */ 1408 boolean_t enc_vpd_is_global; 1409 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1410 uint32_t enc_required_pcie_bandwidth_mbps; 1411 uint32_t enc_max_pcie_link_gen; 1412 /* Firmware verifies integrity of NVRAM updates */ 1413 uint32_t enc_nvram_update_verify_result_supported; 1414 /* Firmware support for extended MAC_STATS buffer */ 1415 uint32_t enc_mac_stats_nstats; 1416 boolean_t enc_fec_counters; 1417 boolean_t enc_hlb_counters; 1418 /* Firmware support for "FLAG" and "MARK" filter actions */ 1419 boolean_t enc_filter_action_flag_supported; 1420 boolean_t enc_filter_action_mark_supported; 1421 uint32_t enc_filter_action_mark_max; 1422 } efx_nic_cfg_t; 1423 1424 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1425 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1426 1427 #define EFX_PCI_FUNCTION(_encp) \ 1428 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1429 1430 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1431 1432 extern const efx_nic_cfg_t * 1433 efx_nic_cfg_get( 1434 __in efx_nic_t *enp); 1435 1436 /* RxDPCPU firmware id values by which FW variant can be identified */ 1437 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1438 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1439 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1440 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1441 #define EFX_RXDP_DPDK_FW_ID 0x6 1442 1443 typedef struct efx_nic_fw_info_s { 1444 /* Basic FW version information */ 1445 uint16_t enfi_mc_fw_version[4]; 1446 /* 1447 * If datapath capabilities can be detected, 1448 * additional FW information is to be shown 1449 */ 1450 boolean_t enfi_dpcpu_fw_ids_valid; 1451 /* Rx and Tx datapath CPU FW IDs */ 1452 uint16_t enfi_rx_dpcpu_fw_id; 1453 uint16_t enfi_tx_dpcpu_fw_id; 1454 } efx_nic_fw_info_t; 1455 1456 extern __checkReturn efx_rc_t 1457 efx_nic_get_fw_version( 1458 __in efx_nic_t *enp, 1459 __out efx_nic_fw_info_t *enfip); 1460 1461 /* Driver resource limits (minimum required/maximum usable). */ 1462 typedef struct efx_drv_limits_s { 1463 uint32_t edl_min_evq_count; 1464 uint32_t edl_max_evq_count; 1465 1466 uint32_t edl_min_rxq_count; 1467 uint32_t edl_max_rxq_count; 1468 1469 uint32_t edl_min_txq_count; 1470 uint32_t edl_max_txq_count; 1471 1472 /* PIO blocks (sub-allocated from piobuf) */ 1473 uint32_t edl_min_pio_alloc_size; 1474 uint32_t edl_max_pio_alloc_count; 1475 } efx_drv_limits_t; 1476 1477 extern __checkReturn efx_rc_t 1478 efx_nic_set_drv_limits( 1479 __inout efx_nic_t *enp, 1480 __in efx_drv_limits_t *edlp); 1481 1482 typedef enum efx_nic_region_e { 1483 EFX_REGION_VI, /* Memory BAR UC mapping */ 1484 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1485 } efx_nic_region_t; 1486 1487 extern __checkReturn efx_rc_t 1488 efx_nic_get_bar_region( 1489 __in efx_nic_t *enp, 1490 __in efx_nic_region_t region, 1491 __out uint32_t *offsetp, 1492 __out size_t *sizep); 1493 1494 extern __checkReturn efx_rc_t 1495 efx_nic_get_vi_pool( 1496 __in efx_nic_t *enp, 1497 __out uint32_t *evq_countp, 1498 __out uint32_t *rxq_countp, 1499 __out uint32_t *txq_countp); 1500 1501 1502 #if EFSYS_OPT_VPD 1503 1504 typedef enum efx_vpd_tag_e { 1505 EFX_VPD_ID = 0x02, 1506 EFX_VPD_END = 0x0f, 1507 EFX_VPD_RO = 0x10, 1508 EFX_VPD_RW = 0x11, 1509 } efx_vpd_tag_t; 1510 1511 typedef uint16_t efx_vpd_keyword_t; 1512 1513 typedef struct efx_vpd_value_s { 1514 efx_vpd_tag_t evv_tag; 1515 efx_vpd_keyword_t evv_keyword; 1516 uint8_t evv_length; 1517 uint8_t evv_value[0x100]; 1518 } efx_vpd_value_t; 1519 1520 1521 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1522 1523 extern __checkReturn efx_rc_t 1524 efx_vpd_init( 1525 __in efx_nic_t *enp); 1526 1527 extern __checkReturn efx_rc_t 1528 efx_vpd_size( 1529 __in efx_nic_t *enp, 1530 __out size_t *sizep); 1531 1532 extern __checkReturn efx_rc_t 1533 efx_vpd_read( 1534 __in efx_nic_t *enp, 1535 __out_bcount(size) caddr_t data, 1536 __in size_t size); 1537 1538 extern __checkReturn efx_rc_t 1539 efx_vpd_verify( 1540 __in efx_nic_t *enp, 1541 __in_bcount(size) caddr_t data, 1542 __in size_t size); 1543 1544 extern __checkReturn efx_rc_t 1545 efx_vpd_reinit( 1546 __in efx_nic_t *enp, 1547 __in_bcount(size) caddr_t data, 1548 __in size_t size); 1549 1550 extern __checkReturn efx_rc_t 1551 efx_vpd_get( 1552 __in efx_nic_t *enp, 1553 __in_bcount(size) caddr_t data, 1554 __in size_t size, 1555 __inout efx_vpd_value_t *evvp); 1556 1557 extern __checkReturn efx_rc_t 1558 efx_vpd_set( 1559 __in efx_nic_t *enp, 1560 __inout_bcount(size) caddr_t data, 1561 __in size_t size, 1562 __in efx_vpd_value_t *evvp); 1563 1564 extern __checkReturn efx_rc_t 1565 efx_vpd_next( 1566 __in efx_nic_t *enp, 1567 __inout_bcount(size) caddr_t data, 1568 __in size_t size, 1569 __out efx_vpd_value_t *evvp, 1570 __inout unsigned int *contp); 1571 1572 extern __checkReturn efx_rc_t 1573 efx_vpd_write( 1574 __in efx_nic_t *enp, 1575 __in_bcount(size) caddr_t data, 1576 __in size_t size); 1577 1578 extern void 1579 efx_vpd_fini( 1580 __in efx_nic_t *enp); 1581 1582 #endif /* EFSYS_OPT_VPD */ 1583 1584 /* NVRAM */ 1585 1586 #if EFSYS_OPT_NVRAM 1587 1588 typedef enum efx_nvram_type_e { 1589 EFX_NVRAM_INVALID = 0, 1590 EFX_NVRAM_BOOTROM, 1591 EFX_NVRAM_BOOTROM_CFG, 1592 EFX_NVRAM_MC_FIRMWARE, 1593 EFX_NVRAM_MC_GOLDEN, 1594 EFX_NVRAM_PHY, 1595 EFX_NVRAM_NULLPHY, 1596 EFX_NVRAM_FPGA, 1597 EFX_NVRAM_FCFW, 1598 EFX_NVRAM_CPLD, 1599 EFX_NVRAM_FPGA_BACKUP, 1600 EFX_NVRAM_DYNAMIC_CFG, 1601 EFX_NVRAM_LICENSE, 1602 EFX_NVRAM_UEFIROM, 1603 EFX_NVRAM_MUM_FIRMWARE, 1604 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1605 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1606 EFX_NVRAM_NTYPES, 1607 } efx_nvram_type_t; 1608 1609 extern __checkReturn efx_rc_t 1610 efx_nvram_init( 1611 __in efx_nic_t *enp); 1612 1613 #if EFSYS_OPT_DIAG 1614 1615 extern __checkReturn efx_rc_t 1616 efx_nvram_test( 1617 __in efx_nic_t *enp); 1618 1619 #endif /* EFSYS_OPT_DIAG */ 1620 1621 extern __checkReturn efx_rc_t 1622 efx_nvram_size( 1623 __in efx_nic_t *enp, 1624 __in efx_nvram_type_t type, 1625 __out size_t *sizep); 1626 1627 extern __checkReturn efx_rc_t 1628 efx_nvram_rw_start( 1629 __in efx_nic_t *enp, 1630 __in efx_nvram_type_t type, 1631 __out_opt size_t *pref_chunkp); 1632 1633 extern __checkReturn efx_rc_t 1634 efx_nvram_rw_finish( 1635 __in efx_nic_t *enp, 1636 __in efx_nvram_type_t type, 1637 __out_opt uint32_t *verify_resultp); 1638 1639 extern __checkReturn efx_rc_t 1640 efx_nvram_get_version( 1641 __in efx_nic_t *enp, 1642 __in efx_nvram_type_t type, 1643 __out uint32_t *subtypep, 1644 __out_ecount(4) uint16_t version[4]); 1645 1646 extern __checkReturn efx_rc_t 1647 efx_nvram_read_chunk( 1648 __in efx_nic_t *enp, 1649 __in efx_nvram_type_t type, 1650 __in unsigned int offset, 1651 __out_bcount(size) caddr_t data, 1652 __in size_t size); 1653 1654 extern __checkReturn efx_rc_t 1655 efx_nvram_read_backup( 1656 __in efx_nic_t *enp, 1657 __in efx_nvram_type_t type, 1658 __in unsigned int offset, 1659 __out_bcount(size) caddr_t data, 1660 __in size_t size); 1661 1662 extern __checkReturn efx_rc_t 1663 efx_nvram_set_version( 1664 __in efx_nic_t *enp, 1665 __in efx_nvram_type_t type, 1666 __in_ecount(4) uint16_t version[4]); 1667 1668 extern __checkReturn efx_rc_t 1669 efx_nvram_validate( 1670 __in efx_nic_t *enp, 1671 __in efx_nvram_type_t type, 1672 __in_bcount(partn_size) caddr_t partn_data, 1673 __in size_t partn_size); 1674 1675 extern __checkReturn efx_rc_t 1676 efx_nvram_erase( 1677 __in efx_nic_t *enp, 1678 __in efx_nvram_type_t type); 1679 1680 extern __checkReturn efx_rc_t 1681 efx_nvram_write_chunk( 1682 __in efx_nic_t *enp, 1683 __in efx_nvram_type_t type, 1684 __in unsigned int offset, 1685 __in_bcount(size) caddr_t data, 1686 __in size_t size); 1687 1688 extern void 1689 efx_nvram_fini( 1690 __in efx_nic_t *enp); 1691 1692 #endif /* EFSYS_OPT_NVRAM */ 1693 1694 #if EFSYS_OPT_BOOTCFG 1695 1696 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1697 extern __checkReturn efx_rc_t 1698 efx_bootcfg_sector_info( 1699 __in efx_nic_t *enp, 1700 __in uint32_t pf, 1701 __out_opt uint32_t *sector_countp, 1702 __out size_t *offsetp, 1703 __out size_t *max_sizep); 1704 1705 /* 1706 * Copy bootcfg sector data to a target buffer which may differ in size. 1707 * Optionally corrects format errors in source buffer. 1708 */ 1709 extern efx_rc_t 1710 efx_bootcfg_copy_sector( 1711 __in efx_nic_t *enp, 1712 __inout_bcount(sector_length) 1713 uint8_t *sector, 1714 __in size_t sector_length, 1715 __out_bcount(data_size) uint8_t *data, 1716 __in size_t data_size, 1717 __in boolean_t handle_format_errors); 1718 1719 extern efx_rc_t 1720 efx_bootcfg_read( 1721 __in efx_nic_t *enp, 1722 __out_bcount(size) uint8_t *data, 1723 __in size_t size); 1724 1725 extern efx_rc_t 1726 efx_bootcfg_write( 1727 __in efx_nic_t *enp, 1728 __in_bcount(size) uint8_t *data, 1729 __in size_t size); 1730 1731 1732 /* 1733 * Processing routines for buffers arranged in the DHCP/BOOTP option format 1734 * (see https://tools.ietf.org/html/rfc1533) 1735 * 1736 * Summarising the format: the buffer is a sequence of options. All options 1737 * begin with a tag octet, which uniquely identifies the option. Fixed- 1738 * length options without data consist of only a tag octet. Only options PAD 1739 * (0) and END (255) are fixed length. All other options are variable-length 1740 * with a length octet following the tag octet. The value of the length 1741 * octet does not include the two octets specifying the tag and length. The 1742 * length octet is followed by "length" octets of data. 1743 * 1744 * Option data may be a sequence of sub-options in the same format. The data 1745 * content of the encapsulating option is one or more encapsulated sub-options, 1746 * with no terminating END tag is required. 1747 * 1748 * To be valid, the top-level sequence of options should be terminated by an 1749 * END tag. The buffer should be padded with the PAD byte. 1750 * 1751 * When stored to NVRAM, the DHCP option format buffer is preceded by a 1752 * checksum octet. The full buffer (including after the END tag) contributes 1753 * to the checksum, hence the need to fill the buffer to the end with PAD. 1754 */ 1755 1756 #define EFX_DHCP_END ((uint8_t)0xff) 1757 #define EFX_DHCP_PAD ((uint8_t)0) 1758 1759 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 1760 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 1761 1762 extern __checkReturn uint8_t 1763 efx_dhcp_csum( 1764 __in_bcount(size) uint8_t const *data, 1765 __in size_t size); 1766 1767 extern __checkReturn efx_rc_t 1768 efx_dhcp_verify( 1769 __in_bcount(size) uint8_t const *data, 1770 __in size_t size, 1771 __out_opt size_t *usedp); 1772 1773 extern __checkReturn efx_rc_t 1774 efx_dhcp_find_tag( 1775 __in_bcount(buffer_length) uint8_t *bufferp, 1776 __in size_t buffer_length, 1777 __in uint16_t opt, 1778 __deref_out uint8_t **valuepp, 1779 __out size_t *value_lengthp); 1780 1781 extern __checkReturn efx_rc_t 1782 efx_dhcp_find_end( 1783 __in_bcount(buffer_length) uint8_t *bufferp, 1784 __in size_t buffer_length, 1785 __deref_out uint8_t **endpp); 1786 1787 1788 extern __checkReturn efx_rc_t 1789 efx_dhcp_delete_tag( 1790 __inout_bcount(buffer_length) uint8_t *bufferp, 1791 __in size_t buffer_length, 1792 __in uint16_t opt); 1793 1794 extern __checkReturn efx_rc_t 1795 efx_dhcp_add_tag( 1796 __inout_bcount(buffer_length) uint8_t *bufferp, 1797 __in size_t buffer_length, 1798 __in uint16_t opt, 1799 __in_bcount_opt(value_length) uint8_t *valuep, 1800 __in size_t value_length); 1801 1802 extern __checkReturn efx_rc_t 1803 efx_dhcp_update_tag( 1804 __inout_bcount(buffer_length) uint8_t *bufferp, 1805 __in size_t buffer_length, 1806 __in uint16_t opt, 1807 __in uint8_t *value_locationp, 1808 __in_bcount_opt(value_length) uint8_t *valuep, 1809 __in size_t value_length); 1810 1811 1812 #endif /* EFSYS_OPT_BOOTCFG */ 1813 1814 #if EFSYS_OPT_IMAGE_LAYOUT 1815 1816 #include "ef10_signed_image_layout.h" 1817 1818 /* 1819 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 1820 * 1821 * NOTE: 1822 * The image header format is extensible. However, older drivers require an 1823 * exact match of image header version and header length when validating and 1824 * writing firmware images. 1825 * 1826 * To avoid breaking backward compatibility, we use the upper bits of the 1827 * controller version fields to contain an extra version number used for 1828 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 1829 * version). See bug39254 and SF-102785-PS for details. 1830 */ 1831 typedef struct efx_image_header_s { 1832 uint32_t eih_magic; 1833 uint32_t eih_version; 1834 uint32_t eih_type; 1835 uint32_t eih_subtype; 1836 uint32_t eih_code_size; 1837 uint32_t eih_size; 1838 union { 1839 uint32_t eih_controller_version_min; 1840 struct { 1841 uint16_t eih_controller_version_min_short; 1842 uint8_t eih_extra_version_a; 1843 uint8_t eih_extra_version_b; 1844 }; 1845 }; 1846 union { 1847 uint32_t eih_controller_version_max; 1848 struct { 1849 uint16_t eih_controller_version_max_short; 1850 uint8_t eih_extra_version_c; 1851 uint8_t eih_extra_version_d; 1852 }; 1853 }; 1854 uint16_t eih_code_version_a; 1855 uint16_t eih_code_version_b; 1856 uint16_t eih_code_version_c; 1857 uint16_t eih_code_version_d; 1858 } efx_image_header_t; 1859 1860 #define EFX_IMAGE_HEADER_SIZE (40) 1861 #define EFX_IMAGE_HEADER_VERSION (4) 1862 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 1863 1864 1865 typedef struct efx_image_trailer_s { 1866 uint32_t eit_crc; 1867 } efx_image_trailer_t; 1868 1869 #define EFX_IMAGE_TRAILER_SIZE (4) 1870 1871 typedef enum efx_image_format_e { 1872 EFX_IMAGE_FORMAT_NO_IMAGE, 1873 EFX_IMAGE_FORMAT_INVALID, 1874 EFX_IMAGE_FORMAT_UNSIGNED, 1875 EFX_IMAGE_FORMAT_SIGNED, 1876 } efx_image_format_t; 1877 1878 typedef struct efx_image_info_s { 1879 efx_image_format_t eii_format; 1880 uint8_t * eii_imagep; 1881 size_t eii_image_size; 1882 efx_image_header_t * eii_headerp; 1883 } efx_image_info_t; 1884 1885 extern __checkReturn efx_rc_t 1886 efx_check_reflash_image( 1887 __in void *bufferp, 1888 __in uint32_t buffer_size, 1889 __out efx_image_info_t *infop); 1890 1891 extern __checkReturn efx_rc_t 1892 efx_build_signed_image_write_buffer( 1893 __out_bcount(buffer_size) 1894 uint8_t *bufferp, 1895 __in uint32_t buffer_size, 1896 __in efx_image_info_t *infop, 1897 __out efx_image_header_t **headerpp); 1898 1899 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 1900 1901 #if EFSYS_OPT_DIAG 1902 1903 typedef enum efx_pattern_type_t { 1904 EFX_PATTERN_BYTE_INCREMENT = 0, 1905 EFX_PATTERN_ALL_THE_SAME, 1906 EFX_PATTERN_BIT_ALTERNATE, 1907 EFX_PATTERN_BYTE_ALTERNATE, 1908 EFX_PATTERN_BYTE_CHANGING, 1909 EFX_PATTERN_BIT_SWEEP, 1910 EFX_PATTERN_NTYPES 1911 } efx_pattern_type_t; 1912 1913 typedef void 1914 (*efx_sram_pattern_fn_t)( 1915 __in size_t row, 1916 __in boolean_t negate, 1917 __out efx_qword_t *eqp); 1918 1919 extern __checkReturn efx_rc_t 1920 efx_sram_test( 1921 __in efx_nic_t *enp, 1922 __in efx_pattern_type_t type); 1923 1924 #endif /* EFSYS_OPT_DIAG */ 1925 1926 extern __checkReturn efx_rc_t 1927 efx_sram_buf_tbl_set( 1928 __in efx_nic_t *enp, 1929 __in uint32_t id, 1930 __in efsys_mem_t *esmp, 1931 __in size_t n); 1932 1933 extern void 1934 efx_sram_buf_tbl_clear( 1935 __in efx_nic_t *enp, 1936 __in uint32_t id, 1937 __in size_t n); 1938 1939 #define EFX_BUF_TBL_SIZE 0x20000 1940 1941 #define EFX_BUF_SIZE 4096 1942 1943 /* EV */ 1944 1945 typedef struct efx_evq_s efx_evq_t; 1946 1947 #if EFSYS_OPT_QSTATS 1948 1949 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1950 typedef enum efx_ev_qstat_e { 1951 EV_ALL, 1952 EV_RX, 1953 EV_RX_OK, 1954 EV_RX_FRM_TRUNC, 1955 EV_RX_TOBE_DISC, 1956 EV_RX_PAUSE_FRM_ERR, 1957 EV_RX_BUF_OWNER_ID_ERR, 1958 EV_RX_IPV4_HDR_CHKSUM_ERR, 1959 EV_RX_TCP_UDP_CHKSUM_ERR, 1960 EV_RX_ETH_CRC_ERR, 1961 EV_RX_IP_FRAG_ERR, 1962 EV_RX_MCAST_PKT, 1963 EV_RX_MCAST_HASH_MATCH, 1964 EV_RX_TCP_IPV4, 1965 EV_RX_TCP_IPV6, 1966 EV_RX_UDP_IPV4, 1967 EV_RX_UDP_IPV6, 1968 EV_RX_OTHER_IPV4, 1969 EV_RX_OTHER_IPV6, 1970 EV_RX_NON_IP, 1971 EV_RX_BATCH, 1972 EV_TX, 1973 EV_TX_WQ_FF_FULL, 1974 EV_TX_PKT_ERR, 1975 EV_TX_PKT_TOO_BIG, 1976 EV_TX_UNEXPECTED, 1977 EV_GLOBAL, 1978 EV_GLOBAL_MNT, 1979 EV_DRIVER, 1980 EV_DRIVER_SRM_UPD_DONE, 1981 EV_DRIVER_TX_DESCQ_FLS_DONE, 1982 EV_DRIVER_RX_DESCQ_FLS_DONE, 1983 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1984 EV_DRIVER_RX_DSC_ERROR, 1985 EV_DRIVER_TX_DSC_ERROR, 1986 EV_DRV_GEN, 1987 EV_MCDI_RESPONSE, 1988 EV_NQSTATS 1989 } efx_ev_qstat_t; 1990 1991 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1992 1993 #endif /* EFSYS_OPT_QSTATS */ 1994 1995 extern __checkReturn efx_rc_t 1996 efx_ev_init( 1997 __in efx_nic_t *enp); 1998 1999 extern void 2000 efx_ev_fini( 2001 __in efx_nic_t *enp); 2002 2003 #define EFX_EVQ_MAXNEVS 32768 2004 #define EFX_EVQ_MINNEVS 512 2005 2006 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 2007 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 2008 2009 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2010 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2011 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2012 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2013 2014 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2015 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2016 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2017 2018 extern __checkReturn efx_rc_t 2019 efx_ev_qcreate( 2020 __in efx_nic_t *enp, 2021 __in unsigned int index, 2022 __in efsys_mem_t *esmp, 2023 __in size_t ndescs, 2024 __in uint32_t id, 2025 __in uint32_t us, 2026 __in uint32_t flags, 2027 __deref_out efx_evq_t **eepp); 2028 2029 extern void 2030 efx_ev_qpost( 2031 __in efx_evq_t *eep, 2032 __in uint16_t data); 2033 2034 typedef __checkReturn boolean_t 2035 (*efx_initialized_ev_t)( 2036 __in_opt void *arg); 2037 2038 #define EFX_PKT_UNICAST 0x0004 2039 #define EFX_PKT_START 0x0008 2040 2041 #define EFX_PKT_VLAN_TAGGED 0x0010 2042 #define EFX_CKSUM_TCPUDP 0x0020 2043 #define EFX_CKSUM_IPV4 0x0040 2044 #define EFX_PKT_CONT 0x0080 2045 2046 #define EFX_CHECK_VLAN 0x0100 2047 #define EFX_PKT_TCP 0x0200 2048 #define EFX_PKT_UDP 0x0400 2049 #define EFX_PKT_IPV4 0x0800 2050 2051 #define EFX_PKT_IPV6 0x1000 2052 #define EFX_PKT_PREFIX_LEN 0x2000 2053 #define EFX_ADDR_MISMATCH 0x4000 2054 #define EFX_DISCARD 0x8000 2055 2056 /* 2057 * The following flags are used only for packed stream 2058 * mode. The values for the flags are reused to fit into 16 bit, 2059 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2060 * packed stream mode 2061 */ 2062 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2063 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2064 2065 2066 #define EFX_EV_RX_NLABELS 32 2067 #define EFX_EV_TX_NLABELS 32 2068 2069 typedef __checkReturn boolean_t 2070 (*efx_rx_ev_t)( 2071 __in_opt void *arg, 2072 __in uint32_t label, 2073 __in uint32_t id, 2074 __in uint32_t size, 2075 __in uint16_t flags); 2076 2077 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2078 2079 /* 2080 * Packed stream mode is documented in SF-112241-TC. 2081 * The general idea is that, instead of putting each incoming 2082 * packet into a separate buffer which is specified in a RX 2083 * descriptor, a large buffer is provided to the hardware and 2084 * packets are put there in a continuous stream. 2085 * The main advantage of such an approach is that RX queue refilling 2086 * happens much less frequently. 2087 * 2088 * Equal stride packed stream mode is documented in SF-119419-TC. 2089 * The general idea is to utilize advantages of the packed stream, 2090 * but avoid indirection in packets representation. 2091 * The main advantage of such an approach is that RX queue refilling 2092 * happens much less frequently and packets buffers are independent 2093 * from upper layers point of view. 2094 */ 2095 2096 typedef __checkReturn boolean_t 2097 (*efx_rx_ps_ev_t)( 2098 __in_opt void *arg, 2099 __in uint32_t label, 2100 __in uint32_t id, 2101 __in uint32_t pkt_count, 2102 __in uint16_t flags); 2103 2104 #endif 2105 2106 typedef __checkReturn boolean_t 2107 (*efx_tx_ev_t)( 2108 __in_opt void *arg, 2109 __in uint32_t label, 2110 __in uint32_t id); 2111 2112 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2113 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2114 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2115 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2116 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2117 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2118 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2119 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2120 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2121 2122 typedef __checkReturn boolean_t 2123 (*efx_exception_ev_t)( 2124 __in_opt void *arg, 2125 __in uint32_t label, 2126 __in uint32_t data); 2127 2128 typedef __checkReturn boolean_t 2129 (*efx_rxq_flush_done_ev_t)( 2130 __in_opt void *arg, 2131 __in uint32_t rxq_index); 2132 2133 typedef __checkReturn boolean_t 2134 (*efx_rxq_flush_failed_ev_t)( 2135 __in_opt void *arg, 2136 __in uint32_t rxq_index); 2137 2138 typedef __checkReturn boolean_t 2139 (*efx_txq_flush_done_ev_t)( 2140 __in_opt void *arg, 2141 __in uint32_t txq_index); 2142 2143 typedef __checkReturn boolean_t 2144 (*efx_software_ev_t)( 2145 __in_opt void *arg, 2146 __in uint16_t magic); 2147 2148 typedef __checkReturn boolean_t 2149 (*efx_sram_ev_t)( 2150 __in_opt void *arg, 2151 __in uint32_t code); 2152 2153 #define EFX_SRAM_CLEAR 0 2154 #define EFX_SRAM_UPDATE 1 2155 #define EFX_SRAM_ILLEGAL_CLEAR 2 2156 2157 typedef __checkReturn boolean_t 2158 (*efx_wake_up_ev_t)( 2159 __in_opt void *arg, 2160 __in uint32_t label); 2161 2162 typedef __checkReturn boolean_t 2163 (*efx_timer_ev_t)( 2164 __in_opt void *arg, 2165 __in uint32_t label); 2166 2167 typedef __checkReturn boolean_t 2168 (*efx_link_change_ev_t)( 2169 __in_opt void *arg, 2170 __in efx_link_mode_t link_mode); 2171 2172 #if EFSYS_OPT_MON_STATS 2173 2174 typedef __checkReturn boolean_t 2175 (*efx_monitor_ev_t)( 2176 __in_opt void *arg, 2177 __in efx_mon_stat_t id, 2178 __in efx_mon_stat_value_t value); 2179 2180 #endif /* EFSYS_OPT_MON_STATS */ 2181 2182 #if EFSYS_OPT_MAC_STATS 2183 2184 typedef __checkReturn boolean_t 2185 (*efx_mac_stats_ev_t)( 2186 __in_opt void *arg, 2187 __in uint32_t generation); 2188 2189 #endif /* EFSYS_OPT_MAC_STATS */ 2190 2191 typedef struct efx_ev_callbacks_s { 2192 efx_initialized_ev_t eec_initialized; 2193 efx_rx_ev_t eec_rx; 2194 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2195 efx_rx_ps_ev_t eec_rx_ps; 2196 #endif 2197 efx_tx_ev_t eec_tx; 2198 efx_exception_ev_t eec_exception; 2199 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2200 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2201 efx_txq_flush_done_ev_t eec_txq_flush_done; 2202 efx_software_ev_t eec_software; 2203 efx_sram_ev_t eec_sram; 2204 efx_wake_up_ev_t eec_wake_up; 2205 efx_timer_ev_t eec_timer; 2206 efx_link_change_ev_t eec_link_change; 2207 #if EFSYS_OPT_MON_STATS 2208 efx_monitor_ev_t eec_monitor; 2209 #endif /* EFSYS_OPT_MON_STATS */ 2210 #if EFSYS_OPT_MAC_STATS 2211 efx_mac_stats_ev_t eec_mac_stats; 2212 #endif /* EFSYS_OPT_MAC_STATS */ 2213 } efx_ev_callbacks_t; 2214 2215 extern __checkReturn boolean_t 2216 efx_ev_qpending( 2217 __in efx_evq_t *eep, 2218 __in unsigned int count); 2219 2220 #if EFSYS_OPT_EV_PREFETCH 2221 2222 extern void 2223 efx_ev_qprefetch( 2224 __in efx_evq_t *eep, 2225 __in unsigned int count); 2226 2227 #endif /* EFSYS_OPT_EV_PREFETCH */ 2228 2229 extern void 2230 efx_ev_qpoll( 2231 __in efx_evq_t *eep, 2232 __inout unsigned int *countp, 2233 __in const efx_ev_callbacks_t *eecp, 2234 __in_opt void *arg); 2235 2236 extern __checkReturn efx_rc_t 2237 efx_ev_usecs_to_ticks( 2238 __in efx_nic_t *enp, 2239 __in unsigned int usecs, 2240 __out unsigned int *ticksp); 2241 2242 extern __checkReturn efx_rc_t 2243 efx_ev_qmoderate( 2244 __in efx_evq_t *eep, 2245 __in unsigned int us); 2246 2247 extern __checkReturn efx_rc_t 2248 efx_ev_qprime( 2249 __in efx_evq_t *eep, 2250 __in unsigned int count); 2251 2252 #if EFSYS_OPT_QSTATS 2253 2254 #if EFSYS_OPT_NAMES 2255 2256 extern const char * 2257 efx_ev_qstat_name( 2258 __in efx_nic_t *enp, 2259 __in unsigned int id); 2260 2261 #endif /* EFSYS_OPT_NAMES */ 2262 2263 extern void 2264 efx_ev_qstats_update( 2265 __in efx_evq_t *eep, 2266 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2267 2268 #endif /* EFSYS_OPT_QSTATS */ 2269 2270 extern void 2271 efx_ev_qdestroy( 2272 __in efx_evq_t *eep); 2273 2274 /* RX */ 2275 2276 extern __checkReturn efx_rc_t 2277 efx_rx_init( 2278 __inout efx_nic_t *enp); 2279 2280 extern void 2281 efx_rx_fini( 2282 __in efx_nic_t *enp); 2283 2284 #if EFSYS_OPT_RX_SCATTER 2285 __checkReturn efx_rc_t 2286 efx_rx_scatter_enable( 2287 __in efx_nic_t *enp, 2288 __in unsigned int buf_size); 2289 #endif /* EFSYS_OPT_RX_SCATTER */ 2290 2291 /* Handle to represent use of the default RSS context. */ 2292 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2293 2294 #if EFSYS_OPT_RX_SCALE 2295 2296 typedef enum efx_rx_hash_alg_e { 2297 EFX_RX_HASHALG_LFSR = 0, 2298 EFX_RX_HASHALG_TOEPLITZ, 2299 EFX_RX_HASHALG_PACKED_STREAM, 2300 EFX_RX_NHASHALGS 2301 } efx_rx_hash_alg_t; 2302 2303 /* 2304 * Legacy hash type flags. 2305 * 2306 * They represent standard tuples for distinct traffic classes. 2307 */ 2308 #define EFX_RX_HASH_IPV4 (1U << 0) 2309 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2310 #define EFX_RX_HASH_IPV6 (1U << 2) 2311 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2312 2313 #define EFX_RX_HASH_LEGACY_MASK \ 2314 (EFX_RX_HASH_IPV4 | \ 2315 EFX_RX_HASH_TCPIPV4 | \ 2316 EFX_RX_HASH_IPV6 | \ 2317 EFX_RX_HASH_TCPIPV6) 2318 2319 /* 2320 * The type of the argument used by efx_rx_scale_mode_set() to 2321 * provide a means for the client drivers to configure hashing. 2322 * 2323 * A properly constructed value can either be: 2324 * - a combination of legacy flags 2325 * - a combination of EFX_RX_HASH() flags 2326 */ 2327 typedef uint32_t efx_rx_hash_type_t; 2328 2329 typedef enum efx_rx_hash_support_e { 2330 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2331 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2332 } efx_rx_hash_support_t; 2333 2334 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2335 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2336 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2337 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2338 2339 typedef enum efx_rx_scale_context_type_e { 2340 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2341 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2342 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2343 } efx_rx_scale_context_type_t; 2344 2345 /* 2346 * Traffic classes eligible for hash computation. 2347 * 2348 * Select packet headers used in computing the receive hash. 2349 * This uses the same encoding as the RSS_MODES field of 2350 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2351 */ 2352 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2353 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2354 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2355 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2356 #define EFX_RX_CLASS_IPV4_LBN 16 2357 #define EFX_RX_CLASS_IPV4_WIDTH 4 2358 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2359 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2360 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2361 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2362 #define EFX_RX_CLASS_IPV6_LBN 28 2363 #define EFX_RX_CLASS_IPV6_WIDTH 4 2364 2365 #define EFX_RX_NCLASSES 6 2366 2367 /* 2368 * Ancillary flags used to construct generic hash tuples. 2369 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2370 */ 2371 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2372 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2373 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2374 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2375 2376 /* 2377 * Generic hash tuples. 2378 * 2379 * They express combinations of packet fields 2380 * which can contribute to the hash value for 2381 * a particular traffic class. 2382 */ 2383 #define EFX_RX_CLASS_HASH_DISABLE 0 2384 2385 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2386 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2387 2388 #define EFX_RX_CLASS_HASH_2TUPLE \ 2389 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2390 EFX_RX_CLASS_HASH_DST_ADDR) 2391 2392 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2393 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2394 EFX_RX_CLASS_HASH_SRC_PORT) 2395 2396 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2397 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2398 EFX_RX_CLASS_HASH_DST_PORT) 2399 2400 #define EFX_RX_CLASS_HASH_4TUPLE \ 2401 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2402 EFX_RX_CLASS_HASH_DST_ADDR | \ 2403 EFX_RX_CLASS_HASH_SRC_PORT | \ 2404 EFX_RX_CLASS_HASH_DST_PORT) 2405 2406 #define EFX_RX_CLASS_HASH_NTUPLES 7 2407 2408 /* 2409 * Hash flag constructor. 2410 * 2411 * Resulting flags encode hash tuples for specific traffic classes. 2412 * The client drivers are encouraged to use these flags to form 2413 * a hash type value. 2414 */ 2415 #define EFX_RX_HASH(_class, _tuple) \ 2416 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2417 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2418 2419 /* 2420 * The maximum number of EFX_RX_HASH() flags. 2421 */ 2422 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2423 2424 extern __checkReturn efx_rc_t 2425 efx_rx_scale_hash_flags_get( 2426 __in efx_nic_t *enp, 2427 __in efx_rx_hash_alg_t hash_alg, 2428 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2429 __in unsigned int max_nflags, 2430 __out unsigned int *nflagsp); 2431 2432 extern __checkReturn efx_rc_t 2433 efx_rx_hash_default_support_get( 2434 __in efx_nic_t *enp, 2435 __out efx_rx_hash_support_t *supportp); 2436 2437 2438 extern __checkReturn efx_rc_t 2439 efx_rx_scale_default_support_get( 2440 __in efx_nic_t *enp, 2441 __out efx_rx_scale_context_type_t *typep); 2442 2443 extern __checkReturn efx_rc_t 2444 efx_rx_scale_context_alloc( 2445 __in efx_nic_t *enp, 2446 __in efx_rx_scale_context_type_t type, 2447 __in uint32_t num_queues, 2448 __out uint32_t *rss_contextp); 2449 2450 extern __checkReturn efx_rc_t 2451 efx_rx_scale_context_free( 2452 __in efx_nic_t *enp, 2453 __in uint32_t rss_context); 2454 2455 extern __checkReturn efx_rc_t 2456 efx_rx_scale_mode_set( 2457 __in efx_nic_t *enp, 2458 __in uint32_t rss_context, 2459 __in efx_rx_hash_alg_t alg, 2460 __in efx_rx_hash_type_t type, 2461 __in boolean_t insert); 2462 2463 extern __checkReturn efx_rc_t 2464 efx_rx_scale_tbl_set( 2465 __in efx_nic_t *enp, 2466 __in uint32_t rss_context, 2467 __in_ecount(n) unsigned int *table, 2468 __in size_t n); 2469 2470 extern __checkReturn efx_rc_t 2471 efx_rx_scale_key_set( 2472 __in efx_nic_t *enp, 2473 __in uint32_t rss_context, 2474 __in_ecount(n) uint8_t *key, 2475 __in size_t n); 2476 2477 extern __checkReturn uint32_t 2478 efx_pseudo_hdr_hash_get( 2479 __in efx_rxq_t *erp, 2480 __in efx_rx_hash_alg_t func, 2481 __in uint8_t *buffer); 2482 2483 #endif /* EFSYS_OPT_RX_SCALE */ 2484 2485 extern __checkReturn efx_rc_t 2486 efx_pseudo_hdr_pkt_length_get( 2487 __in efx_rxq_t *erp, 2488 __in uint8_t *buffer, 2489 __out uint16_t *pkt_lengthp); 2490 2491 #define EFX_RXQ_MAXNDESCS 4096 2492 #define EFX_RXQ_MINNDESCS 512 2493 2494 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2495 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2496 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2497 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2498 2499 typedef enum efx_rxq_type_e { 2500 EFX_RXQ_TYPE_DEFAULT, 2501 EFX_RXQ_TYPE_PACKED_STREAM, 2502 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 2503 EFX_RXQ_NTYPES 2504 } efx_rxq_type_t; 2505 2506 /* 2507 * Dummy flag to be used instead of 0 to make it clear that the argument 2508 * is receive queue flags. 2509 */ 2510 #define EFX_RXQ_FLAG_NONE 0x0 2511 #define EFX_RXQ_FLAG_SCATTER 0x1 2512 /* 2513 * If tunnels are supported and Rx event can provide information about 2514 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2515 * full-feature firmware variant running), outer classes are requested by 2516 * default. However, if the driver supports tunnels, the flag allows to 2517 * request inner classes which are required to be able to interpret inner 2518 * Rx checksum offload results. 2519 */ 2520 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2521 2522 extern __checkReturn efx_rc_t 2523 efx_rx_qcreate( 2524 __in efx_nic_t *enp, 2525 __in unsigned int index, 2526 __in unsigned int label, 2527 __in efx_rxq_type_t type, 2528 __in efsys_mem_t *esmp, 2529 __in size_t ndescs, 2530 __in uint32_t id, 2531 __in unsigned int flags, 2532 __in efx_evq_t *eep, 2533 __deref_out efx_rxq_t **erpp); 2534 2535 #if EFSYS_OPT_RX_PACKED_STREAM 2536 2537 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2538 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2539 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2540 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2541 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2542 2543 extern __checkReturn efx_rc_t 2544 efx_rx_qcreate_packed_stream( 2545 __in efx_nic_t *enp, 2546 __in unsigned int index, 2547 __in unsigned int label, 2548 __in uint32_t ps_buf_size, 2549 __in efsys_mem_t *esmp, 2550 __in size_t ndescs, 2551 __in efx_evq_t *eep, 2552 __deref_out efx_rxq_t **erpp); 2553 2554 #endif 2555 2556 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 2557 2558 /* Maximum head-of-line block timeout in nanoseconds */ 2559 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 2560 2561 extern __checkReturn efx_rc_t 2562 efx_rx_qcreate_es_super_buffer( 2563 __in efx_nic_t *enp, 2564 __in unsigned int index, 2565 __in unsigned int label, 2566 __in uint32_t n_bufs_per_desc, 2567 __in uint32_t max_dma_len, 2568 __in uint32_t buf_stride, 2569 __in uint32_t hol_block_timeout, 2570 __in efsys_mem_t *esmp, 2571 __in size_t ndescs, 2572 __in unsigned int flags, 2573 __in efx_evq_t *eep, 2574 __deref_out efx_rxq_t **erpp); 2575 2576 #endif 2577 2578 typedef struct efx_buffer_s { 2579 efsys_dma_addr_t eb_addr; 2580 size_t eb_size; 2581 boolean_t eb_eop; 2582 } efx_buffer_t; 2583 2584 typedef struct efx_desc_s { 2585 efx_qword_t ed_eq; 2586 } efx_desc_t; 2587 2588 extern void 2589 efx_rx_qpost( 2590 __in efx_rxq_t *erp, 2591 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 2592 __in size_t size, 2593 __in unsigned int ndescs, 2594 __in unsigned int completed, 2595 __in unsigned int added); 2596 2597 extern void 2598 efx_rx_qpush( 2599 __in efx_rxq_t *erp, 2600 __in unsigned int added, 2601 __inout unsigned int *pushedp); 2602 2603 #if EFSYS_OPT_RX_PACKED_STREAM 2604 2605 extern void 2606 efx_rx_qpush_ps_credits( 2607 __in efx_rxq_t *erp); 2608 2609 extern __checkReturn uint8_t * 2610 efx_rx_qps_packet_info( 2611 __in efx_rxq_t *erp, 2612 __in uint8_t *buffer, 2613 __in uint32_t buffer_length, 2614 __in uint32_t current_offset, 2615 __out uint16_t *lengthp, 2616 __out uint32_t *next_offsetp, 2617 __out uint32_t *timestamp); 2618 #endif 2619 2620 extern __checkReturn efx_rc_t 2621 efx_rx_qflush( 2622 __in efx_rxq_t *erp); 2623 2624 extern void 2625 efx_rx_qenable( 2626 __in efx_rxq_t *erp); 2627 2628 extern void 2629 efx_rx_qdestroy( 2630 __in efx_rxq_t *erp); 2631 2632 /* TX */ 2633 2634 typedef struct efx_txq_s efx_txq_t; 2635 2636 #if EFSYS_OPT_QSTATS 2637 2638 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2639 typedef enum efx_tx_qstat_e { 2640 TX_POST, 2641 TX_POST_PIO, 2642 TX_NQSTATS 2643 } efx_tx_qstat_t; 2644 2645 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2646 2647 #endif /* EFSYS_OPT_QSTATS */ 2648 2649 extern __checkReturn efx_rc_t 2650 efx_tx_init( 2651 __in efx_nic_t *enp); 2652 2653 extern void 2654 efx_tx_fini( 2655 __in efx_nic_t *enp); 2656 2657 #define EFX_TXQ_MINNDESCS 512 2658 2659 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2660 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2661 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2662 2663 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2664 2665 #define EFX_TXQ_CKSUM_IPV4 0x0001 2666 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2667 #define EFX_TXQ_FATSOV2 0x0004 2668 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2669 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2670 2671 extern __checkReturn efx_rc_t 2672 efx_tx_qcreate( 2673 __in efx_nic_t *enp, 2674 __in unsigned int index, 2675 __in unsigned int label, 2676 __in efsys_mem_t *esmp, 2677 __in size_t n, 2678 __in uint32_t id, 2679 __in uint16_t flags, 2680 __in efx_evq_t *eep, 2681 __deref_out efx_txq_t **etpp, 2682 __out unsigned int *addedp); 2683 2684 extern __checkReturn efx_rc_t 2685 efx_tx_qpost( 2686 __in efx_txq_t *etp, 2687 __in_ecount(ndescs) efx_buffer_t *eb, 2688 __in unsigned int ndescs, 2689 __in unsigned int completed, 2690 __inout unsigned int *addedp); 2691 2692 extern __checkReturn efx_rc_t 2693 efx_tx_qpace( 2694 __in efx_txq_t *etp, 2695 __in unsigned int ns); 2696 2697 extern void 2698 efx_tx_qpush( 2699 __in efx_txq_t *etp, 2700 __in unsigned int added, 2701 __in unsigned int pushed); 2702 2703 extern __checkReturn efx_rc_t 2704 efx_tx_qflush( 2705 __in efx_txq_t *etp); 2706 2707 extern void 2708 efx_tx_qenable( 2709 __in efx_txq_t *etp); 2710 2711 extern __checkReturn efx_rc_t 2712 efx_tx_qpio_enable( 2713 __in efx_txq_t *etp); 2714 2715 extern void 2716 efx_tx_qpio_disable( 2717 __in efx_txq_t *etp); 2718 2719 extern __checkReturn efx_rc_t 2720 efx_tx_qpio_write( 2721 __in efx_txq_t *etp, 2722 __in_ecount(buf_length) uint8_t *buffer, 2723 __in size_t buf_length, 2724 __in size_t pio_buf_offset); 2725 2726 extern __checkReturn efx_rc_t 2727 efx_tx_qpio_post( 2728 __in efx_txq_t *etp, 2729 __in size_t pkt_length, 2730 __in unsigned int completed, 2731 __inout unsigned int *addedp); 2732 2733 extern __checkReturn efx_rc_t 2734 efx_tx_qdesc_post( 2735 __in efx_txq_t *etp, 2736 __in_ecount(n) efx_desc_t *ed, 2737 __in unsigned int n, 2738 __in unsigned int completed, 2739 __inout unsigned int *addedp); 2740 2741 extern void 2742 efx_tx_qdesc_dma_create( 2743 __in efx_txq_t *etp, 2744 __in efsys_dma_addr_t addr, 2745 __in size_t size, 2746 __in boolean_t eop, 2747 __out efx_desc_t *edp); 2748 2749 extern void 2750 efx_tx_qdesc_tso_create( 2751 __in efx_txq_t *etp, 2752 __in uint16_t ipv4_id, 2753 __in uint32_t tcp_seq, 2754 __in uint8_t tcp_flags, 2755 __out efx_desc_t *edp); 2756 2757 /* Number of FATSOv2 option descriptors */ 2758 #define EFX_TX_FATSOV2_OPT_NDESCS 2 2759 2760 /* Maximum number of DMA segments per TSO packet (not superframe) */ 2761 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2762 2763 extern void 2764 efx_tx_qdesc_tso2_create( 2765 __in efx_txq_t *etp, 2766 __in uint16_t ipv4_id, 2767 __in uint16_t outer_ipv4_id, 2768 __in uint32_t tcp_seq, 2769 __in uint16_t tcp_mss, 2770 __out_ecount(count) efx_desc_t *edp, 2771 __in int count); 2772 2773 extern void 2774 efx_tx_qdesc_vlantci_create( 2775 __in efx_txq_t *etp, 2776 __in uint16_t tci, 2777 __out efx_desc_t *edp); 2778 2779 extern void 2780 efx_tx_qdesc_checksum_create( 2781 __in efx_txq_t *etp, 2782 __in uint16_t flags, 2783 __out efx_desc_t *edp); 2784 2785 #if EFSYS_OPT_QSTATS 2786 2787 #if EFSYS_OPT_NAMES 2788 2789 extern const char * 2790 efx_tx_qstat_name( 2791 __in efx_nic_t *etp, 2792 __in unsigned int id); 2793 2794 #endif /* EFSYS_OPT_NAMES */ 2795 2796 extern void 2797 efx_tx_qstats_update( 2798 __in efx_txq_t *etp, 2799 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2800 2801 #endif /* EFSYS_OPT_QSTATS */ 2802 2803 extern void 2804 efx_tx_qdestroy( 2805 __in efx_txq_t *etp); 2806 2807 2808 /* FILTER */ 2809 2810 #if EFSYS_OPT_FILTER 2811 2812 #define EFX_ETHER_TYPE_IPV4 0x0800 2813 #define EFX_ETHER_TYPE_IPV6 0x86DD 2814 2815 #define EFX_IPPROTO_TCP 6 2816 #define EFX_IPPROTO_UDP 17 2817 #define EFX_IPPROTO_GRE 47 2818 2819 /* Use RSS to spread across multiple queues */ 2820 #define EFX_FILTER_FLAG_RX_RSS 0x01 2821 /* Enable RX scatter */ 2822 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 2823 /* 2824 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2825 * May only be set by the filter implementation for each type. 2826 * A removal request will restore the automatic filter in its place. 2827 */ 2828 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2829 /* Filter is for RX */ 2830 #define EFX_FILTER_FLAG_RX 0x08 2831 /* Filter is for TX */ 2832 #define EFX_FILTER_FLAG_TX 0x10 2833 /* Set match flag on the received packet */ 2834 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 2835 /* Set match mark on the received packet */ 2836 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 2837 2838 typedef uint8_t efx_filter_flags_t; 2839 2840 /* 2841 * Flags which specify the fields to match on. The values are the same as in the 2842 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 2843 */ 2844 2845 /* Match by remote IP host address */ 2846 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 2847 /* Match by local IP host address */ 2848 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 2849 /* Match by remote MAC address */ 2850 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 2851 /* Match by remote TCP/UDP port */ 2852 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 2853 /* Match by remote TCP/UDP port */ 2854 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 2855 /* Match by local TCP/UDP port */ 2856 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 2857 /* Match by Ether-type */ 2858 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 2859 /* Match by inner VLAN ID */ 2860 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 2861 /* Match by outer VLAN ID */ 2862 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 2863 /* Match by IP transport protocol */ 2864 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 2865 /* Match by VNI or VSID */ 2866 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 2867 /* For encapsulated packets, match by inner frame local MAC address */ 2868 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 2869 /* For encapsulated packets, match all multicast inner frames */ 2870 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 2871 /* For encapsulated packets, match all unicast inner frames */ 2872 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 2873 /* 2874 * Match by encap type, this flag does not correspond to 2875 * the MCDI match flags and any unoccupied value may be used 2876 */ 2877 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 2878 /* Match otherwise-unmatched multicast and broadcast packets */ 2879 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 2880 /* Match otherwise-unmatched unicast packets */ 2881 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 2882 2883 typedef uint32_t efx_filter_match_flags_t; 2884 2885 typedef enum efx_filter_priority_s { 2886 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2887 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2888 * address list or hardware 2889 * requirements. This may only be used 2890 * by the filter implementation for 2891 * each NIC type. */ 2892 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2893 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2894 * client (e.g. SR-IOV, HyperV VMQ etc.) 2895 */ 2896 } efx_filter_priority_t; 2897 2898 /* 2899 * FIXME: All these fields are assumed to be in little-endian byte order. 2900 * It may be better for some to be big-endian. See bug42804. 2901 */ 2902 2903 typedef struct efx_filter_spec_s { 2904 efx_filter_match_flags_t efs_match_flags; 2905 uint8_t efs_priority; 2906 efx_filter_flags_t efs_flags; 2907 uint16_t efs_dmaq_id; 2908 uint32_t efs_rss_context; 2909 uint32_t efs_mark; 2910 /* Fields below here are hashed for software filter lookup */ 2911 uint16_t efs_outer_vid; 2912 uint16_t efs_inner_vid; 2913 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2914 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2915 uint16_t efs_ether_type; 2916 uint8_t efs_ip_proto; 2917 efx_tunnel_protocol_t efs_encap_type; 2918 uint16_t efs_loc_port; 2919 uint16_t efs_rem_port; 2920 efx_oword_t efs_rem_host; 2921 efx_oword_t efs_loc_host; 2922 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 2923 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 2924 } efx_filter_spec_t; 2925 2926 2927 /* Default values for use in filter specifications */ 2928 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2929 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2930 2931 extern __checkReturn efx_rc_t 2932 efx_filter_init( 2933 __in efx_nic_t *enp); 2934 2935 extern void 2936 efx_filter_fini( 2937 __in efx_nic_t *enp); 2938 2939 extern __checkReturn efx_rc_t 2940 efx_filter_insert( 2941 __in efx_nic_t *enp, 2942 __inout efx_filter_spec_t *spec); 2943 2944 extern __checkReturn efx_rc_t 2945 efx_filter_remove( 2946 __in efx_nic_t *enp, 2947 __inout efx_filter_spec_t *spec); 2948 2949 extern __checkReturn efx_rc_t 2950 efx_filter_restore( 2951 __in efx_nic_t *enp); 2952 2953 extern __checkReturn efx_rc_t 2954 efx_filter_supported_filters( 2955 __in efx_nic_t *enp, 2956 __out_ecount(buffer_length) uint32_t *buffer, 2957 __in size_t buffer_length, 2958 __out size_t *list_lengthp); 2959 2960 extern void 2961 efx_filter_spec_init_rx( 2962 __out efx_filter_spec_t *spec, 2963 __in efx_filter_priority_t priority, 2964 __in efx_filter_flags_t flags, 2965 __in efx_rxq_t *erp); 2966 2967 extern void 2968 efx_filter_spec_init_tx( 2969 __out efx_filter_spec_t *spec, 2970 __in efx_txq_t *etp); 2971 2972 extern __checkReturn efx_rc_t 2973 efx_filter_spec_set_ipv4_local( 2974 __inout efx_filter_spec_t *spec, 2975 __in uint8_t proto, 2976 __in uint32_t host, 2977 __in uint16_t port); 2978 2979 extern __checkReturn efx_rc_t 2980 efx_filter_spec_set_ipv4_full( 2981 __inout efx_filter_spec_t *spec, 2982 __in uint8_t proto, 2983 __in uint32_t lhost, 2984 __in uint16_t lport, 2985 __in uint32_t rhost, 2986 __in uint16_t rport); 2987 2988 extern __checkReturn efx_rc_t 2989 efx_filter_spec_set_eth_local( 2990 __inout efx_filter_spec_t *spec, 2991 __in uint16_t vid, 2992 __in const uint8_t *addr); 2993 2994 extern void 2995 efx_filter_spec_set_ether_type( 2996 __inout efx_filter_spec_t *spec, 2997 __in uint16_t ether_type); 2998 2999 extern __checkReturn efx_rc_t 3000 efx_filter_spec_set_uc_def( 3001 __inout efx_filter_spec_t *spec); 3002 3003 extern __checkReturn efx_rc_t 3004 efx_filter_spec_set_mc_def( 3005 __inout efx_filter_spec_t *spec); 3006 3007 typedef enum efx_filter_inner_frame_match_e { 3008 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3009 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3010 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3011 } efx_filter_inner_frame_match_t; 3012 3013 extern __checkReturn efx_rc_t 3014 efx_filter_spec_set_encap_type( 3015 __inout efx_filter_spec_t *spec, 3016 __in efx_tunnel_protocol_t encap_type, 3017 __in efx_filter_inner_frame_match_t inner_frame_match); 3018 3019 extern __checkReturn efx_rc_t 3020 efx_filter_spec_set_vxlan( 3021 __inout efx_filter_spec_t *spec, 3022 __in const uint8_t *vni, 3023 __in const uint8_t *inner_addr, 3024 __in const uint8_t *outer_addr); 3025 3026 extern __checkReturn efx_rc_t 3027 efx_filter_spec_set_geneve( 3028 __inout efx_filter_spec_t *spec, 3029 __in const uint8_t *vni, 3030 __in const uint8_t *inner_addr, 3031 __in const uint8_t *outer_addr); 3032 3033 extern __checkReturn efx_rc_t 3034 efx_filter_spec_set_nvgre( 3035 __inout efx_filter_spec_t *spec, 3036 __in const uint8_t *vsid, 3037 __in const uint8_t *inner_addr, 3038 __in const uint8_t *outer_addr); 3039 3040 #if EFSYS_OPT_RX_SCALE 3041 extern __checkReturn efx_rc_t 3042 efx_filter_spec_set_rss_context( 3043 __inout efx_filter_spec_t *spec, 3044 __in uint32_t rss_context); 3045 #endif 3046 #endif /* EFSYS_OPT_FILTER */ 3047 3048 /* HASH */ 3049 3050 extern __checkReturn uint32_t 3051 efx_hash_dwords( 3052 __in_ecount(count) uint32_t const *input, 3053 __in size_t count, 3054 __in uint32_t init); 3055 3056 extern __checkReturn uint32_t 3057 efx_hash_bytes( 3058 __in_ecount(length) uint8_t const *input, 3059 __in size_t length, 3060 __in uint32_t init); 3061 3062 #if EFSYS_OPT_LICENSING 3063 3064 /* LICENSING */ 3065 3066 typedef struct efx_key_stats_s { 3067 uint32_t eks_valid; 3068 uint32_t eks_invalid; 3069 uint32_t eks_blacklisted; 3070 uint32_t eks_unverifiable; 3071 uint32_t eks_wrong_node; 3072 uint32_t eks_licensed_apps_lo; 3073 uint32_t eks_licensed_apps_hi; 3074 uint32_t eks_licensed_features_lo; 3075 uint32_t eks_licensed_features_hi; 3076 } efx_key_stats_t; 3077 3078 extern __checkReturn efx_rc_t 3079 efx_lic_init( 3080 __in efx_nic_t *enp); 3081 3082 extern void 3083 efx_lic_fini( 3084 __in efx_nic_t *enp); 3085 3086 extern __checkReturn boolean_t 3087 efx_lic_check_support( 3088 __in efx_nic_t *enp); 3089 3090 extern __checkReturn efx_rc_t 3091 efx_lic_update_licenses( 3092 __in efx_nic_t *enp); 3093 3094 extern __checkReturn efx_rc_t 3095 efx_lic_get_key_stats( 3096 __in efx_nic_t *enp, 3097 __out efx_key_stats_t *ksp); 3098 3099 extern __checkReturn efx_rc_t 3100 efx_lic_app_state( 3101 __in efx_nic_t *enp, 3102 __in uint64_t app_id, 3103 __out boolean_t *licensedp); 3104 3105 extern __checkReturn efx_rc_t 3106 efx_lic_get_id( 3107 __in efx_nic_t *enp, 3108 __in size_t buffer_size, 3109 __out uint32_t *typep, 3110 __out size_t *lengthp, 3111 __out_opt uint8_t *bufferp); 3112 3113 3114 extern __checkReturn efx_rc_t 3115 efx_lic_find_start( 3116 __in efx_nic_t *enp, 3117 __in_bcount(buffer_size) 3118 caddr_t bufferp, 3119 __in size_t buffer_size, 3120 __out uint32_t *startp); 3121 3122 extern __checkReturn efx_rc_t 3123 efx_lic_find_end( 3124 __in efx_nic_t *enp, 3125 __in_bcount(buffer_size) 3126 caddr_t bufferp, 3127 __in size_t buffer_size, 3128 __in uint32_t offset, 3129 __out uint32_t *endp); 3130 3131 extern __checkReturn __success(return != B_FALSE) boolean_t 3132 efx_lic_find_key( 3133 __in efx_nic_t *enp, 3134 __in_bcount(buffer_size) 3135 caddr_t bufferp, 3136 __in size_t buffer_size, 3137 __in uint32_t offset, 3138 __out uint32_t *startp, 3139 __out uint32_t *lengthp); 3140 3141 extern __checkReturn __success(return != B_FALSE) boolean_t 3142 efx_lic_validate_key( 3143 __in efx_nic_t *enp, 3144 __in_bcount(length) caddr_t keyp, 3145 __in uint32_t length); 3146 3147 extern __checkReturn efx_rc_t 3148 efx_lic_read_key( 3149 __in efx_nic_t *enp, 3150 __in_bcount(buffer_size) 3151 caddr_t bufferp, 3152 __in size_t buffer_size, 3153 __in uint32_t offset, 3154 __in uint32_t length, 3155 __out_bcount_part(key_max_size, *lengthp) 3156 caddr_t keyp, 3157 __in size_t key_max_size, 3158 __out uint32_t *lengthp); 3159 3160 extern __checkReturn efx_rc_t 3161 efx_lic_write_key( 3162 __in efx_nic_t *enp, 3163 __in_bcount(buffer_size) 3164 caddr_t bufferp, 3165 __in size_t buffer_size, 3166 __in uint32_t offset, 3167 __in_bcount(length) caddr_t keyp, 3168 __in uint32_t length, 3169 __out uint32_t *lengthp); 3170 3171 __checkReturn efx_rc_t 3172 efx_lic_delete_key( 3173 __in efx_nic_t *enp, 3174 __in_bcount(buffer_size) 3175 caddr_t bufferp, 3176 __in size_t buffer_size, 3177 __in uint32_t offset, 3178 __in uint32_t length, 3179 __in uint32_t end, 3180 __out uint32_t *deltap); 3181 3182 extern __checkReturn efx_rc_t 3183 efx_lic_create_partition( 3184 __in efx_nic_t *enp, 3185 __in_bcount(buffer_size) 3186 caddr_t bufferp, 3187 __in size_t buffer_size); 3188 3189 extern __checkReturn efx_rc_t 3190 efx_lic_finish_partition( 3191 __in efx_nic_t *enp, 3192 __in_bcount(buffer_size) 3193 caddr_t bufferp, 3194 __in size_t buffer_size); 3195 3196 #endif /* EFSYS_OPT_LICENSING */ 3197 3198 /* TUNNEL */ 3199 3200 #if EFSYS_OPT_TUNNEL 3201 3202 extern __checkReturn efx_rc_t 3203 efx_tunnel_init( 3204 __in efx_nic_t *enp); 3205 3206 extern void 3207 efx_tunnel_fini( 3208 __in efx_nic_t *enp); 3209 3210 /* 3211 * For overlay network encapsulation using UDP, the firmware needs to know 3212 * the configured UDP port for the overlay so it can decode encapsulated 3213 * frames correctly. 3214 * The UDP port/protocol list is global. 3215 */ 3216 3217 extern __checkReturn efx_rc_t 3218 efx_tunnel_config_udp_add( 3219 __in efx_nic_t *enp, 3220 __in uint16_t port /* host/cpu-endian */, 3221 __in efx_tunnel_protocol_t protocol); 3222 3223 extern __checkReturn efx_rc_t 3224 efx_tunnel_config_udp_remove( 3225 __in efx_nic_t *enp, 3226 __in uint16_t port /* host/cpu-endian */, 3227 __in efx_tunnel_protocol_t protocol); 3228 3229 extern void 3230 efx_tunnel_config_clear( 3231 __in efx_nic_t *enp); 3232 3233 /** 3234 * Apply tunnel UDP ports configuration to hardware. 3235 * 3236 * EAGAIN is returned if hardware will be reset (datapath and management CPU 3237 * reboot). 3238 */ 3239 extern __checkReturn efx_rc_t 3240 efx_tunnel_reconfigure( 3241 __in efx_nic_t *enp); 3242 3243 #endif /* EFSYS_OPT_TUNNEL */ 3244 3245 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3246 3247 /** 3248 * Firmware subvariant choice options. 3249 * 3250 * It may be switched to no Tx checksum if attached drivers are either 3251 * preboot or firmware subvariant aware and no VIS are allocated. 3252 * If may be always switched to default explicitly using set request or 3253 * implicitly if unaware driver is attaching. If switching is done when 3254 * a driver is attached, it gets MC_REBOOT event and should recreate its 3255 * datapath. 3256 * 3257 * See SF-119419-TC DPDK Firmware Driver Interface and 3258 * SF-109306-TC EF10 for Driver Writers for details. 3259 */ 3260 typedef enum efx_nic_fw_subvariant_e { 3261 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3262 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3263 EFX_NIC_FW_SUBVARIANT_NTYPES 3264 } efx_nic_fw_subvariant_t; 3265 3266 extern __checkReturn efx_rc_t 3267 efx_nic_get_fw_subvariant( 3268 __in efx_nic_t *enp, 3269 __out efx_nic_fw_subvariant_t *subvariantp); 3270 3271 extern __checkReturn efx_rc_t 3272 efx_nic_set_fw_subvariant( 3273 __in efx_nic_t *enp, 3274 __in efx_nic_fw_subvariant_t subvariant); 3275 3276 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3277 3278 typedef enum efx_phy_fec_type_e { 3279 EFX_PHY_FEC_NONE = 0, 3280 EFX_PHY_FEC_BASER, 3281 EFX_PHY_FEC_RS 3282 } efx_phy_fec_type_t; 3283 3284 extern __checkReturn efx_rc_t 3285 efx_phy_fec_type_get( 3286 __in efx_nic_t *enp, 3287 __out efx_phy_fec_type_t *typep); 3288 3289 typedef struct efx_phy_link_state_s { 3290 uint32_t epls_adv_cap_mask; 3291 uint32_t epls_lp_cap_mask; 3292 uint32_t epls_ld_cap_mask; 3293 unsigned int epls_fcntl; 3294 efx_phy_fec_type_t epls_fec; 3295 efx_link_mode_t epls_link_mode; 3296 } efx_phy_link_state_t; 3297 3298 extern __checkReturn efx_rc_t 3299 efx_phy_link_state_get( 3300 __in efx_nic_t *enp, 3301 __out efx_phy_link_state_t *eplsp); 3302 3303 3304 #ifdef __cplusplus 3305 } 3306 #endif 3307 3308 #endif /* _SYS_EFX_H */ 3309