1 /*- 2 * Copyright 2006-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SYS_EFX_H 29 #define _SYS_EFX_H 30 31 #include "efsys.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1])) 38 39 #define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0])) 40 41 #ifndef EFSYS_MEM_IS_NULL 42 #define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL) 43 #endif 44 45 typedef enum efx_family_e { 46 EFX_FAMILY_INVALID, 47 EFX_FAMILY_FALCON, 48 EFX_FAMILY_SIENA, 49 EFX_FAMILY_NTYPES 50 } efx_family_t; 51 52 extern __checkReturn int 53 efx_family( 54 __in uint16_t venid, 55 __in uint16_t devid, 56 __out efx_family_t *efp); 57 58 extern __checkReturn int 59 efx_infer_family( 60 __in efsys_bar_t *esbp, 61 __out efx_family_t *efp); 62 63 #define EFX_PCI_VENID_SFC 0x1924 64 #define EFX_PCI_DEVID_FALCON 0x0710 65 #define EFX_PCI_DEVID_BETHPAGE 0x0803 66 #define EFX_PCI_DEVID_SIENA 0x0813 67 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 68 69 #define EFX_MEM_BAR 2 70 71 /* Error codes */ 72 73 enum { 74 EFX_ERR_INVALID, 75 EFX_ERR_SRAM_OOB, 76 EFX_ERR_BUFID_DC_OOB, 77 EFX_ERR_MEM_PERR, 78 EFX_ERR_RBUF_OWN, 79 EFX_ERR_TBUF_OWN, 80 EFX_ERR_RDESQ_OWN, 81 EFX_ERR_TDESQ_OWN, 82 EFX_ERR_EVQ_OWN, 83 EFX_ERR_EVFF_OFLO, 84 EFX_ERR_ILL_ADDR, 85 EFX_ERR_SRAM_PERR, 86 EFX_ERR_NCODES 87 }; 88 89 /* NIC */ 90 91 typedef struct efx_nic_s efx_nic_t; 92 93 extern __checkReturn int 94 efx_nic_create( 95 __in efx_family_t family, 96 __in efsys_identifier_t *esip, 97 __in efsys_bar_t *esbp, 98 __in efsys_lock_t *eslp, 99 __deref_out efx_nic_t **enpp); 100 101 extern __checkReturn int 102 efx_nic_probe( 103 __in efx_nic_t *enp); 104 105 #if EFSYS_OPT_PCIE_TUNE 106 107 extern __checkReturn int 108 efx_nic_pcie_tune( 109 __in efx_nic_t *enp, 110 unsigned int nlanes); 111 112 extern __checkReturn int 113 efx_nic_pcie_extended_sync( 114 __in efx_nic_t *enp); 115 116 #endif /* EFSYS_OPT_PCIE_TUNE */ 117 118 extern __checkReturn int 119 efx_nic_init( 120 __in efx_nic_t *enp); 121 122 extern __checkReturn int 123 efx_nic_reset( 124 __in efx_nic_t *enp); 125 126 #if EFSYS_OPT_DIAG 127 128 extern __checkReturn int 129 efx_nic_register_test( 130 __in efx_nic_t *enp); 131 132 #endif /* EFSYS_OPT_DIAG */ 133 134 extern void 135 efx_nic_fini( 136 __in efx_nic_t *enp); 137 138 extern void 139 efx_nic_unprobe( 140 __in efx_nic_t *enp); 141 142 extern void 143 efx_nic_destroy( 144 __in efx_nic_t *enp); 145 146 #if EFSYS_OPT_MCDI 147 148 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 149 150 typedef enum efx_mcdi_exception_e { 151 EFX_MCDI_EXCEPTION_MC_REBOOT, 152 EFX_MCDI_EXCEPTION_MC_BADASSERT, 153 } efx_mcdi_exception_t; 154 155 typedef struct efx_mcdi_transport_s { 156 void *emt_context; 157 void (*emt_execute)(void *, efx_mcdi_req_t *); 158 void (*emt_ev_cpl)(void *); 159 void (*emt_exception)(void *, efx_mcdi_exception_t); 160 } efx_mcdi_transport_t; 161 162 extern __checkReturn int 163 efx_mcdi_init( 164 __in efx_nic_t *enp, 165 __in const efx_mcdi_transport_t *mtp); 166 167 extern __checkReturn int 168 efx_mcdi_reboot( 169 __in efx_nic_t *enp); 170 171 extern void 172 efx_mcdi_request_start( 173 __in efx_nic_t *enp, 174 __in efx_mcdi_req_t *emrp, 175 __in boolean_t ev_cpl); 176 177 extern __checkReturn boolean_t 178 efx_mcdi_request_poll( 179 __in efx_nic_t *enp); 180 181 extern __checkReturn boolean_t 182 efx_mcdi_request_abort( 183 __in efx_nic_t *enp); 184 185 extern void 186 efx_mcdi_fini( 187 __in efx_nic_t *enp); 188 189 #endif /* EFSYS_OPT_MCDI */ 190 191 /* INTR */ 192 193 #define EFX_NINTR_FALCON 64 194 #define EFX_NINTR_SIENA 1024 195 196 typedef enum efx_intr_type_e { 197 EFX_INTR_INVALID = 0, 198 EFX_INTR_LINE, 199 EFX_INTR_MESSAGE, 200 EFX_INTR_NTYPES 201 } efx_intr_type_t; 202 203 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 204 205 extern __checkReturn int 206 efx_intr_init( 207 __in efx_nic_t *enp, 208 __in efx_intr_type_t type, 209 __in efsys_mem_t *esmp); 210 211 extern void 212 efx_intr_enable( 213 __in efx_nic_t *enp); 214 215 extern void 216 efx_intr_disable( 217 __in efx_nic_t *enp); 218 219 extern void 220 efx_intr_disable_unlocked( 221 __in efx_nic_t *enp); 222 223 #define EFX_INTR_NEVQS 32 224 225 extern __checkReturn int 226 efx_intr_trigger( 227 __in efx_nic_t *enp, 228 __in unsigned int level); 229 230 extern void 231 efx_intr_status_line( 232 __in efx_nic_t *enp, 233 __out boolean_t *fatalp, 234 __out uint32_t *maskp); 235 236 extern void 237 efx_intr_status_message( 238 __in efx_nic_t *enp, 239 __in unsigned int message, 240 __out boolean_t *fatalp); 241 242 extern void 243 efx_intr_fatal( 244 __in efx_nic_t *enp); 245 246 extern void 247 efx_intr_fini( 248 __in efx_nic_t *enp); 249 250 /* MAC */ 251 252 #if EFSYS_OPT_MAC_STATS 253 254 /* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */ 255 typedef enum efx_mac_stat_e { 256 EFX_MAC_RX_OCTETS, 257 EFX_MAC_RX_PKTS, 258 EFX_MAC_RX_UNICST_PKTS, 259 EFX_MAC_RX_MULTICST_PKTS, 260 EFX_MAC_RX_BRDCST_PKTS, 261 EFX_MAC_RX_PAUSE_PKTS, 262 EFX_MAC_RX_LE_64_PKTS, 263 EFX_MAC_RX_65_TO_127_PKTS, 264 EFX_MAC_RX_128_TO_255_PKTS, 265 EFX_MAC_RX_256_TO_511_PKTS, 266 EFX_MAC_RX_512_TO_1023_PKTS, 267 EFX_MAC_RX_1024_TO_15XX_PKTS, 268 EFX_MAC_RX_GE_15XX_PKTS, 269 EFX_MAC_RX_ERRORS, 270 EFX_MAC_RX_FCS_ERRORS, 271 EFX_MAC_RX_DROP_EVENTS, 272 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 273 EFX_MAC_RX_SYMBOL_ERRORS, 274 EFX_MAC_RX_ALIGN_ERRORS, 275 EFX_MAC_RX_INTERNAL_ERRORS, 276 EFX_MAC_RX_JABBER_PKTS, 277 EFX_MAC_RX_LANE0_CHAR_ERR, 278 EFX_MAC_RX_LANE1_CHAR_ERR, 279 EFX_MAC_RX_LANE2_CHAR_ERR, 280 EFX_MAC_RX_LANE3_CHAR_ERR, 281 EFX_MAC_RX_LANE0_DISP_ERR, 282 EFX_MAC_RX_LANE1_DISP_ERR, 283 EFX_MAC_RX_LANE2_DISP_ERR, 284 EFX_MAC_RX_LANE3_DISP_ERR, 285 EFX_MAC_RX_MATCH_FAULT, 286 EFX_MAC_RX_NODESC_DROP_CNT, 287 EFX_MAC_TX_OCTETS, 288 EFX_MAC_TX_PKTS, 289 EFX_MAC_TX_UNICST_PKTS, 290 EFX_MAC_TX_MULTICST_PKTS, 291 EFX_MAC_TX_BRDCST_PKTS, 292 EFX_MAC_TX_PAUSE_PKTS, 293 EFX_MAC_TX_LE_64_PKTS, 294 EFX_MAC_TX_65_TO_127_PKTS, 295 EFX_MAC_TX_128_TO_255_PKTS, 296 EFX_MAC_TX_256_TO_511_PKTS, 297 EFX_MAC_TX_512_TO_1023_PKTS, 298 EFX_MAC_TX_1024_TO_15XX_PKTS, 299 EFX_MAC_TX_GE_15XX_PKTS, 300 EFX_MAC_TX_ERRORS, 301 EFX_MAC_TX_SGL_COL_PKTS, 302 EFX_MAC_TX_MULT_COL_PKTS, 303 EFX_MAC_TX_EX_COL_PKTS, 304 EFX_MAC_TX_LATE_COL_PKTS, 305 EFX_MAC_TX_DEF_PKTS, 306 EFX_MAC_TX_EX_DEF_PKTS, 307 EFX_MAC_NSTATS 308 } efx_mac_stat_t; 309 310 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 311 312 #endif /* EFSYS_OPT_MAC_STATS */ 313 314 typedef enum efx_link_mode_e { 315 EFX_LINK_UNKNOWN = 0, 316 EFX_LINK_DOWN, 317 EFX_LINK_10HDX, 318 EFX_LINK_10FDX, 319 EFX_LINK_100HDX, 320 EFX_LINK_100FDX, 321 EFX_LINK_1000HDX, 322 EFX_LINK_1000FDX, 323 EFX_LINK_10000FDX, 324 EFX_LINK_NMODES 325 } efx_link_mode_t; 326 327 #define EFX_MAC_SDU_MAX 9202 328 329 #define EFX_MAC_PDU(_sdu) \ 330 P2ROUNDUP(((_sdu) \ 331 + /* EtherII */ 14 \ 332 + /* VLAN */ 4 \ 333 + /* CRC */ 4 \ 334 + /* bug16011 */ 16), \ 335 (1 << 3)) 336 337 #define EFX_MAC_PDU_MIN 60 338 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 339 340 extern __checkReturn int 341 efx_mac_pdu_set( 342 __in efx_nic_t *enp, 343 __in size_t pdu); 344 345 extern __checkReturn int 346 efx_mac_addr_set( 347 __in efx_nic_t *enp, 348 __in uint8_t *addr); 349 350 extern __checkReturn int 351 efx_mac_filter_set( 352 __in efx_nic_t *enp, 353 __in boolean_t unicst, 354 __in boolean_t brdcst); 355 356 extern __checkReturn int 357 efx_mac_drain( 358 __in efx_nic_t *enp, 359 __in boolean_t enabled); 360 361 extern __checkReturn int 362 efx_mac_up( 363 __in efx_nic_t *enp, 364 __out boolean_t *mac_upp); 365 366 #define EFX_FCNTL_RESPOND 0x00000001 367 #define EFX_FCNTL_GENERATE 0x00000002 368 369 extern __checkReturn int 370 efx_mac_fcntl_set( 371 __in efx_nic_t *enp, 372 __in unsigned int fcntl, 373 __in boolean_t autoneg); 374 375 extern void 376 efx_mac_fcntl_get( 377 __in efx_nic_t *enp, 378 __out unsigned int *fcntl_wantedp, 379 __out unsigned int *fcntl_linkp); 380 381 #define EFX_MAC_HASH_BITS (1 << 8) 382 383 extern __checkReturn int 384 efx_mac_hash_set( 385 __in efx_nic_t *enp, 386 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); 387 388 #if EFSYS_OPT_MAC_STATS 389 390 #if EFSYS_OPT_NAMES 391 392 extern __checkReturn const char __cs * 393 efx_mac_stat_name( 394 __in efx_nic_t *enp, 395 __in unsigned int id); 396 397 #endif /* EFSYS_OPT_NAMES */ 398 399 #define EFX_MAC_STATS_SIZE 0x400 400 401 /* 402 * Upload mac statistics supported by the hardware into the given buffer. 403 * 404 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 405 * and page aligned. 406 * 407 * The hardware will only DMA statistics that it understands (of course). 408 * Drivers should not make any assumptions about which statistics are 409 * supported, especially when the statistics are generated by firmware. 410 * 411 * Thus, drivers should zero this buffer before use, so that not-understood 412 * statistics read back as zero. 413 */ 414 extern __checkReturn int 415 efx_mac_stats_upload( 416 __in efx_nic_t *enp, 417 __in efsys_mem_t *esmp); 418 419 extern __checkReturn int 420 efx_mac_stats_periodic( 421 __in efx_nic_t *enp, 422 __in efsys_mem_t *esmp, 423 __in uint16_t period_ms, 424 __in boolean_t events); 425 426 extern __checkReturn int 427 efx_mac_stats_update( 428 __in efx_nic_t *enp, 429 __in efsys_mem_t *esmp, 430 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 431 __out_opt uint32_t *generationp); 432 433 #endif /* EFSYS_OPT_MAC_STATS */ 434 435 /* MON */ 436 437 typedef enum efx_mon_type_e { 438 EFX_MON_INVALID = 0, 439 EFX_MON_NULL, 440 EFX_MON_LM87, 441 EFX_MON_MAX6647, 442 EFX_MON_SFC90X0, 443 EFX_MON_NTYPES 444 } efx_mon_type_t; 445 446 #if EFSYS_OPT_NAMES 447 448 extern const char __cs * 449 efx_mon_name( 450 __in efx_nic_t *enp); 451 452 #endif /* EFSYS_OPT_NAMES */ 453 454 extern __checkReturn int 455 efx_mon_init( 456 __in efx_nic_t *enp); 457 458 #if EFSYS_OPT_MON_STATS 459 460 #define EFX_MON_STATS_SIZE 0x100 461 462 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 58706a378332aeee */ 463 typedef enum efx_mon_stat_e { 464 EFX_MON_STAT_2_5V, 465 EFX_MON_STAT_VCCP1, 466 EFX_MON_STAT_VCC, 467 EFX_MON_STAT_5V, 468 EFX_MON_STAT_12V, 469 EFX_MON_STAT_VCCP2, 470 EFX_MON_STAT_EXT_TEMP, 471 EFX_MON_STAT_INT_TEMP, 472 EFX_MON_STAT_AIN1, 473 EFX_MON_STAT_AIN2, 474 EFX_MON_STAT_INT_COOLING, 475 EFX_MON_STAT_EXT_COOLING, 476 EFX_MON_STAT_1V, 477 EFX_MON_STAT_1_2V, 478 EFX_MON_STAT_1_8V, 479 EFX_MON_STAT_3_3V, 480 EFX_MON_STAT_1_2VA, 481 EFX_MON_STAT_VREF, 482 EFX_MON_STAT_VAOE, 483 EFX_MON_STAT_AOE_TEMP, 484 EFX_MON_STAT_PSU_AOE_TEMP, 485 EFX_MON_STAT_PSU_TEMP, 486 EFX_MON_STAT_FAN0, 487 EFX_MON_STAT_FAN1, 488 EFX_MON_STAT_FAN2, 489 EFX_MON_STAT_FAN3, 490 EFX_MON_STAT_FAN4, 491 EFX_MON_STAT_VAOE_IN, 492 EFX_MON_STAT_IAOE, 493 EFX_MON_STAT_IAOE_IN, 494 EFX_MON_NSTATS 495 } efx_mon_stat_t; 496 497 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 498 499 typedef enum efx_mon_stat_state_e { 500 EFX_MON_STAT_STATE_OK = 0, 501 EFX_MON_STAT_STATE_WARNING = 1, 502 EFX_MON_STAT_STATE_FATAL = 2, 503 EFX_MON_STAT_STATE_BROKEN = 3, 504 } efx_mon_stat_state_t; 505 506 typedef struct efx_mon_stat_value_t { 507 uint16_t emsv_value; 508 uint16_t emsv_state; 509 } efx_mon_stat_value_t; 510 511 #if EFSYS_OPT_NAMES 512 513 extern const char __cs * 514 efx_mon_stat_name( 515 __in efx_nic_t *enp, 516 __in efx_mon_stat_t id); 517 518 #endif /* EFSYS_OPT_NAMES */ 519 520 extern __checkReturn int 521 efx_mon_stats_update( 522 __in efx_nic_t *enp, 523 __in efsys_mem_t *esmp, 524 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 525 526 #endif /* EFSYS_OPT_MON_STATS */ 527 528 extern void 529 efx_mon_fini( 530 __in efx_nic_t *enp); 531 532 /* PHY */ 533 534 #define PMA_PMD_MMD 1 535 #define PCS_MMD 3 536 #define PHY_XS_MMD 4 537 #define DTE_XS_MMD 5 538 #define AN_MMD 7 539 #define CL22EXT_MMD 29 540 541 #define MAXMMD ((1 << 5) - 1) 542 543 /* PHY types */ 544 #define EFX_PHY_NULL 0x0 545 #define EFX_PHY_TXC43128 0x1 546 #define EFX_PHY_SFX7101 0x3 547 #define EFX_PHY_QT2022C2 0x4 548 #define EFX_PHY_SFT9001A 0x8 549 #define EFX_PHY_QT2025C 0x9 550 #define EFX_PHY_SFT9001B 0xa 551 #define EFX_PHY_QLX111V 0xc 552 553 extern __checkReturn int 554 efx_phy_verify( 555 __in efx_nic_t *enp); 556 557 #if EFSYS_OPT_PHY_LED_CONTROL 558 559 typedef enum efx_phy_led_mode_e { 560 EFX_PHY_LED_DEFAULT = 0, 561 EFX_PHY_LED_OFF, 562 EFX_PHY_LED_ON, 563 EFX_PHY_LED_FLASH, 564 EFX_PHY_LED_NMODES 565 } efx_phy_led_mode_t; 566 567 extern __checkReturn int 568 efx_phy_led_set( 569 __in efx_nic_t *enp, 570 __in efx_phy_led_mode_t mode); 571 572 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 573 574 extern __checkReturn int 575 efx_port_init( 576 __in efx_nic_t *enp); 577 578 #if EFSYS_OPT_LOOPBACK 579 580 typedef enum efx_loopback_type_e { 581 EFX_LOOPBACK_OFF = 0, 582 EFX_LOOPBACK_DATA = 1, 583 EFX_LOOPBACK_GMAC = 2, 584 EFX_LOOPBACK_XGMII = 3, 585 EFX_LOOPBACK_XGXS = 4, 586 EFX_LOOPBACK_XAUI = 5, 587 EFX_LOOPBACK_GMII = 6, 588 EFX_LOOPBACK_SGMII = 7, 589 EFX_LOOPBACK_XGBR = 8, 590 EFX_LOOPBACK_XFI = 9, 591 EFX_LOOPBACK_XAUI_FAR = 10, 592 EFX_LOOPBACK_GMII_FAR = 11, 593 EFX_LOOPBACK_SGMII_FAR = 12, 594 EFX_LOOPBACK_XFI_FAR = 13, 595 EFX_LOOPBACK_GPHY = 14, 596 EFX_LOOPBACK_PHY_XS = 15, 597 EFX_LOOPBACK_PCS = 16, 598 EFX_LOOPBACK_PMA_PMD = 17, 599 EFX_LOOPBACK_NTYPES 600 } efx_loopback_type_t; 601 602 #define EFX_LOOPBACK_MAC_MASK \ 603 ((1 << EFX_LOOPBACK_DATA) | \ 604 (1 << EFX_LOOPBACK_GMAC) | \ 605 (1 << EFX_LOOPBACK_XGMII) | \ 606 (1 << EFX_LOOPBACK_XGXS) | \ 607 (1 << EFX_LOOPBACK_XAUI) | \ 608 (1 << EFX_LOOPBACK_GMII) | \ 609 (1 << EFX_LOOPBACK_SGMII) | \ 610 (1 << EFX_LOOPBACK_XGBR) | \ 611 (1 << EFX_LOOPBACK_XFI) | \ 612 (1 << EFX_LOOPBACK_XAUI_FAR) | \ 613 (1 << EFX_LOOPBACK_GMII_FAR) | \ 614 (1 << EFX_LOOPBACK_SGMII_FAR) | \ 615 (1 << EFX_LOOPBACK_XFI_FAR)) 616 617 #define EFX_LOOPBACK_MASK \ 618 ((1 << EFX_LOOPBACK_NTYPES) - 1) 619 620 extern __checkReturn int 621 efx_port_loopback_set( 622 __in efx_nic_t *enp, 623 __in efx_link_mode_t link_mode, 624 __in efx_loopback_type_t type); 625 626 #if EFSYS_OPT_NAMES 627 628 extern __checkReturn const char __cs * 629 efx_loopback_type_name( 630 __in efx_nic_t *enp, 631 __in efx_loopback_type_t type); 632 633 #endif /* EFSYS_OPT_NAMES */ 634 635 #endif /* EFSYS_OPT_LOOPBACK */ 636 637 extern __checkReturn int 638 efx_port_poll( 639 __in efx_nic_t *enp, 640 __out efx_link_mode_t *link_modep); 641 642 extern void 643 efx_port_fini( 644 __in efx_nic_t *enp); 645 646 typedef enum efx_phy_cap_type_e { 647 EFX_PHY_CAP_INVALID = 0, 648 EFX_PHY_CAP_10HDX, 649 EFX_PHY_CAP_10FDX, 650 EFX_PHY_CAP_100HDX, 651 EFX_PHY_CAP_100FDX, 652 EFX_PHY_CAP_1000HDX, 653 EFX_PHY_CAP_1000FDX, 654 EFX_PHY_CAP_10000FDX, 655 EFX_PHY_CAP_PAUSE, 656 EFX_PHY_CAP_ASYM, 657 EFX_PHY_CAP_AN, 658 EFX_PHY_CAP_NTYPES 659 } efx_phy_cap_type_t; 660 661 662 #define EFX_PHY_CAP_CURRENT 0x00000000 663 #define EFX_PHY_CAP_DEFAULT 0x00000001 664 #define EFX_PHY_CAP_PERM 0x00000002 665 666 extern void 667 efx_phy_adv_cap_get( 668 __in efx_nic_t *enp, 669 __in uint32_t flag, 670 __out uint32_t *maskp); 671 672 extern __checkReturn int 673 efx_phy_adv_cap_set( 674 __in efx_nic_t *enp, 675 __in uint32_t mask); 676 677 extern void 678 efx_phy_lp_cap_get( 679 __in efx_nic_t *enp, 680 __out uint32_t *maskp); 681 682 extern __checkReturn int 683 efx_phy_oui_get( 684 __in efx_nic_t *enp, 685 __out uint32_t *ouip); 686 687 typedef enum efx_phy_media_type_e { 688 EFX_PHY_MEDIA_INVALID = 0, 689 EFX_PHY_MEDIA_XAUI, 690 EFX_PHY_MEDIA_CX4, 691 EFX_PHY_MEDIA_KX4, 692 EFX_PHY_MEDIA_XFP, 693 EFX_PHY_MEDIA_SFP_PLUS, 694 EFX_PHY_MEDIA_BASE_T, 695 EFX_PHY_MEDIA_NTYPES 696 } efx_phy_media_type_t; 697 698 /* Get the type of medium currently used. If the board has ports for 699 * modules, a module is present, and we recognise the media type of 700 * the module, then this will be the media type of the module. 701 * Otherwise it will be the media type of the port. 702 */ 703 extern void 704 efx_phy_media_type_get( 705 __in efx_nic_t *enp, 706 __out efx_phy_media_type_t *typep); 707 708 #if EFSYS_OPT_PHY_STATS 709 710 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 711 typedef enum efx_phy_stat_e { 712 EFX_PHY_STAT_OUI, 713 EFX_PHY_STAT_PMA_PMD_LINK_UP, 714 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 715 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 716 EFX_PHY_STAT_PMA_PMD_REV_A, 717 EFX_PHY_STAT_PMA_PMD_REV_B, 718 EFX_PHY_STAT_PMA_PMD_REV_C, 719 EFX_PHY_STAT_PMA_PMD_REV_D, 720 EFX_PHY_STAT_PCS_LINK_UP, 721 EFX_PHY_STAT_PCS_RX_FAULT, 722 EFX_PHY_STAT_PCS_TX_FAULT, 723 EFX_PHY_STAT_PCS_BER, 724 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 725 EFX_PHY_STAT_PHY_XS_LINK_UP, 726 EFX_PHY_STAT_PHY_XS_RX_FAULT, 727 EFX_PHY_STAT_PHY_XS_TX_FAULT, 728 EFX_PHY_STAT_PHY_XS_ALIGN, 729 EFX_PHY_STAT_PHY_XS_SYNC_A, 730 EFX_PHY_STAT_PHY_XS_SYNC_B, 731 EFX_PHY_STAT_PHY_XS_SYNC_C, 732 EFX_PHY_STAT_PHY_XS_SYNC_D, 733 EFX_PHY_STAT_AN_LINK_UP, 734 EFX_PHY_STAT_AN_MASTER, 735 EFX_PHY_STAT_AN_LOCAL_RX_OK, 736 EFX_PHY_STAT_AN_REMOTE_RX_OK, 737 EFX_PHY_STAT_CL22EXT_LINK_UP, 738 EFX_PHY_STAT_SNR_A, 739 EFX_PHY_STAT_SNR_B, 740 EFX_PHY_STAT_SNR_C, 741 EFX_PHY_STAT_SNR_D, 742 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 743 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 744 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 745 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 746 EFX_PHY_STAT_AN_COMPLETE, 747 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 748 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 749 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 750 EFX_PHY_STAT_PCS_FW_VERSION_0, 751 EFX_PHY_STAT_PCS_FW_VERSION_1, 752 EFX_PHY_STAT_PCS_FW_VERSION_2, 753 EFX_PHY_STAT_PCS_FW_VERSION_3, 754 EFX_PHY_STAT_PCS_FW_BUILD_YY, 755 EFX_PHY_STAT_PCS_FW_BUILD_MM, 756 EFX_PHY_STAT_PCS_FW_BUILD_DD, 757 EFX_PHY_STAT_PCS_OP_MODE, 758 EFX_PHY_NSTATS 759 } efx_phy_stat_t; 760 761 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 762 763 #if EFSYS_OPT_NAMES 764 765 extern const char __cs * 766 efx_phy_stat_name( 767 __in efx_nic_t *enp, 768 __in efx_phy_stat_t stat); 769 770 #endif /* EFSYS_OPT_NAMES */ 771 772 #define EFX_PHY_STATS_SIZE 0x100 773 774 extern __checkReturn int 775 efx_phy_stats_update( 776 __in efx_nic_t *enp, 777 __in efsys_mem_t *esmp, 778 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); 779 780 #endif /* EFSYS_OPT_PHY_STATS */ 781 782 #if EFSYS_OPT_PHY_PROPS 783 784 #if EFSYS_OPT_NAMES 785 786 extern const char __cs * 787 efx_phy_prop_name( 788 __in efx_nic_t *enp, 789 __in unsigned int id); 790 791 #endif /* EFSYS_OPT_NAMES */ 792 793 #define EFX_PHY_PROP_DEFAULT 0x00000001 794 795 extern __checkReturn int 796 efx_phy_prop_get( 797 __in efx_nic_t *enp, 798 __in unsigned int id, 799 __in uint32_t flags, 800 __out uint32_t *valp); 801 802 extern __checkReturn int 803 efx_phy_prop_set( 804 __in efx_nic_t *enp, 805 __in unsigned int id, 806 __in uint32_t val); 807 808 #endif /* EFSYS_OPT_PHY_PROPS */ 809 810 #if EFSYS_OPT_PHY_BIST 811 812 typedef enum efx_phy_bist_type_e { 813 EFX_PHY_BIST_TYPE_UNKNOWN, 814 EFX_PHY_BIST_TYPE_NORMAL, 815 EFX_PHY_BIST_TYPE_CABLE_SHORT, 816 EFX_PHY_BIST_TYPE_CABLE_LONG, 817 EFX_PHY_BIST_TYPE_NTYPES, 818 } efx_phy_bist_type_t; 819 820 typedef enum efx_phy_bist_result_e { 821 EFX_PHY_BIST_RESULT_UNKNOWN, 822 EFX_PHY_BIST_RESULT_RUNNING, 823 EFX_PHY_BIST_RESULT_PASSED, 824 EFX_PHY_BIST_RESULT_FAILED, 825 } efx_phy_bist_result_t; 826 827 typedef enum efx_phy_cable_status_e { 828 EFX_PHY_CABLE_STATUS_OK, 829 EFX_PHY_CABLE_STATUS_INVALID, 830 EFX_PHY_CABLE_STATUS_OPEN, 831 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 832 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 833 EFX_PHY_CABLE_STATUS_BUSY, 834 } efx_phy_cable_status_t; 835 836 typedef enum efx_phy_bist_value_e { 837 EFX_PHY_BIST_CABLE_LENGTH_A, 838 EFX_PHY_BIST_CABLE_LENGTH_B, 839 EFX_PHY_BIST_CABLE_LENGTH_C, 840 EFX_PHY_BIST_CABLE_LENGTH_D, 841 EFX_PHY_BIST_CABLE_STATUS_A, 842 EFX_PHY_BIST_CABLE_STATUS_B, 843 EFX_PHY_BIST_CABLE_STATUS_C, 844 EFX_PHY_BIST_CABLE_STATUS_D, 845 EFX_PHY_BIST_FAULT_CODE, 846 EFX_PHY_BIST_NVALUES, 847 } efx_phy_bist_value_t; 848 849 extern __checkReturn int 850 efx_phy_bist_start( 851 __in efx_nic_t *enp, 852 __in efx_phy_bist_type_t type); 853 854 extern __checkReturn int 855 efx_phy_bist_poll( 856 __in efx_nic_t *enp, 857 __in efx_phy_bist_type_t type, 858 __out efx_phy_bist_result_t *resultp, 859 __out_opt uint32_t *value_maskp, 860 __out_ecount_opt(count) unsigned long *valuesp, 861 __in size_t count); 862 863 extern void 864 efx_phy_bist_stop( 865 __in efx_nic_t *enp, 866 __in efx_phy_bist_type_t type); 867 868 #endif /* EFSYS_OPT_PHY_BIST */ 869 870 #define EFX_FEATURE_IPV6 0x00000001 871 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 872 #define EFX_FEATURE_LINK_EVENTS 0x00000004 873 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 874 #define EFX_FEATURE_WOL 0x00000010 875 #define EFX_FEATURE_MCDI 0x00000020 876 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 877 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 878 #define EFX_FEATURE_TURBO 0x00000100 879 880 typedef struct efx_nic_cfg_s { 881 uint32_t enc_board_type; 882 uint32_t enc_phy_type; 883 #if EFSYS_OPT_NAMES 884 char enc_phy_name[21]; 885 #endif 886 char enc_phy_revision[21]; 887 efx_mon_type_t enc_mon_type; 888 #if EFSYS_OPT_MON_STATS 889 uint32_t enc_mon_stat_mask; 890 #endif 891 unsigned int enc_features; 892 uint8_t enc_mac_addr[6]; 893 uint8_t enc_port; 894 uint32_t enc_evq_limit; 895 uint32_t enc_txq_limit; 896 uint32_t enc_rxq_limit; 897 uint32_t enc_buftbl_limit; 898 uint32_t enc_evq_timer_quantum_ns; 899 uint32_t enc_evq_timer_max_us; 900 uint32_t enc_clk_mult; 901 #if EFSYS_OPT_LOOPBACK 902 uint32_t enc_loopback_types[EFX_LINK_NMODES]; 903 #endif /* EFSYS_OPT_LOOPBACK */ 904 #if EFSYS_OPT_PHY_FLAGS 905 uint32_t enc_phy_flags_mask; 906 #endif /* EFSYS_OPT_PHY_FLAGS */ 907 #if EFSYS_OPT_PHY_LED_CONTROL 908 uint32_t enc_led_mask; 909 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 910 #if EFSYS_OPT_PHY_STATS 911 uint64_t enc_phy_stat_mask; 912 #endif /* EFSYS_OPT_PHY_STATS */ 913 #if EFSYS_OPT_PHY_PROPS 914 unsigned int enc_phy_nprops; 915 #endif /* EFSYS_OPT_PHY_PROPS */ 916 #if EFSYS_OPT_SIENA 917 uint8_t enc_siena_channel; 918 #if EFSYS_OPT_PHY_STATS 919 uint32_t enc_siena_phy_stat_mask; 920 #endif /* EFSYS_OPT_PHY_STATS */ 921 #if EFSYS_OPT_MON_STATS 922 uint32_t enc_siena_mon_stat_mask; 923 #endif /* EFSYS_OPT_MON_STATS */ 924 #endif /* EFSYS_OPT_SIENA */ 925 #if EFSYS_OPT_PHY_BIST 926 uint32_t enc_bist_mask; 927 #endif /* EFSYS_OPT_PHY_BIST */ 928 } efx_nic_cfg_t; 929 930 extern const efx_nic_cfg_t * 931 efx_nic_cfg_get( 932 __in efx_nic_t *enp); 933 934 #if EFSYS_OPT_VPD 935 936 typedef enum efx_vpd_tag_e { 937 EFX_VPD_ID = 0x02, 938 EFX_VPD_END = 0x0f, 939 EFX_VPD_RO = 0x10, 940 EFX_VPD_RW = 0x11, 941 } efx_vpd_tag_t; 942 943 typedef uint16_t efx_vpd_keyword_t; 944 945 typedef struct efx_vpd_value_s { 946 efx_vpd_tag_t evv_tag; 947 efx_vpd_keyword_t evv_keyword; 948 uint8_t evv_length; 949 uint8_t evv_value[0x100]; 950 } efx_vpd_value_t; 951 952 953 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 954 955 extern __checkReturn int 956 efx_vpd_init( 957 __in efx_nic_t *enp); 958 959 extern __checkReturn int 960 efx_vpd_size( 961 __in efx_nic_t *enp, 962 __out size_t *sizep); 963 964 extern __checkReturn int 965 efx_vpd_read( 966 __in efx_nic_t *enp, 967 __out_bcount(size) caddr_t data, 968 __in size_t size); 969 970 extern __checkReturn int 971 efx_vpd_verify( 972 __in efx_nic_t *enp, 973 __in_bcount(size) caddr_t data, 974 __in size_t size); 975 976 extern __checkReturn int 977 efx_vpd_reinit( 978 __in efx_nic_t *enp, 979 __in_bcount(size) caddr_t data, 980 __in size_t size); 981 982 extern __checkReturn int 983 efx_vpd_get( 984 __in efx_nic_t *enp, 985 __in_bcount(size) caddr_t data, 986 __in size_t size, 987 __inout efx_vpd_value_t *evvp); 988 989 extern __checkReturn int 990 efx_vpd_set( 991 __in efx_nic_t *enp, 992 __inout_bcount(size) caddr_t data, 993 __in size_t size, 994 __in efx_vpd_value_t *evvp); 995 996 extern __checkReturn int 997 efx_vpd_next( 998 __in efx_nic_t *enp, 999 __inout_bcount(size) caddr_t data, 1000 __in size_t size, 1001 __out efx_vpd_value_t *evvp, 1002 __inout unsigned int *contp); 1003 1004 extern __checkReturn int 1005 efx_vpd_write( 1006 __in efx_nic_t *enp, 1007 __in_bcount(size) caddr_t data, 1008 __in size_t size); 1009 1010 extern void 1011 efx_vpd_fini( 1012 __in efx_nic_t *enp); 1013 1014 #endif /* EFSYS_OPT_VPD */ 1015 1016 /* NVRAM */ 1017 1018 #if EFSYS_OPT_NVRAM 1019 1020 typedef enum efx_nvram_type_e { 1021 EFX_NVRAM_INVALID = 0, 1022 EFX_NVRAM_BOOTROM, 1023 EFX_NVRAM_BOOTROM_CFG, 1024 EFX_NVRAM_MC_FIRMWARE, 1025 EFX_NVRAM_MC_GOLDEN, 1026 EFX_NVRAM_PHY, 1027 EFX_NVRAM_NULLPHY, 1028 EFX_NVRAM_FPGA, 1029 EFX_NVRAM_FCFW, 1030 EFX_NVRAM_CPLD, 1031 EFX_NVRAM_FPGA_BACKUP, 1032 EFX_NVRAM_NTYPES, 1033 } efx_nvram_type_t; 1034 1035 extern __checkReturn int 1036 efx_nvram_init( 1037 __in efx_nic_t *enp); 1038 1039 #if EFSYS_OPT_DIAG 1040 1041 extern __checkReturn int 1042 efx_nvram_test( 1043 __in efx_nic_t *enp); 1044 1045 #endif /* EFSYS_OPT_DIAG */ 1046 1047 extern __checkReturn int 1048 efx_nvram_size( 1049 __in efx_nic_t *enp, 1050 __in efx_nvram_type_t type, 1051 __out size_t *sizep); 1052 1053 extern __checkReturn int 1054 efx_nvram_rw_start( 1055 __in efx_nic_t *enp, 1056 __in efx_nvram_type_t type, 1057 __out_opt size_t *pref_chunkp); 1058 1059 extern void 1060 efx_nvram_rw_finish( 1061 __in efx_nic_t *enp, 1062 __in efx_nvram_type_t type); 1063 1064 extern __checkReturn int 1065 efx_nvram_get_version( 1066 __in efx_nic_t *enp, 1067 __in efx_nvram_type_t type, 1068 __out uint32_t *subtypep, 1069 __out_ecount(4) uint16_t version[4]); 1070 1071 extern __checkReturn int 1072 efx_nvram_read_chunk( 1073 __in efx_nic_t *enp, 1074 __in efx_nvram_type_t type, 1075 __in unsigned int offset, 1076 __out_bcount(size) caddr_t data, 1077 __in size_t size); 1078 1079 extern __checkReturn int 1080 efx_nvram_set_version( 1081 __in efx_nic_t *enp, 1082 __in efx_nvram_type_t type, 1083 __out uint16_t version[4]); 1084 1085 extern __checkReturn int 1086 efx_nvram_erase( 1087 __in efx_nic_t *enp, 1088 __in efx_nvram_type_t type); 1089 1090 extern __checkReturn int 1091 efx_nvram_write_chunk( 1092 __in efx_nic_t *enp, 1093 __in efx_nvram_type_t type, 1094 __in unsigned int offset, 1095 __in_bcount(size) caddr_t data, 1096 __in size_t size); 1097 1098 extern void 1099 efx_nvram_fini( 1100 __in efx_nic_t *enp); 1101 1102 #endif /* EFSYS_OPT_NVRAM */ 1103 1104 #if EFSYS_OPT_BOOTCFG 1105 1106 extern int 1107 efx_bootcfg_read( 1108 __in efx_nic_t *enp, 1109 __out_bcount(size) caddr_t data, 1110 __in size_t size); 1111 1112 extern int 1113 efx_bootcfg_write( 1114 __in efx_nic_t *enp, 1115 __in_bcount(size) caddr_t data, 1116 __in size_t size); 1117 1118 #endif /* EFSYS_OPT_BOOTCFG */ 1119 1120 #if EFSYS_OPT_WOL 1121 1122 typedef enum efx_wol_type_e { 1123 EFX_WOL_TYPE_INVALID, 1124 EFX_WOL_TYPE_MAGIC, 1125 EFX_WOL_TYPE_BITMAP, 1126 EFX_WOL_TYPE_LINK, 1127 EFX_WOL_NTYPES, 1128 } efx_wol_type_t; 1129 1130 typedef enum efx_lightsout_offload_type_e { 1131 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1132 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1133 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1134 } efx_lightsout_offload_type_t; 1135 1136 #define EFX_WOL_BITMAP_MASK_SIZE (48) 1137 #define EFX_WOL_BITMAP_VALUE_SIZE (128) 1138 1139 typedef union efx_wol_param_u { 1140 struct { 1141 uint8_t mac_addr[6]; 1142 } ewp_magic; 1143 struct { 1144 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1145 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1146 uint8_t value_len; 1147 } ewp_bitmap; 1148 } efx_wol_param_t; 1149 1150 typedef union efx_lightsout_offload_param_u { 1151 struct { 1152 uint8_t mac_addr[6]; 1153 uint32_t ip; 1154 } elop_arp; 1155 struct { 1156 uint8_t mac_addr[6]; 1157 uint32_t solicited_node[4]; 1158 uint32_t ip[4]; 1159 } elop_ns; 1160 } efx_lightsout_offload_param_t; 1161 1162 extern __checkReturn int 1163 efx_wol_init( 1164 __in efx_nic_t *enp); 1165 1166 extern __checkReturn int 1167 efx_wol_filter_clear( 1168 __in efx_nic_t *enp); 1169 1170 extern __checkReturn int 1171 efx_wol_filter_add( 1172 __in efx_nic_t *enp, 1173 __in efx_wol_type_t type, 1174 __in efx_wol_param_t *paramp, 1175 __out uint32_t *filter_idp); 1176 1177 extern __checkReturn int 1178 efx_wol_filter_remove( 1179 __in efx_nic_t *enp, 1180 __in uint32_t filter_id); 1181 1182 extern __checkReturn int 1183 efx_lightsout_offload_add( 1184 __in efx_nic_t *enp, 1185 __in efx_lightsout_offload_type_t type, 1186 __in efx_lightsout_offload_param_t *paramp, 1187 __out uint32_t *filter_idp); 1188 1189 extern __checkReturn int 1190 efx_lightsout_offload_remove( 1191 __in efx_nic_t *enp, 1192 __in efx_lightsout_offload_type_t type, 1193 __in uint32_t filter_id); 1194 1195 extern void 1196 efx_wol_fini( 1197 __in efx_nic_t *enp); 1198 1199 #endif /* EFSYS_OPT_WOL */ 1200 1201 #if EFSYS_OPT_DIAG 1202 1203 typedef enum efx_pattern_type_t { 1204 EFX_PATTERN_BYTE_INCREMENT = 0, 1205 EFX_PATTERN_ALL_THE_SAME, 1206 EFX_PATTERN_BIT_ALTERNATE, 1207 EFX_PATTERN_BYTE_ALTERNATE, 1208 EFX_PATTERN_BYTE_CHANGING, 1209 EFX_PATTERN_BIT_SWEEP, 1210 EFX_PATTERN_NTYPES 1211 } efx_pattern_type_t; 1212 1213 typedef void 1214 (*efx_sram_pattern_fn_t)( 1215 __in size_t row, 1216 __in boolean_t negate, 1217 __out efx_qword_t *eqp); 1218 1219 extern __checkReturn int 1220 efx_sram_test( 1221 __in efx_nic_t *enp, 1222 __in efx_pattern_type_t type); 1223 1224 #endif /* EFSYS_OPT_DIAG */ 1225 1226 extern __checkReturn int 1227 efx_sram_buf_tbl_set( 1228 __in efx_nic_t *enp, 1229 __in uint32_t id, 1230 __in efsys_mem_t *esmp, 1231 __in size_t n); 1232 1233 extern void 1234 efx_sram_buf_tbl_clear( 1235 __in efx_nic_t *enp, 1236 __in uint32_t id, 1237 __in size_t n); 1238 1239 #define EFX_BUF_TBL_SIZE 0x20000 1240 1241 #define EFX_BUF_SIZE 4096 1242 1243 /* EV */ 1244 1245 typedef struct efx_evq_s efx_evq_t; 1246 1247 #if EFSYS_OPT_QSTATS 1248 1249 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */ 1250 typedef enum efx_ev_qstat_e { 1251 EV_ALL, 1252 EV_RX, 1253 EV_RX_OK, 1254 EV_RX_RECOVERY, 1255 EV_RX_FRM_TRUNC, 1256 EV_RX_TOBE_DISC, 1257 EV_RX_PAUSE_FRM_ERR, 1258 EV_RX_BUF_OWNER_ID_ERR, 1259 EV_RX_IPV4_HDR_CHKSUM_ERR, 1260 EV_RX_TCP_UDP_CHKSUM_ERR, 1261 EV_RX_ETH_CRC_ERR, 1262 EV_RX_IP_FRAG_ERR, 1263 EV_RX_MCAST_PKT, 1264 EV_RX_MCAST_HASH_MATCH, 1265 EV_RX_TCP_IPV4, 1266 EV_RX_TCP_IPV6, 1267 EV_RX_UDP_IPV4, 1268 EV_RX_UDP_IPV6, 1269 EV_RX_OTHER_IPV4, 1270 EV_RX_OTHER_IPV6, 1271 EV_RX_NON_IP, 1272 EV_RX_OVERRUN, 1273 EV_TX, 1274 EV_TX_WQ_FF_FULL, 1275 EV_TX_PKT_ERR, 1276 EV_TX_PKT_TOO_BIG, 1277 EV_TX_UNEXPECTED, 1278 EV_GLOBAL, 1279 EV_GLOBAL_PHY, 1280 EV_GLOBAL_MNT, 1281 EV_GLOBAL_RX_RECOVERY, 1282 EV_DRIVER, 1283 EV_DRIVER_SRM_UPD_DONE, 1284 EV_DRIVER_TX_DESCQ_FLS_DONE, 1285 EV_DRIVER_RX_DESCQ_FLS_DONE, 1286 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1287 EV_DRIVER_RX_DSC_ERROR, 1288 EV_DRIVER_TX_DSC_ERROR, 1289 EV_DRV_GEN, 1290 EV_MCDI_RESPONSE, 1291 EV_NQSTATS 1292 } efx_ev_qstat_t; 1293 1294 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1295 1296 #endif /* EFSYS_OPT_QSTATS */ 1297 1298 extern __checkReturn int 1299 efx_ev_init( 1300 __in efx_nic_t *enp); 1301 1302 extern void 1303 efx_ev_fini( 1304 __in efx_nic_t *enp); 1305 1306 #define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min)) 1307 1308 #define EFX_EVQ_MAXNEVS 32768 1309 #define EFX_EVQ_MINNEVS 512 1310 1311 #define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS) 1312 1313 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1314 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1315 1316 extern __checkReturn int 1317 efx_ev_qcreate( 1318 __in efx_nic_t *enp, 1319 __in unsigned int index, 1320 __in efsys_mem_t *esmp, 1321 __in size_t n, 1322 __in uint32_t id, 1323 __deref_out efx_evq_t **eepp); 1324 1325 extern void 1326 efx_ev_qpost( 1327 __in efx_evq_t *eep, 1328 __in uint16_t data); 1329 1330 typedef __checkReturn boolean_t 1331 (*efx_initialized_ev_t)( 1332 __in_opt void *arg); 1333 1334 #define EFX_PKT_UNICAST 0x0004 1335 #define EFX_PKT_START 0x0008 1336 1337 #define EFX_PKT_VLAN_TAGGED 0x0010 1338 #define EFX_CKSUM_TCPUDP 0x0020 1339 #define EFX_CKSUM_IPV4 0x0040 1340 #define EFX_PKT_CONT 0x0080 1341 1342 #define EFX_CHECK_VLAN 0x0100 1343 #define EFX_PKT_TCP 0x0200 1344 #define EFX_PKT_UDP 0x0400 1345 #define EFX_PKT_IPV4 0x0800 1346 1347 #define EFX_PKT_IPV6 0x1000 1348 #define EFX_ADDR_MISMATCH 0x4000 1349 #define EFX_DISCARD 0x8000 1350 1351 #define EFX_EV_RX_NLABELS 32 1352 #define EFX_EV_TX_NLABELS 32 1353 1354 typedef __checkReturn boolean_t 1355 (*efx_rx_ev_t)( 1356 __in_opt void *arg, 1357 __in uint32_t label, 1358 __in uint32_t id, 1359 __in uint32_t size, 1360 __in uint16_t flags); 1361 1362 typedef __checkReturn boolean_t 1363 (*efx_tx_ev_t)( 1364 __in_opt void *arg, 1365 __in uint32_t label, 1366 __in uint32_t id); 1367 1368 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1369 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1370 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1371 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1372 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1373 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1374 1375 typedef __checkReturn boolean_t 1376 (*efx_exception_ev_t)( 1377 __in_opt void *arg, 1378 __in uint32_t label, 1379 __in uint32_t data); 1380 1381 typedef __checkReturn boolean_t 1382 (*efx_rxq_flush_done_ev_t)( 1383 __in_opt void *arg, 1384 __in uint32_t rxq_index); 1385 1386 typedef __checkReturn boolean_t 1387 (*efx_rxq_flush_failed_ev_t)( 1388 __in_opt void *arg, 1389 __in uint32_t rxq_index); 1390 1391 typedef __checkReturn boolean_t 1392 (*efx_txq_flush_done_ev_t)( 1393 __in_opt void *arg, 1394 __in uint32_t txq_index); 1395 1396 typedef __checkReturn boolean_t 1397 (*efx_software_ev_t)( 1398 __in_opt void *arg, 1399 __in uint16_t magic); 1400 1401 typedef __checkReturn boolean_t 1402 (*efx_sram_ev_t)( 1403 __in_opt void *arg, 1404 __in uint32_t code); 1405 1406 #define EFX_SRAM_CLEAR 0 1407 #define EFX_SRAM_UPDATE 1 1408 #define EFX_SRAM_ILLEGAL_CLEAR 2 1409 1410 typedef __checkReturn boolean_t 1411 (*efx_wake_up_ev_t)( 1412 __in_opt void *arg, 1413 __in uint32_t label); 1414 1415 typedef __checkReturn boolean_t 1416 (*efx_timer_ev_t)( 1417 __in_opt void *arg, 1418 __in uint32_t label); 1419 1420 typedef __checkReturn boolean_t 1421 (*efx_link_change_ev_t)( 1422 __in_opt void *arg, 1423 __in efx_link_mode_t link_mode); 1424 1425 #if EFSYS_OPT_MON_STATS 1426 1427 typedef __checkReturn boolean_t 1428 (*efx_monitor_ev_t)( 1429 __in_opt void *arg, 1430 __in efx_mon_stat_t id, 1431 __in efx_mon_stat_value_t value); 1432 1433 #endif /* EFSYS_OPT_MON_STATS */ 1434 1435 #if EFSYS_OPT_MAC_STATS 1436 1437 typedef __checkReturn boolean_t 1438 (*efx_mac_stats_ev_t)( 1439 __in_opt void *arg, 1440 __in uint32_t generation 1441 ); 1442 1443 #endif /* EFSYS_OPT_MAC_STATS */ 1444 1445 typedef struct efx_ev_callbacks_s { 1446 efx_initialized_ev_t eec_initialized; 1447 efx_rx_ev_t eec_rx; 1448 efx_tx_ev_t eec_tx; 1449 efx_exception_ev_t eec_exception; 1450 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1451 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1452 efx_txq_flush_done_ev_t eec_txq_flush_done; 1453 efx_software_ev_t eec_software; 1454 efx_sram_ev_t eec_sram; 1455 efx_wake_up_ev_t eec_wake_up; 1456 efx_timer_ev_t eec_timer; 1457 efx_link_change_ev_t eec_link_change; 1458 #if EFSYS_OPT_MON_STATS 1459 efx_monitor_ev_t eec_monitor; 1460 #endif /* EFSYS_OPT_MON_STATS */ 1461 #if EFSYS_OPT_MAC_STATS 1462 efx_mac_stats_ev_t eec_mac_stats; 1463 #endif /* EFSYS_OPT_MON_STATS */ 1464 } efx_ev_callbacks_t; 1465 1466 extern __checkReturn boolean_t 1467 efx_ev_qpending( 1468 __in efx_evq_t *eep, 1469 __in unsigned int count); 1470 1471 #if EFSYS_OPT_EV_PREFETCH 1472 1473 extern void 1474 efx_ev_qprefetch( 1475 __in efx_evq_t *eep, 1476 __in unsigned int count); 1477 1478 #endif /* EFSYS_OPT_EV_PREFETCH */ 1479 1480 extern void 1481 efx_ev_qpoll( 1482 __in efx_evq_t *eep, 1483 __inout unsigned int *countp, 1484 __in const efx_ev_callbacks_t *eecp, 1485 __in_opt void *arg); 1486 1487 extern __checkReturn int 1488 efx_ev_qmoderate( 1489 __in efx_evq_t *eep, 1490 __in unsigned int us); 1491 1492 extern __checkReturn int 1493 efx_ev_qprime( 1494 __in efx_evq_t *eep, 1495 __in unsigned int count); 1496 1497 #if EFSYS_OPT_QSTATS 1498 1499 #if EFSYS_OPT_NAMES 1500 1501 extern const char __cs * 1502 efx_ev_qstat_name( 1503 __in efx_nic_t *enp, 1504 __in unsigned int id); 1505 1506 #endif /* EFSYS_OPT_NAMES */ 1507 1508 extern void 1509 efx_ev_qstats_update( 1510 __in efx_evq_t *eep, 1511 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1512 1513 #endif /* EFSYS_OPT_QSTATS */ 1514 1515 extern void 1516 efx_ev_qdestroy( 1517 __in efx_evq_t *eep); 1518 1519 /* RX */ 1520 1521 typedef struct efx_rxq_s efx_rxq_t; 1522 1523 extern __checkReturn int 1524 efx_rx_init( 1525 __in efx_nic_t *enp); 1526 1527 extern void 1528 efx_rx_fini( 1529 __in efx_nic_t *enp); 1530 1531 #if EFSYS_OPT_RX_HDR_SPLIT 1532 __checkReturn int 1533 efx_rx_hdr_split_enable( 1534 __in efx_nic_t *enp, 1535 __in unsigned int hdr_buf_size, 1536 __in unsigned int pld_buf_size); 1537 1538 #endif /* EFSYS_OPT_RX_HDR_SPLIT */ 1539 1540 #if EFSYS_OPT_RX_SCATTER 1541 __checkReturn int 1542 efx_rx_scatter_enable( 1543 __in efx_nic_t *enp, 1544 __in unsigned int buf_size); 1545 #endif /* EFSYS_OPT_RX_SCATTER */ 1546 1547 #if EFSYS_OPT_RX_SCALE 1548 1549 typedef enum efx_rx_hash_alg_e { 1550 EFX_RX_HASHALG_LFSR = 0, 1551 EFX_RX_HASHALG_TOEPLITZ 1552 } efx_rx_hash_alg_t; 1553 1554 typedef enum efx_rx_hash_type_e { 1555 EFX_RX_HASH_IPV4 = 0, 1556 EFX_RX_HASH_TCPIPV4, 1557 EFX_RX_HASH_IPV6, 1558 EFX_RX_HASH_TCPIPV6, 1559 } efx_rx_hash_type_t; 1560 1561 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1562 #define EFX_MAXRSS 64 /* RX indirection entry range */ 1563 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1564 1565 extern __checkReturn int 1566 efx_rx_scale_mode_set( 1567 __in efx_nic_t *enp, 1568 __in efx_rx_hash_alg_t alg, 1569 __in efx_rx_hash_type_t type, 1570 __in boolean_t insert); 1571 1572 extern __checkReturn int 1573 efx_rx_scale_tbl_set( 1574 __in efx_nic_t *enp, 1575 __in_ecount(n) unsigned int *table, 1576 __in size_t n); 1577 1578 extern __checkReturn int 1579 efx_rx_scale_toeplitz_ipv4_key_set( 1580 __in efx_nic_t *enp, 1581 __in_ecount(n) uint8_t *key, 1582 __in size_t n); 1583 1584 extern __checkReturn int 1585 efx_rx_scale_toeplitz_ipv6_key_set( 1586 __in efx_nic_t *enp, 1587 __in_ecount(n) uint8_t *key, 1588 __in size_t n); 1589 1590 /* 1591 * The prefix is a byte array of one of the forms: 1592 * 1593 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1594 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT 1595 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL 1596 * 1597 * where: 1598 * 1599 * TT.TT.TT.TT is a 32-bit Toeplitz hash 1600 * LL.LL is a 16-bit LFSR hash 1601 * 1602 * Hash values are in network (big-endian) byte order. 1603 */ 1604 1605 #define EFX_RX_PREFIX_SIZE 16 1606 1607 #define EFX_RX_HASH_VALUE(_func, _buffer) \ 1608 (((_func) == EFX_RX_HASHALG_LFSR) ? \ 1609 ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \ 1610 ((uint32_t)(((_buffer)[12] << 24) | \ 1611 ((_buffer)[13] << 16) | \ 1612 ((_buffer)[14] << 8) | \ 1613 (_buffer)[15]))) 1614 1615 #define EFX_RX_HASH_SIZE(_func) \ 1616 (((_func) == EFX_RX_HASHALG_LFSR) ? \ 1617 sizeof (uint16_t) : \ 1618 sizeof (uint32_t)) 1619 1620 #endif /* EFSYS_OPT_RX_SCALE */ 1621 1622 #define EFX_RXQ_MAXNDESCS 4096 1623 #define EFX_RXQ_MINNDESCS 512 1624 1625 #define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS) 1626 1627 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1628 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1629 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1630 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1631 1632 typedef enum efx_rxq_type_e { 1633 EFX_RXQ_TYPE_DEFAULT, 1634 EFX_RXQ_TYPE_SPLIT_HEADER, 1635 EFX_RXQ_TYPE_SPLIT_PAYLOAD, 1636 EFX_RXQ_TYPE_SCATTER, 1637 EFX_RXQ_NTYPES 1638 } efx_rxq_type_t; 1639 1640 extern __checkReturn int 1641 efx_rx_qcreate( 1642 __in efx_nic_t *enp, 1643 __in unsigned int index, 1644 __in unsigned int label, 1645 __in efx_rxq_type_t type, 1646 __in efsys_mem_t *esmp, 1647 __in size_t n, 1648 __in uint32_t id, 1649 __in efx_evq_t *eep, 1650 __deref_out efx_rxq_t **erpp); 1651 1652 typedef struct efx_buffer_s { 1653 efsys_dma_addr_t eb_addr; 1654 size_t eb_size; 1655 boolean_t eb_eop; 1656 } efx_buffer_t; 1657 1658 extern void 1659 efx_rx_qpost( 1660 __in efx_rxq_t *erp, 1661 __in_ecount(n) efsys_dma_addr_t *addrp, 1662 __in size_t size, 1663 __in unsigned int n, 1664 __in unsigned int completed, 1665 __in unsigned int added); 1666 1667 extern void 1668 efx_rx_qpush( 1669 __in efx_rxq_t *erp, 1670 __in unsigned int added); 1671 1672 extern void 1673 efx_rx_qflush( 1674 __in efx_rxq_t *erp); 1675 1676 extern void 1677 efx_rx_qenable( 1678 __in efx_rxq_t *erp); 1679 1680 extern void 1681 efx_rx_qdestroy( 1682 __in efx_rxq_t *erp); 1683 1684 /* TX */ 1685 1686 typedef struct efx_txq_s efx_txq_t; 1687 1688 #if EFSYS_OPT_QSTATS 1689 1690 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */ 1691 typedef enum efx_tx_qstat_e { 1692 TX_POST, 1693 TX_UNALIGNED_SPLIT, 1694 TX_NQSTATS 1695 } efx_tx_qstat_t; 1696 1697 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 1698 1699 #endif /* EFSYS_OPT_QSTATS */ 1700 1701 extern __checkReturn int 1702 efx_tx_init( 1703 __in efx_nic_t *enp); 1704 1705 extern void 1706 efx_tx_fini( 1707 __in efx_nic_t *enp); 1708 1709 #define EFX_TXQ_MAXNDESCS 4096 1710 #define EFX_TXQ_MINNDESCS 512 1711 1712 #define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS) 1713 1714 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1715 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1716 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1717 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1718 1719 extern __checkReturn int 1720 efx_tx_qcreate( 1721 __in efx_nic_t *enp, 1722 __in unsigned int index, 1723 __in unsigned int label, 1724 __in efsys_mem_t *esmp, 1725 __in size_t n, 1726 __in uint32_t id, 1727 __in uint16_t flags, 1728 __in efx_evq_t *eep, 1729 __deref_out efx_txq_t **etpp); 1730 1731 extern __checkReturn int 1732 efx_tx_qpost( 1733 __in efx_txq_t *etp, 1734 __in_ecount(n) efx_buffer_t *eb, 1735 __in unsigned int n, 1736 __in unsigned int completed, 1737 __inout unsigned int *addedp); 1738 1739 extern __checkReturn int 1740 efx_tx_qpace( 1741 __in efx_txq_t *etp, 1742 __in unsigned int ns); 1743 1744 extern void 1745 efx_tx_qpush( 1746 __in efx_txq_t *etp, 1747 __in unsigned int added); 1748 1749 extern void 1750 efx_tx_qflush( 1751 __in efx_txq_t *etp); 1752 1753 extern void 1754 efx_tx_qenable( 1755 __in efx_txq_t *etp); 1756 1757 #if EFSYS_OPT_QSTATS 1758 1759 #if EFSYS_OPT_NAMES 1760 1761 extern const char __cs * 1762 efx_tx_qstat_name( 1763 __in efx_nic_t *etp, 1764 __in unsigned int id); 1765 1766 #endif /* EFSYS_OPT_NAMES */ 1767 1768 extern void 1769 efx_tx_qstats_update( 1770 __in efx_txq_t *etp, 1771 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 1772 1773 #endif /* EFSYS_OPT_QSTATS */ 1774 1775 extern void 1776 efx_tx_qdestroy( 1777 __in efx_txq_t *etp); 1778 1779 1780 /* FILTER */ 1781 1782 #if EFSYS_OPT_FILTER 1783 1784 typedef enum efx_filter_flag_e { 1785 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 1786 * multiple queues */ 1787 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 1788 EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides 1789 * any matching IP filter */ 1790 } efx_filter_flag_t; 1791 1792 typedef struct efx_filter_spec_s { 1793 uint8_t efs_type; 1794 uint8_t efs_flags; 1795 uint16_t efs_dmaq_id; 1796 uint32_t efs_dword[3]; 1797 } efx_filter_spec_t; 1798 1799 extern __checkReturn int 1800 efx_filter_init( 1801 __in efx_nic_t *enp); 1802 1803 extern void 1804 efx_filter_fini( 1805 __in efx_nic_t *enp); 1806 1807 extern __checkReturn int 1808 efx_rx_filter_insert( 1809 __in efx_rxq_t *erp, 1810 __inout efx_filter_spec_t *spec); 1811 1812 extern __checkReturn int 1813 efx_rx_filter_remove( 1814 __in efx_rxq_t *erp, 1815 __inout efx_filter_spec_t *spec); 1816 1817 void 1818 efx_filter_restore( 1819 __in efx_nic_t *enp); 1820 1821 extern void 1822 efx_filter_spec_rx_ipv4_tcp_full( 1823 __inout efx_filter_spec_t *spec, 1824 __in unsigned int flags, 1825 __in uint32_t src_ip, 1826 __in uint16_t src_tcp, 1827 __in uint32_t dest_ip, 1828 __in uint16_t dest_tcp); 1829 1830 extern void 1831 efx_filter_spec_rx_ipv4_tcp_wild( 1832 __inout efx_filter_spec_t *spec, 1833 __in unsigned int flags, 1834 __in uint32_t dest_ip, 1835 __in uint16_t dest_tcp); 1836 1837 extern void 1838 efx_filter_spec_rx_ipv4_udp_full( 1839 __inout efx_filter_spec_t *spec, 1840 __in unsigned int flags, 1841 __in uint32_t src_ip, 1842 __in uint16_t src_udp, 1843 __in uint32_t dest_ip, 1844 __in uint16_t dest_udp); 1845 1846 extern void 1847 efx_filter_spec_rx_ipv4_udp_wild( 1848 __inout efx_filter_spec_t *spec, 1849 __in unsigned int flags, 1850 __in uint32_t dest_ip, 1851 __in uint16_t dest_udp); 1852 1853 extern void 1854 efx_filter_spec_rx_mac_full( 1855 __inout efx_filter_spec_t *spec, 1856 __in unsigned int flags, 1857 __in uint16_t vlan_id, 1858 __in uint8_t *dest_mac); 1859 1860 extern void 1861 efx_filter_spec_rx_mac_wild( 1862 __inout efx_filter_spec_t *spec, 1863 __in unsigned int flags, 1864 __in uint8_t *dest_mac); 1865 1866 1867 extern __checkReturn int 1868 efx_tx_filter_insert( 1869 __in efx_txq_t *etp, 1870 __inout efx_filter_spec_t *spec); 1871 1872 extern __checkReturn int 1873 efx_tx_filter_remove( 1874 __in efx_txq_t *etp, 1875 __inout efx_filter_spec_t *spec); 1876 1877 extern void 1878 efx_filter_spec_tx_ipv4_tcp_full( 1879 __inout efx_filter_spec_t *spec, 1880 __in uint32_t src_ip, 1881 __in uint16_t src_tcp, 1882 __in uint32_t dest_ip, 1883 __in uint16_t dest_tcp); 1884 1885 extern void 1886 efx_filter_spec_tx_ipv4_tcp_wild( 1887 __inout efx_filter_spec_t *spec, 1888 __in uint32_t src_ip, 1889 __in uint16_t src_tcp); 1890 1891 extern void 1892 efx_filter_spec_tx_ipv4_udp_full( 1893 __inout efx_filter_spec_t *spec, 1894 __in uint32_t src_ip, 1895 __in uint16_t src_udp, 1896 __in uint32_t dest_ip, 1897 __in uint16_t dest_udp); 1898 1899 extern void 1900 efx_filter_spec_tx_ipv4_udp_wild( 1901 __inout efx_filter_spec_t *spec, 1902 __in uint32_t src_ip, 1903 __in uint16_t src_udp); 1904 1905 extern void 1906 efx_filter_spec_tx_mac_full( 1907 __inout efx_filter_spec_t *spec, 1908 __in uint16_t vlan_id, 1909 __in uint8_t *src_mac); 1910 1911 extern void 1912 efx_filter_spec_tx_mac_wild( 1913 __inout efx_filter_spec_t *spec, 1914 __in uint8_t *src_mac); 1915 1916 #endif /* EFSYS_OPT_FILTER */ 1917 1918 1919 #ifdef __cplusplus 1920 } 1921 #endif 1922 1923 #endif /* _SYS_EFX_H */ 1924