1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_H 36 #define _SYS_EFX_H 37 38 #include "efsys.h" 39 #include "efx_check.h" 40 #include "efx_phy_ids.h" 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define EFX_STATIC_ASSERT(_cond) \ 47 ((void)sizeof(char[(_cond) ? 1 : -1])) 48 49 #define EFX_ARRAY_SIZE(_array) \ 50 (sizeof(_array) / sizeof((_array)[0])) 51 52 #define EFX_FIELD_OFFSET(_type, _field) \ 53 ((size_t) &(((_type *)0)->_field)) 54 55 /* The macro expands divider twice */ 56 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 57 58 /* Return codes */ 59 60 typedef __success(return == 0) int efx_rc_t; 61 62 63 /* Chip families */ 64 65 typedef enum efx_family_e { 66 EFX_FAMILY_INVALID, 67 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 68 EFX_FAMILY_SIENA, 69 EFX_FAMILY_HUNTINGTON, 70 EFX_FAMILY_MEDFORD, 71 EFX_FAMILY_NTYPES 72 } efx_family_t; 73 74 extern __checkReturn efx_rc_t 75 efx_family( 76 __in uint16_t venid, 77 __in uint16_t devid, 78 __out efx_family_t *efp); 79 80 81 #define EFX_PCI_VENID_SFC 0x1924 82 83 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 84 85 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 86 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 87 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 88 89 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 90 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 91 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 92 93 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 94 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 95 96 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 97 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 98 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 99 100 #define EFX_MEM_BAR 2 101 102 /* Error codes */ 103 104 enum { 105 EFX_ERR_INVALID, 106 EFX_ERR_SRAM_OOB, 107 EFX_ERR_BUFID_DC_OOB, 108 EFX_ERR_MEM_PERR, 109 EFX_ERR_RBUF_OWN, 110 EFX_ERR_TBUF_OWN, 111 EFX_ERR_RDESQ_OWN, 112 EFX_ERR_TDESQ_OWN, 113 EFX_ERR_EVQ_OWN, 114 EFX_ERR_EVFF_OFLO, 115 EFX_ERR_ILL_ADDR, 116 EFX_ERR_SRAM_PERR, 117 EFX_ERR_NCODES 118 }; 119 120 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 121 extern __checkReturn uint32_t 122 efx_crc32_calculate( 123 __in uint32_t crc_init, 124 __in_ecount(length) uint8_t const *input, 125 __in int length); 126 127 128 /* Type prototypes */ 129 130 typedef struct efx_rxq_s efx_rxq_t; 131 132 /* NIC */ 133 134 typedef struct efx_nic_s efx_nic_t; 135 136 extern __checkReturn efx_rc_t 137 efx_nic_create( 138 __in efx_family_t family, 139 __in efsys_identifier_t *esip, 140 __in efsys_bar_t *esbp, 141 __in efsys_lock_t *eslp, 142 __deref_out efx_nic_t **enpp); 143 144 extern __checkReturn efx_rc_t 145 efx_nic_probe( 146 __in efx_nic_t *enp); 147 148 extern __checkReturn efx_rc_t 149 efx_nic_init( 150 __in efx_nic_t *enp); 151 152 extern __checkReturn efx_rc_t 153 efx_nic_reset( 154 __in efx_nic_t *enp); 155 156 #if EFSYS_OPT_DIAG 157 158 extern __checkReturn efx_rc_t 159 efx_nic_register_test( 160 __in efx_nic_t *enp); 161 162 #endif /* EFSYS_OPT_DIAG */ 163 164 extern void 165 efx_nic_fini( 166 __in efx_nic_t *enp); 167 168 extern void 169 efx_nic_unprobe( 170 __in efx_nic_t *enp); 171 172 extern void 173 efx_nic_destroy( 174 __in efx_nic_t *enp); 175 176 #define EFX_PCIE_LINK_SPEED_GEN1 1 177 #define EFX_PCIE_LINK_SPEED_GEN2 2 178 #define EFX_PCIE_LINK_SPEED_GEN3 3 179 180 typedef enum efx_pcie_link_performance_e { 181 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 182 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 184 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 185 } efx_pcie_link_performance_t; 186 187 extern __checkReturn efx_rc_t 188 efx_nic_calculate_pcie_link_bandwidth( 189 __in uint32_t pcie_link_width, 190 __in uint32_t pcie_link_gen, 191 __out uint32_t *bandwidth_mbpsp); 192 193 extern __checkReturn efx_rc_t 194 efx_nic_check_pcie_link_speed( 195 __in efx_nic_t *enp, 196 __in uint32_t pcie_link_width, 197 __in uint32_t pcie_link_gen, 198 __out efx_pcie_link_performance_t *resultp); 199 200 #if EFSYS_OPT_MCDI 201 202 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 203 /* Huntington and Medford require MCDIv2 commands */ 204 #define WITH_MCDI_V2 1 205 #endif 206 207 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 208 209 typedef enum efx_mcdi_exception_e { 210 EFX_MCDI_EXCEPTION_MC_REBOOT, 211 EFX_MCDI_EXCEPTION_MC_BADASSERT, 212 } efx_mcdi_exception_t; 213 214 #if EFSYS_OPT_MCDI_LOGGING 215 typedef enum efx_log_msg_e { 216 EFX_LOG_INVALID, 217 EFX_LOG_MCDI_REQUEST, 218 EFX_LOG_MCDI_RESPONSE, 219 } efx_log_msg_t; 220 #endif /* EFSYS_OPT_MCDI_LOGGING */ 221 222 typedef struct efx_mcdi_transport_s { 223 void *emt_context; 224 efsys_mem_t *emt_dma_mem; 225 void (*emt_execute)(void *, efx_mcdi_req_t *); 226 void (*emt_ev_cpl)(void *); 227 void (*emt_exception)(void *, efx_mcdi_exception_t); 228 #if EFSYS_OPT_MCDI_LOGGING 229 void (*emt_logger)(void *, efx_log_msg_t, 230 void *, size_t, void *, size_t); 231 #endif /* EFSYS_OPT_MCDI_LOGGING */ 232 #if EFSYS_OPT_MCDI_PROXY_AUTH 233 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 234 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 235 } efx_mcdi_transport_t; 236 237 extern __checkReturn efx_rc_t 238 efx_mcdi_init( 239 __in efx_nic_t *enp, 240 __in const efx_mcdi_transport_t *mtp); 241 242 extern __checkReturn efx_rc_t 243 efx_mcdi_reboot( 244 __in efx_nic_t *enp); 245 246 void 247 efx_mcdi_new_epoch( 248 __in efx_nic_t *enp); 249 250 extern void 251 efx_mcdi_get_timeout( 252 __in efx_nic_t *enp, 253 __in efx_mcdi_req_t *emrp, 254 __out uint32_t *usec_timeoutp); 255 256 extern void 257 efx_mcdi_request_start( 258 __in efx_nic_t *enp, 259 __in efx_mcdi_req_t *emrp, 260 __in boolean_t ev_cpl); 261 262 extern __checkReturn boolean_t 263 efx_mcdi_request_poll( 264 __in efx_nic_t *enp); 265 266 extern __checkReturn boolean_t 267 efx_mcdi_request_abort( 268 __in efx_nic_t *enp); 269 270 extern void 271 efx_mcdi_fini( 272 __in efx_nic_t *enp); 273 274 #endif /* EFSYS_OPT_MCDI */ 275 276 /* INTR */ 277 278 #define EFX_NINTR_SIENA 1024 279 280 typedef enum efx_intr_type_e { 281 EFX_INTR_INVALID = 0, 282 EFX_INTR_LINE, 283 EFX_INTR_MESSAGE, 284 EFX_INTR_NTYPES 285 } efx_intr_type_t; 286 287 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 288 289 extern __checkReturn efx_rc_t 290 efx_intr_init( 291 __in efx_nic_t *enp, 292 __in efx_intr_type_t type, 293 __in efsys_mem_t *esmp); 294 295 extern void 296 efx_intr_enable( 297 __in efx_nic_t *enp); 298 299 extern void 300 efx_intr_disable( 301 __in efx_nic_t *enp); 302 303 extern void 304 efx_intr_disable_unlocked( 305 __in efx_nic_t *enp); 306 307 #define EFX_INTR_NEVQS 32 308 309 extern __checkReturn efx_rc_t 310 efx_intr_trigger( 311 __in efx_nic_t *enp, 312 __in unsigned int level); 313 314 extern void 315 efx_intr_status_line( 316 __in efx_nic_t *enp, 317 __out boolean_t *fatalp, 318 __out uint32_t *maskp); 319 320 extern void 321 efx_intr_status_message( 322 __in efx_nic_t *enp, 323 __in unsigned int message, 324 __out boolean_t *fatalp); 325 326 extern void 327 efx_intr_fatal( 328 __in efx_nic_t *enp); 329 330 extern void 331 efx_intr_fini( 332 __in efx_nic_t *enp); 333 334 /* MAC */ 335 336 #if EFSYS_OPT_MAC_STATS 337 338 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 339 typedef enum efx_mac_stat_e { 340 EFX_MAC_RX_OCTETS, 341 EFX_MAC_RX_PKTS, 342 EFX_MAC_RX_UNICST_PKTS, 343 EFX_MAC_RX_MULTICST_PKTS, 344 EFX_MAC_RX_BRDCST_PKTS, 345 EFX_MAC_RX_PAUSE_PKTS, 346 EFX_MAC_RX_LE_64_PKTS, 347 EFX_MAC_RX_65_TO_127_PKTS, 348 EFX_MAC_RX_128_TO_255_PKTS, 349 EFX_MAC_RX_256_TO_511_PKTS, 350 EFX_MAC_RX_512_TO_1023_PKTS, 351 EFX_MAC_RX_1024_TO_15XX_PKTS, 352 EFX_MAC_RX_GE_15XX_PKTS, 353 EFX_MAC_RX_ERRORS, 354 EFX_MAC_RX_FCS_ERRORS, 355 EFX_MAC_RX_DROP_EVENTS, 356 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 357 EFX_MAC_RX_SYMBOL_ERRORS, 358 EFX_MAC_RX_ALIGN_ERRORS, 359 EFX_MAC_RX_INTERNAL_ERRORS, 360 EFX_MAC_RX_JABBER_PKTS, 361 EFX_MAC_RX_LANE0_CHAR_ERR, 362 EFX_MAC_RX_LANE1_CHAR_ERR, 363 EFX_MAC_RX_LANE2_CHAR_ERR, 364 EFX_MAC_RX_LANE3_CHAR_ERR, 365 EFX_MAC_RX_LANE0_DISP_ERR, 366 EFX_MAC_RX_LANE1_DISP_ERR, 367 EFX_MAC_RX_LANE2_DISP_ERR, 368 EFX_MAC_RX_LANE3_DISP_ERR, 369 EFX_MAC_RX_MATCH_FAULT, 370 EFX_MAC_RX_NODESC_DROP_CNT, 371 EFX_MAC_TX_OCTETS, 372 EFX_MAC_TX_PKTS, 373 EFX_MAC_TX_UNICST_PKTS, 374 EFX_MAC_TX_MULTICST_PKTS, 375 EFX_MAC_TX_BRDCST_PKTS, 376 EFX_MAC_TX_PAUSE_PKTS, 377 EFX_MAC_TX_LE_64_PKTS, 378 EFX_MAC_TX_65_TO_127_PKTS, 379 EFX_MAC_TX_128_TO_255_PKTS, 380 EFX_MAC_TX_256_TO_511_PKTS, 381 EFX_MAC_TX_512_TO_1023_PKTS, 382 EFX_MAC_TX_1024_TO_15XX_PKTS, 383 EFX_MAC_TX_GE_15XX_PKTS, 384 EFX_MAC_TX_ERRORS, 385 EFX_MAC_TX_SGL_COL_PKTS, 386 EFX_MAC_TX_MULT_COL_PKTS, 387 EFX_MAC_TX_EX_COL_PKTS, 388 EFX_MAC_TX_LATE_COL_PKTS, 389 EFX_MAC_TX_DEF_PKTS, 390 EFX_MAC_TX_EX_DEF_PKTS, 391 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 392 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 393 EFX_MAC_PM_TRUNC_VFIFO_FULL, 394 EFX_MAC_PM_DISCARD_VFIFO_FULL, 395 EFX_MAC_PM_TRUNC_QBB, 396 EFX_MAC_PM_DISCARD_QBB, 397 EFX_MAC_PM_DISCARD_MAPPING, 398 EFX_MAC_RXDP_Q_DISABLED_PKTS, 399 EFX_MAC_RXDP_DI_DROPPED_PKTS, 400 EFX_MAC_RXDP_STREAMING_PKTS, 401 EFX_MAC_RXDP_HLB_FETCH, 402 EFX_MAC_RXDP_HLB_WAIT, 403 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 404 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 405 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 406 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 407 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 408 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 409 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 410 EFX_MAC_VADAPTER_RX_BAD_BYTES, 411 EFX_MAC_VADAPTER_RX_OVERFLOW, 412 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 413 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 414 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 415 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 416 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 417 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 418 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 419 EFX_MAC_VADAPTER_TX_BAD_BYTES, 420 EFX_MAC_VADAPTER_TX_OVERFLOW, 421 EFX_MAC_NSTATS 422 } efx_mac_stat_t; 423 424 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 425 426 #endif /* EFSYS_OPT_MAC_STATS */ 427 428 typedef enum efx_link_mode_e { 429 EFX_LINK_UNKNOWN = 0, 430 EFX_LINK_DOWN, 431 EFX_LINK_10HDX, 432 EFX_LINK_10FDX, 433 EFX_LINK_100HDX, 434 EFX_LINK_100FDX, 435 EFX_LINK_1000HDX, 436 EFX_LINK_1000FDX, 437 EFX_LINK_10000FDX, 438 EFX_LINK_40000FDX, 439 EFX_LINK_NMODES 440 } efx_link_mode_t; 441 442 #define EFX_MAC_ADDR_LEN 6 443 444 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 445 446 #define EFX_MAC_MULTICAST_LIST_MAX 256 447 448 #define EFX_MAC_SDU_MAX 9202 449 450 #define EFX_MAC_PDU_ADJUSTMENT \ 451 (/* EtherII */ 14 \ 452 + /* VLAN */ 4 \ 453 + /* CRC */ 4 \ 454 + /* bug16011 */ 16) \ 455 456 #define EFX_MAC_PDU(_sdu) \ 457 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 458 459 /* 460 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 461 * the SDU rounded up slightly. 462 */ 463 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 464 465 #define EFX_MAC_PDU_MIN 60 466 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 467 468 extern __checkReturn efx_rc_t 469 efx_mac_pdu_get( 470 __in efx_nic_t *enp, 471 __out size_t *pdu); 472 473 extern __checkReturn efx_rc_t 474 efx_mac_pdu_set( 475 __in efx_nic_t *enp, 476 __in size_t pdu); 477 478 extern __checkReturn efx_rc_t 479 efx_mac_addr_set( 480 __in efx_nic_t *enp, 481 __in uint8_t *addr); 482 483 extern __checkReturn efx_rc_t 484 efx_mac_filter_set( 485 __in efx_nic_t *enp, 486 __in boolean_t all_unicst, 487 __in boolean_t mulcst, 488 __in boolean_t all_mulcst, 489 __in boolean_t brdcst); 490 491 extern __checkReturn efx_rc_t 492 efx_mac_multicast_list_set( 493 __in efx_nic_t *enp, 494 __in_ecount(6*count) uint8_t const *addrs, 495 __in int count); 496 497 extern __checkReturn efx_rc_t 498 efx_mac_filter_default_rxq_set( 499 __in efx_nic_t *enp, 500 __in efx_rxq_t *erp, 501 __in boolean_t using_rss); 502 503 extern void 504 efx_mac_filter_default_rxq_clear( 505 __in efx_nic_t *enp); 506 507 extern __checkReturn efx_rc_t 508 efx_mac_drain( 509 __in efx_nic_t *enp, 510 __in boolean_t enabled); 511 512 extern __checkReturn efx_rc_t 513 efx_mac_up( 514 __in efx_nic_t *enp, 515 __out boolean_t *mac_upp); 516 517 #define EFX_FCNTL_RESPOND 0x00000001 518 #define EFX_FCNTL_GENERATE 0x00000002 519 520 extern __checkReturn efx_rc_t 521 efx_mac_fcntl_set( 522 __in efx_nic_t *enp, 523 __in unsigned int fcntl, 524 __in boolean_t autoneg); 525 526 extern void 527 efx_mac_fcntl_get( 528 __in efx_nic_t *enp, 529 __out unsigned int *fcntl_wantedp, 530 __out unsigned int *fcntl_linkp); 531 532 533 #if EFSYS_OPT_MAC_STATS 534 535 #if EFSYS_OPT_NAMES 536 537 extern __checkReturn const char * 538 efx_mac_stat_name( 539 __in efx_nic_t *enp, 540 __in unsigned int id); 541 542 #endif /* EFSYS_OPT_NAMES */ 543 544 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 545 546 #define EFX_MAC_STATS_MASK_NPAGES \ 547 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 548 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 549 550 /* 551 * Get mask of MAC statistics supported by the hardware. 552 * 553 * If mask_size is insufficient to return the mask, EINVAL error is 554 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 555 * (which is sizeof (uint32_t)) is sufficient. 556 */ 557 extern __checkReturn efx_rc_t 558 efx_mac_stats_get_mask( 559 __in efx_nic_t *enp, 560 __out_bcount(mask_size) uint32_t *maskp, 561 __in size_t mask_size); 562 563 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 564 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 565 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 566 567 #define EFX_MAC_STATS_SIZE 0x400 568 569 extern __checkReturn efx_rc_t 570 efx_mac_stats_clear( 571 __in efx_nic_t *enp); 572 573 /* 574 * Upload mac statistics supported by the hardware into the given buffer. 575 * 576 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 577 * and page aligned. 578 * 579 * The hardware will only DMA statistics that it understands (of course). 580 * Drivers should not make any assumptions about which statistics are 581 * supported, especially when the statistics are generated by firmware. 582 * 583 * Thus, drivers should zero this buffer before use, so that not-understood 584 * statistics read back as zero. 585 */ 586 extern __checkReturn efx_rc_t 587 efx_mac_stats_upload( 588 __in efx_nic_t *enp, 589 __in efsys_mem_t *esmp); 590 591 extern __checkReturn efx_rc_t 592 efx_mac_stats_periodic( 593 __in efx_nic_t *enp, 594 __in efsys_mem_t *esmp, 595 __in uint16_t period_ms, 596 __in boolean_t events); 597 598 extern __checkReturn efx_rc_t 599 efx_mac_stats_update( 600 __in efx_nic_t *enp, 601 __in efsys_mem_t *esmp, 602 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 603 __inout_opt uint32_t *generationp); 604 605 #endif /* EFSYS_OPT_MAC_STATS */ 606 607 /* MON */ 608 609 typedef enum efx_mon_type_e { 610 EFX_MON_INVALID = 0, 611 EFX_MON_SFC90X0, 612 EFX_MON_SFC91X0, 613 EFX_MON_SFC92X0, 614 EFX_MON_NTYPES 615 } efx_mon_type_t; 616 617 #if EFSYS_OPT_NAMES 618 619 extern const char * 620 efx_mon_name( 621 __in efx_nic_t *enp); 622 623 #endif /* EFSYS_OPT_NAMES */ 624 625 extern __checkReturn efx_rc_t 626 efx_mon_init( 627 __in efx_nic_t *enp); 628 629 #if EFSYS_OPT_MON_STATS 630 631 #define EFX_MON_STATS_PAGE_SIZE 0x100 632 #define EFX_MON_MASK_ELEMENT_SIZE 32 633 634 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */ 635 typedef enum efx_mon_stat_e { 636 EFX_MON_STAT_2_5V, 637 EFX_MON_STAT_VCCP1, 638 EFX_MON_STAT_VCC, 639 EFX_MON_STAT_5V, 640 EFX_MON_STAT_12V, 641 EFX_MON_STAT_VCCP2, 642 EFX_MON_STAT_EXT_TEMP, 643 EFX_MON_STAT_INT_TEMP, 644 EFX_MON_STAT_AIN1, 645 EFX_MON_STAT_AIN2, 646 EFX_MON_STAT_INT_COOLING, 647 EFX_MON_STAT_EXT_COOLING, 648 EFX_MON_STAT_1V, 649 EFX_MON_STAT_1_2V, 650 EFX_MON_STAT_1_8V, 651 EFX_MON_STAT_3_3V, 652 EFX_MON_STAT_1_2VA, 653 EFX_MON_STAT_VREF, 654 EFX_MON_STAT_VAOE, 655 EFX_MON_STAT_AOE_TEMP, 656 EFX_MON_STAT_PSU_AOE_TEMP, 657 EFX_MON_STAT_PSU_TEMP, 658 EFX_MON_STAT_FAN0, 659 EFX_MON_STAT_FAN1, 660 EFX_MON_STAT_FAN2, 661 EFX_MON_STAT_FAN3, 662 EFX_MON_STAT_FAN4, 663 EFX_MON_STAT_VAOE_IN, 664 EFX_MON_STAT_IAOE, 665 EFX_MON_STAT_IAOE_IN, 666 EFX_MON_STAT_NIC_POWER, 667 EFX_MON_STAT_0_9V, 668 EFX_MON_STAT_I0_9V, 669 EFX_MON_STAT_I1_2V, 670 EFX_MON_STAT_0_9V_ADC, 671 EFX_MON_STAT_INT_TEMP2, 672 EFX_MON_STAT_VREG_TEMP, 673 EFX_MON_STAT_VREG_0_9V_TEMP, 674 EFX_MON_STAT_VREG_1_2V_TEMP, 675 EFX_MON_STAT_INT_VPTAT, 676 EFX_MON_STAT_INT_ADC_TEMP, 677 EFX_MON_STAT_EXT_VPTAT, 678 EFX_MON_STAT_EXT_ADC_TEMP, 679 EFX_MON_STAT_AMBIENT_TEMP, 680 EFX_MON_STAT_AIRFLOW, 681 EFX_MON_STAT_VDD08D_VSS08D_CSR, 682 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 683 EFX_MON_STAT_HOTPOINT_TEMP, 684 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 685 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 686 EFX_MON_STAT_MUM_VCC, 687 EFX_MON_STAT_0V9_A, 688 EFX_MON_STAT_I0V9_A, 689 EFX_MON_STAT_0V9_A_TEMP, 690 EFX_MON_STAT_0V9_B, 691 EFX_MON_STAT_I0V9_B, 692 EFX_MON_STAT_0V9_B_TEMP, 693 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 694 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 695 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 696 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 697 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 698 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 699 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 700 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 701 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 702 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 703 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 704 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 705 EFX_MON_STAT_SODIMM_VOUT, 706 EFX_MON_STAT_SODIMM_0_TEMP, 707 EFX_MON_STAT_SODIMM_1_TEMP, 708 EFX_MON_STAT_PHY0_VCC, 709 EFX_MON_STAT_PHY1_VCC, 710 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 711 EFX_MON_STAT_BOARD_FRONT_TEMP, 712 EFX_MON_STAT_BOARD_BACK_TEMP, 713 EFX_MON_NSTATS 714 } efx_mon_stat_t; 715 716 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 717 718 typedef enum efx_mon_stat_state_e { 719 EFX_MON_STAT_STATE_OK = 0, 720 EFX_MON_STAT_STATE_WARNING = 1, 721 EFX_MON_STAT_STATE_FATAL = 2, 722 EFX_MON_STAT_STATE_BROKEN = 3, 723 EFX_MON_STAT_STATE_NO_READING = 4, 724 } efx_mon_stat_state_t; 725 726 typedef struct efx_mon_stat_value_s { 727 uint16_t emsv_value; 728 uint16_t emsv_state; 729 } efx_mon_stat_value_t; 730 731 #if EFSYS_OPT_NAMES 732 733 extern const char * 734 efx_mon_stat_name( 735 __in efx_nic_t *enp, 736 __in efx_mon_stat_t id); 737 738 #endif /* EFSYS_OPT_NAMES */ 739 740 extern __checkReturn efx_rc_t 741 efx_mon_stats_update( 742 __in efx_nic_t *enp, 743 __in efsys_mem_t *esmp, 744 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 745 746 #endif /* EFSYS_OPT_MON_STATS */ 747 748 extern void 749 efx_mon_fini( 750 __in efx_nic_t *enp); 751 752 /* PHY */ 753 754 extern __checkReturn efx_rc_t 755 efx_phy_verify( 756 __in efx_nic_t *enp); 757 758 #if EFSYS_OPT_PHY_LED_CONTROL 759 760 typedef enum efx_phy_led_mode_e { 761 EFX_PHY_LED_DEFAULT = 0, 762 EFX_PHY_LED_OFF, 763 EFX_PHY_LED_ON, 764 EFX_PHY_LED_FLASH, 765 EFX_PHY_LED_NMODES 766 } efx_phy_led_mode_t; 767 768 extern __checkReturn efx_rc_t 769 efx_phy_led_set( 770 __in efx_nic_t *enp, 771 __in efx_phy_led_mode_t mode); 772 773 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 774 775 extern __checkReturn efx_rc_t 776 efx_port_init( 777 __in efx_nic_t *enp); 778 779 #if EFSYS_OPT_LOOPBACK 780 781 typedef enum efx_loopback_type_e { 782 EFX_LOOPBACK_OFF = 0, 783 EFX_LOOPBACK_DATA = 1, 784 EFX_LOOPBACK_GMAC = 2, 785 EFX_LOOPBACK_XGMII = 3, 786 EFX_LOOPBACK_XGXS = 4, 787 EFX_LOOPBACK_XAUI = 5, 788 EFX_LOOPBACK_GMII = 6, 789 EFX_LOOPBACK_SGMII = 7, 790 EFX_LOOPBACK_XGBR = 8, 791 EFX_LOOPBACK_XFI = 9, 792 EFX_LOOPBACK_XAUI_FAR = 10, 793 EFX_LOOPBACK_GMII_FAR = 11, 794 EFX_LOOPBACK_SGMII_FAR = 12, 795 EFX_LOOPBACK_XFI_FAR = 13, 796 EFX_LOOPBACK_GPHY = 14, 797 EFX_LOOPBACK_PHY_XS = 15, 798 EFX_LOOPBACK_PCS = 16, 799 EFX_LOOPBACK_PMA_PMD = 17, 800 EFX_LOOPBACK_XPORT = 18, 801 EFX_LOOPBACK_XGMII_WS = 19, 802 EFX_LOOPBACK_XAUI_WS = 20, 803 EFX_LOOPBACK_XAUI_WS_FAR = 21, 804 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 805 EFX_LOOPBACK_GMII_WS = 23, 806 EFX_LOOPBACK_XFI_WS = 24, 807 EFX_LOOPBACK_XFI_WS_FAR = 25, 808 EFX_LOOPBACK_PHYXS_WS = 26, 809 EFX_LOOPBACK_PMA_INT = 27, 810 EFX_LOOPBACK_SD_NEAR = 28, 811 EFX_LOOPBACK_SD_FAR = 29, 812 EFX_LOOPBACK_PMA_INT_WS = 30, 813 EFX_LOOPBACK_SD_FEP2_WS = 31, 814 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 815 EFX_LOOPBACK_SD_FEP_WS = 33, 816 EFX_LOOPBACK_SD_FES_WS = 34, 817 EFX_LOOPBACK_NTYPES 818 } efx_loopback_type_t; 819 820 typedef enum efx_loopback_kind_e { 821 EFX_LOOPBACK_KIND_OFF = 0, 822 EFX_LOOPBACK_KIND_ALL, 823 EFX_LOOPBACK_KIND_MAC, 824 EFX_LOOPBACK_KIND_PHY, 825 EFX_LOOPBACK_NKINDS 826 } efx_loopback_kind_t; 827 828 extern void 829 efx_loopback_mask( 830 __in efx_loopback_kind_t loopback_kind, 831 __out efx_qword_t *maskp); 832 833 extern __checkReturn efx_rc_t 834 efx_port_loopback_set( 835 __in efx_nic_t *enp, 836 __in efx_link_mode_t link_mode, 837 __in efx_loopback_type_t type); 838 839 #if EFSYS_OPT_NAMES 840 841 extern __checkReturn const char * 842 efx_loopback_type_name( 843 __in efx_nic_t *enp, 844 __in efx_loopback_type_t type); 845 846 #endif /* EFSYS_OPT_NAMES */ 847 848 #endif /* EFSYS_OPT_LOOPBACK */ 849 850 extern __checkReturn efx_rc_t 851 efx_port_poll( 852 __in efx_nic_t *enp, 853 __out_opt efx_link_mode_t *link_modep); 854 855 extern void 856 efx_port_fini( 857 __in efx_nic_t *enp); 858 859 typedef enum efx_phy_cap_type_e { 860 EFX_PHY_CAP_INVALID = 0, 861 EFX_PHY_CAP_10HDX, 862 EFX_PHY_CAP_10FDX, 863 EFX_PHY_CAP_100HDX, 864 EFX_PHY_CAP_100FDX, 865 EFX_PHY_CAP_1000HDX, 866 EFX_PHY_CAP_1000FDX, 867 EFX_PHY_CAP_10000FDX, 868 EFX_PHY_CAP_PAUSE, 869 EFX_PHY_CAP_ASYM, 870 EFX_PHY_CAP_AN, 871 EFX_PHY_CAP_40000FDX, 872 EFX_PHY_CAP_NTYPES 873 } efx_phy_cap_type_t; 874 875 876 #define EFX_PHY_CAP_CURRENT 0x00000000 877 #define EFX_PHY_CAP_DEFAULT 0x00000001 878 #define EFX_PHY_CAP_PERM 0x00000002 879 880 extern void 881 efx_phy_adv_cap_get( 882 __in efx_nic_t *enp, 883 __in uint32_t flag, 884 __out uint32_t *maskp); 885 886 extern __checkReturn efx_rc_t 887 efx_phy_adv_cap_set( 888 __in efx_nic_t *enp, 889 __in uint32_t mask); 890 891 extern void 892 efx_phy_lp_cap_get( 893 __in efx_nic_t *enp, 894 __out uint32_t *maskp); 895 896 extern __checkReturn efx_rc_t 897 efx_phy_oui_get( 898 __in efx_nic_t *enp, 899 __out uint32_t *ouip); 900 901 typedef enum efx_phy_media_type_e { 902 EFX_PHY_MEDIA_INVALID = 0, 903 EFX_PHY_MEDIA_XAUI, 904 EFX_PHY_MEDIA_CX4, 905 EFX_PHY_MEDIA_KX4, 906 EFX_PHY_MEDIA_XFP, 907 EFX_PHY_MEDIA_SFP_PLUS, 908 EFX_PHY_MEDIA_BASE_T, 909 EFX_PHY_MEDIA_QSFP_PLUS, 910 EFX_PHY_MEDIA_NTYPES 911 } efx_phy_media_type_t; 912 913 /* Get the type of medium currently used. If the board has ports for 914 * modules, a module is present, and we recognise the media type of 915 * the module, then this will be the media type of the module. 916 * Otherwise it will be the media type of the port. 917 */ 918 extern void 919 efx_phy_media_type_get( 920 __in efx_nic_t *enp, 921 __out efx_phy_media_type_t *typep); 922 923 extern __checkReturn efx_rc_t 924 efx_phy_module_get_info( 925 __in efx_nic_t *enp, 926 __in uint8_t dev_addr, 927 __in uint8_t offset, 928 __in uint8_t len, 929 __out_bcount(len) uint8_t *data); 930 931 #if EFSYS_OPT_PHY_STATS 932 933 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 934 typedef enum efx_phy_stat_e { 935 EFX_PHY_STAT_OUI, 936 EFX_PHY_STAT_PMA_PMD_LINK_UP, 937 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 938 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 939 EFX_PHY_STAT_PMA_PMD_REV_A, 940 EFX_PHY_STAT_PMA_PMD_REV_B, 941 EFX_PHY_STAT_PMA_PMD_REV_C, 942 EFX_PHY_STAT_PMA_PMD_REV_D, 943 EFX_PHY_STAT_PCS_LINK_UP, 944 EFX_PHY_STAT_PCS_RX_FAULT, 945 EFX_PHY_STAT_PCS_TX_FAULT, 946 EFX_PHY_STAT_PCS_BER, 947 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 948 EFX_PHY_STAT_PHY_XS_LINK_UP, 949 EFX_PHY_STAT_PHY_XS_RX_FAULT, 950 EFX_PHY_STAT_PHY_XS_TX_FAULT, 951 EFX_PHY_STAT_PHY_XS_ALIGN, 952 EFX_PHY_STAT_PHY_XS_SYNC_A, 953 EFX_PHY_STAT_PHY_XS_SYNC_B, 954 EFX_PHY_STAT_PHY_XS_SYNC_C, 955 EFX_PHY_STAT_PHY_XS_SYNC_D, 956 EFX_PHY_STAT_AN_LINK_UP, 957 EFX_PHY_STAT_AN_MASTER, 958 EFX_PHY_STAT_AN_LOCAL_RX_OK, 959 EFX_PHY_STAT_AN_REMOTE_RX_OK, 960 EFX_PHY_STAT_CL22EXT_LINK_UP, 961 EFX_PHY_STAT_SNR_A, 962 EFX_PHY_STAT_SNR_B, 963 EFX_PHY_STAT_SNR_C, 964 EFX_PHY_STAT_SNR_D, 965 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 966 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 967 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 968 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 969 EFX_PHY_STAT_AN_COMPLETE, 970 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 971 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 972 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 973 EFX_PHY_STAT_PCS_FW_VERSION_0, 974 EFX_PHY_STAT_PCS_FW_VERSION_1, 975 EFX_PHY_STAT_PCS_FW_VERSION_2, 976 EFX_PHY_STAT_PCS_FW_VERSION_3, 977 EFX_PHY_STAT_PCS_FW_BUILD_YY, 978 EFX_PHY_STAT_PCS_FW_BUILD_MM, 979 EFX_PHY_STAT_PCS_FW_BUILD_DD, 980 EFX_PHY_STAT_PCS_OP_MODE, 981 EFX_PHY_NSTATS 982 } efx_phy_stat_t; 983 984 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 985 986 #if EFSYS_OPT_NAMES 987 988 extern const char * 989 efx_phy_stat_name( 990 __in efx_nic_t *enp, 991 __in efx_phy_stat_t stat); 992 993 #endif /* EFSYS_OPT_NAMES */ 994 995 #define EFX_PHY_STATS_SIZE 0x100 996 997 extern __checkReturn efx_rc_t 998 efx_phy_stats_update( 999 __in efx_nic_t *enp, 1000 __in efsys_mem_t *esmp, 1001 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1002 1003 #endif /* EFSYS_OPT_PHY_STATS */ 1004 1005 1006 #if EFSYS_OPT_BIST 1007 1008 typedef enum efx_bist_type_e { 1009 EFX_BIST_TYPE_UNKNOWN, 1010 EFX_BIST_TYPE_PHY_NORMAL, 1011 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1012 EFX_BIST_TYPE_PHY_CABLE_LONG, 1013 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1014 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 1015 EFX_BIST_TYPE_REG, /* Test the register memories */ 1016 EFX_BIST_TYPE_NTYPES, 1017 } efx_bist_type_t; 1018 1019 typedef enum efx_bist_result_e { 1020 EFX_BIST_RESULT_UNKNOWN, 1021 EFX_BIST_RESULT_RUNNING, 1022 EFX_BIST_RESULT_PASSED, 1023 EFX_BIST_RESULT_FAILED, 1024 } efx_bist_result_t; 1025 1026 typedef enum efx_phy_cable_status_e { 1027 EFX_PHY_CABLE_STATUS_OK, 1028 EFX_PHY_CABLE_STATUS_INVALID, 1029 EFX_PHY_CABLE_STATUS_OPEN, 1030 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1031 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1032 EFX_PHY_CABLE_STATUS_BUSY, 1033 } efx_phy_cable_status_t; 1034 1035 typedef enum efx_bist_value_e { 1036 EFX_BIST_PHY_CABLE_LENGTH_A, 1037 EFX_BIST_PHY_CABLE_LENGTH_B, 1038 EFX_BIST_PHY_CABLE_LENGTH_C, 1039 EFX_BIST_PHY_CABLE_LENGTH_D, 1040 EFX_BIST_PHY_CABLE_STATUS_A, 1041 EFX_BIST_PHY_CABLE_STATUS_B, 1042 EFX_BIST_PHY_CABLE_STATUS_C, 1043 EFX_BIST_PHY_CABLE_STATUS_D, 1044 EFX_BIST_FAULT_CODE, 1045 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1046 * response. */ 1047 EFX_BIST_MEM_TEST, 1048 EFX_BIST_MEM_ADDR, 1049 EFX_BIST_MEM_BUS, 1050 EFX_BIST_MEM_EXPECT, 1051 EFX_BIST_MEM_ACTUAL, 1052 EFX_BIST_MEM_ECC, 1053 EFX_BIST_MEM_ECC_PARITY, 1054 EFX_BIST_MEM_ECC_FATAL, 1055 EFX_BIST_NVALUES, 1056 } efx_bist_value_t; 1057 1058 extern __checkReturn efx_rc_t 1059 efx_bist_enable_offline( 1060 __in efx_nic_t *enp); 1061 1062 extern __checkReturn efx_rc_t 1063 efx_bist_start( 1064 __in efx_nic_t *enp, 1065 __in efx_bist_type_t type); 1066 1067 extern __checkReturn efx_rc_t 1068 efx_bist_poll( 1069 __in efx_nic_t *enp, 1070 __in efx_bist_type_t type, 1071 __out efx_bist_result_t *resultp, 1072 __out_opt uint32_t *value_maskp, 1073 __out_ecount_opt(count) unsigned long *valuesp, 1074 __in size_t count); 1075 1076 extern void 1077 efx_bist_stop( 1078 __in efx_nic_t *enp, 1079 __in efx_bist_type_t type); 1080 1081 #endif /* EFSYS_OPT_BIST */ 1082 1083 #define EFX_FEATURE_IPV6 0x00000001 1084 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1085 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1086 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1087 #define EFX_FEATURE_MCDI 0x00000020 1088 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1089 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1090 #define EFX_FEATURE_TURBO 0x00000100 1091 #define EFX_FEATURE_MCDI_DMA 0x00000200 1092 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1093 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1094 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1095 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1096 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1097 1098 typedef enum efx_tunnel_protocol_e { 1099 EFX_TUNNEL_PROTOCOL_NONE = 0, 1100 EFX_TUNNEL_PROTOCOL_VXLAN, 1101 EFX_TUNNEL_PROTOCOL_GENEVE, 1102 EFX_TUNNEL_PROTOCOL_NVGRE, 1103 EFX_TUNNEL_NPROTOS 1104 } efx_tunnel_protocol_t; 1105 1106 typedef struct efx_nic_cfg_s { 1107 uint32_t enc_board_type; 1108 uint32_t enc_phy_type; 1109 #if EFSYS_OPT_NAMES 1110 char enc_phy_name[21]; 1111 #endif 1112 char enc_phy_revision[21]; 1113 efx_mon_type_t enc_mon_type; 1114 #if EFSYS_OPT_MON_STATS 1115 uint32_t enc_mon_stat_dma_buf_size; 1116 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1117 #endif 1118 unsigned int enc_features; 1119 uint8_t enc_mac_addr[6]; 1120 uint8_t enc_port; /* PHY port number */ 1121 uint32_t enc_intr_vec_base; 1122 uint32_t enc_intr_limit; 1123 uint32_t enc_evq_limit; 1124 uint32_t enc_txq_limit; 1125 uint32_t enc_rxq_limit; 1126 uint32_t enc_txq_max_ndescs; 1127 uint32_t enc_buftbl_limit; 1128 uint32_t enc_piobuf_limit; 1129 uint32_t enc_piobuf_size; 1130 uint32_t enc_piobuf_min_alloc_size; 1131 uint32_t enc_evq_timer_quantum_ns; 1132 uint32_t enc_evq_timer_max_us; 1133 uint32_t enc_clk_mult; 1134 uint32_t enc_rx_prefix_size; 1135 uint32_t enc_rx_buf_align_start; 1136 uint32_t enc_rx_buf_align_end; 1137 uint32_t enc_rx_scale_max_exclusive_contexts; 1138 #if EFSYS_OPT_LOOPBACK 1139 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1140 #endif /* EFSYS_OPT_LOOPBACK */ 1141 #if EFSYS_OPT_PHY_FLAGS 1142 uint32_t enc_phy_flags_mask; 1143 #endif /* EFSYS_OPT_PHY_FLAGS */ 1144 #if EFSYS_OPT_PHY_LED_CONTROL 1145 uint32_t enc_led_mask; 1146 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1147 #if EFSYS_OPT_PHY_STATS 1148 uint64_t enc_phy_stat_mask; 1149 #endif /* EFSYS_OPT_PHY_STATS */ 1150 #if EFSYS_OPT_MCDI 1151 uint8_t enc_mcdi_mdio_channel; 1152 #if EFSYS_OPT_PHY_STATS 1153 uint32_t enc_mcdi_phy_stat_mask; 1154 #endif /* EFSYS_OPT_PHY_STATS */ 1155 #if EFSYS_OPT_MON_STATS 1156 uint32_t *enc_mcdi_sensor_maskp; 1157 uint32_t enc_mcdi_sensor_mask_size; 1158 #endif /* EFSYS_OPT_MON_STATS */ 1159 #endif /* EFSYS_OPT_MCDI */ 1160 #if EFSYS_OPT_BIST 1161 uint32_t enc_bist_mask; 1162 #endif /* EFSYS_OPT_BIST */ 1163 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1164 uint32_t enc_pf; 1165 uint32_t enc_vf; 1166 uint32_t enc_privilege_mask; 1167 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1168 boolean_t enc_bug26807_workaround; 1169 boolean_t enc_bug35388_workaround; 1170 boolean_t enc_bug41750_workaround; 1171 boolean_t enc_bug61265_workaround; 1172 boolean_t enc_rx_batching_enabled; 1173 /* Maximum number of descriptors completed in an rx event. */ 1174 uint32_t enc_rx_batch_max; 1175 /* Number of rx descriptors the hardware requires for a push. */ 1176 uint32_t enc_rx_push_align; 1177 /* Maximum amount of data in DMA descriptor */ 1178 uint32_t enc_tx_dma_desc_size_max; 1179 /* 1180 * Boundary which DMA descriptor data must not cross or 0 if no 1181 * limitation. 1182 */ 1183 uint32_t enc_tx_dma_desc_boundary; 1184 /* 1185 * Maximum number of bytes into the packet the TCP header can start for 1186 * the hardware to apply TSO packet edits. 1187 */ 1188 uint32_t enc_tx_tso_tcp_header_offset_limit; 1189 boolean_t enc_fw_assisted_tso_enabled; 1190 boolean_t enc_fw_assisted_tso_v2_enabled; 1191 /* Number of TSO contexts on the NIC (FATSOv2) */ 1192 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1193 boolean_t enc_hw_tx_insert_vlan_enabled; 1194 /* Number of PFs on the NIC */ 1195 uint32_t enc_hw_pf_count; 1196 /* Datapath firmware vadapter/vport/vswitch support */ 1197 boolean_t enc_datapath_cap_evb; 1198 boolean_t enc_rx_disable_scatter_supported; 1199 boolean_t enc_allow_set_mac_with_installed_filters; 1200 boolean_t enc_enhanced_set_mac_supported; 1201 boolean_t enc_init_evq_v2_supported; 1202 boolean_t enc_rx_packed_stream_supported; 1203 boolean_t enc_rx_var_packed_stream_supported; 1204 boolean_t enc_pm_and_rxdp_counters; 1205 boolean_t enc_mac_stats_40g_tx_size_bins; 1206 uint32_t enc_tunnel_encapsulations_supported; 1207 /* External port identifier */ 1208 uint8_t enc_external_port; 1209 uint32_t enc_mcdi_max_payload_length; 1210 /* VPD may be per-PF or global */ 1211 boolean_t enc_vpd_is_global; 1212 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1213 uint32_t enc_required_pcie_bandwidth_mbps; 1214 uint32_t enc_max_pcie_link_gen; 1215 /* Firmware verifies integrity of NVRAM updates */ 1216 uint32_t enc_nvram_update_verify_result_supported; 1217 } efx_nic_cfg_t; 1218 1219 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1220 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1221 1222 #define EFX_PCI_FUNCTION(_encp) \ 1223 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1224 1225 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1226 1227 extern const efx_nic_cfg_t * 1228 efx_nic_cfg_get( 1229 __in efx_nic_t *enp); 1230 1231 typedef struct efx_nic_fw_info_s { 1232 /* Basic FW version information */ 1233 uint16_t enfi_mc_fw_version[4]; 1234 /* 1235 * If datapath capabilities can be detected, 1236 * additional FW information is to be shown 1237 */ 1238 boolean_t enfi_dpcpu_fw_ids_valid; 1239 /* Rx and Tx datapath CPU FW IDs */ 1240 uint16_t enfi_rx_dpcpu_fw_id; 1241 uint16_t enfi_tx_dpcpu_fw_id; 1242 } efx_nic_fw_info_t; 1243 1244 extern __checkReturn efx_rc_t 1245 efx_nic_get_fw_version( 1246 __in efx_nic_t *enp, 1247 __out efx_nic_fw_info_t *enfip); 1248 1249 /* Driver resource limits (minimum required/maximum usable). */ 1250 typedef struct efx_drv_limits_s { 1251 uint32_t edl_min_evq_count; 1252 uint32_t edl_max_evq_count; 1253 1254 uint32_t edl_min_rxq_count; 1255 uint32_t edl_max_rxq_count; 1256 1257 uint32_t edl_min_txq_count; 1258 uint32_t edl_max_txq_count; 1259 1260 /* PIO blocks (sub-allocated from piobuf) */ 1261 uint32_t edl_min_pio_alloc_size; 1262 uint32_t edl_max_pio_alloc_count; 1263 } efx_drv_limits_t; 1264 1265 extern __checkReturn efx_rc_t 1266 efx_nic_set_drv_limits( 1267 __inout efx_nic_t *enp, 1268 __in efx_drv_limits_t *edlp); 1269 1270 typedef enum efx_nic_region_e { 1271 EFX_REGION_VI, /* Memory BAR UC mapping */ 1272 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1273 } efx_nic_region_t; 1274 1275 extern __checkReturn efx_rc_t 1276 efx_nic_get_bar_region( 1277 __in efx_nic_t *enp, 1278 __in efx_nic_region_t region, 1279 __out uint32_t *offsetp, 1280 __out size_t *sizep); 1281 1282 extern __checkReturn efx_rc_t 1283 efx_nic_get_vi_pool( 1284 __in efx_nic_t *enp, 1285 __out uint32_t *evq_countp, 1286 __out uint32_t *rxq_countp, 1287 __out uint32_t *txq_countp); 1288 1289 1290 #if EFSYS_OPT_VPD 1291 1292 typedef enum efx_vpd_tag_e { 1293 EFX_VPD_ID = 0x02, 1294 EFX_VPD_END = 0x0f, 1295 EFX_VPD_RO = 0x10, 1296 EFX_VPD_RW = 0x11, 1297 } efx_vpd_tag_t; 1298 1299 typedef uint16_t efx_vpd_keyword_t; 1300 1301 typedef struct efx_vpd_value_s { 1302 efx_vpd_tag_t evv_tag; 1303 efx_vpd_keyword_t evv_keyword; 1304 uint8_t evv_length; 1305 uint8_t evv_value[0x100]; 1306 } efx_vpd_value_t; 1307 1308 1309 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1310 1311 extern __checkReturn efx_rc_t 1312 efx_vpd_init( 1313 __in efx_nic_t *enp); 1314 1315 extern __checkReturn efx_rc_t 1316 efx_vpd_size( 1317 __in efx_nic_t *enp, 1318 __out size_t *sizep); 1319 1320 extern __checkReturn efx_rc_t 1321 efx_vpd_read( 1322 __in efx_nic_t *enp, 1323 __out_bcount(size) caddr_t data, 1324 __in size_t size); 1325 1326 extern __checkReturn efx_rc_t 1327 efx_vpd_verify( 1328 __in efx_nic_t *enp, 1329 __in_bcount(size) caddr_t data, 1330 __in size_t size); 1331 1332 extern __checkReturn efx_rc_t 1333 efx_vpd_reinit( 1334 __in efx_nic_t *enp, 1335 __in_bcount(size) caddr_t data, 1336 __in size_t size); 1337 1338 extern __checkReturn efx_rc_t 1339 efx_vpd_get( 1340 __in efx_nic_t *enp, 1341 __in_bcount(size) caddr_t data, 1342 __in size_t size, 1343 __inout efx_vpd_value_t *evvp); 1344 1345 extern __checkReturn efx_rc_t 1346 efx_vpd_set( 1347 __in efx_nic_t *enp, 1348 __inout_bcount(size) caddr_t data, 1349 __in size_t size, 1350 __in efx_vpd_value_t *evvp); 1351 1352 extern __checkReturn efx_rc_t 1353 efx_vpd_next( 1354 __in efx_nic_t *enp, 1355 __inout_bcount(size) caddr_t data, 1356 __in size_t size, 1357 __out efx_vpd_value_t *evvp, 1358 __inout unsigned int *contp); 1359 1360 extern __checkReturn efx_rc_t 1361 efx_vpd_write( 1362 __in efx_nic_t *enp, 1363 __in_bcount(size) caddr_t data, 1364 __in size_t size); 1365 1366 extern void 1367 efx_vpd_fini( 1368 __in efx_nic_t *enp); 1369 1370 #endif /* EFSYS_OPT_VPD */ 1371 1372 /* NVRAM */ 1373 1374 #if EFSYS_OPT_NVRAM 1375 1376 typedef enum efx_nvram_type_e { 1377 EFX_NVRAM_INVALID = 0, 1378 EFX_NVRAM_BOOTROM, 1379 EFX_NVRAM_BOOTROM_CFG, 1380 EFX_NVRAM_MC_FIRMWARE, 1381 EFX_NVRAM_MC_GOLDEN, 1382 EFX_NVRAM_PHY, 1383 EFX_NVRAM_NULLPHY, 1384 EFX_NVRAM_FPGA, 1385 EFX_NVRAM_FCFW, 1386 EFX_NVRAM_CPLD, 1387 EFX_NVRAM_FPGA_BACKUP, 1388 EFX_NVRAM_DYNAMIC_CFG, 1389 EFX_NVRAM_LICENSE, 1390 EFX_NVRAM_UEFIROM, 1391 EFX_NVRAM_MUM_FIRMWARE, 1392 EFX_NVRAM_NTYPES, 1393 } efx_nvram_type_t; 1394 1395 extern __checkReturn efx_rc_t 1396 efx_nvram_init( 1397 __in efx_nic_t *enp); 1398 1399 #if EFSYS_OPT_DIAG 1400 1401 extern __checkReturn efx_rc_t 1402 efx_nvram_test( 1403 __in efx_nic_t *enp); 1404 1405 #endif /* EFSYS_OPT_DIAG */ 1406 1407 extern __checkReturn efx_rc_t 1408 efx_nvram_size( 1409 __in efx_nic_t *enp, 1410 __in efx_nvram_type_t type, 1411 __out size_t *sizep); 1412 1413 extern __checkReturn efx_rc_t 1414 efx_nvram_rw_start( 1415 __in efx_nic_t *enp, 1416 __in efx_nvram_type_t type, 1417 __out_opt size_t *pref_chunkp); 1418 1419 extern __checkReturn efx_rc_t 1420 efx_nvram_rw_finish( 1421 __in efx_nic_t *enp, 1422 __in efx_nvram_type_t type, 1423 __out_opt uint32_t *verify_resultp); 1424 1425 extern __checkReturn efx_rc_t 1426 efx_nvram_get_version( 1427 __in efx_nic_t *enp, 1428 __in efx_nvram_type_t type, 1429 __out uint32_t *subtypep, 1430 __out_ecount(4) uint16_t version[4]); 1431 1432 extern __checkReturn efx_rc_t 1433 efx_nvram_read_chunk( 1434 __in efx_nic_t *enp, 1435 __in efx_nvram_type_t type, 1436 __in unsigned int offset, 1437 __out_bcount(size) caddr_t data, 1438 __in size_t size); 1439 1440 extern __checkReturn efx_rc_t 1441 efx_nvram_read_backup( 1442 __in efx_nic_t *enp, 1443 __in efx_nvram_type_t type, 1444 __in unsigned int offset, 1445 __out_bcount(size) caddr_t data, 1446 __in size_t size); 1447 1448 extern __checkReturn efx_rc_t 1449 efx_nvram_set_version( 1450 __in efx_nic_t *enp, 1451 __in efx_nvram_type_t type, 1452 __in_ecount(4) uint16_t version[4]); 1453 1454 extern __checkReturn efx_rc_t 1455 efx_nvram_validate( 1456 __in efx_nic_t *enp, 1457 __in efx_nvram_type_t type, 1458 __in_bcount(partn_size) caddr_t partn_data, 1459 __in size_t partn_size); 1460 1461 extern __checkReturn efx_rc_t 1462 efx_nvram_erase( 1463 __in efx_nic_t *enp, 1464 __in efx_nvram_type_t type); 1465 1466 extern __checkReturn efx_rc_t 1467 efx_nvram_write_chunk( 1468 __in efx_nic_t *enp, 1469 __in efx_nvram_type_t type, 1470 __in unsigned int offset, 1471 __in_bcount(size) caddr_t data, 1472 __in size_t size); 1473 1474 extern void 1475 efx_nvram_fini( 1476 __in efx_nic_t *enp); 1477 1478 #endif /* EFSYS_OPT_NVRAM */ 1479 1480 #if EFSYS_OPT_BOOTCFG 1481 1482 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1483 extern __checkReturn efx_rc_t 1484 efx_bootcfg_sector_info( 1485 __in efx_nic_t *enp, 1486 __in uint32_t pf, 1487 __out_opt uint32_t *sector_countp, 1488 __out size_t *offsetp, 1489 __out size_t *max_sizep); 1490 1491 /* 1492 * Copy bootcfg sector data to a target buffer which may differ in size. 1493 * Optionally corrects format errors in source buffer. 1494 */ 1495 extern efx_rc_t 1496 efx_bootcfg_copy_sector( 1497 __in efx_nic_t *enp, 1498 __inout_bcount(sector_length) 1499 uint8_t *sector, 1500 __in size_t sector_length, 1501 __out_bcount(data_size) uint8_t *data, 1502 __in size_t data_size, 1503 __in boolean_t handle_format_errors); 1504 1505 extern efx_rc_t 1506 efx_bootcfg_read( 1507 __in efx_nic_t *enp, 1508 __out_bcount(size) caddr_t data, 1509 __in size_t size); 1510 1511 extern efx_rc_t 1512 efx_bootcfg_write( 1513 __in efx_nic_t *enp, 1514 __in_bcount(size) caddr_t data, 1515 __in size_t size); 1516 1517 #endif /* EFSYS_OPT_BOOTCFG */ 1518 1519 #if EFSYS_OPT_DIAG 1520 1521 typedef enum efx_pattern_type_t { 1522 EFX_PATTERN_BYTE_INCREMENT = 0, 1523 EFX_PATTERN_ALL_THE_SAME, 1524 EFX_PATTERN_BIT_ALTERNATE, 1525 EFX_PATTERN_BYTE_ALTERNATE, 1526 EFX_PATTERN_BYTE_CHANGING, 1527 EFX_PATTERN_BIT_SWEEP, 1528 EFX_PATTERN_NTYPES 1529 } efx_pattern_type_t; 1530 1531 typedef void 1532 (*efx_sram_pattern_fn_t)( 1533 __in size_t row, 1534 __in boolean_t negate, 1535 __out efx_qword_t *eqp); 1536 1537 extern __checkReturn efx_rc_t 1538 efx_sram_test( 1539 __in efx_nic_t *enp, 1540 __in efx_pattern_type_t type); 1541 1542 #endif /* EFSYS_OPT_DIAG */ 1543 1544 extern __checkReturn efx_rc_t 1545 efx_sram_buf_tbl_set( 1546 __in efx_nic_t *enp, 1547 __in uint32_t id, 1548 __in efsys_mem_t *esmp, 1549 __in size_t n); 1550 1551 extern void 1552 efx_sram_buf_tbl_clear( 1553 __in efx_nic_t *enp, 1554 __in uint32_t id, 1555 __in size_t n); 1556 1557 #define EFX_BUF_TBL_SIZE 0x20000 1558 1559 #define EFX_BUF_SIZE 4096 1560 1561 /* EV */ 1562 1563 typedef struct efx_evq_s efx_evq_t; 1564 1565 #if EFSYS_OPT_QSTATS 1566 1567 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1568 typedef enum efx_ev_qstat_e { 1569 EV_ALL, 1570 EV_RX, 1571 EV_RX_OK, 1572 EV_RX_FRM_TRUNC, 1573 EV_RX_TOBE_DISC, 1574 EV_RX_PAUSE_FRM_ERR, 1575 EV_RX_BUF_OWNER_ID_ERR, 1576 EV_RX_IPV4_HDR_CHKSUM_ERR, 1577 EV_RX_TCP_UDP_CHKSUM_ERR, 1578 EV_RX_ETH_CRC_ERR, 1579 EV_RX_IP_FRAG_ERR, 1580 EV_RX_MCAST_PKT, 1581 EV_RX_MCAST_HASH_MATCH, 1582 EV_RX_TCP_IPV4, 1583 EV_RX_TCP_IPV6, 1584 EV_RX_UDP_IPV4, 1585 EV_RX_UDP_IPV6, 1586 EV_RX_OTHER_IPV4, 1587 EV_RX_OTHER_IPV6, 1588 EV_RX_NON_IP, 1589 EV_RX_BATCH, 1590 EV_TX, 1591 EV_TX_WQ_FF_FULL, 1592 EV_TX_PKT_ERR, 1593 EV_TX_PKT_TOO_BIG, 1594 EV_TX_UNEXPECTED, 1595 EV_GLOBAL, 1596 EV_GLOBAL_MNT, 1597 EV_DRIVER, 1598 EV_DRIVER_SRM_UPD_DONE, 1599 EV_DRIVER_TX_DESCQ_FLS_DONE, 1600 EV_DRIVER_RX_DESCQ_FLS_DONE, 1601 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1602 EV_DRIVER_RX_DSC_ERROR, 1603 EV_DRIVER_TX_DSC_ERROR, 1604 EV_DRV_GEN, 1605 EV_MCDI_RESPONSE, 1606 EV_NQSTATS 1607 } efx_ev_qstat_t; 1608 1609 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1610 1611 #endif /* EFSYS_OPT_QSTATS */ 1612 1613 extern __checkReturn efx_rc_t 1614 efx_ev_init( 1615 __in efx_nic_t *enp); 1616 1617 extern void 1618 efx_ev_fini( 1619 __in efx_nic_t *enp); 1620 1621 #define EFX_EVQ_MAXNEVS 32768 1622 #define EFX_EVQ_MINNEVS 512 1623 1624 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1625 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1626 1627 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 1628 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 1629 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 1630 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 1631 1632 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 1633 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 1634 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 1635 1636 extern __checkReturn efx_rc_t 1637 efx_ev_qcreate( 1638 __in efx_nic_t *enp, 1639 __in unsigned int index, 1640 __in efsys_mem_t *esmp, 1641 __in size_t n, 1642 __in uint32_t id, 1643 __in uint32_t us, 1644 __in uint32_t flags, 1645 __deref_out efx_evq_t **eepp); 1646 1647 extern void 1648 efx_ev_qpost( 1649 __in efx_evq_t *eep, 1650 __in uint16_t data); 1651 1652 typedef __checkReturn boolean_t 1653 (*efx_initialized_ev_t)( 1654 __in_opt void *arg); 1655 1656 #define EFX_PKT_UNICAST 0x0004 1657 #define EFX_PKT_START 0x0008 1658 1659 #define EFX_PKT_VLAN_TAGGED 0x0010 1660 #define EFX_CKSUM_TCPUDP 0x0020 1661 #define EFX_CKSUM_IPV4 0x0040 1662 #define EFX_PKT_CONT 0x0080 1663 1664 #define EFX_CHECK_VLAN 0x0100 1665 #define EFX_PKT_TCP 0x0200 1666 #define EFX_PKT_UDP 0x0400 1667 #define EFX_PKT_IPV4 0x0800 1668 1669 #define EFX_PKT_IPV6 0x1000 1670 #define EFX_PKT_PREFIX_LEN 0x2000 1671 #define EFX_ADDR_MISMATCH 0x4000 1672 #define EFX_DISCARD 0x8000 1673 1674 /* 1675 * The following flags are used only for packed stream 1676 * mode. The values for the flags are reused to fit into 16 bit, 1677 * since EFX_PKT_START and EFX_PKT_CONT are never used in 1678 * packed stream mode 1679 */ 1680 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 1681 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 1682 1683 1684 #define EFX_EV_RX_NLABELS 32 1685 #define EFX_EV_TX_NLABELS 32 1686 1687 typedef __checkReturn boolean_t 1688 (*efx_rx_ev_t)( 1689 __in_opt void *arg, 1690 __in uint32_t label, 1691 __in uint32_t id, 1692 __in uint32_t size, 1693 __in uint16_t flags); 1694 1695 #if EFSYS_OPT_RX_PACKED_STREAM 1696 1697 /* 1698 * Packed stream mode is documented in SF-112241-TC. 1699 * The general idea is that, instead of putting each incoming 1700 * packet into a separate buffer which is specified in a RX 1701 * descriptor, a large buffer is provided to the hardware and 1702 * packets are put there in a continuous stream. 1703 * The main advantage of such an approach is that RX queue refilling 1704 * happens much less frequently. 1705 */ 1706 1707 typedef __checkReturn boolean_t 1708 (*efx_rx_ps_ev_t)( 1709 __in_opt void *arg, 1710 __in uint32_t label, 1711 __in uint32_t id, 1712 __in uint32_t pkt_count, 1713 __in uint16_t flags); 1714 1715 #endif 1716 1717 typedef __checkReturn boolean_t 1718 (*efx_tx_ev_t)( 1719 __in_opt void *arg, 1720 __in uint32_t label, 1721 __in uint32_t id); 1722 1723 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1724 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1725 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1726 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1727 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1728 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1729 #define EFX_EXCEPTION_RX_ERROR 0x00000007 1730 #define EFX_EXCEPTION_TX_ERROR 0x00000008 1731 #define EFX_EXCEPTION_EV_ERROR 0x00000009 1732 1733 typedef __checkReturn boolean_t 1734 (*efx_exception_ev_t)( 1735 __in_opt void *arg, 1736 __in uint32_t label, 1737 __in uint32_t data); 1738 1739 typedef __checkReturn boolean_t 1740 (*efx_rxq_flush_done_ev_t)( 1741 __in_opt void *arg, 1742 __in uint32_t rxq_index); 1743 1744 typedef __checkReturn boolean_t 1745 (*efx_rxq_flush_failed_ev_t)( 1746 __in_opt void *arg, 1747 __in uint32_t rxq_index); 1748 1749 typedef __checkReturn boolean_t 1750 (*efx_txq_flush_done_ev_t)( 1751 __in_opt void *arg, 1752 __in uint32_t txq_index); 1753 1754 typedef __checkReturn boolean_t 1755 (*efx_software_ev_t)( 1756 __in_opt void *arg, 1757 __in uint16_t magic); 1758 1759 typedef __checkReturn boolean_t 1760 (*efx_sram_ev_t)( 1761 __in_opt void *arg, 1762 __in uint32_t code); 1763 1764 #define EFX_SRAM_CLEAR 0 1765 #define EFX_SRAM_UPDATE 1 1766 #define EFX_SRAM_ILLEGAL_CLEAR 2 1767 1768 typedef __checkReturn boolean_t 1769 (*efx_wake_up_ev_t)( 1770 __in_opt void *arg, 1771 __in uint32_t label); 1772 1773 typedef __checkReturn boolean_t 1774 (*efx_timer_ev_t)( 1775 __in_opt void *arg, 1776 __in uint32_t label); 1777 1778 typedef __checkReturn boolean_t 1779 (*efx_link_change_ev_t)( 1780 __in_opt void *arg, 1781 __in efx_link_mode_t link_mode); 1782 1783 #if EFSYS_OPT_MON_STATS 1784 1785 typedef __checkReturn boolean_t 1786 (*efx_monitor_ev_t)( 1787 __in_opt void *arg, 1788 __in efx_mon_stat_t id, 1789 __in efx_mon_stat_value_t value); 1790 1791 #endif /* EFSYS_OPT_MON_STATS */ 1792 1793 #if EFSYS_OPT_MAC_STATS 1794 1795 typedef __checkReturn boolean_t 1796 (*efx_mac_stats_ev_t)( 1797 __in_opt void *arg, 1798 __in uint32_t generation 1799 ); 1800 1801 #endif /* EFSYS_OPT_MAC_STATS */ 1802 1803 typedef struct efx_ev_callbacks_s { 1804 efx_initialized_ev_t eec_initialized; 1805 efx_rx_ev_t eec_rx; 1806 #if EFSYS_OPT_RX_PACKED_STREAM 1807 efx_rx_ps_ev_t eec_rx_ps; 1808 #endif 1809 efx_tx_ev_t eec_tx; 1810 efx_exception_ev_t eec_exception; 1811 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1812 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1813 efx_txq_flush_done_ev_t eec_txq_flush_done; 1814 efx_software_ev_t eec_software; 1815 efx_sram_ev_t eec_sram; 1816 efx_wake_up_ev_t eec_wake_up; 1817 efx_timer_ev_t eec_timer; 1818 efx_link_change_ev_t eec_link_change; 1819 #if EFSYS_OPT_MON_STATS 1820 efx_monitor_ev_t eec_monitor; 1821 #endif /* EFSYS_OPT_MON_STATS */ 1822 #if EFSYS_OPT_MAC_STATS 1823 efx_mac_stats_ev_t eec_mac_stats; 1824 #endif /* EFSYS_OPT_MAC_STATS */ 1825 } efx_ev_callbacks_t; 1826 1827 extern __checkReturn boolean_t 1828 efx_ev_qpending( 1829 __in efx_evq_t *eep, 1830 __in unsigned int count); 1831 1832 #if EFSYS_OPT_EV_PREFETCH 1833 1834 extern void 1835 efx_ev_qprefetch( 1836 __in efx_evq_t *eep, 1837 __in unsigned int count); 1838 1839 #endif /* EFSYS_OPT_EV_PREFETCH */ 1840 1841 extern void 1842 efx_ev_qpoll( 1843 __in efx_evq_t *eep, 1844 __inout unsigned int *countp, 1845 __in const efx_ev_callbacks_t *eecp, 1846 __in_opt void *arg); 1847 1848 extern __checkReturn efx_rc_t 1849 efx_ev_usecs_to_ticks( 1850 __in efx_nic_t *enp, 1851 __in unsigned int usecs, 1852 __out unsigned int *ticksp); 1853 1854 extern __checkReturn efx_rc_t 1855 efx_ev_qmoderate( 1856 __in efx_evq_t *eep, 1857 __in unsigned int us); 1858 1859 extern __checkReturn efx_rc_t 1860 efx_ev_qprime( 1861 __in efx_evq_t *eep, 1862 __in unsigned int count); 1863 1864 #if EFSYS_OPT_QSTATS 1865 1866 #if EFSYS_OPT_NAMES 1867 1868 extern const char * 1869 efx_ev_qstat_name( 1870 __in efx_nic_t *enp, 1871 __in unsigned int id); 1872 1873 #endif /* EFSYS_OPT_NAMES */ 1874 1875 extern void 1876 efx_ev_qstats_update( 1877 __in efx_evq_t *eep, 1878 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1879 1880 #endif /* EFSYS_OPT_QSTATS */ 1881 1882 extern void 1883 efx_ev_qdestroy( 1884 __in efx_evq_t *eep); 1885 1886 /* RX */ 1887 1888 extern __checkReturn efx_rc_t 1889 efx_rx_init( 1890 __inout efx_nic_t *enp); 1891 1892 extern void 1893 efx_rx_fini( 1894 __in efx_nic_t *enp); 1895 1896 #if EFSYS_OPT_RX_SCATTER 1897 __checkReturn efx_rc_t 1898 efx_rx_scatter_enable( 1899 __in efx_nic_t *enp, 1900 __in unsigned int buf_size); 1901 #endif /* EFSYS_OPT_RX_SCATTER */ 1902 1903 /* Handle to represent use of the default RSS context. */ 1904 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 1905 1906 #if EFSYS_OPT_RX_SCALE 1907 1908 typedef enum efx_rx_hash_alg_e { 1909 EFX_RX_HASHALG_LFSR = 0, 1910 EFX_RX_HASHALG_TOEPLITZ 1911 } efx_rx_hash_alg_t; 1912 1913 #define EFX_RX_HASH_IPV4 (1U << 0) 1914 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 1915 #define EFX_RX_HASH_IPV6 (1U << 2) 1916 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 1917 1918 typedef unsigned int efx_rx_hash_type_t; 1919 1920 typedef enum efx_rx_hash_support_e { 1921 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1922 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1923 } efx_rx_hash_support_t; 1924 1925 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 1926 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1927 #define EFX_MAXRSS 64 /* RX indirection entry range */ 1928 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1929 1930 typedef enum efx_rx_scale_context_type_e { 1931 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 1932 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1933 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1934 } efx_rx_scale_context_type_t; 1935 1936 extern __checkReturn efx_rc_t 1937 efx_rx_hash_default_support_get( 1938 __in efx_nic_t *enp, 1939 __out efx_rx_hash_support_t *supportp); 1940 1941 1942 extern __checkReturn efx_rc_t 1943 efx_rx_scale_default_support_get( 1944 __in efx_nic_t *enp, 1945 __out efx_rx_scale_context_type_t *typep); 1946 1947 extern __checkReturn efx_rc_t 1948 efx_rx_scale_context_alloc( 1949 __in efx_nic_t *enp, 1950 __in efx_rx_scale_context_type_t type, 1951 __in uint32_t num_queues, 1952 __out uint32_t *rss_contextp); 1953 1954 extern __checkReturn efx_rc_t 1955 efx_rx_scale_context_free( 1956 __in efx_nic_t *enp, 1957 __in uint32_t rss_context); 1958 1959 extern __checkReturn efx_rc_t 1960 efx_rx_scale_mode_set( 1961 __in efx_nic_t *enp, 1962 __in uint32_t rss_context, 1963 __in efx_rx_hash_alg_t alg, 1964 __in efx_rx_hash_type_t type, 1965 __in boolean_t insert); 1966 1967 extern __checkReturn efx_rc_t 1968 efx_rx_scale_tbl_set( 1969 __in efx_nic_t *enp, 1970 __in uint32_t rss_context, 1971 __in_ecount(n) unsigned int *table, 1972 __in size_t n); 1973 1974 extern __checkReturn efx_rc_t 1975 efx_rx_scale_key_set( 1976 __in efx_nic_t *enp, 1977 __in uint32_t rss_context, 1978 __in_ecount(n) uint8_t *key, 1979 __in size_t n); 1980 1981 extern __checkReturn uint32_t 1982 efx_pseudo_hdr_hash_get( 1983 __in efx_rxq_t *erp, 1984 __in efx_rx_hash_alg_t func, 1985 __in uint8_t *buffer); 1986 1987 #endif /* EFSYS_OPT_RX_SCALE */ 1988 1989 extern __checkReturn efx_rc_t 1990 efx_pseudo_hdr_pkt_length_get( 1991 __in efx_rxq_t *erp, 1992 __in uint8_t *buffer, 1993 __out uint16_t *pkt_lengthp); 1994 1995 #define EFX_RXQ_MAXNDESCS 4096 1996 #define EFX_RXQ_MINNDESCS 512 1997 1998 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1999 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2000 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2001 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2002 2003 typedef enum efx_rxq_type_e { 2004 EFX_RXQ_TYPE_DEFAULT, 2005 EFX_RXQ_TYPE_SCATTER, 2006 EFX_RXQ_TYPE_PACKED_STREAM_1M, 2007 EFX_RXQ_TYPE_PACKED_STREAM_512K, 2008 EFX_RXQ_TYPE_PACKED_STREAM_256K, 2009 EFX_RXQ_TYPE_PACKED_STREAM_128K, 2010 EFX_RXQ_TYPE_PACKED_STREAM_64K, 2011 EFX_RXQ_NTYPES 2012 } efx_rxq_type_t; 2013 2014 extern __checkReturn efx_rc_t 2015 efx_rx_qcreate( 2016 __in efx_nic_t *enp, 2017 __in unsigned int index, 2018 __in unsigned int label, 2019 __in efx_rxq_type_t type, 2020 __in efsys_mem_t *esmp, 2021 __in size_t n, 2022 __in uint32_t id, 2023 __in efx_evq_t *eep, 2024 __deref_out efx_rxq_t **erpp); 2025 2026 typedef struct efx_buffer_s { 2027 efsys_dma_addr_t eb_addr; 2028 size_t eb_size; 2029 boolean_t eb_eop; 2030 } efx_buffer_t; 2031 2032 typedef struct efx_desc_s { 2033 efx_qword_t ed_eq; 2034 } efx_desc_t; 2035 2036 extern void 2037 efx_rx_qpost( 2038 __in efx_rxq_t *erp, 2039 __in_ecount(n) efsys_dma_addr_t *addrp, 2040 __in size_t size, 2041 __in unsigned int n, 2042 __in unsigned int completed, 2043 __in unsigned int added); 2044 2045 extern void 2046 efx_rx_qpush( 2047 __in efx_rxq_t *erp, 2048 __in unsigned int added, 2049 __inout unsigned int *pushedp); 2050 2051 #if EFSYS_OPT_RX_PACKED_STREAM 2052 2053 extern void 2054 efx_rx_qpush_ps_credits( 2055 __in efx_rxq_t *erp); 2056 2057 extern __checkReturn uint8_t * 2058 efx_rx_qps_packet_info( 2059 __in efx_rxq_t *erp, 2060 __in uint8_t *buffer, 2061 __in uint32_t buffer_length, 2062 __in uint32_t current_offset, 2063 __out uint16_t *lengthp, 2064 __out uint32_t *next_offsetp, 2065 __out uint32_t *timestamp); 2066 #endif 2067 2068 extern __checkReturn efx_rc_t 2069 efx_rx_qflush( 2070 __in efx_rxq_t *erp); 2071 2072 extern void 2073 efx_rx_qenable( 2074 __in efx_rxq_t *erp); 2075 2076 extern void 2077 efx_rx_qdestroy( 2078 __in efx_rxq_t *erp); 2079 2080 /* TX */ 2081 2082 typedef struct efx_txq_s efx_txq_t; 2083 2084 #if EFSYS_OPT_QSTATS 2085 2086 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2087 typedef enum efx_tx_qstat_e { 2088 TX_POST, 2089 TX_POST_PIO, 2090 TX_NQSTATS 2091 } efx_tx_qstat_t; 2092 2093 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2094 2095 #endif /* EFSYS_OPT_QSTATS */ 2096 2097 extern __checkReturn efx_rc_t 2098 efx_tx_init( 2099 __in efx_nic_t *enp); 2100 2101 extern void 2102 efx_tx_fini( 2103 __in efx_nic_t *enp); 2104 2105 #define EFX_TXQ_MINNDESCS 512 2106 2107 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2108 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2109 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2110 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2111 2112 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2113 2114 #define EFX_TXQ_CKSUM_IPV4 0x0001 2115 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2116 #define EFX_TXQ_FATSOV2 0x0004 2117 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2118 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2119 2120 extern __checkReturn efx_rc_t 2121 efx_tx_qcreate( 2122 __in efx_nic_t *enp, 2123 __in unsigned int index, 2124 __in unsigned int label, 2125 __in efsys_mem_t *esmp, 2126 __in size_t n, 2127 __in uint32_t id, 2128 __in uint16_t flags, 2129 __in efx_evq_t *eep, 2130 __deref_out efx_txq_t **etpp, 2131 __out unsigned int *addedp); 2132 2133 extern __checkReturn efx_rc_t 2134 efx_tx_qpost( 2135 __in efx_txq_t *etp, 2136 __in_ecount(n) efx_buffer_t *eb, 2137 __in unsigned int n, 2138 __in unsigned int completed, 2139 __inout unsigned int *addedp); 2140 2141 extern __checkReturn efx_rc_t 2142 efx_tx_qpace( 2143 __in efx_txq_t *etp, 2144 __in unsigned int ns); 2145 2146 extern void 2147 efx_tx_qpush( 2148 __in efx_txq_t *etp, 2149 __in unsigned int added, 2150 __in unsigned int pushed); 2151 2152 extern __checkReturn efx_rc_t 2153 efx_tx_qflush( 2154 __in efx_txq_t *etp); 2155 2156 extern void 2157 efx_tx_qenable( 2158 __in efx_txq_t *etp); 2159 2160 extern __checkReturn efx_rc_t 2161 efx_tx_qpio_enable( 2162 __in efx_txq_t *etp); 2163 2164 extern void 2165 efx_tx_qpio_disable( 2166 __in efx_txq_t *etp); 2167 2168 extern __checkReturn efx_rc_t 2169 efx_tx_qpio_write( 2170 __in efx_txq_t *etp, 2171 __in_ecount(buf_length) uint8_t *buffer, 2172 __in size_t buf_length, 2173 __in size_t pio_buf_offset); 2174 2175 extern __checkReturn efx_rc_t 2176 efx_tx_qpio_post( 2177 __in efx_txq_t *etp, 2178 __in size_t pkt_length, 2179 __in unsigned int completed, 2180 __inout unsigned int *addedp); 2181 2182 extern __checkReturn efx_rc_t 2183 efx_tx_qdesc_post( 2184 __in efx_txq_t *etp, 2185 __in_ecount(n) efx_desc_t *ed, 2186 __in unsigned int n, 2187 __in unsigned int completed, 2188 __inout unsigned int *addedp); 2189 2190 extern void 2191 efx_tx_qdesc_dma_create( 2192 __in efx_txq_t *etp, 2193 __in efsys_dma_addr_t addr, 2194 __in size_t size, 2195 __in boolean_t eop, 2196 __out efx_desc_t *edp); 2197 2198 extern void 2199 efx_tx_qdesc_tso_create( 2200 __in efx_txq_t *etp, 2201 __in uint16_t ipv4_id, 2202 __in uint32_t tcp_seq, 2203 __in uint8_t tcp_flags, 2204 __out efx_desc_t *edp); 2205 2206 /* Number of FATSOv2 option descriptors */ 2207 #define EFX_TX_FATSOV2_OPT_NDESCS 2 2208 2209 /* Maximum number of DMA segments per TSO packet (not superframe) */ 2210 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2211 2212 extern void 2213 efx_tx_qdesc_tso2_create( 2214 __in efx_txq_t *etp, 2215 __in uint16_t ipv4_id, 2216 __in uint32_t tcp_seq, 2217 __in uint16_t tcp_mss, 2218 __out_ecount(count) efx_desc_t *edp, 2219 __in int count); 2220 2221 extern void 2222 efx_tx_qdesc_vlantci_create( 2223 __in efx_txq_t *etp, 2224 __in uint16_t tci, 2225 __out efx_desc_t *edp); 2226 2227 #if EFSYS_OPT_QSTATS 2228 2229 #if EFSYS_OPT_NAMES 2230 2231 extern const char * 2232 efx_tx_qstat_name( 2233 __in efx_nic_t *etp, 2234 __in unsigned int id); 2235 2236 #endif /* EFSYS_OPT_NAMES */ 2237 2238 extern void 2239 efx_tx_qstats_update( 2240 __in efx_txq_t *etp, 2241 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2242 2243 #endif /* EFSYS_OPT_QSTATS */ 2244 2245 extern void 2246 efx_tx_qdestroy( 2247 __in efx_txq_t *etp); 2248 2249 2250 /* FILTER */ 2251 2252 #if EFSYS_OPT_FILTER 2253 2254 #define EFX_ETHER_TYPE_IPV4 0x0800 2255 #define EFX_ETHER_TYPE_IPV6 0x86DD 2256 2257 #define EFX_IPPROTO_TCP 6 2258 #define EFX_IPPROTO_UDP 17 2259 #define EFX_IPPROTO_GRE 47 2260 2261 /* Use RSS to spread across multiple queues */ 2262 #define EFX_FILTER_FLAG_RX_RSS 0x01 2263 /* Enable RX scatter */ 2264 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 2265 /* 2266 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2267 * May only be set by the filter implementation for each type. 2268 * A removal request will restore the automatic filter in its place. 2269 */ 2270 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2271 /* Filter is for RX */ 2272 #define EFX_FILTER_FLAG_RX 0x08 2273 /* Filter is for TX */ 2274 #define EFX_FILTER_FLAG_TX 0x10 2275 2276 typedef unsigned int efx_filter_flags_t; 2277 2278 /* 2279 * Flags which specify the fields to match on. The values are the same as in the 2280 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 2281 */ 2282 typedef enum efx_filter_match_flags_e { 2283 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2284 * address */ 2285 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2286 * address */ 2287 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2288 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2289 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2290 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2291 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2292 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2293 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2294 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2295 * protocol */ 2296 /* For encapsulated packets, match all multicast inner frames */ 2297 EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST = 0x01000000, 2298 /* For encapsulated packets, match all unicast inner frames */ 2299 EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST = 0x02000000, 2300 /* Match otherwise-unmatched multicast and broadcast packets */ 2301 EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000, 2302 /* Match otherwise-unmatched unicast packets */ 2303 EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000, 2304 } efx_filter_match_flags_t; 2305 2306 typedef enum efx_filter_priority_s { 2307 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2308 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2309 * address list or hardware 2310 * requirements. This may only be used 2311 * by the filter implementation for 2312 * each NIC type. */ 2313 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2314 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2315 * client (e.g. SR-IOV, HyperV VMQ etc.) 2316 */ 2317 } efx_filter_priority_t; 2318 2319 /* 2320 * FIXME: All these fields are assumed to be in little-endian byte order. 2321 * It may be better for some to be big-endian. See bug42804. 2322 */ 2323 2324 typedef struct efx_filter_spec_s { 2325 uint32_t efs_match_flags; 2326 uint32_t efs_priority:2; 2327 uint32_t efs_flags:6; 2328 uint32_t efs_dmaq_id:12; 2329 uint32_t efs_rss_context; 2330 uint16_t efs_outer_vid; 2331 uint16_t efs_inner_vid; 2332 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2333 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2334 uint16_t efs_ether_type; 2335 uint8_t efs_ip_proto; 2336 efx_tunnel_protocol_t efs_encap_type; 2337 uint16_t efs_loc_port; 2338 uint16_t efs_rem_port; 2339 efx_oword_t efs_rem_host; 2340 efx_oword_t efs_loc_host; 2341 } efx_filter_spec_t; 2342 2343 2344 /* Default values for use in filter specifications */ 2345 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2346 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2347 2348 extern __checkReturn efx_rc_t 2349 efx_filter_init( 2350 __in efx_nic_t *enp); 2351 2352 extern void 2353 efx_filter_fini( 2354 __in efx_nic_t *enp); 2355 2356 extern __checkReturn efx_rc_t 2357 efx_filter_insert( 2358 __in efx_nic_t *enp, 2359 __inout efx_filter_spec_t *spec); 2360 2361 extern __checkReturn efx_rc_t 2362 efx_filter_remove( 2363 __in efx_nic_t *enp, 2364 __inout efx_filter_spec_t *spec); 2365 2366 extern __checkReturn efx_rc_t 2367 efx_filter_restore( 2368 __in efx_nic_t *enp); 2369 2370 extern __checkReturn efx_rc_t 2371 efx_filter_supported_filters( 2372 __in efx_nic_t *enp, 2373 __out_ecount(buffer_length) uint32_t *buffer, 2374 __in size_t buffer_length, 2375 __out size_t *list_lengthp); 2376 2377 extern void 2378 efx_filter_spec_init_rx( 2379 __out efx_filter_spec_t *spec, 2380 __in efx_filter_priority_t priority, 2381 __in efx_filter_flags_t flags, 2382 __in efx_rxq_t *erp); 2383 2384 extern void 2385 efx_filter_spec_init_tx( 2386 __out efx_filter_spec_t *spec, 2387 __in efx_txq_t *etp); 2388 2389 extern __checkReturn efx_rc_t 2390 efx_filter_spec_set_ipv4_local( 2391 __inout efx_filter_spec_t *spec, 2392 __in uint8_t proto, 2393 __in uint32_t host, 2394 __in uint16_t port); 2395 2396 extern __checkReturn efx_rc_t 2397 efx_filter_spec_set_ipv4_full( 2398 __inout efx_filter_spec_t *spec, 2399 __in uint8_t proto, 2400 __in uint32_t lhost, 2401 __in uint16_t lport, 2402 __in uint32_t rhost, 2403 __in uint16_t rport); 2404 2405 extern __checkReturn efx_rc_t 2406 efx_filter_spec_set_eth_local( 2407 __inout efx_filter_spec_t *spec, 2408 __in uint16_t vid, 2409 __in const uint8_t *addr); 2410 2411 extern void 2412 efx_filter_spec_set_ether_type( 2413 __inout efx_filter_spec_t *spec, 2414 __in uint16_t ether_type); 2415 2416 extern __checkReturn efx_rc_t 2417 efx_filter_spec_set_uc_def( 2418 __inout efx_filter_spec_t *spec); 2419 2420 extern __checkReturn efx_rc_t 2421 efx_filter_spec_set_mc_def( 2422 __inout efx_filter_spec_t *spec); 2423 2424 typedef enum efx_filter_inner_frame_match_e { 2425 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 2426 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 2427 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 2428 } efx_filter_inner_frame_match_t; 2429 2430 extern __checkReturn efx_rc_t 2431 efx_filter_spec_set_encap_type( 2432 __inout efx_filter_spec_t *spec, 2433 __in efx_tunnel_protocol_t encap_type, 2434 __in efx_filter_inner_frame_match_t inner_frame_match); 2435 2436 #if EFSYS_OPT_RX_SCALE 2437 extern __checkReturn efx_rc_t 2438 efx_filter_spec_set_rss_context( 2439 __inout efx_filter_spec_t *spec, 2440 __in uint32_t rss_context); 2441 #endif 2442 #endif /* EFSYS_OPT_FILTER */ 2443 2444 /* HASH */ 2445 2446 extern __checkReturn uint32_t 2447 efx_hash_dwords( 2448 __in_ecount(count) uint32_t const *input, 2449 __in size_t count, 2450 __in uint32_t init); 2451 2452 extern __checkReturn uint32_t 2453 efx_hash_bytes( 2454 __in_ecount(length) uint8_t const *input, 2455 __in size_t length, 2456 __in uint32_t init); 2457 2458 #if EFSYS_OPT_LICENSING 2459 2460 /* LICENSING */ 2461 2462 typedef struct efx_key_stats_s { 2463 uint32_t eks_valid; 2464 uint32_t eks_invalid; 2465 uint32_t eks_blacklisted; 2466 uint32_t eks_unverifiable; 2467 uint32_t eks_wrong_node; 2468 uint32_t eks_licensed_apps_lo; 2469 uint32_t eks_licensed_apps_hi; 2470 uint32_t eks_licensed_features_lo; 2471 uint32_t eks_licensed_features_hi; 2472 } efx_key_stats_t; 2473 2474 extern __checkReturn efx_rc_t 2475 efx_lic_init( 2476 __in efx_nic_t *enp); 2477 2478 extern void 2479 efx_lic_fini( 2480 __in efx_nic_t *enp); 2481 2482 extern __checkReturn boolean_t 2483 efx_lic_check_support( 2484 __in efx_nic_t *enp); 2485 2486 extern __checkReturn efx_rc_t 2487 efx_lic_update_licenses( 2488 __in efx_nic_t *enp); 2489 2490 extern __checkReturn efx_rc_t 2491 efx_lic_get_key_stats( 2492 __in efx_nic_t *enp, 2493 __out efx_key_stats_t *ksp); 2494 2495 extern __checkReturn efx_rc_t 2496 efx_lic_app_state( 2497 __in efx_nic_t *enp, 2498 __in uint64_t app_id, 2499 __out boolean_t *licensedp); 2500 2501 extern __checkReturn efx_rc_t 2502 efx_lic_get_id( 2503 __in efx_nic_t *enp, 2504 __in size_t buffer_size, 2505 __out uint32_t *typep, 2506 __out size_t *lengthp, 2507 __out_opt uint8_t *bufferp); 2508 2509 2510 extern __checkReturn efx_rc_t 2511 efx_lic_find_start( 2512 __in efx_nic_t *enp, 2513 __in_bcount(buffer_size) 2514 caddr_t bufferp, 2515 __in size_t buffer_size, 2516 __out uint32_t *startp 2517 ); 2518 2519 extern __checkReturn efx_rc_t 2520 efx_lic_find_end( 2521 __in efx_nic_t *enp, 2522 __in_bcount(buffer_size) 2523 caddr_t bufferp, 2524 __in size_t buffer_size, 2525 __in uint32_t offset, 2526 __out uint32_t *endp 2527 ); 2528 2529 extern __checkReturn __success(return != B_FALSE) boolean_t 2530 efx_lic_find_key( 2531 __in efx_nic_t *enp, 2532 __in_bcount(buffer_size) 2533 caddr_t bufferp, 2534 __in size_t buffer_size, 2535 __in uint32_t offset, 2536 __out uint32_t *startp, 2537 __out uint32_t *lengthp 2538 ); 2539 2540 extern __checkReturn __success(return != B_FALSE) boolean_t 2541 efx_lic_validate_key( 2542 __in efx_nic_t *enp, 2543 __in_bcount(length) caddr_t keyp, 2544 __in uint32_t length 2545 ); 2546 2547 extern __checkReturn efx_rc_t 2548 efx_lic_read_key( 2549 __in efx_nic_t *enp, 2550 __in_bcount(buffer_size) 2551 caddr_t bufferp, 2552 __in size_t buffer_size, 2553 __in uint32_t offset, 2554 __in uint32_t length, 2555 __out_bcount_part(key_max_size, *lengthp) 2556 caddr_t keyp, 2557 __in size_t key_max_size, 2558 __out uint32_t *lengthp 2559 ); 2560 2561 extern __checkReturn efx_rc_t 2562 efx_lic_write_key( 2563 __in efx_nic_t *enp, 2564 __in_bcount(buffer_size) 2565 caddr_t bufferp, 2566 __in size_t buffer_size, 2567 __in uint32_t offset, 2568 __in_bcount(length) caddr_t keyp, 2569 __in uint32_t length, 2570 __out uint32_t *lengthp 2571 ); 2572 2573 __checkReturn efx_rc_t 2574 efx_lic_delete_key( 2575 __in efx_nic_t *enp, 2576 __in_bcount(buffer_size) 2577 caddr_t bufferp, 2578 __in size_t buffer_size, 2579 __in uint32_t offset, 2580 __in uint32_t length, 2581 __in uint32_t end, 2582 __out uint32_t *deltap 2583 ); 2584 2585 extern __checkReturn efx_rc_t 2586 efx_lic_create_partition( 2587 __in efx_nic_t *enp, 2588 __in_bcount(buffer_size) 2589 caddr_t bufferp, 2590 __in size_t buffer_size 2591 ); 2592 2593 extern __checkReturn efx_rc_t 2594 efx_lic_finish_partition( 2595 __in efx_nic_t *enp, 2596 __in_bcount(buffer_size) 2597 caddr_t bufferp, 2598 __in size_t buffer_size 2599 ); 2600 2601 #endif /* EFSYS_OPT_LICENSING */ 2602 2603 2604 2605 #ifdef __cplusplus 2606 } 2607 #endif 2608 2609 #endif /* _SYS_EFX_H */ 2610