1 /*- 2 * Copyright (c) 2006-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EFX_H 34 #define _SYS_EFX_H 35 36 #include "efsys.h" 37 #include "efx_check.h" 38 #include "efx_phy_ids.h" 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #define EFX_STATIC_ASSERT(_cond) \ 45 ((void)sizeof(char[(_cond) ? 1 : -1])) 46 47 #define EFX_ARRAY_SIZE(_array) \ 48 (sizeof(_array) / sizeof((_array)[0])) 49 50 #define EFX_FIELD_OFFSET(_type, _field) \ 51 ((size_t) &(((_type *)0)->_field)) 52 53 /* Return codes */ 54 55 typedef __success(return == 0) int efx_rc_t; 56 57 58 /* Chip families */ 59 60 typedef enum efx_family_e { 61 EFX_FAMILY_INVALID, 62 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 63 EFX_FAMILY_SIENA, 64 EFX_FAMILY_HUNTINGTON, 65 EFX_FAMILY_MEDFORD, 66 EFX_FAMILY_NTYPES 67 } efx_family_t; 68 69 extern __checkReturn efx_rc_t 70 efx_family( 71 __in uint16_t venid, 72 __in uint16_t devid, 73 __out efx_family_t *efp); 74 75 76 #define EFX_PCI_VENID_SFC 0x1924 77 78 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 79 80 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 81 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 82 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 83 84 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 85 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 86 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 87 88 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 89 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 90 91 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 92 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 93 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 94 95 #define EFX_MEM_BAR 2 96 97 /* Error codes */ 98 99 enum { 100 EFX_ERR_INVALID, 101 EFX_ERR_SRAM_OOB, 102 EFX_ERR_BUFID_DC_OOB, 103 EFX_ERR_MEM_PERR, 104 EFX_ERR_RBUF_OWN, 105 EFX_ERR_TBUF_OWN, 106 EFX_ERR_RDESQ_OWN, 107 EFX_ERR_TDESQ_OWN, 108 EFX_ERR_EVQ_OWN, 109 EFX_ERR_EVFF_OFLO, 110 EFX_ERR_ILL_ADDR, 111 EFX_ERR_SRAM_PERR, 112 EFX_ERR_NCODES 113 }; 114 115 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 116 extern __checkReturn uint32_t 117 efx_crc32_calculate( 118 __in uint32_t crc_init, 119 __in_ecount(length) uint8_t const *input, 120 __in int length); 121 122 123 /* Type prototypes */ 124 125 typedef struct efx_rxq_s efx_rxq_t; 126 127 /* NIC */ 128 129 typedef struct efx_nic_s efx_nic_t; 130 131 #define EFX_NIC_FUNC_PRIMARY 0x00000001 132 #define EFX_NIC_FUNC_LINKCTRL 0x00000002 133 #define EFX_NIC_FUNC_TRUSTED 0x00000004 134 135 136 extern __checkReturn efx_rc_t 137 efx_nic_create( 138 __in efx_family_t family, 139 __in efsys_identifier_t *esip, 140 __in efsys_bar_t *esbp, 141 __in efsys_lock_t *eslp, 142 __deref_out efx_nic_t **enpp); 143 144 extern __checkReturn efx_rc_t 145 efx_nic_probe( 146 __in efx_nic_t *enp); 147 148 extern __checkReturn efx_rc_t 149 efx_nic_init( 150 __in efx_nic_t *enp); 151 152 extern __checkReturn efx_rc_t 153 efx_nic_reset( 154 __in efx_nic_t *enp); 155 156 #if EFSYS_OPT_DIAG 157 158 extern __checkReturn efx_rc_t 159 efx_nic_register_test( 160 __in efx_nic_t *enp); 161 162 #endif /* EFSYS_OPT_DIAG */ 163 164 extern void 165 efx_nic_fini( 166 __in efx_nic_t *enp); 167 168 extern void 169 efx_nic_unprobe( 170 __in efx_nic_t *enp); 171 172 extern void 173 efx_nic_destroy( 174 __in efx_nic_t *enp); 175 176 #define EFX_PCIE_LINK_SPEED_GEN1 1 177 #define EFX_PCIE_LINK_SPEED_GEN2 2 178 #define EFX_PCIE_LINK_SPEED_GEN3 3 179 180 typedef enum efx_pcie_link_performance_e { 181 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 182 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 184 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 185 } efx_pcie_link_performance_t; 186 187 extern __checkReturn efx_rc_t 188 efx_nic_calculate_pcie_link_bandwidth( 189 __in uint32_t pcie_link_width, 190 __in uint32_t pcie_link_gen, 191 __out uint32_t *bandwidth_mbpsp); 192 193 extern __checkReturn efx_rc_t 194 efx_nic_check_pcie_link_speed( 195 __in efx_nic_t *enp, 196 __in uint32_t pcie_link_width, 197 __in uint32_t pcie_link_gen, 198 __out efx_pcie_link_performance_t *resultp); 199 200 #if EFSYS_OPT_MCDI 201 202 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 203 /* Huntington and Medford require MCDIv2 commands */ 204 #define WITH_MCDI_V2 1 205 #endif 206 207 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 208 209 typedef enum efx_mcdi_exception_e { 210 EFX_MCDI_EXCEPTION_MC_REBOOT, 211 EFX_MCDI_EXCEPTION_MC_BADASSERT, 212 } efx_mcdi_exception_t; 213 214 #if EFSYS_OPT_MCDI_LOGGING 215 typedef enum efx_log_msg_e 216 { 217 EFX_LOG_INVALID, 218 EFX_LOG_MCDI_REQUEST, 219 EFX_LOG_MCDI_RESPONSE, 220 } efx_log_msg_t; 221 #endif /* EFSYS_OPT_MCDI_LOGGING */ 222 223 typedef struct efx_mcdi_transport_s { 224 void *emt_context; 225 efsys_mem_t *emt_dma_mem; 226 void (*emt_execute)(void *, efx_mcdi_req_t *); 227 void (*emt_ev_cpl)(void *); 228 void (*emt_exception)(void *, efx_mcdi_exception_t); 229 #if EFSYS_OPT_MCDI_LOGGING 230 void (*emt_logger)(void *, efx_log_msg_t, 231 void *, size_t, void *, size_t); 232 #endif /* EFSYS_OPT_MCDI_LOGGING */ 233 #if EFSYS_OPT_MCDI_PROXY_AUTH 234 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 235 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 236 } efx_mcdi_transport_t; 237 238 extern __checkReturn efx_rc_t 239 efx_mcdi_init( 240 __in efx_nic_t *enp, 241 __in const efx_mcdi_transport_t *mtp); 242 243 extern __checkReturn efx_rc_t 244 efx_mcdi_reboot( 245 __in efx_nic_t *enp); 246 247 void 248 efx_mcdi_new_epoch( 249 __in efx_nic_t *enp); 250 251 extern void 252 efx_mcdi_request_start( 253 __in efx_nic_t *enp, 254 __in efx_mcdi_req_t *emrp, 255 __in boolean_t ev_cpl); 256 257 extern __checkReturn boolean_t 258 efx_mcdi_request_poll( 259 __in efx_nic_t *enp); 260 261 extern __checkReturn boolean_t 262 efx_mcdi_request_abort( 263 __in efx_nic_t *enp); 264 265 extern void 266 efx_mcdi_fini( 267 __in efx_nic_t *enp); 268 269 #endif /* EFSYS_OPT_MCDI */ 270 271 /* INTR */ 272 273 #define EFX_NINTR_SIENA 1024 274 275 typedef enum efx_intr_type_e { 276 EFX_INTR_INVALID = 0, 277 EFX_INTR_LINE, 278 EFX_INTR_MESSAGE, 279 EFX_INTR_NTYPES 280 } efx_intr_type_t; 281 282 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 283 284 extern __checkReturn efx_rc_t 285 efx_intr_init( 286 __in efx_nic_t *enp, 287 __in efx_intr_type_t type, 288 __in efsys_mem_t *esmp); 289 290 extern void 291 efx_intr_enable( 292 __in efx_nic_t *enp); 293 294 extern void 295 efx_intr_disable( 296 __in efx_nic_t *enp); 297 298 extern void 299 efx_intr_disable_unlocked( 300 __in efx_nic_t *enp); 301 302 #define EFX_INTR_NEVQS 32 303 304 extern __checkReturn efx_rc_t 305 efx_intr_trigger( 306 __in efx_nic_t *enp, 307 __in unsigned int level); 308 309 extern void 310 efx_intr_status_line( 311 __in efx_nic_t *enp, 312 __out boolean_t *fatalp, 313 __out uint32_t *maskp); 314 315 extern void 316 efx_intr_status_message( 317 __in efx_nic_t *enp, 318 __in unsigned int message, 319 __out boolean_t *fatalp); 320 321 extern void 322 efx_intr_fatal( 323 __in efx_nic_t *enp); 324 325 extern void 326 efx_intr_fini( 327 __in efx_nic_t *enp); 328 329 /* MAC */ 330 331 #if EFSYS_OPT_MAC_STATS 332 333 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 334 typedef enum efx_mac_stat_e { 335 EFX_MAC_RX_OCTETS, 336 EFX_MAC_RX_PKTS, 337 EFX_MAC_RX_UNICST_PKTS, 338 EFX_MAC_RX_MULTICST_PKTS, 339 EFX_MAC_RX_BRDCST_PKTS, 340 EFX_MAC_RX_PAUSE_PKTS, 341 EFX_MAC_RX_LE_64_PKTS, 342 EFX_MAC_RX_65_TO_127_PKTS, 343 EFX_MAC_RX_128_TO_255_PKTS, 344 EFX_MAC_RX_256_TO_511_PKTS, 345 EFX_MAC_RX_512_TO_1023_PKTS, 346 EFX_MAC_RX_1024_TO_15XX_PKTS, 347 EFX_MAC_RX_GE_15XX_PKTS, 348 EFX_MAC_RX_ERRORS, 349 EFX_MAC_RX_FCS_ERRORS, 350 EFX_MAC_RX_DROP_EVENTS, 351 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 352 EFX_MAC_RX_SYMBOL_ERRORS, 353 EFX_MAC_RX_ALIGN_ERRORS, 354 EFX_MAC_RX_INTERNAL_ERRORS, 355 EFX_MAC_RX_JABBER_PKTS, 356 EFX_MAC_RX_LANE0_CHAR_ERR, 357 EFX_MAC_RX_LANE1_CHAR_ERR, 358 EFX_MAC_RX_LANE2_CHAR_ERR, 359 EFX_MAC_RX_LANE3_CHAR_ERR, 360 EFX_MAC_RX_LANE0_DISP_ERR, 361 EFX_MAC_RX_LANE1_DISP_ERR, 362 EFX_MAC_RX_LANE2_DISP_ERR, 363 EFX_MAC_RX_LANE3_DISP_ERR, 364 EFX_MAC_RX_MATCH_FAULT, 365 EFX_MAC_RX_NODESC_DROP_CNT, 366 EFX_MAC_TX_OCTETS, 367 EFX_MAC_TX_PKTS, 368 EFX_MAC_TX_UNICST_PKTS, 369 EFX_MAC_TX_MULTICST_PKTS, 370 EFX_MAC_TX_BRDCST_PKTS, 371 EFX_MAC_TX_PAUSE_PKTS, 372 EFX_MAC_TX_LE_64_PKTS, 373 EFX_MAC_TX_65_TO_127_PKTS, 374 EFX_MAC_TX_128_TO_255_PKTS, 375 EFX_MAC_TX_256_TO_511_PKTS, 376 EFX_MAC_TX_512_TO_1023_PKTS, 377 EFX_MAC_TX_1024_TO_15XX_PKTS, 378 EFX_MAC_TX_GE_15XX_PKTS, 379 EFX_MAC_TX_ERRORS, 380 EFX_MAC_TX_SGL_COL_PKTS, 381 EFX_MAC_TX_MULT_COL_PKTS, 382 EFX_MAC_TX_EX_COL_PKTS, 383 EFX_MAC_TX_LATE_COL_PKTS, 384 EFX_MAC_TX_DEF_PKTS, 385 EFX_MAC_TX_EX_DEF_PKTS, 386 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 387 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 388 EFX_MAC_PM_TRUNC_VFIFO_FULL, 389 EFX_MAC_PM_DISCARD_VFIFO_FULL, 390 EFX_MAC_PM_TRUNC_QBB, 391 EFX_MAC_PM_DISCARD_QBB, 392 EFX_MAC_PM_DISCARD_MAPPING, 393 EFX_MAC_RXDP_Q_DISABLED_PKTS, 394 EFX_MAC_RXDP_DI_DROPPED_PKTS, 395 EFX_MAC_RXDP_STREAMING_PKTS, 396 EFX_MAC_RXDP_HLB_FETCH, 397 EFX_MAC_RXDP_HLB_WAIT, 398 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 399 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 400 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 401 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 402 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 403 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 404 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 405 EFX_MAC_VADAPTER_RX_BAD_BYTES, 406 EFX_MAC_VADAPTER_RX_OVERFLOW, 407 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 408 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 409 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 410 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 411 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 412 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 413 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 414 EFX_MAC_VADAPTER_TX_BAD_BYTES, 415 EFX_MAC_VADAPTER_TX_OVERFLOW, 416 EFX_MAC_NSTATS 417 } efx_mac_stat_t; 418 419 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 420 421 #endif /* EFSYS_OPT_MAC_STATS */ 422 423 typedef enum efx_link_mode_e { 424 EFX_LINK_UNKNOWN = 0, 425 EFX_LINK_DOWN, 426 EFX_LINK_10HDX, 427 EFX_LINK_10FDX, 428 EFX_LINK_100HDX, 429 EFX_LINK_100FDX, 430 EFX_LINK_1000HDX, 431 EFX_LINK_1000FDX, 432 EFX_LINK_10000FDX, 433 EFX_LINK_40000FDX, 434 EFX_LINK_NMODES 435 } efx_link_mode_t; 436 437 #define EFX_MAC_ADDR_LEN 6 438 439 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01) 440 441 #define EFX_MAC_MULTICAST_LIST_MAX 256 442 443 #define EFX_MAC_SDU_MAX 9202 444 445 #define EFX_MAC_PDU_ADJUSTMENT \ 446 (/* EtherII */ 14 \ 447 + /* VLAN */ 4 \ 448 + /* CRC */ 4 \ 449 + /* bug16011 */ 16) \ 450 451 #define EFX_MAC_PDU(_sdu) \ 452 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 453 454 /* 455 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 456 * the SDU rounded up slightly. 457 */ 458 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 459 460 #define EFX_MAC_PDU_MIN 60 461 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 462 463 extern __checkReturn efx_rc_t 464 efx_mac_pdu_get( 465 __in efx_nic_t *enp, 466 __out size_t *pdu); 467 468 extern __checkReturn efx_rc_t 469 efx_mac_pdu_set( 470 __in efx_nic_t *enp, 471 __in size_t pdu); 472 473 extern __checkReturn efx_rc_t 474 efx_mac_addr_set( 475 __in efx_nic_t *enp, 476 __in uint8_t *addr); 477 478 extern __checkReturn efx_rc_t 479 efx_mac_filter_set( 480 __in efx_nic_t *enp, 481 __in boolean_t all_unicst, 482 __in boolean_t mulcst, 483 __in boolean_t all_mulcst, 484 __in boolean_t brdcst); 485 486 extern __checkReturn efx_rc_t 487 efx_mac_multicast_list_set( 488 __in efx_nic_t *enp, 489 __in_ecount(6*count) uint8_t const *addrs, 490 __in int count); 491 492 extern __checkReturn efx_rc_t 493 efx_mac_filter_default_rxq_set( 494 __in efx_nic_t *enp, 495 __in efx_rxq_t *erp, 496 __in boolean_t using_rss); 497 498 extern void 499 efx_mac_filter_default_rxq_clear( 500 __in efx_nic_t *enp); 501 502 extern __checkReturn efx_rc_t 503 efx_mac_drain( 504 __in efx_nic_t *enp, 505 __in boolean_t enabled); 506 507 extern __checkReturn efx_rc_t 508 efx_mac_up( 509 __in efx_nic_t *enp, 510 __out boolean_t *mac_upp); 511 512 #define EFX_FCNTL_RESPOND 0x00000001 513 #define EFX_FCNTL_GENERATE 0x00000002 514 515 extern __checkReturn efx_rc_t 516 efx_mac_fcntl_set( 517 __in efx_nic_t *enp, 518 __in unsigned int fcntl, 519 __in boolean_t autoneg); 520 521 extern void 522 efx_mac_fcntl_get( 523 __in efx_nic_t *enp, 524 __out unsigned int *fcntl_wantedp, 525 __out unsigned int *fcntl_linkp); 526 527 528 #if EFSYS_OPT_MAC_STATS 529 530 #if EFSYS_OPT_NAMES 531 532 extern __checkReturn const char * 533 efx_mac_stat_name( 534 __in efx_nic_t *enp, 535 __in unsigned int id); 536 537 #endif /* EFSYS_OPT_NAMES */ 538 539 #define EFX_MAC_STATS_SIZE 0x400 540 541 /* 542 * Upload mac statistics supported by the hardware into the given buffer. 543 * 544 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 545 * and page aligned. 546 * 547 * The hardware will only DMA statistics that it understands (of course). 548 * Drivers should not make any assumptions about which statistics are 549 * supported, especially when the statistics are generated by firmware. 550 * 551 * Thus, drivers should zero this buffer before use, so that not-understood 552 * statistics read back as zero. 553 */ 554 extern __checkReturn efx_rc_t 555 efx_mac_stats_upload( 556 __in efx_nic_t *enp, 557 __in efsys_mem_t *esmp); 558 559 extern __checkReturn efx_rc_t 560 efx_mac_stats_periodic( 561 __in efx_nic_t *enp, 562 __in efsys_mem_t *esmp, 563 __in uint16_t period_ms, 564 __in boolean_t events); 565 566 extern __checkReturn efx_rc_t 567 efx_mac_stats_update( 568 __in efx_nic_t *enp, 569 __in efsys_mem_t *esmp, 570 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 571 __inout_opt uint32_t *generationp); 572 573 #endif /* EFSYS_OPT_MAC_STATS */ 574 575 /* MON */ 576 577 typedef enum efx_mon_type_e { 578 EFX_MON_INVALID = 0, 579 EFX_MON_SFC90X0, 580 EFX_MON_SFC91X0, 581 EFX_MON_SFC92X0, 582 EFX_MON_NTYPES 583 } efx_mon_type_t; 584 585 #if EFSYS_OPT_NAMES 586 587 extern const char * 588 efx_mon_name( 589 __in efx_nic_t *enp); 590 591 #endif /* EFSYS_OPT_NAMES */ 592 593 extern __checkReturn efx_rc_t 594 efx_mon_init( 595 __in efx_nic_t *enp); 596 597 #if EFSYS_OPT_MON_STATS 598 599 #define EFX_MON_STATS_PAGE_SIZE 0x100 600 #define EFX_MON_MASK_ELEMENT_SIZE 32 601 602 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */ 603 typedef enum efx_mon_stat_e { 604 EFX_MON_STAT_2_5V, 605 EFX_MON_STAT_VCCP1, 606 EFX_MON_STAT_VCC, 607 EFX_MON_STAT_5V, 608 EFX_MON_STAT_12V, 609 EFX_MON_STAT_VCCP2, 610 EFX_MON_STAT_EXT_TEMP, 611 EFX_MON_STAT_INT_TEMP, 612 EFX_MON_STAT_AIN1, 613 EFX_MON_STAT_AIN2, 614 EFX_MON_STAT_INT_COOLING, 615 EFX_MON_STAT_EXT_COOLING, 616 EFX_MON_STAT_1V, 617 EFX_MON_STAT_1_2V, 618 EFX_MON_STAT_1_8V, 619 EFX_MON_STAT_3_3V, 620 EFX_MON_STAT_1_2VA, 621 EFX_MON_STAT_VREF, 622 EFX_MON_STAT_VAOE, 623 EFX_MON_STAT_AOE_TEMP, 624 EFX_MON_STAT_PSU_AOE_TEMP, 625 EFX_MON_STAT_PSU_TEMP, 626 EFX_MON_STAT_FAN0, 627 EFX_MON_STAT_FAN1, 628 EFX_MON_STAT_FAN2, 629 EFX_MON_STAT_FAN3, 630 EFX_MON_STAT_FAN4, 631 EFX_MON_STAT_VAOE_IN, 632 EFX_MON_STAT_IAOE, 633 EFX_MON_STAT_IAOE_IN, 634 EFX_MON_STAT_NIC_POWER, 635 EFX_MON_STAT_0_9V, 636 EFX_MON_STAT_I0_9V, 637 EFX_MON_STAT_I1_2V, 638 EFX_MON_STAT_0_9V_ADC, 639 EFX_MON_STAT_INT_TEMP2, 640 EFX_MON_STAT_VREG_TEMP, 641 EFX_MON_STAT_VREG_0_9V_TEMP, 642 EFX_MON_STAT_VREG_1_2V_TEMP, 643 EFX_MON_STAT_INT_VPTAT, 644 EFX_MON_STAT_INT_ADC_TEMP, 645 EFX_MON_STAT_EXT_VPTAT, 646 EFX_MON_STAT_EXT_ADC_TEMP, 647 EFX_MON_STAT_AMBIENT_TEMP, 648 EFX_MON_STAT_AIRFLOW, 649 EFX_MON_STAT_VDD08D_VSS08D_CSR, 650 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 651 EFX_MON_STAT_HOTPOINT_TEMP, 652 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 653 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 654 EFX_MON_STAT_MUM_VCC, 655 EFX_MON_STAT_0V9_A, 656 EFX_MON_STAT_I0V9_A, 657 EFX_MON_STAT_0V9_A_TEMP, 658 EFX_MON_STAT_0V9_B, 659 EFX_MON_STAT_I0V9_B, 660 EFX_MON_STAT_0V9_B_TEMP, 661 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 662 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 663 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 664 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 665 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 666 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 667 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 668 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 669 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 670 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 671 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 672 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 673 EFX_MON_STAT_SODIMM_VOUT, 674 EFX_MON_STAT_SODIMM_0_TEMP, 675 EFX_MON_STAT_SODIMM_1_TEMP, 676 EFX_MON_STAT_PHY0_VCC, 677 EFX_MON_STAT_PHY1_VCC, 678 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 679 EFX_MON_STAT_BOARD_FRONT_TEMP, 680 EFX_MON_STAT_BOARD_BACK_TEMP, 681 EFX_MON_NSTATS 682 } efx_mon_stat_t; 683 684 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 685 686 typedef enum efx_mon_stat_state_e { 687 EFX_MON_STAT_STATE_OK = 0, 688 EFX_MON_STAT_STATE_WARNING = 1, 689 EFX_MON_STAT_STATE_FATAL = 2, 690 EFX_MON_STAT_STATE_BROKEN = 3, 691 EFX_MON_STAT_STATE_NO_READING = 4, 692 } efx_mon_stat_state_t; 693 694 typedef struct efx_mon_stat_value_s { 695 uint16_t emsv_value; 696 uint16_t emsv_state; 697 } efx_mon_stat_value_t; 698 699 #if EFSYS_OPT_NAMES 700 701 extern const char * 702 efx_mon_stat_name( 703 __in efx_nic_t *enp, 704 __in efx_mon_stat_t id); 705 706 #endif /* EFSYS_OPT_NAMES */ 707 708 extern __checkReturn efx_rc_t 709 efx_mon_stats_update( 710 __in efx_nic_t *enp, 711 __in efsys_mem_t *esmp, 712 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 713 714 #endif /* EFSYS_OPT_MON_STATS */ 715 716 extern void 717 efx_mon_fini( 718 __in efx_nic_t *enp); 719 720 /* PHY */ 721 722 extern __checkReturn efx_rc_t 723 efx_phy_verify( 724 __in efx_nic_t *enp); 725 726 #if EFSYS_OPT_PHY_LED_CONTROL 727 728 typedef enum efx_phy_led_mode_e { 729 EFX_PHY_LED_DEFAULT = 0, 730 EFX_PHY_LED_OFF, 731 EFX_PHY_LED_ON, 732 EFX_PHY_LED_FLASH, 733 EFX_PHY_LED_NMODES 734 } efx_phy_led_mode_t; 735 736 extern __checkReturn efx_rc_t 737 efx_phy_led_set( 738 __in efx_nic_t *enp, 739 __in efx_phy_led_mode_t mode); 740 741 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 742 743 extern __checkReturn efx_rc_t 744 efx_port_init( 745 __in efx_nic_t *enp); 746 747 #if EFSYS_OPT_LOOPBACK 748 749 typedef enum efx_loopback_type_e { 750 EFX_LOOPBACK_OFF = 0, 751 EFX_LOOPBACK_DATA = 1, 752 EFX_LOOPBACK_GMAC = 2, 753 EFX_LOOPBACK_XGMII = 3, 754 EFX_LOOPBACK_XGXS = 4, 755 EFX_LOOPBACK_XAUI = 5, 756 EFX_LOOPBACK_GMII = 6, 757 EFX_LOOPBACK_SGMII = 7, 758 EFX_LOOPBACK_XGBR = 8, 759 EFX_LOOPBACK_XFI = 9, 760 EFX_LOOPBACK_XAUI_FAR = 10, 761 EFX_LOOPBACK_GMII_FAR = 11, 762 EFX_LOOPBACK_SGMII_FAR = 12, 763 EFX_LOOPBACK_XFI_FAR = 13, 764 EFX_LOOPBACK_GPHY = 14, 765 EFX_LOOPBACK_PHY_XS = 15, 766 EFX_LOOPBACK_PCS = 16, 767 EFX_LOOPBACK_PMA_PMD = 17, 768 EFX_LOOPBACK_XPORT = 18, 769 EFX_LOOPBACK_XGMII_WS = 19, 770 EFX_LOOPBACK_XAUI_WS = 20, 771 EFX_LOOPBACK_XAUI_WS_FAR = 21, 772 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 773 EFX_LOOPBACK_GMII_WS = 23, 774 EFX_LOOPBACK_XFI_WS = 24, 775 EFX_LOOPBACK_XFI_WS_FAR = 25, 776 EFX_LOOPBACK_PHYXS_WS = 26, 777 EFX_LOOPBACK_PMA_INT = 27, 778 EFX_LOOPBACK_SD_NEAR = 28, 779 EFX_LOOPBACK_SD_FAR = 29, 780 EFX_LOOPBACK_PMA_INT_WS = 30, 781 EFX_LOOPBACK_SD_FEP2_WS = 31, 782 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 783 EFX_LOOPBACK_SD_FEP_WS = 33, 784 EFX_LOOPBACK_SD_FES_WS = 34, 785 EFX_LOOPBACK_NTYPES 786 } efx_loopback_type_t; 787 788 typedef enum efx_loopback_kind_e { 789 EFX_LOOPBACK_KIND_OFF = 0, 790 EFX_LOOPBACK_KIND_ALL, 791 EFX_LOOPBACK_KIND_MAC, 792 EFX_LOOPBACK_KIND_PHY, 793 EFX_LOOPBACK_NKINDS 794 } efx_loopback_kind_t; 795 796 extern void 797 efx_loopback_mask( 798 __in efx_loopback_kind_t loopback_kind, 799 __out efx_qword_t *maskp); 800 801 extern __checkReturn efx_rc_t 802 efx_port_loopback_set( 803 __in efx_nic_t *enp, 804 __in efx_link_mode_t link_mode, 805 __in efx_loopback_type_t type); 806 807 #if EFSYS_OPT_NAMES 808 809 extern __checkReturn const char * 810 efx_loopback_type_name( 811 __in efx_nic_t *enp, 812 __in efx_loopback_type_t type); 813 814 #endif /* EFSYS_OPT_NAMES */ 815 816 #endif /* EFSYS_OPT_LOOPBACK */ 817 818 extern __checkReturn efx_rc_t 819 efx_port_poll( 820 __in efx_nic_t *enp, 821 __out_opt efx_link_mode_t *link_modep); 822 823 extern void 824 efx_port_fini( 825 __in efx_nic_t *enp); 826 827 typedef enum efx_phy_cap_type_e { 828 EFX_PHY_CAP_INVALID = 0, 829 EFX_PHY_CAP_10HDX, 830 EFX_PHY_CAP_10FDX, 831 EFX_PHY_CAP_100HDX, 832 EFX_PHY_CAP_100FDX, 833 EFX_PHY_CAP_1000HDX, 834 EFX_PHY_CAP_1000FDX, 835 EFX_PHY_CAP_10000FDX, 836 EFX_PHY_CAP_PAUSE, 837 EFX_PHY_CAP_ASYM, 838 EFX_PHY_CAP_AN, 839 EFX_PHY_CAP_40000FDX, 840 EFX_PHY_CAP_NTYPES 841 } efx_phy_cap_type_t; 842 843 844 #define EFX_PHY_CAP_CURRENT 0x00000000 845 #define EFX_PHY_CAP_DEFAULT 0x00000001 846 #define EFX_PHY_CAP_PERM 0x00000002 847 848 extern void 849 efx_phy_adv_cap_get( 850 __in efx_nic_t *enp, 851 __in uint32_t flag, 852 __out uint32_t *maskp); 853 854 extern __checkReturn efx_rc_t 855 efx_phy_adv_cap_set( 856 __in efx_nic_t *enp, 857 __in uint32_t mask); 858 859 extern void 860 efx_phy_lp_cap_get( 861 __in efx_nic_t *enp, 862 __out uint32_t *maskp); 863 864 extern __checkReturn efx_rc_t 865 efx_phy_oui_get( 866 __in efx_nic_t *enp, 867 __out uint32_t *ouip); 868 869 typedef enum efx_phy_media_type_e { 870 EFX_PHY_MEDIA_INVALID = 0, 871 EFX_PHY_MEDIA_XAUI, 872 EFX_PHY_MEDIA_CX4, 873 EFX_PHY_MEDIA_KX4, 874 EFX_PHY_MEDIA_XFP, 875 EFX_PHY_MEDIA_SFP_PLUS, 876 EFX_PHY_MEDIA_BASE_T, 877 EFX_PHY_MEDIA_QSFP_PLUS, 878 EFX_PHY_MEDIA_NTYPES 879 } efx_phy_media_type_t; 880 881 /* Get the type of medium currently used. If the board has ports for 882 * modules, a module is present, and we recognise the media type of 883 * the module, then this will be the media type of the module. 884 * Otherwise it will be the media type of the port. 885 */ 886 extern void 887 efx_phy_media_type_get( 888 __in efx_nic_t *enp, 889 __out efx_phy_media_type_t *typep); 890 891 extern efx_rc_t 892 efx_phy_module_get_info( 893 __in efx_nic_t *enp, 894 __in uint8_t dev_addr, 895 __in uint8_t offset, 896 __in uint8_t len, 897 __out_bcount(len) uint8_t *data); 898 899 #if EFSYS_OPT_PHY_STATS 900 901 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 902 typedef enum efx_phy_stat_e { 903 EFX_PHY_STAT_OUI, 904 EFX_PHY_STAT_PMA_PMD_LINK_UP, 905 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 906 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 907 EFX_PHY_STAT_PMA_PMD_REV_A, 908 EFX_PHY_STAT_PMA_PMD_REV_B, 909 EFX_PHY_STAT_PMA_PMD_REV_C, 910 EFX_PHY_STAT_PMA_PMD_REV_D, 911 EFX_PHY_STAT_PCS_LINK_UP, 912 EFX_PHY_STAT_PCS_RX_FAULT, 913 EFX_PHY_STAT_PCS_TX_FAULT, 914 EFX_PHY_STAT_PCS_BER, 915 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 916 EFX_PHY_STAT_PHY_XS_LINK_UP, 917 EFX_PHY_STAT_PHY_XS_RX_FAULT, 918 EFX_PHY_STAT_PHY_XS_TX_FAULT, 919 EFX_PHY_STAT_PHY_XS_ALIGN, 920 EFX_PHY_STAT_PHY_XS_SYNC_A, 921 EFX_PHY_STAT_PHY_XS_SYNC_B, 922 EFX_PHY_STAT_PHY_XS_SYNC_C, 923 EFX_PHY_STAT_PHY_XS_SYNC_D, 924 EFX_PHY_STAT_AN_LINK_UP, 925 EFX_PHY_STAT_AN_MASTER, 926 EFX_PHY_STAT_AN_LOCAL_RX_OK, 927 EFX_PHY_STAT_AN_REMOTE_RX_OK, 928 EFX_PHY_STAT_CL22EXT_LINK_UP, 929 EFX_PHY_STAT_SNR_A, 930 EFX_PHY_STAT_SNR_B, 931 EFX_PHY_STAT_SNR_C, 932 EFX_PHY_STAT_SNR_D, 933 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 934 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 935 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 936 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 937 EFX_PHY_STAT_AN_COMPLETE, 938 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 939 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 940 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 941 EFX_PHY_STAT_PCS_FW_VERSION_0, 942 EFX_PHY_STAT_PCS_FW_VERSION_1, 943 EFX_PHY_STAT_PCS_FW_VERSION_2, 944 EFX_PHY_STAT_PCS_FW_VERSION_3, 945 EFX_PHY_STAT_PCS_FW_BUILD_YY, 946 EFX_PHY_STAT_PCS_FW_BUILD_MM, 947 EFX_PHY_STAT_PCS_FW_BUILD_DD, 948 EFX_PHY_STAT_PCS_OP_MODE, 949 EFX_PHY_NSTATS 950 } efx_phy_stat_t; 951 952 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 953 954 #if EFSYS_OPT_NAMES 955 956 extern const char * 957 efx_phy_stat_name( 958 __in efx_nic_t *enp, 959 __in efx_phy_stat_t stat); 960 961 #endif /* EFSYS_OPT_NAMES */ 962 963 #define EFX_PHY_STATS_SIZE 0x100 964 965 extern __checkReturn efx_rc_t 966 efx_phy_stats_update( 967 __in efx_nic_t *enp, 968 __in efsys_mem_t *esmp, 969 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 970 971 #endif /* EFSYS_OPT_PHY_STATS */ 972 973 974 #if EFSYS_OPT_BIST 975 976 typedef enum efx_bist_type_e { 977 EFX_BIST_TYPE_UNKNOWN, 978 EFX_BIST_TYPE_PHY_NORMAL, 979 EFX_BIST_TYPE_PHY_CABLE_SHORT, 980 EFX_BIST_TYPE_PHY_CABLE_LONG, 981 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 982 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 983 EFX_BIST_TYPE_REG, /* Test the register memories */ 984 EFX_BIST_TYPE_NTYPES, 985 } efx_bist_type_t; 986 987 typedef enum efx_bist_result_e { 988 EFX_BIST_RESULT_UNKNOWN, 989 EFX_BIST_RESULT_RUNNING, 990 EFX_BIST_RESULT_PASSED, 991 EFX_BIST_RESULT_FAILED, 992 } efx_bist_result_t; 993 994 typedef enum efx_phy_cable_status_e { 995 EFX_PHY_CABLE_STATUS_OK, 996 EFX_PHY_CABLE_STATUS_INVALID, 997 EFX_PHY_CABLE_STATUS_OPEN, 998 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 999 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1000 EFX_PHY_CABLE_STATUS_BUSY, 1001 } efx_phy_cable_status_t; 1002 1003 typedef enum efx_bist_value_e { 1004 EFX_BIST_PHY_CABLE_LENGTH_A, 1005 EFX_BIST_PHY_CABLE_LENGTH_B, 1006 EFX_BIST_PHY_CABLE_LENGTH_C, 1007 EFX_BIST_PHY_CABLE_LENGTH_D, 1008 EFX_BIST_PHY_CABLE_STATUS_A, 1009 EFX_BIST_PHY_CABLE_STATUS_B, 1010 EFX_BIST_PHY_CABLE_STATUS_C, 1011 EFX_BIST_PHY_CABLE_STATUS_D, 1012 EFX_BIST_FAULT_CODE, 1013 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1014 * response. */ 1015 EFX_BIST_MEM_TEST, 1016 EFX_BIST_MEM_ADDR, 1017 EFX_BIST_MEM_BUS, 1018 EFX_BIST_MEM_EXPECT, 1019 EFX_BIST_MEM_ACTUAL, 1020 EFX_BIST_MEM_ECC, 1021 EFX_BIST_MEM_ECC_PARITY, 1022 EFX_BIST_MEM_ECC_FATAL, 1023 EFX_BIST_NVALUES, 1024 } efx_bist_value_t; 1025 1026 extern __checkReturn efx_rc_t 1027 efx_bist_enable_offline( 1028 __in efx_nic_t *enp); 1029 1030 extern __checkReturn efx_rc_t 1031 efx_bist_start( 1032 __in efx_nic_t *enp, 1033 __in efx_bist_type_t type); 1034 1035 extern __checkReturn efx_rc_t 1036 efx_bist_poll( 1037 __in efx_nic_t *enp, 1038 __in efx_bist_type_t type, 1039 __out efx_bist_result_t *resultp, 1040 __out_opt uint32_t *value_maskp, 1041 __out_ecount_opt(count) unsigned long *valuesp, 1042 __in size_t count); 1043 1044 extern void 1045 efx_bist_stop( 1046 __in efx_nic_t *enp, 1047 __in efx_bist_type_t type); 1048 1049 #endif /* EFSYS_OPT_BIST */ 1050 1051 #define EFX_FEATURE_IPV6 0x00000001 1052 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1053 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1054 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1055 #define EFX_FEATURE_WOL 0x00000010 1056 #define EFX_FEATURE_MCDI 0x00000020 1057 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1058 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1059 #define EFX_FEATURE_TURBO 0x00000100 1060 #define EFX_FEATURE_MCDI_DMA 0x00000200 1061 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1062 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1063 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1064 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1065 1066 typedef struct efx_nic_cfg_s { 1067 uint32_t enc_board_type; 1068 uint32_t enc_phy_type; 1069 #if EFSYS_OPT_NAMES 1070 char enc_phy_name[21]; 1071 #endif 1072 char enc_phy_revision[21]; 1073 efx_mon_type_t enc_mon_type; 1074 #if EFSYS_OPT_MON_STATS 1075 uint32_t enc_mon_stat_dma_buf_size; 1076 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1077 #endif 1078 unsigned int enc_features; 1079 uint8_t enc_mac_addr[6]; 1080 uint8_t enc_port; /* PHY port number */ 1081 uint32_t enc_func_flags; 1082 uint32_t enc_intr_vec_base; 1083 uint32_t enc_intr_limit; 1084 uint32_t enc_evq_limit; 1085 uint32_t enc_txq_limit; 1086 uint32_t enc_rxq_limit; 1087 uint32_t enc_buftbl_limit; 1088 uint32_t enc_piobuf_limit; 1089 uint32_t enc_piobuf_size; 1090 uint32_t enc_piobuf_min_alloc_size; 1091 uint32_t enc_evq_timer_quantum_ns; 1092 uint32_t enc_evq_timer_max_us; 1093 uint32_t enc_clk_mult; 1094 uint32_t enc_rx_prefix_size; 1095 uint32_t enc_rx_buf_align_start; 1096 uint32_t enc_rx_buf_align_end; 1097 #if EFSYS_OPT_LOOPBACK 1098 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1099 #endif /* EFSYS_OPT_LOOPBACK */ 1100 #if EFSYS_OPT_PHY_FLAGS 1101 uint32_t enc_phy_flags_mask; 1102 #endif /* EFSYS_OPT_PHY_FLAGS */ 1103 #if EFSYS_OPT_PHY_LED_CONTROL 1104 uint32_t enc_led_mask; 1105 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1106 #if EFSYS_OPT_PHY_STATS 1107 uint64_t enc_phy_stat_mask; 1108 #endif /* EFSYS_OPT_PHY_STATS */ 1109 #if EFSYS_OPT_SIENA 1110 uint8_t enc_mcdi_mdio_channel; 1111 #if EFSYS_OPT_PHY_STATS 1112 uint32_t enc_mcdi_phy_stat_mask; 1113 #endif /* EFSYS_OPT_PHY_STATS */ 1114 #endif /* EFSYS_OPT_SIENA */ 1115 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 1116 #if EFSYS_OPT_MON_STATS 1117 uint32_t *enc_mcdi_sensor_maskp; 1118 uint32_t enc_mcdi_sensor_mask_size; 1119 #endif /* EFSYS_OPT_MON_STATS */ 1120 #endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 1121 #if EFSYS_OPT_BIST 1122 uint32_t enc_bist_mask; 1123 #endif /* EFSYS_OPT_BIST */ 1124 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1125 uint32_t enc_pf; 1126 uint32_t enc_vf; 1127 uint32_t enc_privilege_mask; 1128 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1129 boolean_t enc_bug26807_workaround; 1130 boolean_t enc_bug35388_workaround; 1131 boolean_t enc_bug41750_workaround; 1132 boolean_t enc_rx_batching_enabled; 1133 /* Maximum number of descriptors completed in an rx event. */ 1134 uint32_t enc_rx_batch_max; 1135 /* Number of rx descriptors the hardware requires for a push. */ 1136 uint32_t enc_rx_push_align; 1137 /* 1138 * Maximum number of bytes into the packet the TCP header can start for 1139 * the hardware to apply TSO packet edits. 1140 */ 1141 uint32_t enc_tx_tso_tcp_header_offset_limit; 1142 boolean_t enc_fw_assisted_tso_enabled; 1143 boolean_t enc_fw_assisted_tso_v2_enabled; 1144 boolean_t enc_hw_tx_insert_vlan_enabled; 1145 /* Datapath firmware vadapter/vport/vswitch support */ 1146 boolean_t enc_datapath_cap_evb; 1147 boolean_t enc_rx_disable_scatter_supported; 1148 boolean_t enc_allow_set_mac_with_installed_filters; 1149 boolean_t enc_enhanced_set_mac_supported; 1150 /* External port identifier */ 1151 uint8_t enc_external_port; 1152 uint32_t enc_mcdi_max_payload_length; 1153 /* VPD may be per-PF or global */ 1154 boolean_t enc_vpd_is_global; 1155 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1156 uint32_t enc_required_pcie_bandwidth_mbps; 1157 uint32_t enc_max_pcie_link_gen; 1158 } efx_nic_cfg_t; 1159 1160 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1161 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1162 1163 #define EFX_PCI_FUNCTION(_encp) \ 1164 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1165 1166 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1167 1168 extern const efx_nic_cfg_t * 1169 efx_nic_cfg_get( 1170 __in efx_nic_t *enp); 1171 1172 /* Driver resource limits (minimum required/maximum usable). */ 1173 typedef struct efx_drv_limits_s 1174 { 1175 uint32_t edl_min_evq_count; 1176 uint32_t edl_max_evq_count; 1177 1178 uint32_t edl_min_rxq_count; 1179 uint32_t edl_max_rxq_count; 1180 1181 uint32_t edl_min_txq_count; 1182 uint32_t edl_max_txq_count; 1183 1184 /* PIO blocks (sub-allocated from piobuf) */ 1185 uint32_t edl_min_pio_alloc_size; 1186 uint32_t edl_max_pio_alloc_count; 1187 } efx_drv_limits_t; 1188 1189 extern __checkReturn efx_rc_t 1190 efx_nic_set_drv_limits( 1191 __inout efx_nic_t *enp, 1192 __in efx_drv_limits_t *edlp); 1193 1194 typedef enum efx_nic_region_e { 1195 EFX_REGION_VI, /* Memory BAR UC mapping */ 1196 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1197 } efx_nic_region_t; 1198 1199 extern __checkReturn efx_rc_t 1200 efx_nic_get_bar_region( 1201 __in efx_nic_t *enp, 1202 __in efx_nic_region_t region, 1203 __out uint32_t *offsetp, 1204 __out size_t *sizep); 1205 1206 extern __checkReturn efx_rc_t 1207 efx_nic_get_vi_pool( 1208 __in efx_nic_t *enp, 1209 __out uint32_t *evq_countp, 1210 __out uint32_t *rxq_countp, 1211 __out uint32_t *txq_countp); 1212 1213 1214 #if EFSYS_OPT_VPD 1215 1216 typedef enum efx_vpd_tag_e { 1217 EFX_VPD_ID = 0x02, 1218 EFX_VPD_END = 0x0f, 1219 EFX_VPD_RO = 0x10, 1220 EFX_VPD_RW = 0x11, 1221 } efx_vpd_tag_t; 1222 1223 typedef uint16_t efx_vpd_keyword_t; 1224 1225 typedef struct efx_vpd_value_s { 1226 efx_vpd_tag_t evv_tag; 1227 efx_vpd_keyword_t evv_keyword; 1228 uint8_t evv_length; 1229 uint8_t evv_value[0x100]; 1230 } efx_vpd_value_t; 1231 1232 1233 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1234 1235 extern __checkReturn efx_rc_t 1236 efx_vpd_init( 1237 __in efx_nic_t *enp); 1238 1239 extern __checkReturn efx_rc_t 1240 efx_vpd_size( 1241 __in efx_nic_t *enp, 1242 __out size_t *sizep); 1243 1244 extern __checkReturn efx_rc_t 1245 efx_vpd_read( 1246 __in efx_nic_t *enp, 1247 __out_bcount(size) caddr_t data, 1248 __in size_t size); 1249 1250 extern __checkReturn efx_rc_t 1251 efx_vpd_verify( 1252 __in efx_nic_t *enp, 1253 __in_bcount(size) caddr_t data, 1254 __in size_t size); 1255 1256 extern __checkReturn efx_rc_t 1257 efx_vpd_reinit( 1258 __in efx_nic_t *enp, 1259 __in_bcount(size) caddr_t data, 1260 __in size_t size); 1261 1262 extern __checkReturn efx_rc_t 1263 efx_vpd_get( 1264 __in efx_nic_t *enp, 1265 __in_bcount(size) caddr_t data, 1266 __in size_t size, 1267 __inout efx_vpd_value_t *evvp); 1268 1269 extern __checkReturn efx_rc_t 1270 efx_vpd_set( 1271 __in efx_nic_t *enp, 1272 __inout_bcount(size) caddr_t data, 1273 __in size_t size, 1274 __in efx_vpd_value_t *evvp); 1275 1276 extern __checkReturn efx_rc_t 1277 efx_vpd_next( 1278 __in efx_nic_t *enp, 1279 __inout_bcount(size) caddr_t data, 1280 __in size_t size, 1281 __out efx_vpd_value_t *evvp, 1282 __inout unsigned int *contp); 1283 1284 extern __checkReturn efx_rc_t 1285 efx_vpd_write( 1286 __in efx_nic_t *enp, 1287 __in_bcount(size) caddr_t data, 1288 __in size_t size); 1289 1290 extern void 1291 efx_vpd_fini( 1292 __in efx_nic_t *enp); 1293 1294 #endif /* EFSYS_OPT_VPD */ 1295 1296 /* NVRAM */ 1297 1298 #if EFSYS_OPT_NVRAM 1299 1300 typedef enum efx_nvram_type_e { 1301 EFX_NVRAM_INVALID = 0, 1302 EFX_NVRAM_BOOTROM, 1303 EFX_NVRAM_BOOTROM_CFG, 1304 EFX_NVRAM_MC_FIRMWARE, 1305 EFX_NVRAM_MC_GOLDEN, 1306 EFX_NVRAM_PHY, 1307 EFX_NVRAM_NULLPHY, 1308 EFX_NVRAM_FPGA, 1309 EFX_NVRAM_FCFW, 1310 EFX_NVRAM_CPLD, 1311 EFX_NVRAM_FPGA_BACKUP, 1312 EFX_NVRAM_DYNAMIC_CFG, 1313 EFX_NVRAM_LICENSE, 1314 EFX_NVRAM_NTYPES, 1315 } efx_nvram_type_t; 1316 1317 extern __checkReturn efx_rc_t 1318 efx_nvram_init( 1319 __in efx_nic_t *enp); 1320 1321 #if EFSYS_OPT_DIAG 1322 1323 extern __checkReturn efx_rc_t 1324 efx_nvram_test( 1325 __in efx_nic_t *enp); 1326 1327 #endif /* EFSYS_OPT_DIAG */ 1328 1329 extern __checkReturn efx_rc_t 1330 efx_nvram_size( 1331 __in efx_nic_t *enp, 1332 __in efx_nvram_type_t type, 1333 __out size_t *sizep); 1334 1335 extern __checkReturn efx_rc_t 1336 efx_nvram_rw_start( 1337 __in efx_nic_t *enp, 1338 __in efx_nvram_type_t type, 1339 __out_opt size_t *pref_chunkp); 1340 1341 extern void 1342 efx_nvram_rw_finish( 1343 __in efx_nic_t *enp, 1344 __in efx_nvram_type_t type); 1345 1346 extern __checkReturn efx_rc_t 1347 efx_nvram_get_version( 1348 __in efx_nic_t *enp, 1349 __in efx_nvram_type_t type, 1350 __out uint32_t *subtypep, 1351 __out_ecount(4) uint16_t version[4]); 1352 1353 extern __checkReturn efx_rc_t 1354 efx_nvram_read_chunk( 1355 __in efx_nic_t *enp, 1356 __in efx_nvram_type_t type, 1357 __in unsigned int offset, 1358 __out_bcount(size) caddr_t data, 1359 __in size_t size); 1360 1361 extern __checkReturn efx_rc_t 1362 efx_nvram_set_version( 1363 __in efx_nic_t *enp, 1364 __in efx_nvram_type_t type, 1365 __in_ecount(4) uint16_t version[4]); 1366 1367 extern __checkReturn efx_rc_t 1368 efx_nvram_validate( 1369 __in efx_nic_t *enp, 1370 __in efx_nvram_type_t type, 1371 __in_bcount(partn_size) caddr_t partn_data, 1372 __in size_t partn_size); 1373 1374 extern __checkReturn efx_rc_t 1375 efx_nvram_erase( 1376 __in efx_nic_t *enp, 1377 __in efx_nvram_type_t type); 1378 1379 extern __checkReturn efx_rc_t 1380 efx_nvram_write_chunk( 1381 __in efx_nic_t *enp, 1382 __in efx_nvram_type_t type, 1383 __in unsigned int offset, 1384 __in_bcount(size) caddr_t data, 1385 __in size_t size); 1386 1387 extern void 1388 efx_nvram_fini( 1389 __in efx_nic_t *enp); 1390 1391 #endif /* EFSYS_OPT_NVRAM */ 1392 1393 #if EFSYS_OPT_BOOTCFG 1394 1395 extern efx_rc_t 1396 efx_bootcfg_read( 1397 __in efx_nic_t *enp, 1398 __out_bcount(size) caddr_t data, 1399 __in size_t size); 1400 1401 extern efx_rc_t 1402 efx_bootcfg_write( 1403 __in efx_nic_t *enp, 1404 __in_bcount(size) caddr_t data, 1405 __in size_t size); 1406 1407 #endif /* EFSYS_OPT_BOOTCFG */ 1408 1409 #if EFSYS_OPT_WOL 1410 1411 typedef enum efx_wol_type_e { 1412 EFX_WOL_TYPE_INVALID, 1413 EFX_WOL_TYPE_MAGIC, 1414 EFX_WOL_TYPE_BITMAP, 1415 EFX_WOL_TYPE_LINK, 1416 EFX_WOL_NTYPES, 1417 } efx_wol_type_t; 1418 1419 typedef enum efx_lightsout_offload_type_e { 1420 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1421 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1422 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1423 } efx_lightsout_offload_type_t; 1424 1425 #define EFX_WOL_BITMAP_MASK_SIZE (48) 1426 #define EFX_WOL_BITMAP_VALUE_SIZE (128) 1427 1428 typedef union efx_wol_param_u { 1429 struct { 1430 uint8_t mac_addr[6]; 1431 } ewp_magic; 1432 struct { 1433 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1434 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1435 uint8_t value_len; 1436 } ewp_bitmap; 1437 } efx_wol_param_t; 1438 1439 typedef union efx_lightsout_offload_param_u { 1440 struct { 1441 uint8_t mac_addr[6]; 1442 uint32_t ip; 1443 } elop_arp; 1444 struct { 1445 uint8_t mac_addr[6]; 1446 uint32_t solicited_node[4]; 1447 uint32_t ip[4]; 1448 } elop_ns; 1449 } efx_lightsout_offload_param_t; 1450 1451 extern __checkReturn efx_rc_t 1452 efx_wol_init( 1453 __in efx_nic_t *enp); 1454 1455 extern __checkReturn efx_rc_t 1456 efx_wol_filter_clear( 1457 __in efx_nic_t *enp); 1458 1459 extern __checkReturn efx_rc_t 1460 efx_wol_filter_add( 1461 __in efx_nic_t *enp, 1462 __in efx_wol_type_t type, 1463 __in efx_wol_param_t *paramp, 1464 __out uint32_t *filter_idp); 1465 1466 extern __checkReturn efx_rc_t 1467 efx_wol_filter_remove( 1468 __in efx_nic_t *enp, 1469 __in uint32_t filter_id); 1470 1471 extern __checkReturn efx_rc_t 1472 efx_lightsout_offload_add( 1473 __in efx_nic_t *enp, 1474 __in efx_lightsout_offload_type_t type, 1475 __in efx_lightsout_offload_param_t *paramp, 1476 __out uint32_t *filter_idp); 1477 1478 extern __checkReturn efx_rc_t 1479 efx_lightsout_offload_remove( 1480 __in efx_nic_t *enp, 1481 __in efx_lightsout_offload_type_t type, 1482 __in uint32_t filter_id); 1483 1484 extern void 1485 efx_wol_fini( 1486 __in efx_nic_t *enp); 1487 1488 #endif /* EFSYS_OPT_WOL */ 1489 1490 #if EFSYS_OPT_DIAG 1491 1492 typedef enum efx_pattern_type_t { 1493 EFX_PATTERN_BYTE_INCREMENT = 0, 1494 EFX_PATTERN_ALL_THE_SAME, 1495 EFX_PATTERN_BIT_ALTERNATE, 1496 EFX_PATTERN_BYTE_ALTERNATE, 1497 EFX_PATTERN_BYTE_CHANGING, 1498 EFX_PATTERN_BIT_SWEEP, 1499 EFX_PATTERN_NTYPES 1500 } efx_pattern_type_t; 1501 1502 typedef void 1503 (*efx_sram_pattern_fn_t)( 1504 __in size_t row, 1505 __in boolean_t negate, 1506 __out efx_qword_t *eqp); 1507 1508 extern __checkReturn efx_rc_t 1509 efx_sram_test( 1510 __in efx_nic_t *enp, 1511 __in efx_pattern_type_t type); 1512 1513 #endif /* EFSYS_OPT_DIAG */ 1514 1515 extern __checkReturn efx_rc_t 1516 efx_sram_buf_tbl_set( 1517 __in efx_nic_t *enp, 1518 __in uint32_t id, 1519 __in efsys_mem_t *esmp, 1520 __in size_t n); 1521 1522 extern void 1523 efx_sram_buf_tbl_clear( 1524 __in efx_nic_t *enp, 1525 __in uint32_t id, 1526 __in size_t n); 1527 1528 #define EFX_BUF_TBL_SIZE 0x20000 1529 1530 #define EFX_BUF_SIZE 4096 1531 1532 /* EV */ 1533 1534 typedef struct efx_evq_s efx_evq_t; 1535 1536 #if EFSYS_OPT_QSTATS 1537 1538 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1539 typedef enum efx_ev_qstat_e { 1540 EV_ALL, 1541 EV_RX, 1542 EV_RX_OK, 1543 EV_RX_FRM_TRUNC, 1544 EV_RX_TOBE_DISC, 1545 EV_RX_PAUSE_FRM_ERR, 1546 EV_RX_BUF_OWNER_ID_ERR, 1547 EV_RX_IPV4_HDR_CHKSUM_ERR, 1548 EV_RX_TCP_UDP_CHKSUM_ERR, 1549 EV_RX_ETH_CRC_ERR, 1550 EV_RX_IP_FRAG_ERR, 1551 EV_RX_MCAST_PKT, 1552 EV_RX_MCAST_HASH_MATCH, 1553 EV_RX_TCP_IPV4, 1554 EV_RX_TCP_IPV6, 1555 EV_RX_UDP_IPV4, 1556 EV_RX_UDP_IPV6, 1557 EV_RX_OTHER_IPV4, 1558 EV_RX_OTHER_IPV6, 1559 EV_RX_NON_IP, 1560 EV_RX_BATCH, 1561 EV_TX, 1562 EV_TX_WQ_FF_FULL, 1563 EV_TX_PKT_ERR, 1564 EV_TX_PKT_TOO_BIG, 1565 EV_TX_UNEXPECTED, 1566 EV_GLOBAL, 1567 EV_GLOBAL_MNT, 1568 EV_DRIVER, 1569 EV_DRIVER_SRM_UPD_DONE, 1570 EV_DRIVER_TX_DESCQ_FLS_DONE, 1571 EV_DRIVER_RX_DESCQ_FLS_DONE, 1572 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1573 EV_DRIVER_RX_DSC_ERROR, 1574 EV_DRIVER_TX_DSC_ERROR, 1575 EV_DRV_GEN, 1576 EV_MCDI_RESPONSE, 1577 EV_NQSTATS 1578 } efx_ev_qstat_t; 1579 1580 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1581 1582 #endif /* EFSYS_OPT_QSTATS */ 1583 1584 extern __checkReturn efx_rc_t 1585 efx_ev_init( 1586 __in efx_nic_t *enp); 1587 1588 extern void 1589 efx_ev_fini( 1590 __in efx_nic_t *enp); 1591 1592 #define EFX_EVQ_MAXNEVS 32768 1593 #define EFX_EVQ_MINNEVS 512 1594 1595 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1596 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1597 1598 extern __checkReturn efx_rc_t 1599 efx_ev_qcreate( 1600 __in efx_nic_t *enp, 1601 __in unsigned int index, 1602 __in efsys_mem_t *esmp, 1603 __in size_t n, 1604 __in uint32_t id, 1605 __deref_out efx_evq_t **eepp); 1606 1607 extern void 1608 efx_ev_qpost( 1609 __in efx_evq_t *eep, 1610 __in uint16_t data); 1611 1612 typedef __checkReturn boolean_t 1613 (*efx_initialized_ev_t)( 1614 __in_opt void *arg); 1615 1616 #define EFX_PKT_UNICAST 0x0004 1617 #define EFX_PKT_START 0x0008 1618 1619 #define EFX_PKT_VLAN_TAGGED 0x0010 1620 #define EFX_CKSUM_TCPUDP 0x0020 1621 #define EFX_CKSUM_IPV4 0x0040 1622 #define EFX_PKT_CONT 0x0080 1623 1624 #define EFX_CHECK_VLAN 0x0100 1625 #define EFX_PKT_TCP 0x0200 1626 #define EFX_PKT_UDP 0x0400 1627 #define EFX_PKT_IPV4 0x0800 1628 1629 #define EFX_PKT_IPV6 0x1000 1630 #define EFX_PKT_PREFIX_LEN 0x2000 1631 #define EFX_ADDR_MISMATCH 0x4000 1632 #define EFX_DISCARD 0x8000 1633 1634 #define EFX_EV_RX_NLABELS 32 1635 #define EFX_EV_TX_NLABELS 32 1636 1637 typedef __checkReturn boolean_t 1638 (*efx_rx_ev_t)( 1639 __in_opt void *arg, 1640 __in uint32_t label, 1641 __in uint32_t id, 1642 __in uint32_t size, 1643 __in uint16_t flags); 1644 1645 typedef __checkReturn boolean_t 1646 (*efx_tx_ev_t)( 1647 __in_opt void *arg, 1648 __in uint32_t label, 1649 __in uint32_t id); 1650 1651 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1652 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1653 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1654 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1655 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1656 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1657 #define EFX_EXCEPTION_RX_ERROR 0x00000007 1658 #define EFX_EXCEPTION_TX_ERROR 0x00000008 1659 #define EFX_EXCEPTION_EV_ERROR 0x00000009 1660 1661 typedef __checkReturn boolean_t 1662 (*efx_exception_ev_t)( 1663 __in_opt void *arg, 1664 __in uint32_t label, 1665 __in uint32_t data); 1666 1667 typedef __checkReturn boolean_t 1668 (*efx_rxq_flush_done_ev_t)( 1669 __in_opt void *arg, 1670 __in uint32_t rxq_index); 1671 1672 typedef __checkReturn boolean_t 1673 (*efx_rxq_flush_failed_ev_t)( 1674 __in_opt void *arg, 1675 __in uint32_t rxq_index); 1676 1677 typedef __checkReturn boolean_t 1678 (*efx_txq_flush_done_ev_t)( 1679 __in_opt void *arg, 1680 __in uint32_t txq_index); 1681 1682 typedef __checkReturn boolean_t 1683 (*efx_software_ev_t)( 1684 __in_opt void *arg, 1685 __in uint16_t magic); 1686 1687 typedef __checkReturn boolean_t 1688 (*efx_sram_ev_t)( 1689 __in_opt void *arg, 1690 __in uint32_t code); 1691 1692 #define EFX_SRAM_CLEAR 0 1693 #define EFX_SRAM_UPDATE 1 1694 #define EFX_SRAM_ILLEGAL_CLEAR 2 1695 1696 typedef __checkReturn boolean_t 1697 (*efx_wake_up_ev_t)( 1698 __in_opt void *arg, 1699 __in uint32_t label); 1700 1701 typedef __checkReturn boolean_t 1702 (*efx_timer_ev_t)( 1703 __in_opt void *arg, 1704 __in uint32_t label); 1705 1706 typedef __checkReturn boolean_t 1707 (*efx_link_change_ev_t)( 1708 __in_opt void *arg, 1709 __in efx_link_mode_t link_mode); 1710 1711 #if EFSYS_OPT_MON_STATS 1712 1713 typedef __checkReturn boolean_t 1714 (*efx_monitor_ev_t)( 1715 __in_opt void *arg, 1716 __in efx_mon_stat_t id, 1717 __in efx_mon_stat_value_t value); 1718 1719 #endif /* EFSYS_OPT_MON_STATS */ 1720 1721 #if EFSYS_OPT_MAC_STATS 1722 1723 typedef __checkReturn boolean_t 1724 (*efx_mac_stats_ev_t)( 1725 __in_opt void *arg, 1726 __in uint32_t generation 1727 ); 1728 1729 #endif /* EFSYS_OPT_MAC_STATS */ 1730 1731 typedef struct efx_ev_callbacks_s { 1732 efx_initialized_ev_t eec_initialized; 1733 efx_rx_ev_t eec_rx; 1734 efx_tx_ev_t eec_tx; 1735 efx_exception_ev_t eec_exception; 1736 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1737 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1738 efx_txq_flush_done_ev_t eec_txq_flush_done; 1739 efx_software_ev_t eec_software; 1740 efx_sram_ev_t eec_sram; 1741 efx_wake_up_ev_t eec_wake_up; 1742 efx_timer_ev_t eec_timer; 1743 efx_link_change_ev_t eec_link_change; 1744 #if EFSYS_OPT_MON_STATS 1745 efx_monitor_ev_t eec_monitor; 1746 #endif /* EFSYS_OPT_MON_STATS */ 1747 #if EFSYS_OPT_MAC_STATS 1748 efx_mac_stats_ev_t eec_mac_stats; 1749 #endif /* EFSYS_OPT_MAC_STATS */ 1750 } efx_ev_callbacks_t; 1751 1752 extern __checkReturn boolean_t 1753 efx_ev_qpending( 1754 __in efx_evq_t *eep, 1755 __in unsigned int count); 1756 1757 #if EFSYS_OPT_EV_PREFETCH 1758 1759 extern void 1760 efx_ev_qprefetch( 1761 __in efx_evq_t *eep, 1762 __in unsigned int count); 1763 1764 #endif /* EFSYS_OPT_EV_PREFETCH */ 1765 1766 extern void 1767 efx_ev_qpoll( 1768 __in efx_evq_t *eep, 1769 __inout unsigned int *countp, 1770 __in const efx_ev_callbacks_t *eecp, 1771 __in_opt void *arg); 1772 1773 extern __checkReturn efx_rc_t 1774 efx_ev_qmoderate( 1775 __in efx_evq_t *eep, 1776 __in unsigned int us); 1777 1778 extern __checkReturn efx_rc_t 1779 efx_ev_qprime( 1780 __in efx_evq_t *eep, 1781 __in unsigned int count); 1782 1783 #if EFSYS_OPT_QSTATS 1784 1785 #if EFSYS_OPT_NAMES 1786 1787 extern const char * 1788 efx_ev_qstat_name( 1789 __in efx_nic_t *enp, 1790 __in unsigned int id); 1791 1792 #endif /* EFSYS_OPT_NAMES */ 1793 1794 extern void 1795 efx_ev_qstats_update( 1796 __in efx_evq_t *eep, 1797 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1798 1799 #endif /* EFSYS_OPT_QSTATS */ 1800 1801 extern void 1802 efx_ev_qdestroy( 1803 __in efx_evq_t *eep); 1804 1805 /* RX */ 1806 1807 extern __checkReturn efx_rc_t 1808 efx_rx_init( 1809 __inout efx_nic_t *enp); 1810 1811 extern void 1812 efx_rx_fini( 1813 __in efx_nic_t *enp); 1814 1815 #if EFSYS_OPT_RX_SCATTER 1816 __checkReturn efx_rc_t 1817 efx_rx_scatter_enable( 1818 __in efx_nic_t *enp, 1819 __in unsigned int buf_size); 1820 #endif /* EFSYS_OPT_RX_SCATTER */ 1821 1822 #if EFSYS_OPT_RX_SCALE 1823 1824 typedef enum efx_rx_hash_alg_e { 1825 EFX_RX_HASHALG_LFSR = 0, 1826 EFX_RX_HASHALG_TOEPLITZ 1827 } efx_rx_hash_alg_t; 1828 1829 typedef enum efx_rx_hash_type_e { 1830 EFX_RX_HASH_IPV4 = 0, 1831 EFX_RX_HASH_TCPIPV4, 1832 EFX_RX_HASH_IPV6, 1833 EFX_RX_HASH_TCPIPV6, 1834 } efx_rx_hash_type_t; 1835 1836 typedef enum efx_rx_hash_support_e { 1837 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1838 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1839 } efx_rx_hash_support_t; 1840 1841 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1842 #define EFX_MAXRSS 64 /* RX indirection entry range */ 1843 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1844 1845 typedef enum efx_rx_scale_support_e { 1846 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1847 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1848 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1849 } efx_rx_scale_support_t; 1850 1851 extern __checkReturn efx_rc_t 1852 efx_rx_hash_support_get( 1853 __in efx_nic_t *enp, 1854 __out efx_rx_hash_support_t *supportp); 1855 1856 1857 extern __checkReturn efx_rc_t 1858 efx_rx_scale_support_get( 1859 __in efx_nic_t *enp, 1860 __out efx_rx_scale_support_t *supportp); 1861 1862 extern __checkReturn efx_rc_t 1863 efx_rx_scale_mode_set( 1864 __in efx_nic_t *enp, 1865 __in efx_rx_hash_alg_t alg, 1866 __in efx_rx_hash_type_t type, 1867 __in boolean_t insert); 1868 1869 extern __checkReturn efx_rc_t 1870 efx_rx_scale_tbl_set( 1871 __in efx_nic_t *enp, 1872 __in_ecount(n) unsigned int *table, 1873 __in size_t n); 1874 1875 extern __checkReturn efx_rc_t 1876 efx_rx_scale_key_set( 1877 __in efx_nic_t *enp, 1878 __in_ecount(n) uint8_t *key, 1879 __in size_t n); 1880 1881 extern __checkReturn uint32_t 1882 efx_psuedo_hdr_hash_get( 1883 __in efx_nic_t *enp, 1884 __in efx_rx_hash_alg_t func, 1885 __in uint8_t *buffer); 1886 1887 #endif /* EFSYS_OPT_RX_SCALE */ 1888 1889 extern __checkReturn efx_rc_t 1890 efx_psuedo_hdr_pkt_length_get( 1891 __in efx_nic_t *enp, 1892 __in uint8_t *buffer, 1893 __out uint16_t *pkt_lengthp); 1894 1895 #define EFX_RXQ_MAXNDESCS 4096 1896 #define EFX_RXQ_MINNDESCS 512 1897 1898 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1899 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1900 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1901 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1902 1903 typedef enum efx_rxq_type_e { 1904 EFX_RXQ_TYPE_DEFAULT, 1905 EFX_RXQ_TYPE_SCATTER, 1906 EFX_RXQ_NTYPES 1907 } efx_rxq_type_t; 1908 1909 extern __checkReturn efx_rc_t 1910 efx_rx_qcreate( 1911 __in efx_nic_t *enp, 1912 __in unsigned int index, 1913 __in unsigned int label, 1914 __in efx_rxq_type_t type, 1915 __in efsys_mem_t *esmp, 1916 __in size_t n, 1917 __in uint32_t id, 1918 __in efx_evq_t *eep, 1919 __deref_out efx_rxq_t **erpp); 1920 1921 typedef struct efx_buffer_s { 1922 efsys_dma_addr_t eb_addr; 1923 size_t eb_size; 1924 boolean_t eb_eop; 1925 } efx_buffer_t; 1926 1927 typedef struct efx_desc_s { 1928 efx_qword_t ed_eq; 1929 } efx_desc_t; 1930 1931 extern void 1932 efx_rx_qpost( 1933 __in efx_rxq_t *erp, 1934 __in_ecount(n) efsys_dma_addr_t *addrp, 1935 __in size_t size, 1936 __in unsigned int n, 1937 __in unsigned int completed, 1938 __in unsigned int added); 1939 1940 extern void 1941 efx_rx_qpush( 1942 __in efx_rxq_t *erp, 1943 __in unsigned int added, 1944 __inout unsigned int *pushedp); 1945 1946 extern __checkReturn efx_rc_t 1947 efx_rx_qflush( 1948 __in efx_rxq_t *erp); 1949 1950 extern void 1951 efx_rx_qenable( 1952 __in efx_rxq_t *erp); 1953 1954 extern void 1955 efx_rx_qdestroy( 1956 __in efx_rxq_t *erp); 1957 1958 /* TX */ 1959 1960 typedef struct efx_txq_s efx_txq_t; 1961 1962 #if EFSYS_OPT_QSTATS 1963 1964 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 1965 typedef enum efx_tx_qstat_e { 1966 TX_POST, 1967 TX_POST_PIO, 1968 TX_NQSTATS 1969 } efx_tx_qstat_t; 1970 1971 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 1972 1973 #endif /* EFSYS_OPT_QSTATS */ 1974 1975 extern __checkReturn efx_rc_t 1976 efx_tx_init( 1977 __in efx_nic_t *enp); 1978 1979 extern void 1980 efx_tx_fini( 1981 __in efx_nic_t *enp); 1982 1983 #define EFX_BUG35388_WORKAROUND(_encp) \ 1984 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 1985 1986 #define EFX_TXQ_MAXNDESCS(_encp) \ 1987 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 1988 1989 #define EFX_TXQ_MINNDESCS 512 1990 1991 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1992 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1993 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1994 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1995 1996 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 1997 1998 #define EFX_TXQ_CKSUM_IPV4 0x0001 1999 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2000 #define EFX_TXQ_FATSOV2 0x0004 2001 2002 extern __checkReturn efx_rc_t 2003 efx_tx_qcreate( 2004 __in efx_nic_t *enp, 2005 __in unsigned int index, 2006 __in unsigned int label, 2007 __in efsys_mem_t *esmp, 2008 __in size_t n, 2009 __in uint32_t id, 2010 __in uint16_t flags, 2011 __in efx_evq_t *eep, 2012 __deref_out efx_txq_t **etpp, 2013 __out unsigned int *addedp); 2014 2015 extern __checkReturn efx_rc_t 2016 efx_tx_qpost( 2017 __in efx_txq_t *etp, 2018 __in_ecount(n) efx_buffer_t *eb, 2019 __in unsigned int n, 2020 __in unsigned int completed, 2021 __inout unsigned int *addedp); 2022 2023 extern __checkReturn efx_rc_t 2024 efx_tx_qpace( 2025 __in efx_txq_t *etp, 2026 __in unsigned int ns); 2027 2028 extern void 2029 efx_tx_qpush( 2030 __in efx_txq_t *etp, 2031 __in unsigned int added, 2032 __in unsigned int pushed); 2033 2034 extern __checkReturn efx_rc_t 2035 efx_tx_qflush( 2036 __in efx_txq_t *etp); 2037 2038 extern void 2039 efx_tx_qenable( 2040 __in efx_txq_t *etp); 2041 2042 extern __checkReturn efx_rc_t 2043 efx_tx_qpio_enable( 2044 __in efx_txq_t *etp); 2045 2046 extern void 2047 efx_tx_qpio_disable( 2048 __in efx_txq_t *etp); 2049 2050 extern __checkReturn efx_rc_t 2051 efx_tx_qpio_write( 2052 __in efx_txq_t *etp, 2053 __in_ecount(buf_length) uint8_t *buffer, 2054 __in size_t buf_length, 2055 __in size_t pio_buf_offset); 2056 2057 extern __checkReturn efx_rc_t 2058 efx_tx_qpio_post( 2059 __in efx_txq_t *etp, 2060 __in size_t pkt_length, 2061 __in unsigned int completed, 2062 __inout unsigned int *addedp); 2063 2064 extern __checkReturn efx_rc_t 2065 efx_tx_qdesc_post( 2066 __in efx_txq_t *etp, 2067 __in_ecount(n) efx_desc_t *ed, 2068 __in unsigned int n, 2069 __in unsigned int completed, 2070 __inout unsigned int *addedp); 2071 2072 extern void 2073 efx_tx_qdesc_dma_create( 2074 __in efx_txq_t *etp, 2075 __in efsys_dma_addr_t addr, 2076 __in size_t size, 2077 __in boolean_t eop, 2078 __out efx_desc_t *edp); 2079 2080 extern void 2081 efx_tx_qdesc_tso_create( 2082 __in efx_txq_t *etp, 2083 __in uint16_t ipv4_id, 2084 __in uint32_t tcp_seq, 2085 __in uint8_t tcp_flags, 2086 __out efx_desc_t *edp); 2087 2088 /* Number of FATSOv2 option descriptors */ 2089 #define EFX_TX_FATSOV2_OPT_NDESCS 2 2090 2091 /* Maximum number of DMA segments per TSO packet (not superframe) */ 2092 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2093 2094 extern void 2095 efx_tx_qdesc_tso2_create( 2096 __in efx_txq_t *etp, 2097 __in uint16_t ipv4_id, 2098 __in uint32_t tcp_seq, 2099 __in uint16_t tcp_mss, 2100 __out_ecount(count) efx_desc_t *edp, 2101 __in int count); 2102 2103 extern void 2104 efx_tx_qdesc_vlantci_create( 2105 __in efx_txq_t *etp, 2106 __in uint16_t tci, 2107 __out efx_desc_t *edp); 2108 2109 #if EFSYS_OPT_QSTATS 2110 2111 #if EFSYS_OPT_NAMES 2112 2113 extern const char * 2114 efx_tx_qstat_name( 2115 __in efx_nic_t *etp, 2116 __in unsigned int id); 2117 2118 #endif /* EFSYS_OPT_NAMES */ 2119 2120 extern void 2121 efx_tx_qstats_update( 2122 __in efx_txq_t *etp, 2123 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2124 2125 #endif /* EFSYS_OPT_QSTATS */ 2126 2127 extern void 2128 efx_tx_qdestroy( 2129 __in efx_txq_t *etp); 2130 2131 2132 /* FILTER */ 2133 2134 #if EFSYS_OPT_FILTER 2135 2136 #define EFX_ETHER_TYPE_IPV4 0x0800 2137 #define EFX_ETHER_TYPE_IPV6 0x86DD 2138 2139 #define EFX_IPPROTO_TCP 6 2140 #define EFX_IPPROTO_UDP 17 2141 2142 typedef enum efx_filter_flag_e { 2143 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 2144 * multiple queues */ 2145 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 2146 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter 2147 * (priority EFX_FILTER_PRI_AUTO). 2148 * May only be set by the filter 2149 * implementation for each type. 2150 * A removal request will 2151 * restore the automatic filter 2152 * in its place. */ 2153 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */ 2154 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */ 2155 } efx_filter_flag_t; 2156 2157 typedef enum efx_filter_match_flags_e { 2158 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2159 * address */ 2160 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2161 * address */ 2162 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2163 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2164 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2165 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2166 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2167 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2168 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2169 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2170 * protocol */ 2171 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address 2172 * I/G bit. Used for RX default 2173 * unicast and multicast/ 2174 * broadcast filters. */ 2175 } efx_filter_match_flags_t; 2176 2177 typedef enum efx_filter_priority_s { 2178 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2179 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2180 * address list or hardware 2181 * requirements. This may only be used 2182 * by the filter implementation for 2183 * each NIC type. */ 2184 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2185 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2186 * client (e.g. SR-IOV, HyperV VMQ etc.) 2187 */ 2188 } efx_filter_priority_t; 2189 2190 /* 2191 * FIXME: All these fields are assumed to be in little-endian byte order. 2192 * It may be better for some to be big-endian. See bug42804. 2193 */ 2194 2195 typedef struct efx_filter_spec_s { 2196 uint32_t efs_match_flags:12; 2197 uint32_t efs_priority:2; 2198 uint32_t efs_flags:6; 2199 uint32_t efs_dmaq_id:12; 2200 uint32_t efs_rss_context; 2201 uint16_t efs_outer_vid; 2202 uint16_t efs_inner_vid; 2203 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2204 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2205 uint16_t efs_ether_type; 2206 uint8_t efs_ip_proto; 2207 uint16_t efs_loc_port; 2208 uint16_t efs_rem_port; 2209 efx_oword_t efs_rem_host; 2210 efx_oword_t efs_loc_host; 2211 } efx_filter_spec_t; 2212 2213 2214 /* Default values for use in filter specifications */ 2215 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2216 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2217 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2218 2219 extern __checkReturn efx_rc_t 2220 efx_filter_init( 2221 __in efx_nic_t *enp); 2222 2223 extern void 2224 efx_filter_fini( 2225 __in efx_nic_t *enp); 2226 2227 extern __checkReturn efx_rc_t 2228 efx_filter_insert( 2229 __in efx_nic_t *enp, 2230 __inout efx_filter_spec_t *spec); 2231 2232 extern __checkReturn efx_rc_t 2233 efx_filter_remove( 2234 __in efx_nic_t *enp, 2235 __inout efx_filter_spec_t *spec); 2236 2237 extern __checkReturn efx_rc_t 2238 efx_filter_restore( 2239 __in efx_nic_t *enp); 2240 2241 extern __checkReturn efx_rc_t 2242 efx_filter_supported_filters( 2243 __in efx_nic_t *enp, 2244 __out uint32_t *list, 2245 __out size_t *length); 2246 2247 extern void 2248 efx_filter_spec_init_rx( 2249 __out efx_filter_spec_t *spec, 2250 __in efx_filter_priority_t priority, 2251 __in efx_filter_flag_t flags, 2252 __in efx_rxq_t *erp); 2253 2254 extern void 2255 efx_filter_spec_init_tx( 2256 __out efx_filter_spec_t *spec, 2257 __in efx_txq_t *etp); 2258 2259 extern __checkReturn efx_rc_t 2260 efx_filter_spec_set_ipv4_local( 2261 __inout efx_filter_spec_t *spec, 2262 __in uint8_t proto, 2263 __in uint32_t host, 2264 __in uint16_t port); 2265 2266 extern __checkReturn efx_rc_t 2267 efx_filter_spec_set_ipv4_full( 2268 __inout efx_filter_spec_t *spec, 2269 __in uint8_t proto, 2270 __in uint32_t lhost, 2271 __in uint16_t lport, 2272 __in uint32_t rhost, 2273 __in uint16_t rport); 2274 2275 extern __checkReturn efx_rc_t 2276 efx_filter_spec_set_eth_local( 2277 __inout efx_filter_spec_t *spec, 2278 __in uint16_t vid, 2279 __in const uint8_t *addr); 2280 2281 extern __checkReturn efx_rc_t 2282 efx_filter_spec_set_uc_def( 2283 __inout efx_filter_spec_t *spec); 2284 2285 extern __checkReturn efx_rc_t 2286 efx_filter_spec_set_mc_def( 2287 __inout efx_filter_spec_t *spec); 2288 2289 #endif /* EFSYS_OPT_FILTER */ 2290 2291 /* HASH */ 2292 2293 extern __checkReturn uint32_t 2294 efx_hash_dwords( 2295 __in_ecount(count) uint32_t const *input, 2296 __in size_t count, 2297 __in uint32_t init); 2298 2299 extern __checkReturn uint32_t 2300 efx_hash_bytes( 2301 __in_ecount(length) uint8_t const *input, 2302 __in size_t length, 2303 __in uint32_t init); 2304 2305 #if EFSYS_OPT_LICENSING 2306 2307 /* LICENSING */ 2308 2309 typedef struct efx_key_stats_s { 2310 uint32_t eks_valid; 2311 uint32_t eks_invalid; 2312 uint32_t eks_blacklisted; 2313 uint32_t eks_unverifiable; 2314 uint32_t eks_wrong_node; 2315 uint32_t eks_licensed_apps_lo; 2316 uint32_t eks_licensed_apps_hi; 2317 uint32_t eks_licensed_features_lo; 2318 uint32_t eks_licensed_features_hi; 2319 } efx_key_stats_t; 2320 2321 extern __checkReturn efx_rc_t 2322 efx_lic_init( 2323 __in efx_nic_t *enp); 2324 2325 extern void 2326 efx_lic_fini( 2327 __in efx_nic_t *enp); 2328 2329 extern __checkReturn boolean_t 2330 efx_lic_check_support( 2331 __in efx_nic_t *enp); 2332 2333 extern __checkReturn efx_rc_t 2334 efx_lic_update_licenses( 2335 __in efx_nic_t *enp); 2336 2337 extern __checkReturn efx_rc_t 2338 efx_lic_get_key_stats( 2339 __in efx_nic_t *enp, 2340 __out efx_key_stats_t *ksp); 2341 2342 extern __checkReturn efx_rc_t 2343 efx_lic_app_state( 2344 __in efx_nic_t *enp, 2345 __in uint64_t app_id, 2346 __out boolean_t *licensedp); 2347 2348 extern __checkReturn efx_rc_t 2349 efx_lic_get_id( 2350 __in efx_nic_t *enp, 2351 __in size_t buffer_size, 2352 __out uint32_t *typep, 2353 __out size_t *lengthp, 2354 __out_opt uint8_t *bufferp); 2355 2356 2357 extern __checkReturn efx_rc_t 2358 efx_lic_find_start( 2359 __in efx_nic_t *enp, 2360 __in_bcount(buffer_size) 2361 caddr_t bufferp, 2362 __in size_t buffer_size, 2363 __out uint32_t *startp 2364 ); 2365 2366 extern __checkReturn efx_rc_t 2367 efx_lic_find_end( 2368 __in efx_nic_t *enp, 2369 __in_bcount(buffer_size) 2370 caddr_t bufferp, 2371 __in size_t buffer_size, 2372 __in uint32_t offset, 2373 __out uint32_t *endp 2374 ); 2375 2376 extern __checkReturn __success(return != B_FALSE) boolean_t 2377 efx_lic_find_key( 2378 __in efx_nic_t *enp, 2379 __in_bcount(buffer_size) 2380 caddr_t bufferp, 2381 __in size_t buffer_size, 2382 __in uint32_t offset, 2383 __out uint32_t *startp, 2384 __out uint32_t *lengthp 2385 ); 2386 2387 extern __checkReturn __success(return != B_FALSE) boolean_t 2388 efx_lic_validate_key( 2389 __in efx_nic_t *enp, 2390 __in_bcount(length) caddr_t keyp, 2391 __in uint32_t length 2392 ); 2393 2394 extern __checkReturn efx_rc_t 2395 efx_lic_read_key( 2396 __in efx_nic_t *enp, 2397 __in_bcount(buffer_size) 2398 caddr_t bufferp, 2399 __in size_t buffer_size, 2400 __in uint32_t offset, 2401 __in uint32_t length, 2402 __out_bcount_part(key_max_size, *lengthp) 2403 caddr_t keyp, 2404 __in size_t key_max_size, 2405 __out uint32_t *lengthp 2406 ); 2407 2408 extern __checkReturn efx_rc_t 2409 efx_lic_write_key( 2410 __in efx_nic_t *enp, 2411 __in_bcount(buffer_size) 2412 caddr_t bufferp, 2413 __in size_t buffer_size, 2414 __in uint32_t offset, 2415 __in_bcount(length) caddr_t keyp, 2416 __in uint32_t length, 2417 __out uint32_t *lengthp 2418 ); 2419 2420 __checkReturn efx_rc_t 2421 efx_lic_delete_key( 2422 __in efx_nic_t *enp, 2423 __in_bcount(buffer_size) 2424 caddr_t bufferp, 2425 __in size_t buffer_size, 2426 __in uint32_t offset, 2427 __in uint32_t length, 2428 __in uint32_t end, 2429 __out uint32_t *deltap 2430 ); 2431 2432 extern __checkReturn efx_rc_t 2433 efx_lic_create_partition( 2434 __in efx_nic_t *enp, 2435 __in_bcount(buffer_size) 2436 caddr_t bufferp, 2437 __in size_t buffer_size 2438 ); 2439 2440 extern __checkReturn efx_rc_t 2441 efx_lic_finish_partition( 2442 __in efx_nic_t *enp, 2443 __in_bcount(buffer_size) 2444 caddr_t bufferp, 2445 __in size_t buffer_size 2446 ); 2447 2448 #endif /* EFSYS_OPT_LICENSING */ 2449 2450 2451 2452 #ifdef __cplusplus 2453 } 2454 #endif 2455 2456 #endif /* _SYS_EFX_H */ 2457