1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_H 36 #define _SYS_EFX_H 37 38 #include "efx_annote.h" 39 #include "efsys.h" 40 #include "efx_check.h" 41 #include "efx_phy_ids.h" 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #define EFX_STATIC_ASSERT(_cond) \ 48 ((void)sizeof (char[(_cond) ? 1 : -1])) 49 50 #define EFX_ARRAY_SIZE(_array) \ 51 (sizeof (_array) / sizeof ((_array)[0])) 52 53 #define EFX_FIELD_OFFSET(_type, _field) \ 54 ((size_t)&(((_type *)0)->_field)) 55 56 /* The macro expands divider twice */ 57 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 58 59 /* Round value up to the nearest power of two. */ 60 #define EFX_P2ROUNDUP(_type, _value, _align) \ 61 (-(-(_type)(_value) & -(_type)(_align))) 62 63 /* Align value down to the nearest power of two. */ 64 #define EFX_P2ALIGN(_type, _value, _align) \ 65 ((_type)(_value) & -(_type)(_align)) 66 67 /* Test if value is power of 2 aligned. */ 68 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 69 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 70 71 /* Return codes */ 72 73 typedef __success(return == 0) int efx_rc_t; 74 75 76 /* Chip families */ 77 78 typedef enum efx_family_e { 79 EFX_FAMILY_INVALID, 80 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 81 EFX_FAMILY_SIENA, 82 EFX_FAMILY_HUNTINGTON, 83 EFX_FAMILY_MEDFORD, 84 EFX_FAMILY_MEDFORD2, 85 EFX_FAMILY_NTYPES 86 } efx_family_t; 87 88 extern __checkReturn efx_rc_t 89 efx_family( 90 __in uint16_t venid, 91 __in uint16_t devid, 92 __out efx_family_t *efp, 93 __out unsigned int *membarp); 94 95 96 #define EFX_PCI_VENID_SFC 0x1924 97 98 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 99 100 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 101 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 102 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 103 104 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 105 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 106 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 107 108 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 109 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 110 111 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 112 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 113 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 114 115 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 116 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 117 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 118 119 120 #define EFX_MEM_BAR_SIENA 2 121 122 #define EFX_MEM_BAR_HUNTINGTON_PF 2 123 #define EFX_MEM_BAR_HUNTINGTON_VF 0 124 125 #define EFX_MEM_BAR_MEDFORD_PF 2 126 #define EFX_MEM_BAR_MEDFORD_VF 0 127 128 #define EFX_MEM_BAR_MEDFORD2 0 129 130 131 /* Error codes */ 132 133 enum { 134 EFX_ERR_INVALID, 135 EFX_ERR_SRAM_OOB, 136 EFX_ERR_BUFID_DC_OOB, 137 EFX_ERR_MEM_PERR, 138 EFX_ERR_RBUF_OWN, 139 EFX_ERR_TBUF_OWN, 140 EFX_ERR_RDESQ_OWN, 141 EFX_ERR_TDESQ_OWN, 142 EFX_ERR_EVQ_OWN, 143 EFX_ERR_EVFF_OFLO, 144 EFX_ERR_ILL_ADDR, 145 EFX_ERR_SRAM_PERR, 146 EFX_ERR_NCODES 147 }; 148 149 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 150 extern __checkReturn uint32_t 151 efx_crc32_calculate( 152 __in uint32_t crc_init, 153 __in_ecount(length) uint8_t const *input, 154 __in int length); 155 156 157 /* Type prototypes */ 158 159 typedef struct efx_rxq_s efx_rxq_t; 160 161 /* NIC */ 162 163 typedef struct efx_nic_s efx_nic_t; 164 165 extern __checkReturn efx_rc_t 166 efx_nic_create( 167 __in efx_family_t family, 168 __in efsys_identifier_t *esip, 169 __in efsys_bar_t *esbp, 170 __in efsys_lock_t *eslp, 171 __deref_out efx_nic_t **enpp); 172 173 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 174 typedef enum efx_fw_variant_e { 175 EFX_FW_VARIANT_FULL_FEATURED, 176 EFX_FW_VARIANT_LOW_LATENCY, 177 EFX_FW_VARIANT_PACKED_STREAM, 178 EFX_FW_VARIANT_HIGH_TX_RATE, 179 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 180 EFX_FW_VARIANT_RULES_ENGINE, 181 EFX_FW_VARIANT_DPDK, 182 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 183 } efx_fw_variant_t; 184 185 extern __checkReturn efx_rc_t 186 efx_nic_probe( 187 __in efx_nic_t *enp, 188 __in efx_fw_variant_t efv); 189 190 extern __checkReturn efx_rc_t 191 efx_nic_init( 192 __in efx_nic_t *enp); 193 194 extern __checkReturn efx_rc_t 195 efx_nic_reset( 196 __in efx_nic_t *enp); 197 198 extern __checkReturn boolean_t 199 efx_nic_hw_unavailable( 200 __in efx_nic_t *enp); 201 202 extern void 203 efx_nic_set_hw_unavailable( 204 __in efx_nic_t *enp); 205 206 #if EFSYS_OPT_DIAG 207 208 extern __checkReturn efx_rc_t 209 efx_nic_register_test( 210 __in efx_nic_t *enp); 211 212 #endif /* EFSYS_OPT_DIAG */ 213 214 extern void 215 efx_nic_fini( 216 __in efx_nic_t *enp); 217 218 extern void 219 efx_nic_unprobe( 220 __in efx_nic_t *enp); 221 222 extern void 223 efx_nic_destroy( 224 __in efx_nic_t *enp); 225 226 #define EFX_PCIE_LINK_SPEED_GEN1 1 227 #define EFX_PCIE_LINK_SPEED_GEN2 2 228 #define EFX_PCIE_LINK_SPEED_GEN3 3 229 230 typedef enum efx_pcie_link_performance_e { 231 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 232 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 233 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 234 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 235 } efx_pcie_link_performance_t; 236 237 extern __checkReturn efx_rc_t 238 efx_nic_calculate_pcie_link_bandwidth( 239 __in uint32_t pcie_link_width, 240 __in uint32_t pcie_link_gen, 241 __out uint32_t *bandwidth_mbpsp); 242 243 extern __checkReturn efx_rc_t 244 efx_nic_check_pcie_link_speed( 245 __in efx_nic_t *enp, 246 __in uint32_t pcie_link_width, 247 __in uint32_t pcie_link_gen, 248 __out efx_pcie_link_performance_t *resultp); 249 250 #if EFSYS_OPT_MCDI 251 252 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 253 /* Huntington and Medford require MCDIv2 commands */ 254 #define WITH_MCDI_V2 1 255 #endif 256 257 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 258 259 typedef enum efx_mcdi_exception_e { 260 EFX_MCDI_EXCEPTION_MC_REBOOT, 261 EFX_MCDI_EXCEPTION_MC_BADASSERT, 262 } efx_mcdi_exception_t; 263 264 #if EFSYS_OPT_MCDI_LOGGING 265 typedef enum efx_log_msg_e { 266 EFX_LOG_INVALID, 267 EFX_LOG_MCDI_REQUEST, 268 EFX_LOG_MCDI_RESPONSE, 269 } efx_log_msg_t; 270 #endif /* EFSYS_OPT_MCDI_LOGGING */ 271 272 typedef struct efx_mcdi_transport_s { 273 void *emt_context; 274 efsys_mem_t *emt_dma_mem; 275 void (*emt_execute)(void *, efx_mcdi_req_t *); 276 void (*emt_ev_cpl)(void *); 277 void (*emt_exception)(void *, efx_mcdi_exception_t); 278 #if EFSYS_OPT_MCDI_LOGGING 279 void (*emt_logger)(void *, efx_log_msg_t, 280 void *, size_t, void *, size_t); 281 #endif /* EFSYS_OPT_MCDI_LOGGING */ 282 #if EFSYS_OPT_MCDI_PROXY_AUTH 283 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 284 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 285 } efx_mcdi_transport_t; 286 287 extern __checkReturn efx_rc_t 288 efx_mcdi_init( 289 __in efx_nic_t *enp, 290 __in const efx_mcdi_transport_t *mtp); 291 292 extern __checkReturn efx_rc_t 293 efx_mcdi_reboot( 294 __in efx_nic_t *enp); 295 296 void 297 efx_mcdi_new_epoch( 298 __in efx_nic_t *enp); 299 300 extern void 301 efx_mcdi_get_timeout( 302 __in efx_nic_t *enp, 303 __in efx_mcdi_req_t *emrp, 304 __out uint32_t *usec_timeoutp); 305 306 extern void 307 efx_mcdi_request_start( 308 __in efx_nic_t *enp, 309 __in efx_mcdi_req_t *emrp, 310 __in boolean_t ev_cpl); 311 312 extern __checkReturn boolean_t 313 efx_mcdi_request_poll( 314 __in efx_nic_t *enp); 315 316 extern __checkReturn boolean_t 317 efx_mcdi_request_abort( 318 __in efx_nic_t *enp); 319 320 extern void 321 efx_mcdi_fini( 322 __in efx_nic_t *enp); 323 324 #endif /* EFSYS_OPT_MCDI */ 325 326 /* INTR */ 327 328 #define EFX_NINTR_SIENA 1024 329 330 typedef enum efx_intr_type_e { 331 EFX_INTR_INVALID = 0, 332 EFX_INTR_LINE, 333 EFX_INTR_MESSAGE, 334 EFX_INTR_NTYPES 335 } efx_intr_type_t; 336 337 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 338 339 extern __checkReturn efx_rc_t 340 efx_intr_init( 341 __in efx_nic_t *enp, 342 __in efx_intr_type_t type, 343 __in_opt efsys_mem_t *esmp); 344 345 extern void 346 efx_intr_enable( 347 __in efx_nic_t *enp); 348 349 extern void 350 efx_intr_disable( 351 __in efx_nic_t *enp); 352 353 extern void 354 efx_intr_disable_unlocked( 355 __in efx_nic_t *enp); 356 357 #define EFX_INTR_NEVQS 32 358 359 extern __checkReturn efx_rc_t 360 efx_intr_trigger( 361 __in efx_nic_t *enp, 362 __in unsigned int level); 363 364 extern void 365 efx_intr_status_line( 366 __in efx_nic_t *enp, 367 __out boolean_t *fatalp, 368 __out uint32_t *maskp); 369 370 extern void 371 efx_intr_status_message( 372 __in efx_nic_t *enp, 373 __in unsigned int message, 374 __out boolean_t *fatalp); 375 376 extern void 377 efx_intr_fatal( 378 __in efx_nic_t *enp); 379 380 extern void 381 efx_intr_fini( 382 __in efx_nic_t *enp); 383 384 /* MAC */ 385 386 #if EFSYS_OPT_MAC_STATS 387 388 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 389 typedef enum efx_mac_stat_e { 390 EFX_MAC_RX_OCTETS, 391 EFX_MAC_RX_PKTS, 392 EFX_MAC_RX_UNICST_PKTS, 393 EFX_MAC_RX_MULTICST_PKTS, 394 EFX_MAC_RX_BRDCST_PKTS, 395 EFX_MAC_RX_PAUSE_PKTS, 396 EFX_MAC_RX_LE_64_PKTS, 397 EFX_MAC_RX_65_TO_127_PKTS, 398 EFX_MAC_RX_128_TO_255_PKTS, 399 EFX_MAC_RX_256_TO_511_PKTS, 400 EFX_MAC_RX_512_TO_1023_PKTS, 401 EFX_MAC_RX_1024_TO_15XX_PKTS, 402 EFX_MAC_RX_GE_15XX_PKTS, 403 EFX_MAC_RX_ERRORS, 404 EFX_MAC_RX_FCS_ERRORS, 405 EFX_MAC_RX_DROP_EVENTS, 406 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 407 EFX_MAC_RX_SYMBOL_ERRORS, 408 EFX_MAC_RX_ALIGN_ERRORS, 409 EFX_MAC_RX_INTERNAL_ERRORS, 410 EFX_MAC_RX_JABBER_PKTS, 411 EFX_MAC_RX_LANE0_CHAR_ERR, 412 EFX_MAC_RX_LANE1_CHAR_ERR, 413 EFX_MAC_RX_LANE2_CHAR_ERR, 414 EFX_MAC_RX_LANE3_CHAR_ERR, 415 EFX_MAC_RX_LANE0_DISP_ERR, 416 EFX_MAC_RX_LANE1_DISP_ERR, 417 EFX_MAC_RX_LANE2_DISP_ERR, 418 EFX_MAC_RX_LANE3_DISP_ERR, 419 EFX_MAC_RX_MATCH_FAULT, 420 EFX_MAC_RX_NODESC_DROP_CNT, 421 EFX_MAC_TX_OCTETS, 422 EFX_MAC_TX_PKTS, 423 EFX_MAC_TX_UNICST_PKTS, 424 EFX_MAC_TX_MULTICST_PKTS, 425 EFX_MAC_TX_BRDCST_PKTS, 426 EFX_MAC_TX_PAUSE_PKTS, 427 EFX_MAC_TX_LE_64_PKTS, 428 EFX_MAC_TX_65_TO_127_PKTS, 429 EFX_MAC_TX_128_TO_255_PKTS, 430 EFX_MAC_TX_256_TO_511_PKTS, 431 EFX_MAC_TX_512_TO_1023_PKTS, 432 EFX_MAC_TX_1024_TO_15XX_PKTS, 433 EFX_MAC_TX_GE_15XX_PKTS, 434 EFX_MAC_TX_ERRORS, 435 EFX_MAC_TX_SGL_COL_PKTS, 436 EFX_MAC_TX_MULT_COL_PKTS, 437 EFX_MAC_TX_EX_COL_PKTS, 438 EFX_MAC_TX_LATE_COL_PKTS, 439 EFX_MAC_TX_DEF_PKTS, 440 EFX_MAC_TX_EX_DEF_PKTS, 441 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 442 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 443 EFX_MAC_PM_TRUNC_VFIFO_FULL, 444 EFX_MAC_PM_DISCARD_VFIFO_FULL, 445 EFX_MAC_PM_TRUNC_QBB, 446 EFX_MAC_PM_DISCARD_QBB, 447 EFX_MAC_PM_DISCARD_MAPPING, 448 EFX_MAC_RXDP_Q_DISABLED_PKTS, 449 EFX_MAC_RXDP_DI_DROPPED_PKTS, 450 EFX_MAC_RXDP_STREAMING_PKTS, 451 EFX_MAC_RXDP_HLB_FETCH, 452 EFX_MAC_RXDP_HLB_WAIT, 453 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 454 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 455 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 456 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 457 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 458 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 459 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 460 EFX_MAC_VADAPTER_RX_BAD_BYTES, 461 EFX_MAC_VADAPTER_RX_OVERFLOW, 462 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 463 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 464 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 465 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 466 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 467 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 468 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 469 EFX_MAC_VADAPTER_TX_BAD_BYTES, 470 EFX_MAC_VADAPTER_TX_OVERFLOW, 471 EFX_MAC_FEC_UNCORRECTED_ERRORS, 472 EFX_MAC_FEC_CORRECTED_ERRORS, 473 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 474 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 475 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 476 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 477 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 478 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 479 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 480 EFX_MAC_CTPIO_OVERFLOW_FAIL, 481 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 482 EFX_MAC_CTPIO_TIMEOUT_FAIL, 483 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 484 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 485 EFX_MAC_CTPIO_INVALID_WR_FAIL, 486 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 487 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 488 EFX_MAC_CTPIO_RUNT_FALLBACK, 489 EFX_MAC_CTPIO_SUCCESS, 490 EFX_MAC_CTPIO_FALLBACK, 491 EFX_MAC_CTPIO_POISON, 492 EFX_MAC_CTPIO_ERASE, 493 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 494 EFX_MAC_RXDP_HLB_IDLE, 495 EFX_MAC_RXDP_HLB_TIMEOUT, 496 EFX_MAC_NSTATS 497 } efx_mac_stat_t; 498 499 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 500 501 #endif /* EFSYS_OPT_MAC_STATS */ 502 503 typedef enum efx_link_mode_e { 504 EFX_LINK_UNKNOWN = 0, 505 EFX_LINK_DOWN, 506 EFX_LINK_10HDX, 507 EFX_LINK_10FDX, 508 EFX_LINK_100HDX, 509 EFX_LINK_100FDX, 510 EFX_LINK_1000HDX, 511 EFX_LINK_1000FDX, 512 EFX_LINK_10000FDX, 513 EFX_LINK_40000FDX, 514 EFX_LINK_25000FDX, 515 EFX_LINK_50000FDX, 516 EFX_LINK_100000FDX, 517 EFX_LINK_NMODES 518 } efx_link_mode_t; 519 520 #define EFX_MAC_ADDR_LEN 6 521 522 #define EFX_VNI_OR_VSID_LEN 3 523 524 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 525 526 #define EFX_MAC_MULTICAST_LIST_MAX 256 527 528 #define EFX_MAC_SDU_MAX 9202 529 530 #define EFX_MAC_PDU_ADJUSTMENT \ 531 (/* EtherII */ 14 \ 532 + /* VLAN */ 4 \ 533 + /* CRC */ 4 \ 534 + /* bug16011 */ 16) \ 535 536 #define EFX_MAC_PDU(_sdu) \ 537 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 538 539 /* 540 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 541 * the SDU rounded up slightly. 542 */ 543 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 544 545 #define EFX_MAC_PDU_MIN 60 546 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 547 548 extern __checkReturn efx_rc_t 549 efx_mac_pdu_get( 550 __in efx_nic_t *enp, 551 __out size_t *pdu); 552 553 extern __checkReturn efx_rc_t 554 efx_mac_pdu_set( 555 __in efx_nic_t *enp, 556 __in size_t pdu); 557 558 extern __checkReturn efx_rc_t 559 efx_mac_addr_set( 560 __in efx_nic_t *enp, 561 __in uint8_t *addr); 562 563 extern __checkReturn efx_rc_t 564 efx_mac_filter_set( 565 __in efx_nic_t *enp, 566 __in boolean_t all_unicst, 567 __in boolean_t mulcst, 568 __in boolean_t all_mulcst, 569 __in boolean_t brdcst); 570 571 extern __checkReturn efx_rc_t 572 efx_mac_multicast_list_set( 573 __in efx_nic_t *enp, 574 __in_ecount(6*count) uint8_t const *addrs, 575 __in int count); 576 577 extern __checkReturn efx_rc_t 578 efx_mac_filter_default_rxq_set( 579 __in efx_nic_t *enp, 580 __in efx_rxq_t *erp, 581 __in boolean_t using_rss); 582 583 extern void 584 efx_mac_filter_default_rxq_clear( 585 __in efx_nic_t *enp); 586 587 extern __checkReturn efx_rc_t 588 efx_mac_drain( 589 __in efx_nic_t *enp, 590 __in boolean_t enabled); 591 592 extern __checkReturn efx_rc_t 593 efx_mac_up( 594 __in efx_nic_t *enp, 595 __out boolean_t *mac_upp); 596 597 #define EFX_FCNTL_RESPOND 0x00000001 598 #define EFX_FCNTL_GENERATE 0x00000002 599 600 extern __checkReturn efx_rc_t 601 efx_mac_fcntl_set( 602 __in efx_nic_t *enp, 603 __in unsigned int fcntl, 604 __in boolean_t autoneg); 605 606 extern void 607 efx_mac_fcntl_get( 608 __in efx_nic_t *enp, 609 __out unsigned int *fcntl_wantedp, 610 __out unsigned int *fcntl_linkp); 611 612 613 #if EFSYS_OPT_MAC_STATS 614 615 #if EFSYS_OPT_NAMES 616 617 extern __checkReturn const char * 618 efx_mac_stat_name( 619 __in efx_nic_t *enp, 620 __in unsigned int id); 621 622 #endif /* EFSYS_OPT_NAMES */ 623 624 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 625 626 #define EFX_MAC_STATS_MASK_NPAGES \ 627 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 628 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 629 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 630 631 /* 632 * Get mask of MAC statistics supported by the hardware. 633 * 634 * If mask_size is insufficient to return the mask, EINVAL error is 635 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 636 * (which is sizeof (uint32_t)) is sufficient. 637 */ 638 extern __checkReturn efx_rc_t 639 efx_mac_stats_get_mask( 640 __in efx_nic_t *enp, 641 __out_bcount(mask_size) uint32_t *maskp, 642 __in size_t mask_size); 643 644 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 645 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 646 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 647 648 649 extern __checkReturn efx_rc_t 650 efx_mac_stats_clear( 651 __in efx_nic_t *enp); 652 653 /* 654 * Upload mac statistics supported by the hardware into the given buffer. 655 * 656 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 657 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 658 * 659 * The hardware will only DMA statistics that it understands (of course). 660 * Drivers should not make any assumptions about which statistics are 661 * supported, especially when the statistics are generated by firmware. 662 * 663 * Thus, drivers should zero this buffer before use, so that not-understood 664 * statistics read back as zero. 665 */ 666 extern __checkReturn efx_rc_t 667 efx_mac_stats_upload( 668 __in efx_nic_t *enp, 669 __in efsys_mem_t *esmp); 670 671 extern __checkReturn efx_rc_t 672 efx_mac_stats_periodic( 673 __in efx_nic_t *enp, 674 __in efsys_mem_t *esmp, 675 __in uint16_t period_ms, 676 __in boolean_t events); 677 678 extern __checkReturn efx_rc_t 679 efx_mac_stats_update( 680 __in efx_nic_t *enp, 681 __in efsys_mem_t *esmp, 682 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 683 __inout_opt uint32_t *generationp); 684 685 #endif /* EFSYS_OPT_MAC_STATS */ 686 687 /* MON */ 688 689 typedef enum efx_mon_type_e { 690 EFX_MON_INVALID = 0, 691 EFX_MON_SFC90X0, 692 EFX_MON_SFC91X0, 693 EFX_MON_SFC92X0, 694 EFX_MON_NTYPES 695 } efx_mon_type_t; 696 697 #if EFSYS_OPT_NAMES 698 699 extern const char * 700 efx_mon_name( 701 __in efx_nic_t *enp); 702 703 #endif /* EFSYS_OPT_NAMES */ 704 705 extern __checkReturn efx_rc_t 706 efx_mon_init( 707 __in efx_nic_t *enp); 708 709 #if EFSYS_OPT_MON_STATS 710 711 #define EFX_MON_STATS_PAGE_SIZE 0x100 712 #define EFX_MON_MASK_ELEMENT_SIZE 32 713 714 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 715 typedef enum efx_mon_stat_e { 716 EFX_MON_STAT_CONTROLLER_TEMP, 717 EFX_MON_STAT_PHY_COMMON_TEMP, 718 EFX_MON_STAT_CONTROLLER_COOLING, 719 EFX_MON_STAT_PHY0_TEMP, 720 EFX_MON_STAT_PHY0_COOLING, 721 EFX_MON_STAT_PHY1_TEMP, 722 EFX_MON_STAT_PHY1_COOLING, 723 EFX_MON_STAT_IN_1V0, 724 EFX_MON_STAT_IN_1V2, 725 EFX_MON_STAT_IN_1V8, 726 EFX_MON_STAT_IN_2V5, 727 EFX_MON_STAT_IN_3V3, 728 EFX_MON_STAT_IN_12V0, 729 EFX_MON_STAT_IN_1V2A, 730 EFX_MON_STAT_IN_VREF, 731 EFX_MON_STAT_OUT_VAOE, 732 EFX_MON_STAT_AOE_TEMP, 733 EFX_MON_STAT_PSU_AOE_TEMP, 734 EFX_MON_STAT_PSU_TEMP, 735 EFX_MON_STAT_FAN_0, 736 EFX_MON_STAT_FAN_1, 737 EFX_MON_STAT_FAN_2, 738 EFX_MON_STAT_FAN_3, 739 EFX_MON_STAT_FAN_4, 740 EFX_MON_STAT_IN_VAOE, 741 EFX_MON_STAT_OUT_IAOE, 742 EFX_MON_STAT_IN_IAOE, 743 EFX_MON_STAT_NIC_POWER, 744 EFX_MON_STAT_IN_0V9, 745 EFX_MON_STAT_IN_I0V9, 746 EFX_MON_STAT_IN_I1V2, 747 EFX_MON_STAT_IN_0V9_ADC, 748 EFX_MON_STAT_CONTROLLER_2_TEMP, 749 EFX_MON_STAT_VREG_INTERNAL_TEMP, 750 EFX_MON_STAT_VREG_0V9_TEMP, 751 EFX_MON_STAT_VREG_1V2_TEMP, 752 EFX_MON_STAT_CONTROLLER_VPTAT, 753 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 754 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 755 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 756 EFX_MON_STAT_AMBIENT_TEMP, 757 EFX_MON_STAT_AIRFLOW, 758 EFX_MON_STAT_VDD08D_VSS08D_CSR, 759 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 760 EFX_MON_STAT_HOTPOINT_TEMP, 761 EFX_MON_STAT_PHY_POWER_PORT0, 762 EFX_MON_STAT_PHY_POWER_PORT1, 763 EFX_MON_STAT_MUM_VCC, 764 EFX_MON_STAT_IN_0V9_A, 765 EFX_MON_STAT_IN_I0V9_A, 766 EFX_MON_STAT_VREG_0V9_A_TEMP, 767 EFX_MON_STAT_IN_0V9_B, 768 EFX_MON_STAT_IN_I0V9_B, 769 EFX_MON_STAT_VREG_0V9_B_TEMP, 770 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 771 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 772 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 773 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 774 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 775 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 776 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 777 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 778 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 779 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 780 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 781 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 782 EFX_MON_STAT_SODIMM_VOUT, 783 EFX_MON_STAT_SODIMM_0_TEMP, 784 EFX_MON_STAT_SODIMM_1_TEMP, 785 EFX_MON_STAT_PHY0_VCC, 786 EFX_MON_STAT_PHY1_VCC, 787 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 788 EFX_MON_STAT_BOARD_FRONT_TEMP, 789 EFX_MON_STAT_BOARD_BACK_TEMP, 790 EFX_MON_STAT_IN_I1V8, 791 EFX_MON_STAT_IN_I2V5, 792 EFX_MON_STAT_IN_I3V3, 793 EFX_MON_STAT_IN_I12V0, 794 EFX_MON_STAT_IN_1V3, 795 EFX_MON_STAT_IN_I1V3, 796 EFX_MON_NSTATS 797 } efx_mon_stat_t; 798 799 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 800 801 typedef enum efx_mon_stat_state_e { 802 EFX_MON_STAT_STATE_OK = 0, 803 EFX_MON_STAT_STATE_WARNING = 1, 804 EFX_MON_STAT_STATE_FATAL = 2, 805 EFX_MON_STAT_STATE_BROKEN = 3, 806 EFX_MON_STAT_STATE_NO_READING = 4, 807 } efx_mon_stat_state_t; 808 809 typedef enum efx_mon_stat_unit_e { 810 EFX_MON_STAT_UNIT_UNKNOWN = 0, 811 EFX_MON_STAT_UNIT_BOOL, 812 EFX_MON_STAT_UNIT_TEMP_C, 813 EFX_MON_STAT_UNIT_VOLTAGE_MV, 814 EFX_MON_STAT_UNIT_CURRENT_MA, 815 EFX_MON_STAT_UNIT_POWER_W, 816 EFX_MON_STAT_UNIT_RPM, 817 EFX_MON_NUNITS 818 } efx_mon_stat_unit_t; 819 820 typedef struct efx_mon_stat_value_s { 821 uint16_t emsv_value; 822 efx_mon_stat_state_t emsv_state; 823 efx_mon_stat_unit_t emsv_unit; 824 } efx_mon_stat_value_t; 825 826 typedef struct efx_mon_limit_value_s { 827 uint16_t emlv_warning_min; 828 uint16_t emlv_warning_max; 829 uint16_t emlv_fatal_min; 830 uint16_t emlv_fatal_max; 831 } efx_mon_stat_limits_t; 832 833 typedef enum efx_mon_stat_portmask_e { 834 EFX_MON_STAT_PORTMAP_NONE = 0, 835 EFX_MON_STAT_PORTMAP_PORT0 = 1, 836 EFX_MON_STAT_PORTMAP_PORT1 = 2, 837 EFX_MON_STAT_PORTMAP_PORT2 = 3, 838 EFX_MON_STAT_PORTMAP_PORT3 = 4, 839 EFX_MON_STAT_PORTMAP_ALL = (-1), 840 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 841 } efx_mon_stat_portmask_t; 842 843 #if EFSYS_OPT_NAMES 844 845 extern const char * 846 efx_mon_stat_name( 847 __in efx_nic_t *enp, 848 __in efx_mon_stat_t id); 849 850 extern const char * 851 efx_mon_stat_description( 852 __in efx_nic_t *enp, 853 __in efx_mon_stat_t id); 854 855 #endif /* EFSYS_OPT_NAMES */ 856 857 extern __checkReturn boolean_t 858 efx_mon_mcdi_to_efx_stat( 859 __in int mcdi_index, 860 __out efx_mon_stat_t *statp); 861 862 extern __checkReturn boolean_t 863 efx_mon_get_stat_unit( 864 __in efx_mon_stat_t stat, 865 __out efx_mon_stat_unit_t *unitp); 866 867 extern __checkReturn boolean_t 868 efx_mon_get_stat_portmap( 869 __in efx_mon_stat_t stat, 870 __out efx_mon_stat_portmask_t *maskp); 871 872 extern __checkReturn efx_rc_t 873 efx_mon_stats_update( 874 __in efx_nic_t *enp, 875 __in efsys_mem_t *esmp, 876 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 877 878 extern __checkReturn efx_rc_t 879 efx_mon_limits_update( 880 __in efx_nic_t *enp, 881 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 882 883 #endif /* EFSYS_OPT_MON_STATS */ 884 885 extern void 886 efx_mon_fini( 887 __in efx_nic_t *enp); 888 889 /* PHY */ 890 891 extern __checkReturn efx_rc_t 892 efx_phy_verify( 893 __in efx_nic_t *enp); 894 895 #if EFSYS_OPT_PHY_LED_CONTROL 896 897 typedef enum efx_phy_led_mode_e { 898 EFX_PHY_LED_DEFAULT = 0, 899 EFX_PHY_LED_OFF, 900 EFX_PHY_LED_ON, 901 EFX_PHY_LED_FLASH, 902 EFX_PHY_LED_NMODES 903 } efx_phy_led_mode_t; 904 905 extern __checkReturn efx_rc_t 906 efx_phy_led_set( 907 __in efx_nic_t *enp, 908 __in efx_phy_led_mode_t mode); 909 910 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 911 912 extern __checkReturn efx_rc_t 913 efx_port_init( 914 __in efx_nic_t *enp); 915 916 #if EFSYS_OPT_LOOPBACK 917 918 typedef enum efx_loopback_type_e { 919 EFX_LOOPBACK_OFF = 0, 920 EFX_LOOPBACK_DATA = 1, 921 EFX_LOOPBACK_GMAC = 2, 922 EFX_LOOPBACK_XGMII = 3, 923 EFX_LOOPBACK_XGXS = 4, 924 EFX_LOOPBACK_XAUI = 5, 925 EFX_LOOPBACK_GMII = 6, 926 EFX_LOOPBACK_SGMII = 7, 927 EFX_LOOPBACK_XGBR = 8, 928 EFX_LOOPBACK_XFI = 9, 929 EFX_LOOPBACK_XAUI_FAR = 10, 930 EFX_LOOPBACK_GMII_FAR = 11, 931 EFX_LOOPBACK_SGMII_FAR = 12, 932 EFX_LOOPBACK_XFI_FAR = 13, 933 EFX_LOOPBACK_GPHY = 14, 934 EFX_LOOPBACK_PHY_XS = 15, 935 EFX_LOOPBACK_PCS = 16, 936 EFX_LOOPBACK_PMA_PMD = 17, 937 EFX_LOOPBACK_XPORT = 18, 938 EFX_LOOPBACK_XGMII_WS = 19, 939 EFX_LOOPBACK_XAUI_WS = 20, 940 EFX_LOOPBACK_XAUI_WS_FAR = 21, 941 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 942 EFX_LOOPBACK_GMII_WS = 23, 943 EFX_LOOPBACK_XFI_WS = 24, 944 EFX_LOOPBACK_XFI_WS_FAR = 25, 945 EFX_LOOPBACK_PHYXS_WS = 26, 946 EFX_LOOPBACK_PMA_INT = 27, 947 EFX_LOOPBACK_SD_NEAR = 28, 948 EFX_LOOPBACK_SD_FAR = 29, 949 EFX_LOOPBACK_PMA_INT_WS = 30, 950 EFX_LOOPBACK_SD_FEP2_WS = 31, 951 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 952 EFX_LOOPBACK_SD_FEP_WS = 33, 953 EFX_LOOPBACK_SD_FES_WS = 34, 954 EFX_LOOPBACK_AOE_INT_NEAR = 35, 955 EFX_LOOPBACK_DATA_WS = 36, 956 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 957 EFX_LOOPBACK_NTYPES 958 } efx_loopback_type_t; 959 960 typedef enum efx_loopback_kind_e { 961 EFX_LOOPBACK_KIND_OFF = 0, 962 EFX_LOOPBACK_KIND_ALL, 963 EFX_LOOPBACK_KIND_MAC, 964 EFX_LOOPBACK_KIND_PHY, 965 EFX_LOOPBACK_NKINDS 966 } efx_loopback_kind_t; 967 968 extern void 969 efx_loopback_mask( 970 __in efx_loopback_kind_t loopback_kind, 971 __out efx_qword_t *maskp); 972 973 extern __checkReturn efx_rc_t 974 efx_port_loopback_set( 975 __in efx_nic_t *enp, 976 __in efx_link_mode_t link_mode, 977 __in efx_loopback_type_t type); 978 979 #if EFSYS_OPT_NAMES 980 981 extern __checkReturn const char * 982 efx_loopback_type_name( 983 __in efx_nic_t *enp, 984 __in efx_loopback_type_t type); 985 986 #endif /* EFSYS_OPT_NAMES */ 987 988 #endif /* EFSYS_OPT_LOOPBACK */ 989 990 extern __checkReturn efx_rc_t 991 efx_port_poll( 992 __in efx_nic_t *enp, 993 __out_opt efx_link_mode_t *link_modep); 994 995 extern void 996 efx_port_fini( 997 __in efx_nic_t *enp); 998 999 typedef enum efx_phy_cap_type_e { 1000 EFX_PHY_CAP_INVALID = 0, 1001 EFX_PHY_CAP_10HDX, 1002 EFX_PHY_CAP_10FDX, 1003 EFX_PHY_CAP_100HDX, 1004 EFX_PHY_CAP_100FDX, 1005 EFX_PHY_CAP_1000HDX, 1006 EFX_PHY_CAP_1000FDX, 1007 EFX_PHY_CAP_10000FDX, 1008 EFX_PHY_CAP_PAUSE, 1009 EFX_PHY_CAP_ASYM, 1010 EFX_PHY_CAP_AN, 1011 EFX_PHY_CAP_40000FDX, 1012 EFX_PHY_CAP_DDM, 1013 EFX_PHY_CAP_100000FDX, 1014 EFX_PHY_CAP_25000FDX, 1015 EFX_PHY_CAP_50000FDX, 1016 EFX_PHY_CAP_BASER_FEC, 1017 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1018 EFX_PHY_CAP_RS_FEC, 1019 EFX_PHY_CAP_RS_FEC_REQUESTED, 1020 EFX_PHY_CAP_25G_BASER_FEC, 1021 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1022 EFX_PHY_CAP_NTYPES 1023 } efx_phy_cap_type_t; 1024 1025 1026 #define EFX_PHY_CAP_CURRENT 0x00000000 1027 #define EFX_PHY_CAP_DEFAULT 0x00000001 1028 #define EFX_PHY_CAP_PERM 0x00000002 1029 1030 extern void 1031 efx_phy_adv_cap_get( 1032 __in efx_nic_t *enp, 1033 __in uint32_t flag, 1034 __out uint32_t *maskp); 1035 1036 extern __checkReturn efx_rc_t 1037 efx_phy_adv_cap_set( 1038 __in efx_nic_t *enp, 1039 __in uint32_t mask); 1040 1041 extern void 1042 efx_phy_lp_cap_get( 1043 __in efx_nic_t *enp, 1044 __out uint32_t *maskp); 1045 1046 extern __checkReturn efx_rc_t 1047 efx_phy_oui_get( 1048 __in efx_nic_t *enp, 1049 __out uint32_t *ouip); 1050 1051 typedef enum efx_phy_media_type_e { 1052 EFX_PHY_MEDIA_INVALID = 0, 1053 EFX_PHY_MEDIA_XAUI, 1054 EFX_PHY_MEDIA_CX4, 1055 EFX_PHY_MEDIA_KX4, 1056 EFX_PHY_MEDIA_XFP, 1057 EFX_PHY_MEDIA_SFP_PLUS, 1058 EFX_PHY_MEDIA_BASE_T, 1059 EFX_PHY_MEDIA_QSFP_PLUS, 1060 EFX_PHY_MEDIA_NTYPES 1061 } efx_phy_media_type_t; 1062 1063 /* 1064 * Get the type of medium currently used. If the board has ports for 1065 * modules, a module is present, and we recognise the media type of 1066 * the module, then this will be the media type of the module. 1067 * Otherwise it will be the media type of the port. 1068 */ 1069 extern void 1070 efx_phy_media_type_get( 1071 __in efx_nic_t *enp, 1072 __out efx_phy_media_type_t *typep); 1073 1074 /* 1075 * 2-wire device address of the base information in accordance with SFF-8472 1076 * Diagnostic Monitoring Interface for Optical Transceivers section 1077 * 4 Memory Organization. 1078 */ 1079 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1080 1081 /* 1082 * 2-wire device address of the digital diagnostics monitoring interface 1083 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1084 * Transceivers section 4 Memory Organization. 1085 */ 1086 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1087 1088 /* 1089 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1090 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1091 * Operation. 1092 */ 1093 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1094 1095 /* 1096 * Maximum accessible data offset for PHY module information. 1097 */ 1098 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1099 1100 1101 extern __checkReturn efx_rc_t 1102 efx_phy_module_get_info( 1103 __in efx_nic_t *enp, 1104 __in uint8_t dev_addr, 1105 __in size_t offset, 1106 __in size_t len, 1107 __out_bcount(len) uint8_t *data); 1108 1109 #if EFSYS_OPT_PHY_STATS 1110 1111 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1112 typedef enum efx_phy_stat_e { 1113 EFX_PHY_STAT_OUI, 1114 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1115 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1116 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1117 EFX_PHY_STAT_PMA_PMD_REV_A, 1118 EFX_PHY_STAT_PMA_PMD_REV_B, 1119 EFX_PHY_STAT_PMA_PMD_REV_C, 1120 EFX_PHY_STAT_PMA_PMD_REV_D, 1121 EFX_PHY_STAT_PCS_LINK_UP, 1122 EFX_PHY_STAT_PCS_RX_FAULT, 1123 EFX_PHY_STAT_PCS_TX_FAULT, 1124 EFX_PHY_STAT_PCS_BER, 1125 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1126 EFX_PHY_STAT_PHY_XS_LINK_UP, 1127 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1128 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1129 EFX_PHY_STAT_PHY_XS_ALIGN, 1130 EFX_PHY_STAT_PHY_XS_SYNC_A, 1131 EFX_PHY_STAT_PHY_XS_SYNC_B, 1132 EFX_PHY_STAT_PHY_XS_SYNC_C, 1133 EFX_PHY_STAT_PHY_XS_SYNC_D, 1134 EFX_PHY_STAT_AN_LINK_UP, 1135 EFX_PHY_STAT_AN_MASTER, 1136 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1137 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1138 EFX_PHY_STAT_CL22EXT_LINK_UP, 1139 EFX_PHY_STAT_SNR_A, 1140 EFX_PHY_STAT_SNR_B, 1141 EFX_PHY_STAT_SNR_C, 1142 EFX_PHY_STAT_SNR_D, 1143 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1144 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1145 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1146 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1147 EFX_PHY_STAT_AN_COMPLETE, 1148 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1149 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1150 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1151 EFX_PHY_STAT_PCS_FW_VERSION_0, 1152 EFX_PHY_STAT_PCS_FW_VERSION_1, 1153 EFX_PHY_STAT_PCS_FW_VERSION_2, 1154 EFX_PHY_STAT_PCS_FW_VERSION_3, 1155 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1156 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1157 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1158 EFX_PHY_STAT_PCS_OP_MODE, 1159 EFX_PHY_NSTATS 1160 } efx_phy_stat_t; 1161 1162 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1163 1164 #if EFSYS_OPT_NAMES 1165 1166 extern const char * 1167 efx_phy_stat_name( 1168 __in efx_nic_t *enp, 1169 __in efx_phy_stat_t stat); 1170 1171 #endif /* EFSYS_OPT_NAMES */ 1172 1173 #define EFX_PHY_STATS_SIZE 0x100 1174 1175 extern __checkReturn efx_rc_t 1176 efx_phy_stats_update( 1177 __in efx_nic_t *enp, 1178 __in efsys_mem_t *esmp, 1179 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1180 1181 #endif /* EFSYS_OPT_PHY_STATS */ 1182 1183 1184 #if EFSYS_OPT_BIST 1185 1186 typedef enum efx_bist_type_e { 1187 EFX_BIST_TYPE_UNKNOWN, 1188 EFX_BIST_TYPE_PHY_NORMAL, 1189 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1190 EFX_BIST_TYPE_PHY_CABLE_LONG, 1191 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1192 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1193 EFX_BIST_TYPE_REG, /* Test the register memories */ 1194 EFX_BIST_TYPE_NTYPES, 1195 } efx_bist_type_t; 1196 1197 typedef enum efx_bist_result_e { 1198 EFX_BIST_RESULT_UNKNOWN, 1199 EFX_BIST_RESULT_RUNNING, 1200 EFX_BIST_RESULT_PASSED, 1201 EFX_BIST_RESULT_FAILED, 1202 } efx_bist_result_t; 1203 1204 typedef enum efx_phy_cable_status_e { 1205 EFX_PHY_CABLE_STATUS_OK, 1206 EFX_PHY_CABLE_STATUS_INVALID, 1207 EFX_PHY_CABLE_STATUS_OPEN, 1208 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1209 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1210 EFX_PHY_CABLE_STATUS_BUSY, 1211 } efx_phy_cable_status_t; 1212 1213 typedef enum efx_bist_value_e { 1214 EFX_BIST_PHY_CABLE_LENGTH_A, 1215 EFX_BIST_PHY_CABLE_LENGTH_B, 1216 EFX_BIST_PHY_CABLE_LENGTH_C, 1217 EFX_BIST_PHY_CABLE_LENGTH_D, 1218 EFX_BIST_PHY_CABLE_STATUS_A, 1219 EFX_BIST_PHY_CABLE_STATUS_B, 1220 EFX_BIST_PHY_CABLE_STATUS_C, 1221 EFX_BIST_PHY_CABLE_STATUS_D, 1222 EFX_BIST_FAULT_CODE, 1223 /* 1224 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1225 * response. 1226 */ 1227 EFX_BIST_MEM_TEST, 1228 EFX_BIST_MEM_ADDR, 1229 EFX_BIST_MEM_BUS, 1230 EFX_BIST_MEM_EXPECT, 1231 EFX_BIST_MEM_ACTUAL, 1232 EFX_BIST_MEM_ECC, 1233 EFX_BIST_MEM_ECC_PARITY, 1234 EFX_BIST_MEM_ECC_FATAL, 1235 EFX_BIST_NVALUES, 1236 } efx_bist_value_t; 1237 1238 extern __checkReturn efx_rc_t 1239 efx_bist_enable_offline( 1240 __in efx_nic_t *enp); 1241 1242 extern __checkReturn efx_rc_t 1243 efx_bist_start( 1244 __in efx_nic_t *enp, 1245 __in efx_bist_type_t type); 1246 1247 extern __checkReturn efx_rc_t 1248 efx_bist_poll( 1249 __in efx_nic_t *enp, 1250 __in efx_bist_type_t type, 1251 __out efx_bist_result_t *resultp, 1252 __out_opt uint32_t *value_maskp, 1253 __out_ecount_opt(count) unsigned long *valuesp, 1254 __in size_t count); 1255 1256 extern void 1257 efx_bist_stop( 1258 __in efx_nic_t *enp, 1259 __in efx_bist_type_t type); 1260 1261 #endif /* EFSYS_OPT_BIST */ 1262 1263 #define EFX_FEATURE_IPV6 0x00000001 1264 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1265 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1266 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1267 #define EFX_FEATURE_MCDI 0x00000020 1268 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1269 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1270 #define EFX_FEATURE_TURBO 0x00000100 1271 #define EFX_FEATURE_MCDI_DMA 0x00000200 1272 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1273 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1274 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1275 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1276 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1277 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1278 1279 typedef enum efx_tunnel_protocol_e { 1280 EFX_TUNNEL_PROTOCOL_NONE = 0, 1281 EFX_TUNNEL_PROTOCOL_VXLAN, 1282 EFX_TUNNEL_PROTOCOL_GENEVE, 1283 EFX_TUNNEL_PROTOCOL_NVGRE, 1284 EFX_TUNNEL_NPROTOS 1285 } efx_tunnel_protocol_t; 1286 1287 typedef enum efx_vi_window_shift_e { 1288 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1289 EFX_VI_WINDOW_SHIFT_8K = 13, 1290 EFX_VI_WINDOW_SHIFT_16K = 14, 1291 EFX_VI_WINDOW_SHIFT_64K = 16, 1292 } efx_vi_window_shift_t; 1293 1294 typedef struct efx_nic_cfg_s { 1295 uint32_t enc_board_type; 1296 uint32_t enc_phy_type; 1297 #if EFSYS_OPT_NAMES 1298 char enc_phy_name[21]; 1299 #endif 1300 char enc_phy_revision[21]; 1301 efx_mon_type_t enc_mon_type; 1302 #if EFSYS_OPT_MON_STATS 1303 uint32_t enc_mon_stat_dma_buf_size; 1304 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1305 #endif 1306 unsigned int enc_features; 1307 efx_vi_window_shift_t enc_vi_window_shift; 1308 uint8_t enc_mac_addr[6]; 1309 uint8_t enc_port; /* PHY port number */ 1310 uint32_t enc_intr_vec_base; 1311 uint32_t enc_intr_limit; 1312 uint32_t enc_evq_limit; 1313 uint32_t enc_txq_limit; 1314 uint32_t enc_rxq_limit; 1315 uint32_t enc_txq_max_ndescs; 1316 uint32_t enc_buftbl_limit; 1317 uint32_t enc_piobuf_limit; 1318 uint32_t enc_piobuf_size; 1319 uint32_t enc_piobuf_min_alloc_size; 1320 uint32_t enc_evq_timer_quantum_ns; 1321 uint32_t enc_evq_timer_max_us; 1322 uint32_t enc_clk_mult; 1323 uint32_t enc_rx_prefix_size; 1324 uint32_t enc_rx_buf_align_start; 1325 uint32_t enc_rx_buf_align_end; 1326 #if EFSYS_OPT_RX_SCALE 1327 uint32_t enc_rx_scale_max_exclusive_contexts; 1328 /* 1329 * Mask of supported hash algorithms. 1330 * Hash algorithm types are used as the bit indices. 1331 */ 1332 uint32_t enc_rx_scale_hash_alg_mask; 1333 /* 1334 * Indicates whether port numbers can be included to the 1335 * input data for hash computation. 1336 */ 1337 boolean_t enc_rx_scale_l4_hash_supported; 1338 boolean_t enc_rx_scale_additional_modes_supported; 1339 #endif /* EFSYS_OPT_RX_SCALE */ 1340 #if EFSYS_OPT_LOOPBACK 1341 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1342 #endif /* EFSYS_OPT_LOOPBACK */ 1343 #if EFSYS_OPT_PHY_FLAGS 1344 uint32_t enc_phy_flags_mask; 1345 #endif /* EFSYS_OPT_PHY_FLAGS */ 1346 #if EFSYS_OPT_PHY_LED_CONTROL 1347 uint32_t enc_led_mask; 1348 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1349 #if EFSYS_OPT_PHY_STATS 1350 uint64_t enc_phy_stat_mask; 1351 #endif /* EFSYS_OPT_PHY_STATS */ 1352 #if EFSYS_OPT_MCDI 1353 uint8_t enc_mcdi_mdio_channel; 1354 #if EFSYS_OPT_PHY_STATS 1355 uint32_t enc_mcdi_phy_stat_mask; 1356 #endif /* EFSYS_OPT_PHY_STATS */ 1357 #if EFSYS_OPT_MON_STATS 1358 uint32_t *enc_mcdi_sensor_maskp; 1359 uint32_t enc_mcdi_sensor_mask_size; 1360 #endif /* EFSYS_OPT_MON_STATS */ 1361 #endif /* EFSYS_OPT_MCDI */ 1362 #if EFSYS_OPT_BIST 1363 uint32_t enc_bist_mask; 1364 #endif /* EFSYS_OPT_BIST */ 1365 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 1366 uint32_t enc_pf; 1367 uint32_t enc_vf; 1368 uint32_t enc_privilege_mask; 1369 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 1370 boolean_t enc_bug26807_workaround; 1371 boolean_t enc_bug35388_workaround; 1372 boolean_t enc_bug41750_workaround; 1373 boolean_t enc_bug61265_workaround; 1374 boolean_t enc_bug61297_workaround; 1375 boolean_t enc_rx_batching_enabled; 1376 /* Maximum number of descriptors completed in an rx event. */ 1377 uint32_t enc_rx_batch_max; 1378 /* Number of rx descriptors the hardware requires for a push. */ 1379 uint32_t enc_rx_push_align; 1380 /* Maximum amount of data in DMA descriptor */ 1381 uint32_t enc_tx_dma_desc_size_max; 1382 /* 1383 * Boundary which DMA descriptor data must not cross or 0 if no 1384 * limitation. 1385 */ 1386 uint32_t enc_tx_dma_desc_boundary; 1387 /* 1388 * Maximum number of bytes into the packet the TCP header can start for 1389 * the hardware to apply TSO packet edits. 1390 */ 1391 uint32_t enc_tx_tso_tcp_header_offset_limit; 1392 boolean_t enc_fw_assisted_tso_enabled; 1393 boolean_t enc_fw_assisted_tso_v2_enabled; 1394 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1395 /* Number of TSO contexts on the NIC (FATSOv2) */ 1396 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1397 boolean_t enc_hw_tx_insert_vlan_enabled; 1398 /* Number of PFs on the NIC */ 1399 uint32_t enc_hw_pf_count; 1400 /* Datapath firmware vadapter/vport/vswitch support */ 1401 boolean_t enc_datapath_cap_evb; 1402 boolean_t enc_rx_disable_scatter_supported; 1403 boolean_t enc_allow_set_mac_with_installed_filters; 1404 boolean_t enc_enhanced_set_mac_supported; 1405 boolean_t enc_init_evq_v2_supported; 1406 boolean_t enc_rx_packed_stream_supported; 1407 boolean_t enc_rx_var_packed_stream_supported; 1408 boolean_t enc_rx_es_super_buffer_supported; 1409 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1410 boolean_t enc_pm_and_rxdp_counters; 1411 boolean_t enc_mac_stats_40g_tx_size_bins; 1412 uint32_t enc_tunnel_encapsulations_supported; 1413 /* 1414 * NIC global maximum for unique UDP tunnel ports shared by all 1415 * functions. 1416 */ 1417 uint32_t enc_tunnel_config_udp_entries_max; 1418 /* External port identifier */ 1419 uint8_t enc_external_port; 1420 uint32_t enc_mcdi_max_payload_length; 1421 /* VPD may be per-PF or global */ 1422 boolean_t enc_vpd_is_global; 1423 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1424 uint32_t enc_required_pcie_bandwidth_mbps; 1425 uint32_t enc_max_pcie_link_gen; 1426 /* Firmware verifies integrity of NVRAM updates */ 1427 uint32_t enc_nvram_update_verify_result_supported; 1428 /* Firmware support for extended MAC_STATS buffer */ 1429 uint32_t enc_mac_stats_nstats; 1430 boolean_t enc_fec_counters; 1431 boolean_t enc_hlb_counters; 1432 /* Firmware support for "FLAG" and "MARK" filter actions */ 1433 boolean_t enc_filter_action_flag_supported; 1434 boolean_t enc_filter_action_mark_supported; 1435 uint32_t enc_filter_action_mark_max; 1436 } efx_nic_cfg_t; 1437 1438 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1439 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1440 1441 #define EFX_PCI_FUNCTION(_encp) \ 1442 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1443 1444 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1445 1446 extern const efx_nic_cfg_t * 1447 efx_nic_cfg_get( 1448 __in efx_nic_t *enp); 1449 1450 /* RxDPCPU firmware id values by which FW variant can be identified */ 1451 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1452 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1453 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1454 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1455 #define EFX_RXDP_DPDK_FW_ID 0x6 1456 1457 typedef struct efx_nic_fw_info_s { 1458 /* Basic FW version information */ 1459 uint16_t enfi_mc_fw_version[4]; 1460 /* 1461 * If datapath capabilities can be detected, 1462 * additional FW information is to be shown 1463 */ 1464 boolean_t enfi_dpcpu_fw_ids_valid; 1465 /* Rx and Tx datapath CPU FW IDs */ 1466 uint16_t enfi_rx_dpcpu_fw_id; 1467 uint16_t enfi_tx_dpcpu_fw_id; 1468 } efx_nic_fw_info_t; 1469 1470 extern __checkReturn efx_rc_t 1471 efx_nic_get_fw_version( 1472 __in efx_nic_t *enp, 1473 __out efx_nic_fw_info_t *enfip); 1474 1475 /* Driver resource limits (minimum required/maximum usable). */ 1476 typedef struct efx_drv_limits_s { 1477 uint32_t edl_min_evq_count; 1478 uint32_t edl_max_evq_count; 1479 1480 uint32_t edl_min_rxq_count; 1481 uint32_t edl_max_rxq_count; 1482 1483 uint32_t edl_min_txq_count; 1484 uint32_t edl_max_txq_count; 1485 1486 /* PIO blocks (sub-allocated from piobuf) */ 1487 uint32_t edl_min_pio_alloc_size; 1488 uint32_t edl_max_pio_alloc_count; 1489 } efx_drv_limits_t; 1490 1491 extern __checkReturn efx_rc_t 1492 efx_nic_set_drv_limits( 1493 __inout efx_nic_t *enp, 1494 __in efx_drv_limits_t *edlp); 1495 1496 typedef enum efx_nic_region_e { 1497 EFX_REGION_VI, /* Memory BAR UC mapping */ 1498 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1499 } efx_nic_region_t; 1500 1501 extern __checkReturn efx_rc_t 1502 efx_nic_get_bar_region( 1503 __in efx_nic_t *enp, 1504 __in efx_nic_region_t region, 1505 __out uint32_t *offsetp, 1506 __out size_t *sizep); 1507 1508 extern __checkReturn efx_rc_t 1509 efx_nic_get_vi_pool( 1510 __in efx_nic_t *enp, 1511 __out uint32_t *evq_countp, 1512 __out uint32_t *rxq_countp, 1513 __out uint32_t *txq_countp); 1514 1515 1516 #if EFSYS_OPT_VPD 1517 1518 typedef enum efx_vpd_tag_e { 1519 EFX_VPD_ID = 0x02, 1520 EFX_VPD_END = 0x0f, 1521 EFX_VPD_RO = 0x10, 1522 EFX_VPD_RW = 0x11, 1523 } efx_vpd_tag_t; 1524 1525 typedef uint16_t efx_vpd_keyword_t; 1526 1527 typedef struct efx_vpd_value_s { 1528 efx_vpd_tag_t evv_tag; 1529 efx_vpd_keyword_t evv_keyword; 1530 uint8_t evv_length; 1531 uint8_t evv_value[0x100]; 1532 } efx_vpd_value_t; 1533 1534 1535 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1536 1537 extern __checkReturn efx_rc_t 1538 efx_vpd_init( 1539 __in efx_nic_t *enp); 1540 1541 extern __checkReturn efx_rc_t 1542 efx_vpd_size( 1543 __in efx_nic_t *enp, 1544 __out size_t *sizep); 1545 1546 extern __checkReturn efx_rc_t 1547 efx_vpd_read( 1548 __in efx_nic_t *enp, 1549 __out_bcount(size) caddr_t data, 1550 __in size_t size); 1551 1552 extern __checkReturn efx_rc_t 1553 efx_vpd_verify( 1554 __in efx_nic_t *enp, 1555 __in_bcount(size) caddr_t data, 1556 __in size_t size); 1557 1558 extern __checkReturn efx_rc_t 1559 efx_vpd_reinit( 1560 __in efx_nic_t *enp, 1561 __in_bcount(size) caddr_t data, 1562 __in size_t size); 1563 1564 extern __checkReturn efx_rc_t 1565 efx_vpd_get( 1566 __in efx_nic_t *enp, 1567 __in_bcount(size) caddr_t data, 1568 __in size_t size, 1569 __inout efx_vpd_value_t *evvp); 1570 1571 extern __checkReturn efx_rc_t 1572 efx_vpd_set( 1573 __in efx_nic_t *enp, 1574 __inout_bcount(size) caddr_t data, 1575 __in size_t size, 1576 __in efx_vpd_value_t *evvp); 1577 1578 extern __checkReturn efx_rc_t 1579 efx_vpd_next( 1580 __in efx_nic_t *enp, 1581 __inout_bcount(size) caddr_t data, 1582 __in size_t size, 1583 __out efx_vpd_value_t *evvp, 1584 __inout unsigned int *contp); 1585 1586 extern __checkReturn efx_rc_t 1587 efx_vpd_write( 1588 __in efx_nic_t *enp, 1589 __in_bcount(size) caddr_t data, 1590 __in size_t size); 1591 1592 extern void 1593 efx_vpd_fini( 1594 __in efx_nic_t *enp); 1595 1596 #endif /* EFSYS_OPT_VPD */ 1597 1598 /* NVRAM */ 1599 1600 #if EFSYS_OPT_NVRAM 1601 1602 typedef enum efx_nvram_type_e { 1603 EFX_NVRAM_INVALID = 0, 1604 EFX_NVRAM_BOOTROM, 1605 EFX_NVRAM_BOOTROM_CFG, 1606 EFX_NVRAM_MC_FIRMWARE, 1607 EFX_NVRAM_MC_GOLDEN, 1608 EFX_NVRAM_PHY, 1609 EFX_NVRAM_NULLPHY, 1610 EFX_NVRAM_FPGA, 1611 EFX_NVRAM_FCFW, 1612 EFX_NVRAM_CPLD, 1613 EFX_NVRAM_FPGA_BACKUP, 1614 EFX_NVRAM_DYNAMIC_CFG, 1615 EFX_NVRAM_LICENSE, 1616 EFX_NVRAM_UEFIROM, 1617 EFX_NVRAM_MUM_FIRMWARE, 1618 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1619 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1620 EFX_NVRAM_NTYPES, 1621 } efx_nvram_type_t; 1622 1623 extern __checkReturn efx_rc_t 1624 efx_nvram_init( 1625 __in efx_nic_t *enp); 1626 1627 #if EFSYS_OPT_DIAG 1628 1629 extern __checkReturn efx_rc_t 1630 efx_nvram_test( 1631 __in efx_nic_t *enp); 1632 1633 #endif /* EFSYS_OPT_DIAG */ 1634 1635 extern __checkReturn efx_rc_t 1636 efx_nvram_size( 1637 __in efx_nic_t *enp, 1638 __in efx_nvram_type_t type, 1639 __out size_t *sizep); 1640 1641 extern __checkReturn efx_rc_t 1642 efx_nvram_rw_start( 1643 __in efx_nic_t *enp, 1644 __in efx_nvram_type_t type, 1645 __out_opt size_t *pref_chunkp); 1646 1647 extern __checkReturn efx_rc_t 1648 efx_nvram_rw_finish( 1649 __in efx_nic_t *enp, 1650 __in efx_nvram_type_t type, 1651 __out_opt uint32_t *verify_resultp); 1652 1653 extern __checkReturn efx_rc_t 1654 efx_nvram_get_version( 1655 __in efx_nic_t *enp, 1656 __in efx_nvram_type_t type, 1657 __out uint32_t *subtypep, 1658 __out_ecount(4) uint16_t version[4]); 1659 1660 extern __checkReturn efx_rc_t 1661 efx_nvram_read_chunk( 1662 __in efx_nic_t *enp, 1663 __in efx_nvram_type_t type, 1664 __in unsigned int offset, 1665 __out_bcount(size) caddr_t data, 1666 __in size_t size); 1667 1668 extern __checkReturn efx_rc_t 1669 efx_nvram_read_backup( 1670 __in efx_nic_t *enp, 1671 __in efx_nvram_type_t type, 1672 __in unsigned int offset, 1673 __out_bcount(size) caddr_t data, 1674 __in size_t size); 1675 1676 extern __checkReturn efx_rc_t 1677 efx_nvram_set_version( 1678 __in efx_nic_t *enp, 1679 __in efx_nvram_type_t type, 1680 __in_ecount(4) uint16_t version[4]); 1681 1682 extern __checkReturn efx_rc_t 1683 efx_nvram_validate( 1684 __in efx_nic_t *enp, 1685 __in efx_nvram_type_t type, 1686 __in_bcount(partn_size) caddr_t partn_data, 1687 __in size_t partn_size); 1688 1689 extern __checkReturn efx_rc_t 1690 efx_nvram_erase( 1691 __in efx_nic_t *enp, 1692 __in efx_nvram_type_t type); 1693 1694 extern __checkReturn efx_rc_t 1695 efx_nvram_write_chunk( 1696 __in efx_nic_t *enp, 1697 __in efx_nvram_type_t type, 1698 __in unsigned int offset, 1699 __in_bcount(size) caddr_t data, 1700 __in size_t size); 1701 1702 extern void 1703 efx_nvram_fini( 1704 __in efx_nic_t *enp); 1705 1706 #endif /* EFSYS_OPT_NVRAM */ 1707 1708 #if EFSYS_OPT_BOOTCFG 1709 1710 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1711 extern __checkReturn efx_rc_t 1712 efx_bootcfg_sector_info( 1713 __in efx_nic_t *enp, 1714 __in uint32_t pf, 1715 __out_opt uint32_t *sector_countp, 1716 __out size_t *offsetp, 1717 __out size_t *max_sizep); 1718 1719 /* 1720 * Copy bootcfg sector data to a target buffer which may differ in size. 1721 * Optionally corrects format errors in source buffer. 1722 */ 1723 extern efx_rc_t 1724 efx_bootcfg_copy_sector( 1725 __in efx_nic_t *enp, 1726 __inout_bcount(sector_length) 1727 uint8_t *sector, 1728 __in size_t sector_length, 1729 __out_bcount(data_size) uint8_t *data, 1730 __in size_t data_size, 1731 __in boolean_t handle_format_errors); 1732 1733 extern efx_rc_t 1734 efx_bootcfg_read( 1735 __in efx_nic_t *enp, 1736 __out_bcount(size) uint8_t *data, 1737 __in size_t size); 1738 1739 extern efx_rc_t 1740 efx_bootcfg_write( 1741 __in efx_nic_t *enp, 1742 __in_bcount(size) uint8_t *data, 1743 __in size_t size); 1744 1745 1746 /* 1747 * Processing routines for buffers arranged in the DHCP/BOOTP option format 1748 * (see https://tools.ietf.org/html/rfc1533) 1749 * 1750 * Summarising the format: the buffer is a sequence of options. All options 1751 * begin with a tag octet, which uniquely identifies the option. Fixed- 1752 * length options without data consist of only a tag octet. Only options PAD 1753 * (0) and END (255) are fixed length. All other options are variable-length 1754 * with a length octet following the tag octet. The value of the length 1755 * octet does not include the two octets specifying the tag and length. The 1756 * length octet is followed by "length" octets of data. 1757 * 1758 * Option data may be a sequence of sub-options in the same format. The data 1759 * content of the encapsulating option is one or more encapsulated sub-options, 1760 * with no terminating END tag is required. 1761 * 1762 * To be valid, the top-level sequence of options should be terminated by an 1763 * END tag. The buffer should be padded with the PAD byte. 1764 * 1765 * When stored to NVRAM, the DHCP option format buffer is preceded by a 1766 * checksum octet. The full buffer (including after the END tag) contributes 1767 * to the checksum, hence the need to fill the buffer to the end with PAD. 1768 */ 1769 1770 #define EFX_DHCP_END ((uint8_t)0xff) 1771 #define EFX_DHCP_PAD ((uint8_t)0) 1772 1773 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 1774 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 1775 1776 extern __checkReturn uint8_t 1777 efx_dhcp_csum( 1778 __in_bcount(size) uint8_t const *data, 1779 __in size_t size); 1780 1781 extern __checkReturn efx_rc_t 1782 efx_dhcp_verify( 1783 __in_bcount(size) uint8_t const *data, 1784 __in size_t size, 1785 __out_opt size_t *usedp); 1786 1787 extern __checkReturn efx_rc_t 1788 efx_dhcp_find_tag( 1789 __in_bcount(buffer_length) uint8_t *bufferp, 1790 __in size_t buffer_length, 1791 __in uint16_t opt, 1792 __deref_out uint8_t **valuepp, 1793 __out size_t *value_lengthp); 1794 1795 extern __checkReturn efx_rc_t 1796 efx_dhcp_find_end( 1797 __in_bcount(buffer_length) uint8_t *bufferp, 1798 __in size_t buffer_length, 1799 __deref_out uint8_t **endpp); 1800 1801 1802 extern __checkReturn efx_rc_t 1803 efx_dhcp_delete_tag( 1804 __inout_bcount(buffer_length) uint8_t *bufferp, 1805 __in size_t buffer_length, 1806 __in uint16_t opt); 1807 1808 extern __checkReturn efx_rc_t 1809 efx_dhcp_add_tag( 1810 __inout_bcount(buffer_length) uint8_t *bufferp, 1811 __in size_t buffer_length, 1812 __in uint16_t opt, 1813 __in_bcount_opt(value_length) uint8_t *valuep, 1814 __in size_t value_length); 1815 1816 extern __checkReturn efx_rc_t 1817 efx_dhcp_update_tag( 1818 __inout_bcount(buffer_length) uint8_t *bufferp, 1819 __in size_t buffer_length, 1820 __in uint16_t opt, 1821 __in uint8_t *value_locationp, 1822 __in_bcount_opt(value_length) uint8_t *valuep, 1823 __in size_t value_length); 1824 1825 1826 #endif /* EFSYS_OPT_BOOTCFG */ 1827 1828 #if EFSYS_OPT_IMAGE_LAYOUT 1829 1830 #include "ef10_signed_image_layout.h" 1831 1832 /* 1833 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 1834 * 1835 * NOTE: 1836 * The image header format is extensible. However, older drivers require an 1837 * exact match of image header version and header length when validating and 1838 * writing firmware images. 1839 * 1840 * To avoid breaking backward compatibility, we use the upper bits of the 1841 * controller version fields to contain an extra version number used for 1842 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 1843 * version). See bug39254 and SF-102785-PS for details. 1844 */ 1845 typedef struct efx_image_header_s { 1846 uint32_t eih_magic; 1847 uint32_t eih_version; 1848 uint32_t eih_type; 1849 uint32_t eih_subtype; 1850 uint32_t eih_code_size; 1851 uint32_t eih_size; 1852 union { 1853 uint32_t eih_controller_version_min; 1854 struct { 1855 uint16_t eih_controller_version_min_short; 1856 uint8_t eih_extra_version_a; 1857 uint8_t eih_extra_version_b; 1858 }; 1859 }; 1860 union { 1861 uint32_t eih_controller_version_max; 1862 struct { 1863 uint16_t eih_controller_version_max_short; 1864 uint8_t eih_extra_version_c; 1865 uint8_t eih_extra_version_d; 1866 }; 1867 }; 1868 uint16_t eih_code_version_a; 1869 uint16_t eih_code_version_b; 1870 uint16_t eih_code_version_c; 1871 uint16_t eih_code_version_d; 1872 } efx_image_header_t; 1873 1874 #define EFX_IMAGE_HEADER_SIZE (40) 1875 #define EFX_IMAGE_HEADER_VERSION (4) 1876 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 1877 1878 1879 typedef struct efx_image_trailer_s { 1880 uint32_t eit_crc; 1881 } efx_image_trailer_t; 1882 1883 #define EFX_IMAGE_TRAILER_SIZE (4) 1884 1885 typedef enum efx_image_format_e { 1886 EFX_IMAGE_FORMAT_NO_IMAGE, 1887 EFX_IMAGE_FORMAT_INVALID, 1888 EFX_IMAGE_FORMAT_UNSIGNED, 1889 EFX_IMAGE_FORMAT_SIGNED, 1890 } efx_image_format_t; 1891 1892 typedef struct efx_image_info_s { 1893 efx_image_format_t eii_format; 1894 uint8_t * eii_imagep; 1895 size_t eii_image_size; 1896 efx_image_header_t * eii_headerp; 1897 } efx_image_info_t; 1898 1899 extern __checkReturn efx_rc_t 1900 efx_check_reflash_image( 1901 __in void *bufferp, 1902 __in uint32_t buffer_size, 1903 __out efx_image_info_t *infop); 1904 1905 extern __checkReturn efx_rc_t 1906 efx_build_signed_image_write_buffer( 1907 __out_bcount(buffer_size) 1908 uint8_t *bufferp, 1909 __in uint32_t buffer_size, 1910 __in efx_image_info_t *infop, 1911 __out efx_image_header_t **headerpp); 1912 1913 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 1914 1915 #if EFSYS_OPT_DIAG 1916 1917 typedef enum efx_pattern_type_t { 1918 EFX_PATTERN_BYTE_INCREMENT = 0, 1919 EFX_PATTERN_ALL_THE_SAME, 1920 EFX_PATTERN_BIT_ALTERNATE, 1921 EFX_PATTERN_BYTE_ALTERNATE, 1922 EFX_PATTERN_BYTE_CHANGING, 1923 EFX_PATTERN_BIT_SWEEP, 1924 EFX_PATTERN_NTYPES 1925 } efx_pattern_type_t; 1926 1927 typedef void 1928 (*efx_sram_pattern_fn_t)( 1929 __in size_t row, 1930 __in boolean_t negate, 1931 __out efx_qword_t *eqp); 1932 1933 extern __checkReturn efx_rc_t 1934 efx_sram_test( 1935 __in efx_nic_t *enp, 1936 __in efx_pattern_type_t type); 1937 1938 #endif /* EFSYS_OPT_DIAG */ 1939 1940 extern __checkReturn efx_rc_t 1941 efx_sram_buf_tbl_set( 1942 __in efx_nic_t *enp, 1943 __in uint32_t id, 1944 __in efsys_mem_t *esmp, 1945 __in size_t n); 1946 1947 extern void 1948 efx_sram_buf_tbl_clear( 1949 __in efx_nic_t *enp, 1950 __in uint32_t id, 1951 __in size_t n); 1952 1953 #define EFX_BUF_TBL_SIZE 0x20000 1954 1955 #define EFX_BUF_SIZE 4096 1956 1957 /* EV */ 1958 1959 typedef struct efx_evq_s efx_evq_t; 1960 1961 #if EFSYS_OPT_QSTATS 1962 1963 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1964 typedef enum efx_ev_qstat_e { 1965 EV_ALL, 1966 EV_RX, 1967 EV_RX_OK, 1968 EV_RX_FRM_TRUNC, 1969 EV_RX_TOBE_DISC, 1970 EV_RX_PAUSE_FRM_ERR, 1971 EV_RX_BUF_OWNER_ID_ERR, 1972 EV_RX_IPV4_HDR_CHKSUM_ERR, 1973 EV_RX_TCP_UDP_CHKSUM_ERR, 1974 EV_RX_ETH_CRC_ERR, 1975 EV_RX_IP_FRAG_ERR, 1976 EV_RX_MCAST_PKT, 1977 EV_RX_MCAST_HASH_MATCH, 1978 EV_RX_TCP_IPV4, 1979 EV_RX_TCP_IPV6, 1980 EV_RX_UDP_IPV4, 1981 EV_RX_UDP_IPV6, 1982 EV_RX_OTHER_IPV4, 1983 EV_RX_OTHER_IPV6, 1984 EV_RX_NON_IP, 1985 EV_RX_BATCH, 1986 EV_TX, 1987 EV_TX_WQ_FF_FULL, 1988 EV_TX_PKT_ERR, 1989 EV_TX_PKT_TOO_BIG, 1990 EV_TX_UNEXPECTED, 1991 EV_GLOBAL, 1992 EV_GLOBAL_MNT, 1993 EV_DRIVER, 1994 EV_DRIVER_SRM_UPD_DONE, 1995 EV_DRIVER_TX_DESCQ_FLS_DONE, 1996 EV_DRIVER_RX_DESCQ_FLS_DONE, 1997 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1998 EV_DRIVER_RX_DSC_ERROR, 1999 EV_DRIVER_TX_DSC_ERROR, 2000 EV_DRV_GEN, 2001 EV_MCDI_RESPONSE, 2002 EV_NQSTATS 2003 } efx_ev_qstat_t; 2004 2005 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2006 2007 #endif /* EFSYS_OPT_QSTATS */ 2008 2009 extern __checkReturn efx_rc_t 2010 efx_ev_init( 2011 __in efx_nic_t *enp); 2012 2013 extern void 2014 efx_ev_fini( 2015 __in efx_nic_t *enp); 2016 2017 #define EFX_EVQ_MAXNEVS 32768 2018 #define EFX_EVQ_MINNEVS 512 2019 2020 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 2021 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 2022 2023 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2024 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2025 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2026 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2027 2028 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2029 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2030 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2031 2032 extern __checkReturn efx_rc_t 2033 efx_ev_qcreate( 2034 __in efx_nic_t *enp, 2035 __in unsigned int index, 2036 __in efsys_mem_t *esmp, 2037 __in size_t ndescs, 2038 __in uint32_t id, 2039 __in uint32_t us, 2040 __in uint32_t flags, 2041 __deref_out efx_evq_t **eepp); 2042 2043 extern void 2044 efx_ev_qpost( 2045 __in efx_evq_t *eep, 2046 __in uint16_t data); 2047 2048 typedef __checkReturn boolean_t 2049 (*efx_initialized_ev_t)( 2050 __in_opt void *arg); 2051 2052 #define EFX_PKT_UNICAST 0x0004 2053 #define EFX_PKT_START 0x0008 2054 2055 #define EFX_PKT_VLAN_TAGGED 0x0010 2056 #define EFX_CKSUM_TCPUDP 0x0020 2057 #define EFX_CKSUM_IPV4 0x0040 2058 #define EFX_PKT_CONT 0x0080 2059 2060 #define EFX_CHECK_VLAN 0x0100 2061 #define EFX_PKT_TCP 0x0200 2062 #define EFX_PKT_UDP 0x0400 2063 #define EFX_PKT_IPV4 0x0800 2064 2065 #define EFX_PKT_IPV6 0x1000 2066 #define EFX_PKT_PREFIX_LEN 0x2000 2067 #define EFX_ADDR_MISMATCH 0x4000 2068 #define EFX_DISCARD 0x8000 2069 2070 /* 2071 * The following flags are used only for packed stream 2072 * mode. The values for the flags are reused to fit into 16 bit, 2073 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2074 * packed stream mode 2075 */ 2076 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2077 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2078 2079 2080 #define EFX_EV_RX_NLABELS 32 2081 #define EFX_EV_TX_NLABELS 32 2082 2083 typedef __checkReturn boolean_t 2084 (*efx_rx_ev_t)( 2085 __in_opt void *arg, 2086 __in uint32_t label, 2087 __in uint32_t id, 2088 __in uint32_t size, 2089 __in uint16_t flags); 2090 2091 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2092 2093 /* 2094 * Packed stream mode is documented in SF-112241-TC. 2095 * The general idea is that, instead of putting each incoming 2096 * packet into a separate buffer which is specified in a RX 2097 * descriptor, a large buffer is provided to the hardware and 2098 * packets are put there in a continuous stream. 2099 * The main advantage of such an approach is that RX queue refilling 2100 * happens much less frequently. 2101 * 2102 * Equal stride packed stream mode is documented in SF-119419-TC. 2103 * The general idea is to utilize advantages of the packed stream, 2104 * but avoid indirection in packets representation. 2105 * The main advantage of such an approach is that RX queue refilling 2106 * happens much less frequently and packets buffers are independent 2107 * from upper layers point of view. 2108 */ 2109 2110 typedef __checkReturn boolean_t 2111 (*efx_rx_ps_ev_t)( 2112 __in_opt void *arg, 2113 __in uint32_t label, 2114 __in uint32_t id, 2115 __in uint32_t pkt_count, 2116 __in uint16_t flags); 2117 2118 #endif 2119 2120 typedef __checkReturn boolean_t 2121 (*efx_tx_ev_t)( 2122 __in_opt void *arg, 2123 __in uint32_t label, 2124 __in uint32_t id); 2125 2126 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2127 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2128 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2129 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2130 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2131 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2132 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2133 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2134 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2135 2136 typedef __checkReturn boolean_t 2137 (*efx_exception_ev_t)( 2138 __in_opt void *arg, 2139 __in uint32_t label, 2140 __in uint32_t data); 2141 2142 typedef __checkReturn boolean_t 2143 (*efx_rxq_flush_done_ev_t)( 2144 __in_opt void *arg, 2145 __in uint32_t rxq_index); 2146 2147 typedef __checkReturn boolean_t 2148 (*efx_rxq_flush_failed_ev_t)( 2149 __in_opt void *arg, 2150 __in uint32_t rxq_index); 2151 2152 typedef __checkReturn boolean_t 2153 (*efx_txq_flush_done_ev_t)( 2154 __in_opt void *arg, 2155 __in uint32_t txq_index); 2156 2157 typedef __checkReturn boolean_t 2158 (*efx_software_ev_t)( 2159 __in_opt void *arg, 2160 __in uint16_t magic); 2161 2162 typedef __checkReturn boolean_t 2163 (*efx_sram_ev_t)( 2164 __in_opt void *arg, 2165 __in uint32_t code); 2166 2167 #define EFX_SRAM_CLEAR 0 2168 #define EFX_SRAM_UPDATE 1 2169 #define EFX_SRAM_ILLEGAL_CLEAR 2 2170 2171 typedef __checkReturn boolean_t 2172 (*efx_wake_up_ev_t)( 2173 __in_opt void *arg, 2174 __in uint32_t label); 2175 2176 typedef __checkReturn boolean_t 2177 (*efx_timer_ev_t)( 2178 __in_opt void *arg, 2179 __in uint32_t label); 2180 2181 typedef __checkReturn boolean_t 2182 (*efx_link_change_ev_t)( 2183 __in_opt void *arg, 2184 __in efx_link_mode_t link_mode); 2185 2186 #if EFSYS_OPT_MON_STATS 2187 2188 typedef __checkReturn boolean_t 2189 (*efx_monitor_ev_t)( 2190 __in_opt void *arg, 2191 __in efx_mon_stat_t id, 2192 __in efx_mon_stat_value_t value); 2193 2194 #endif /* EFSYS_OPT_MON_STATS */ 2195 2196 #if EFSYS_OPT_MAC_STATS 2197 2198 typedef __checkReturn boolean_t 2199 (*efx_mac_stats_ev_t)( 2200 __in_opt void *arg, 2201 __in uint32_t generation); 2202 2203 #endif /* EFSYS_OPT_MAC_STATS */ 2204 2205 typedef struct efx_ev_callbacks_s { 2206 efx_initialized_ev_t eec_initialized; 2207 efx_rx_ev_t eec_rx; 2208 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2209 efx_rx_ps_ev_t eec_rx_ps; 2210 #endif 2211 efx_tx_ev_t eec_tx; 2212 efx_exception_ev_t eec_exception; 2213 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2214 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2215 efx_txq_flush_done_ev_t eec_txq_flush_done; 2216 efx_software_ev_t eec_software; 2217 efx_sram_ev_t eec_sram; 2218 efx_wake_up_ev_t eec_wake_up; 2219 efx_timer_ev_t eec_timer; 2220 efx_link_change_ev_t eec_link_change; 2221 #if EFSYS_OPT_MON_STATS 2222 efx_monitor_ev_t eec_monitor; 2223 #endif /* EFSYS_OPT_MON_STATS */ 2224 #if EFSYS_OPT_MAC_STATS 2225 efx_mac_stats_ev_t eec_mac_stats; 2226 #endif /* EFSYS_OPT_MAC_STATS */ 2227 } efx_ev_callbacks_t; 2228 2229 extern __checkReturn boolean_t 2230 efx_ev_qpending( 2231 __in efx_evq_t *eep, 2232 __in unsigned int count); 2233 2234 #if EFSYS_OPT_EV_PREFETCH 2235 2236 extern void 2237 efx_ev_qprefetch( 2238 __in efx_evq_t *eep, 2239 __in unsigned int count); 2240 2241 #endif /* EFSYS_OPT_EV_PREFETCH */ 2242 2243 extern void 2244 efx_ev_qpoll( 2245 __in efx_evq_t *eep, 2246 __inout unsigned int *countp, 2247 __in const efx_ev_callbacks_t *eecp, 2248 __in_opt void *arg); 2249 2250 extern __checkReturn efx_rc_t 2251 efx_ev_usecs_to_ticks( 2252 __in efx_nic_t *enp, 2253 __in unsigned int usecs, 2254 __out unsigned int *ticksp); 2255 2256 extern __checkReturn efx_rc_t 2257 efx_ev_qmoderate( 2258 __in efx_evq_t *eep, 2259 __in unsigned int us); 2260 2261 extern __checkReturn efx_rc_t 2262 efx_ev_qprime( 2263 __in efx_evq_t *eep, 2264 __in unsigned int count); 2265 2266 #if EFSYS_OPT_QSTATS 2267 2268 #if EFSYS_OPT_NAMES 2269 2270 extern const char * 2271 efx_ev_qstat_name( 2272 __in efx_nic_t *enp, 2273 __in unsigned int id); 2274 2275 #endif /* EFSYS_OPT_NAMES */ 2276 2277 extern void 2278 efx_ev_qstats_update( 2279 __in efx_evq_t *eep, 2280 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2281 2282 #endif /* EFSYS_OPT_QSTATS */ 2283 2284 extern void 2285 efx_ev_qdestroy( 2286 __in efx_evq_t *eep); 2287 2288 /* RX */ 2289 2290 extern __checkReturn efx_rc_t 2291 efx_rx_init( 2292 __inout efx_nic_t *enp); 2293 2294 extern void 2295 efx_rx_fini( 2296 __in efx_nic_t *enp); 2297 2298 #if EFSYS_OPT_RX_SCATTER 2299 __checkReturn efx_rc_t 2300 efx_rx_scatter_enable( 2301 __in efx_nic_t *enp, 2302 __in unsigned int buf_size); 2303 #endif /* EFSYS_OPT_RX_SCATTER */ 2304 2305 /* Handle to represent use of the default RSS context. */ 2306 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2307 2308 #if EFSYS_OPT_RX_SCALE 2309 2310 typedef enum efx_rx_hash_alg_e { 2311 EFX_RX_HASHALG_LFSR = 0, 2312 EFX_RX_HASHALG_TOEPLITZ, 2313 EFX_RX_HASHALG_PACKED_STREAM, 2314 EFX_RX_NHASHALGS 2315 } efx_rx_hash_alg_t; 2316 2317 /* 2318 * Legacy hash type flags. 2319 * 2320 * They represent standard tuples for distinct traffic classes. 2321 */ 2322 #define EFX_RX_HASH_IPV4 (1U << 0) 2323 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2324 #define EFX_RX_HASH_IPV6 (1U << 2) 2325 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2326 2327 #define EFX_RX_HASH_LEGACY_MASK \ 2328 (EFX_RX_HASH_IPV4 | \ 2329 EFX_RX_HASH_TCPIPV4 | \ 2330 EFX_RX_HASH_IPV6 | \ 2331 EFX_RX_HASH_TCPIPV6) 2332 2333 /* 2334 * The type of the argument used by efx_rx_scale_mode_set() to 2335 * provide a means for the client drivers to configure hashing. 2336 * 2337 * A properly constructed value can either be: 2338 * - a combination of legacy flags 2339 * - a combination of EFX_RX_HASH() flags 2340 */ 2341 typedef uint32_t efx_rx_hash_type_t; 2342 2343 typedef enum efx_rx_hash_support_e { 2344 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2345 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2346 } efx_rx_hash_support_t; 2347 2348 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2349 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2350 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2351 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2352 2353 typedef enum efx_rx_scale_context_type_e { 2354 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2355 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2356 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2357 } efx_rx_scale_context_type_t; 2358 2359 /* 2360 * Traffic classes eligible for hash computation. 2361 * 2362 * Select packet headers used in computing the receive hash. 2363 * This uses the same encoding as the RSS_MODES field of 2364 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2365 */ 2366 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2367 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2368 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2369 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2370 #define EFX_RX_CLASS_IPV4_LBN 16 2371 #define EFX_RX_CLASS_IPV4_WIDTH 4 2372 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2373 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2374 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2375 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2376 #define EFX_RX_CLASS_IPV6_LBN 28 2377 #define EFX_RX_CLASS_IPV6_WIDTH 4 2378 2379 #define EFX_RX_NCLASSES 6 2380 2381 /* 2382 * Ancillary flags used to construct generic hash tuples. 2383 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2384 */ 2385 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2386 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2387 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2388 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2389 2390 /* 2391 * Generic hash tuples. 2392 * 2393 * They express combinations of packet fields 2394 * which can contribute to the hash value for 2395 * a particular traffic class. 2396 */ 2397 #define EFX_RX_CLASS_HASH_DISABLE 0 2398 2399 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2400 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2401 2402 #define EFX_RX_CLASS_HASH_2TUPLE \ 2403 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2404 EFX_RX_CLASS_HASH_DST_ADDR) 2405 2406 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2407 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2408 EFX_RX_CLASS_HASH_SRC_PORT) 2409 2410 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2411 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2412 EFX_RX_CLASS_HASH_DST_PORT) 2413 2414 #define EFX_RX_CLASS_HASH_4TUPLE \ 2415 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2416 EFX_RX_CLASS_HASH_DST_ADDR | \ 2417 EFX_RX_CLASS_HASH_SRC_PORT | \ 2418 EFX_RX_CLASS_HASH_DST_PORT) 2419 2420 #define EFX_RX_CLASS_HASH_NTUPLES 7 2421 2422 /* 2423 * Hash flag constructor. 2424 * 2425 * Resulting flags encode hash tuples for specific traffic classes. 2426 * The client drivers are encouraged to use these flags to form 2427 * a hash type value. 2428 */ 2429 #define EFX_RX_HASH(_class, _tuple) \ 2430 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2431 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2432 2433 /* 2434 * The maximum number of EFX_RX_HASH() flags. 2435 */ 2436 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2437 2438 extern __checkReturn efx_rc_t 2439 efx_rx_scale_hash_flags_get( 2440 __in efx_nic_t *enp, 2441 __in efx_rx_hash_alg_t hash_alg, 2442 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2443 __in unsigned int max_nflags, 2444 __out unsigned int *nflagsp); 2445 2446 extern __checkReturn efx_rc_t 2447 efx_rx_hash_default_support_get( 2448 __in efx_nic_t *enp, 2449 __out efx_rx_hash_support_t *supportp); 2450 2451 2452 extern __checkReturn efx_rc_t 2453 efx_rx_scale_default_support_get( 2454 __in efx_nic_t *enp, 2455 __out efx_rx_scale_context_type_t *typep); 2456 2457 extern __checkReturn efx_rc_t 2458 efx_rx_scale_context_alloc( 2459 __in efx_nic_t *enp, 2460 __in efx_rx_scale_context_type_t type, 2461 __in uint32_t num_queues, 2462 __out uint32_t *rss_contextp); 2463 2464 extern __checkReturn efx_rc_t 2465 efx_rx_scale_context_free( 2466 __in efx_nic_t *enp, 2467 __in uint32_t rss_context); 2468 2469 extern __checkReturn efx_rc_t 2470 efx_rx_scale_mode_set( 2471 __in efx_nic_t *enp, 2472 __in uint32_t rss_context, 2473 __in efx_rx_hash_alg_t alg, 2474 __in efx_rx_hash_type_t type, 2475 __in boolean_t insert); 2476 2477 extern __checkReturn efx_rc_t 2478 efx_rx_scale_tbl_set( 2479 __in efx_nic_t *enp, 2480 __in uint32_t rss_context, 2481 __in_ecount(n) unsigned int *table, 2482 __in size_t n); 2483 2484 extern __checkReturn efx_rc_t 2485 efx_rx_scale_key_set( 2486 __in efx_nic_t *enp, 2487 __in uint32_t rss_context, 2488 __in_ecount(n) uint8_t *key, 2489 __in size_t n); 2490 2491 extern __checkReturn uint32_t 2492 efx_pseudo_hdr_hash_get( 2493 __in efx_rxq_t *erp, 2494 __in efx_rx_hash_alg_t func, 2495 __in uint8_t *buffer); 2496 2497 #endif /* EFSYS_OPT_RX_SCALE */ 2498 2499 extern __checkReturn efx_rc_t 2500 efx_pseudo_hdr_pkt_length_get( 2501 __in efx_rxq_t *erp, 2502 __in uint8_t *buffer, 2503 __out uint16_t *pkt_lengthp); 2504 2505 #define EFX_RXQ_MAXNDESCS 4096 2506 #define EFX_RXQ_MINNDESCS 512 2507 2508 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2509 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2510 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2511 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2512 2513 typedef enum efx_rxq_type_e { 2514 EFX_RXQ_TYPE_DEFAULT, 2515 EFX_RXQ_TYPE_PACKED_STREAM, 2516 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 2517 EFX_RXQ_NTYPES 2518 } efx_rxq_type_t; 2519 2520 /* 2521 * Dummy flag to be used instead of 0 to make it clear that the argument 2522 * is receive queue flags. 2523 */ 2524 #define EFX_RXQ_FLAG_NONE 0x0 2525 #define EFX_RXQ_FLAG_SCATTER 0x1 2526 /* 2527 * If tunnels are supported and Rx event can provide information about 2528 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2529 * full-feature firmware variant running), outer classes are requested by 2530 * default. However, if the driver supports tunnels, the flag allows to 2531 * request inner classes which are required to be able to interpret inner 2532 * Rx checksum offload results. 2533 */ 2534 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2535 2536 extern __checkReturn efx_rc_t 2537 efx_rx_qcreate( 2538 __in efx_nic_t *enp, 2539 __in unsigned int index, 2540 __in unsigned int label, 2541 __in efx_rxq_type_t type, 2542 __in efsys_mem_t *esmp, 2543 __in size_t ndescs, 2544 __in uint32_t id, 2545 __in unsigned int flags, 2546 __in efx_evq_t *eep, 2547 __deref_out efx_rxq_t **erpp); 2548 2549 #if EFSYS_OPT_RX_PACKED_STREAM 2550 2551 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2552 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2553 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2554 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2555 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2556 2557 extern __checkReturn efx_rc_t 2558 efx_rx_qcreate_packed_stream( 2559 __in efx_nic_t *enp, 2560 __in unsigned int index, 2561 __in unsigned int label, 2562 __in uint32_t ps_buf_size, 2563 __in efsys_mem_t *esmp, 2564 __in size_t ndescs, 2565 __in efx_evq_t *eep, 2566 __deref_out efx_rxq_t **erpp); 2567 2568 #endif 2569 2570 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 2571 2572 /* Maximum head-of-line block timeout in nanoseconds */ 2573 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 2574 2575 extern __checkReturn efx_rc_t 2576 efx_rx_qcreate_es_super_buffer( 2577 __in efx_nic_t *enp, 2578 __in unsigned int index, 2579 __in unsigned int label, 2580 __in uint32_t n_bufs_per_desc, 2581 __in uint32_t max_dma_len, 2582 __in uint32_t buf_stride, 2583 __in uint32_t hol_block_timeout, 2584 __in efsys_mem_t *esmp, 2585 __in size_t ndescs, 2586 __in unsigned int flags, 2587 __in efx_evq_t *eep, 2588 __deref_out efx_rxq_t **erpp); 2589 2590 #endif 2591 2592 typedef struct efx_buffer_s { 2593 efsys_dma_addr_t eb_addr; 2594 size_t eb_size; 2595 boolean_t eb_eop; 2596 } efx_buffer_t; 2597 2598 typedef struct efx_desc_s { 2599 efx_qword_t ed_eq; 2600 } efx_desc_t; 2601 2602 extern void 2603 efx_rx_qpost( 2604 __in efx_rxq_t *erp, 2605 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 2606 __in size_t size, 2607 __in unsigned int ndescs, 2608 __in unsigned int completed, 2609 __in unsigned int added); 2610 2611 extern void 2612 efx_rx_qpush( 2613 __in efx_rxq_t *erp, 2614 __in unsigned int added, 2615 __inout unsigned int *pushedp); 2616 2617 #if EFSYS_OPT_RX_PACKED_STREAM 2618 2619 extern void 2620 efx_rx_qpush_ps_credits( 2621 __in efx_rxq_t *erp); 2622 2623 extern __checkReturn uint8_t * 2624 efx_rx_qps_packet_info( 2625 __in efx_rxq_t *erp, 2626 __in uint8_t *buffer, 2627 __in uint32_t buffer_length, 2628 __in uint32_t current_offset, 2629 __out uint16_t *lengthp, 2630 __out uint32_t *next_offsetp, 2631 __out uint32_t *timestamp); 2632 #endif 2633 2634 extern __checkReturn efx_rc_t 2635 efx_rx_qflush( 2636 __in efx_rxq_t *erp); 2637 2638 extern void 2639 efx_rx_qenable( 2640 __in efx_rxq_t *erp); 2641 2642 extern void 2643 efx_rx_qdestroy( 2644 __in efx_rxq_t *erp); 2645 2646 /* TX */ 2647 2648 typedef struct efx_txq_s efx_txq_t; 2649 2650 #if EFSYS_OPT_QSTATS 2651 2652 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2653 typedef enum efx_tx_qstat_e { 2654 TX_POST, 2655 TX_POST_PIO, 2656 TX_NQSTATS 2657 } efx_tx_qstat_t; 2658 2659 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2660 2661 #endif /* EFSYS_OPT_QSTATS */ 2662 2663 extern __checkReturn efx_rc_t 2664 efx_tx_init( 2665 __in efx_nic_t *enp); 2666 2667 extern void 2668 efx_tx_fini( 2669 __in efx_nic_t *enp); 2670 2671 #define EFX_TXQ_MINNDESCS 512 2672 2673 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2674 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2675 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2676 2677 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2678 2679 #define EFX_TXQ_CKSUM_IPV4 0x0001 2680 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2681 #define EFX_TXQ_FATSOV2 0x0004 2682 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2683 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2684 2685 extern __checkReturn efx_rc_t 2686 efx_tx_qcreate( 2687 __in efx_nic_t *enp, 2688 __in unsigned int index, 2689 __in unsigned int label, 2690 __in efsys_mem_t *esmp, 2691 __in size_t n, 2692 __in uint32_t id, 2693 __in uint16_t flags, 2694 __in efx_evq_t *eep, 2695 __deref_out efx_txq_t **etpp, 2696 __out unsigned int *addedp); 2697 2698 extern __checkReturn efx_rc_t 2699 efx_tx_qpost( 2700 __in efx_txq_t *etp, 2701 __in_ecount(ndescs) efx_buffer_t *eb, 2702 __in unsigned int ndescs, 2703 __in unsigned int completed, 2704 __inout unsigned int *addedp); 2705 2706 extern __checkReturn efx_rc_t 2707 efx_tx_qpace( 2708 __in efx_txq_t *etp, 2709 __in unsigned int ns); 2710 2711 extern void 2712 efx_tx_qpush( 2713 __in efx_txq_t *etp, 2714 __in unsigned int added, 2715 __in unsigned int pushed); 2716 2717 extern __checkReturn efx_rc_t 2718 efx_tx_qflush( 2719 __in efx_txq_t *etp); 2720 2721 extern void 2722 efx_tx_qenable( 2723 __in efx_txq_t *etp); 2724 2725 extern __checkReturn efx_rc_t 2726 efx_tx_qpio_enable( 2727 __in efx_txq_t *etp); 2728 2729 extern void 2730 efx_tx_qpio_disable( 2731 __in efx_txq_t *etp); 2732 2733 extern __checkReturn efx_rc_t 2734 efx_tx_qpio_write( 2735 __in efx_txq_t *etp, 2736 __in_ecount(buf_length) uint8_t *buffer, 2737 __in size_t buf_length, 2738 __in size_t pio_buf_offset); 2739 2740 extern __checkReturn efx_rc_t 2741 efx_tx_qpio_post( 2742 __in efx_txq_t *etp, 2743 __in size_t pkt_length, 2744 __in unsigned int completed, 2745 __inout unsigned int *addedp); 2746 2747 extern __checkReturn efx_rc_t 2748 efx_tx_qdesc_post( 2749 __in efx_txq_t *etp, 2750 __in_ecount(n) efx_desc_t *ed, 2751 __in unsigned int n, 2752 __in unsigned int completed, 2753 __inout unsigned int *addedp); 2754 2755 extern void 2756 efx_tx_qdesc_dma_create( 2757 __in efx_txq_t *etp, 2758 __in efsys_dma_addr_t addr, 2759 __in size_t size, 2760 __in boolean_t eop, 2761 __out efx_desc_t *edp); 2762 2763 extern void 2764 efx_tx_qdesc_tso_create( 2765 __in efx_txq_t *etp, 2766 __in uint16_t ipv4_id, 2767 __in uint32_t tcp_seq, 2768 __in uint8_t tcp_flags, 2769 __out efx_desc_t *edp); 2770 2771 /* Number of FATSOv2 option descriptors */ 2772 #define EFX_TX_FATSOV2_OPT_NDESCS 2 2773 2774 /* Maximum number of DMA segments per TSO packet (not superframe) */ 2775 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2776 2777 extern void 2778 efx_tx_qdesc_tso2_create( 2779 __in efx_txq_t *etp, 2780 __in uint16_t ipv4_id, 2781 __in uint16_t outer_ipv4_id, 2782 __in uint32_t tcp_seq, 2783 __in uint16_t tcp_mss, 2784 __out_ecount(count) efx_desc_t *edp, 2785 __in int count); 2786 2787 extern void 2788 efx_tx_qdesc_vlantci_create( 2789 __in efx_txq_t *etp, 2790 __in uint16_t tci, 2791 __out efx_desc_t *edp); 2792 2793 extern void 2794 efx_tx_qdesc_checksum_create( 2795 __in efx_txq_t *etp, 2796 __in uint16_t flags, 2797 __out efx_desc_t *edp); 2798 2799 #if EFSYS_OPT_QSTATS 2800 2801 #if EFSYS_OPT_NAMES 2802 2803 extern const char * 2804 efx_tx_qstat_name( 2805 __in efx_nic_t *etp, 2806 __in unsigned int id); 2807 2808 #endif /* EFSYS_OPT_NAMES */ 2809 2810 extern void 2811 efx_tx_qstats_update( 2812 __in efx_txq_t *etp, 2813 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2814 2815 #endif /* EFSYS_OPT_QSTATS */ 2816 2817 extern void 2818 efx_tx_qdestroy( 2819 __in efx_txq_t *etp); 2820 2821 2822 /* FILTER */ 2823 2824 #if EFSYS_OPT_FILTER 2825 2826 #define EFX_ETHER_TYPE_IPV4 0x0800 2827 #define EFX_ETHER_TYPE_IPV6 0x86DD 2828 2829 #define EFX_IPPROTO_TCP 6 2830 #define EFX_IPPROTO_UDP 17 2831 #define EFX_IPPROTO_GRE 47 2832 2833 /* Use RSS to spread across multiple queues */ 2834 #define EFX_FILTER_FLAG_RX_RSS 0x01 2835 /* Enable RX scatter */ 2836 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 2837 /* 2838 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2839 * May only be set by the filter implementation for each type. 2840 * A removal request will restore the automatic filter in its place. 2841 */ 2842 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2843 /* Filter is for RX */ 2844 #define EFX_FILTER_FLAG_RX 0x08 2845 /* Filter is for TX */ 2846 #define EFX_FILTER_FLAG_TX 0x10 2847 /* Set match flag on the received packet */ 2848 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 2849 /* Set match mark on the received packet */ 2850 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 2851 2852 typedef uint8_t efx_filter_flags_t; 2853 2854 /* 2855 * Flags which specify the fields to match on. The values are the same as in the 2856 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 2857 */ 2858 2859 /* Match by remote IP host address */ 2860 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 2861 /* Match by local IP host address */ 2862 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 2863 /* Match by remote MAC address */ 2864 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 2865 /* Match by remote TCP/UDP port */ 2866 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 2867 /* Match by remote TCP/UDP port */ 2868 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 2869 /* Match by local TCP/UDP port */ 2870 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 2871 /* Match by Ether-type */ 2872 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 2873 /* Match by inner VLAN ID */ 2874 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 2875 /* Match by outer VLAN ID */ 2876 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 2877 /* Match by IP transport protocol */ 2878 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 2879 /* Match by VNI or VSID */ 2880 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 2881 /* For encapsulated packets, match by inner frame local MAC address */ 2882 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 2883 /* For encapsulated packets, match all multicast inner frames */ 2884 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 2885 /* For encapsulated packets, match all unicast inner frames */ 2886 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 2887 /* 2888 * Match by encap type, this flag does not correspond to 2889 * the MCDI match flags and any unoccupied value may be used 2890 */ 2891 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 2892 /* Match otherwise-unmatched multicast and broadcast packets */ 2893 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 2894 /* Match otherwise-unmatched unicast packets */ 2895 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 2896 2897 typedef uint32_t efx_filter_match_flags_t; 2898 2899 typedef enum efx_filter_priority_s { 2900 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2901 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2902 * address list or hardware 2903 * requirements. This may only be used 2904 * by the filter implementation for 2905 * each NIC type. */ 2906 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2907 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2908 * client (e.g. SR-IOV, HyperV VMQ etc.) 2909 */ 2910 } efx_filter_priority_t; 2911 2912 /* 2913 * FIXME: All these fields are assumed to be in little-endian byte order. 2914 * It may be better for some to be big-endian. See bug42804. 2915 */ 2916 2917 typedef struct efx_filter_spec_s { 2918 efx_filter_match_flags_t efs_match_flags; 2919 uint8_t efs_priority; 2920 efx_filter_flags_t efs_flags; 2921 uint16_t efs_dmaq_id; 2922 uint32_t efs_rss_context; 2923 uint32_t efs_mark; 2924 /* Fields below here are hashed for software filter lookup */ 2925 uint16_t efs_outer_vid; 2926 uint16_t efs_inner_vid; 2927 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2928 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2929 uint16_t efs_ether_type; 2930 uint8_t efs_ip_proto; 2931 efx_tunnel_protocol_t efs_encap_type; 2932 uint16_t efs_loc_port; 2933 uint16_t efs_rem_port; 2934 efx_oword_t efs_rem_host; 2935 efx_oword_t efs_loc_host; 2936 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 2937 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 2938 } efx_filter_spec_t; 2939 2940 2941 /* Default values for use in filter specifications */ 2942 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2943 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2944 2945 extern __checkReturn efx_rc_t 2946 efx_filter_init( 2947 __in efx_nic_t *enp); 2948 2949 extern void 2950 efx_filter_fini( 2951 __in efx_nic_t *enp); 2952 2953 extern __checkReturn efx_rc_t 2954 efx_filter_insert( 2955 __in efx_nic_t *enp, 2956 __inout efx_filter_spec_t *spec); 2957 2958 extern __checkReturn efx_rc_t 2959 efx_filter_remove( 2960 __in efx_nic_t *enp, 2961 __inout efx_filter_spec_t *spec); 2962 2963 extern __checkReturn efx_rc_t 2964 efx_filter_restore( 2965 __in efx_nic_t *enp); 2966 2967 extern __checkReturn efx_rc_t 2968 efx_filter_supported_filters( 2969 __in efx_nic_t *enp, 2970 __out_ecount(buffer_length) uint32_t *buffer, 2971 __in size_t buffer_length, 2972 __out size_t *list_lengthp); 2973 2974 extern void 2975 efx_filter_spec_init_rx( 2976 __out efx_filter_spec_t *spec, 2977 __in efx_filter_priority_t priority, 2978 __in efx_filter_flags_t flags, 2979 __in efx_rxq_t *erp); 2980 2981 extern void 2982 efx_filter_spec_init_tx( 2983 __out efx_filter_spec_t *spec, 2984 __in efx_txq_t *etp); 2985 2986 extern __checkReturn efx_rc_t 2987 efx_filter_spec_set_ipv4_local( 2988 __inout efx_filter_spec_t *spec, 2989 __in uint8_t proto, 2990 __in uint32_t host, 2991 __in uint16_t port); 2992 2993 extern __checkReturn efx_rc_t 2994 efx_filter_spec_set_ipv4_full( 2995 __inout efx_filter_spec_t *spec, 2996 __in uint8_t proto, 2997 __in uint32_t lhost, 2998 __in uint16_t lport, 2999 __in uint32_t rhost, 3000 __in uint16_t rport); 3001 3002 extern __checkReturn efx_rc_t 3003 efx_filter_spec_set_eth_local( 3004 __inout efx_filter_spec_t *spec, 3005 __in uint16_t vid, 3006 __in const uint8_t *addr); 3007 3008 extern void 3009 efx_filter_spec_set_ether_type( 3010 __inout efx_filter_spec_t *spec, 3011 __in uint16_t ether_type); 3012 3013 extern __checkReturn efx_rc_t 3014 efx_filter_spec_set_uc_def( 3015 __inout efx_filter_spec_t *spec); 3016 3017 extern __checkReturn efx_rc_t 3018 efx_filter_spec_set_mc_def( 3019 __inout efx_filter_spec_t *spec); 3020 3021 typedef enum efx_filter_inner_frame_match_e { 3022 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3023 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3024 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3025 } efx_filter_inner_frame_match_t; 3026 3027 extern __checkReturn efx_rc_t 3028 efx_filter_spec_set_encap_type( 3029 __inout efx_filter_spec_t *spec, 3030 __in efx_tunnel_protocol_t encap_type, 3031 __in efx_filter_inner_frame_match_t inner_frame_match); 3032 3033 extern __checkReturn efx_rc_t 3034 efx_filter_spec_set_vxlan( 3035 __inout efx_filter_spec_t *spec, 3036 __in const uint8_t *vni, 3037 __in const uint8_t *inner_addr, 3038 __in const uint8_t *outer_addr); 3039 3040 extern __checkReturn efx_rc_t 3041 efx_filter_spec_set_geneve( 3042 __inout efx_filter_spec_t *spec, 3043 __in const uint8_t *vni, 3044 __in const uint8_t *inner_addr, 3045 __in const uint8_t *outer_addr); 3046 3047 extern __checkReturn efx_rc_t 3048 efx_filter_spec_set_nvgre( 3049 __inout efx_filter_spec_t *spec, 3050 __in const uint8_t *vsid, 3051 __in const uint8_t *inner_addr, 3052 __in const uint8_t *outer_addr); 3053 3054 #if EFSYS_OPT_RX_SCALE 3055 extern __checkReturn efx_rc_t 3056 efx_filter_spec_set_rss_context( 3057 __inout efx_filter_spec_t *spec, 3058 __in uint32_t rss_context); 3059 #endif 3060 #endif /* EFSYS_OPT_FILTER */ 3061 3062 /* HASH */ 3063 3064 extern __checkReturn uint32_t 3065 efx_hash_dwords( 3066 __in_ecount(count) uint32_t const *input, 3067 __in size_t count, 3068 __in uint32_t init); 3069 3070 extern __checkReturn uint32_t 3071 efx_hash_bytes( 3072 __in_ecount(length) uint8_t const *input, 3073 __in size_t length, 3074 __in uint32_t init); 3075 3076 #if EFSYS_OPT_LICENSING 3077 3078 /* LICENSING */ 3079 3080 typedef struct efx_key_stats_s { 3081 uint32_t eks_valid; 3082 uint32_t eks_invalid; 3083 uint32_t eks_blacklisted; 3084 uint32_t eks_unverifiable; 3085 uint32_t eks_wrong_node; 3086 uint32_t eks_licensed_apps_lo; 3087 uint32_t eks_licensed_apps_hi; 3088 uint32_t eks_licensed_features_lo; 3089 uint32_t eks_licensed_features_hi; 3090 } efx_key_stats_t; 3091 3092 extern __checkReturn efx_rc_t 3093 efx_lic_init( 3094 __in efx_nic_t *enp); 3095 3096 extern void 3097 efx_lic_fini( 3098 __in efx_nic_t *enp); 3099 3100 extern __checkReturn boolean_t 3101 efx_lic_check_support( 3102 __in efx_nic_t *enp); 3103 3104 extern __checkReturn efx_rc_t 3105 efx_lic_update_licenses( 3106 __in efx_nic_t *enp); 3107 3108 extern __checkReturn efx_rc_t 3109 efx_lic_get_key_stats( 3110 __in efx_nic_t *enp, 3111 __out efx_key_stats_t *ksp); 3112 3113 extern __checkReturn efx_rc_t 3114 efx_lic_app_state( 3115 __in efx_nic_t *enp, 3116 __in uint64_t app_id, 3117 __out boolean_t *licensedp); 3118 3119 extern __checkReturn efx_rc_t 3120 efx_lic_get_id( 3121 __in efx_nic_t *enp, 3122 __in size_t buffer_size, 3123 __out uint32_t *typep, 3124 __out size_t *lengthp, 3125 __out_opt uint8_t *bufferp); 3126 3127 3128 extern __checkReturn efx_rc_t 3129 efx_lic_find_start( 3130 __in efx_nic_t *enp, 3131 __in_bcount(buffer_size) 3132 caddr_t bufferp, 3133 __in size_t buffer_size, 3134 __out uint32_t *startp); 3135 3136 extern __checkReturn efx_rc_t 3137 efx_lic_find_end( 3138 __in efx_nic_t *enp, 3139 __in_bcount(buffer_size) 3140 caddr_t bufferp, 3141 __in size_t buffer_size, 3142 __in uint32_t offset, 3143 __out uint32_t *endp); 3144 3145 extern __checkReturn __success(return != B_FALSE) boolean_t 3146 efx_lic_find_key( 3147 __in efx_nic_t *enp, 3148 __in_bcount(buffer_size) 3149 caddr_t bufferp, 3150 __in size_t buffer_size, 3151 __in uint32_t offset, 3152 __out uint32_t *startp, 3153 __out uint32_t *lengthp); 3154 3155 extern __checkReturn __success(return != B_FALSE) boolean_t 3156 efx_lic_validate_key( 3157 __in efx_nic_t *enp, 3158 __in_bcount(length) caddr_t keyp, 3159 __in uint32_t length); 3160 3161 extern __checkReturn efx_rc_t 3162 efx_lic_read_key( 3163 __in efx_nic_t *enp, 3164 __in_bcount(buffer_size) 3165 caddr_t bufferp, 3166 __in size_t buffer_size, 3167 __in uint32_t offset, 3168 __in uint32_t length, 3169 __out_bcount_part(key_max_size, *lengthp) 3170 caddr_t keyp, 3171 __in size_t key_max_size, 3172 __out uint32_t *lengthp); 3173 3174 extern __checkReturn efx_rc_t 3175 efx_lic_write_key( 3176 __in efx_nic_t *enp, 3177 __in_bcount(buffer_size) 3178 caddr_t bufferp, 3179 __in size_t buffer_size, 3180 __in uint32_t offset, 3181 __in_bcount(length) caddr_t keyp, 3182 __in uint32_t length, 3183 __out uint32_t *lengthp); 3184 3185 __checkReturn efx_rc_t 3186 efx_lic_delete_key( 3187 __in efx_nic_t *enp, 3188 __in_bcount(buffer_size) 3189 caddr_t bufferp, 3190 __in size_t buffer_size, 3191 __in uint32_t offset, 3192 __in uint32_t length, 3193 __in uint32_t end, 3194 __out uint32_t *deltap); 3195 3196 extern __checkReturn efx_rc_t 3197 efx_lic_create_partition( 3198 __in efx_nic_t *enp, 3199 __in_bcount(buffer_size) 3200 caddr_t bufferp, 3201 __in size_t buffer_size); 3202 3203 extern __checkReturn efx_rc_t 3204 efx_lic_finish_partition( 3205 __in efx_nic_t *enp, 3206 __in_bcount(buffer_size) 3207 caddr_t bufferp, 3208 __in size_t buffer_size); 3209 3210 #endif /* EFSYS_OPT_LICENSING */ 3211 3212 /* TUNNEL */ 3213 3214 #if EFSYS_OPT_TUNNEL 3215 3216 extern __checkReturn efx_rc_t 3217 efx_tunnel_init( 3218 __in efx_nic_t *enp); 3219 3220 extern void 3221 efx_tunnel_fini( 3222 __in efx_nic_t *enp); 3223 3224 /* 3225 * For overlay network encapsulation using UDP, the firmware needs to know 3226 * the configured UDP port for the overlay so it can decode encapsulated 3227 * frames correctly. 3228 * The UDP port/protocol list is global. 3229 */ 3230 3231 extern __checkReturn efx_rc_t 3232 efx_tunnel_config_udp_add( 3233 __in efx_nic_t *enp, 3234 __in uint16_t port /* host/cpu-endian */, 3235 __in efx_tunnel_protocol_t protocol); 3236 3237 extern __checkReturn efx_rc_t 3238 efx_tunnel_config_udp_remove( 3239 __in efx_nic_t *enp, 3240 __in uint16_t port /* host/cpu-endian */, 3241 __in efx_tunnel_protocol_t protocol); 3242 3243 extern void 3244 efx_tunnel_config_clear( 3245 __in efx_nic_t *enp); 3246 3247 /** 3248 * Apply tunnel UDP ports configuration to hardware. 3249 * 3250 * EAGAIN is returned if hardware will be reset (datapath and management CPU 3251 * reboot). 3252 */ 3253 extern __checkReturn efx_rc_t 3254 efx_tunnel_reconfigure( 3255 __in efx_nic_t *enp); 3256 3257 #endif /* EFSYS_OPT_TUNNEL */ 3258 3259 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3260 3261 /** 3262 * Firmware subvariant choice options. 3263 * 3264 * It may be switched to no Tx checksum if attached drivers are either 3265 * preboot or firmware subvariant aware and no VIS are allocated. 3266 * If may be always switched to default explicitly using set request or 3267 * implicitly if unaware driver is attaching. If switching is done when 3268 * a driver is attached, it gets MC_REBOOT event and should recreate its 3269 * datapath. 3270 * 3271 * See SF-119419-TC DPDK Firmware Driver Interface and 3272 * SF-109306-TC EF10 for Driver Writers for details. 3273 */ 3274 typedef enum efx_nic_fw_subvariant_e { 3275 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3276 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3277 EFX_NIC_FW_SUBVARIANT_NTYPES 3278 } efx_nic_fw_subvariant_t; 3279 3280 extern __checkReturn efx_rc_t 3281 efx_nic_get_fw_subvariant( 3282 __in efx_nic_t *enp, 3283 __out efx_nic_fw_subvariant_t *subvariantp); 3284 3285 extern __checkReturn efx_rc_t 3286 efx_nic_set_fw_subvariant( 3287 __in efx_nic_t *enp, 3288 __in efx_nic_fw_subvariant_t subvariant); 3289 3290 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3291 3292 typedef enum efx_phy_fec_type_e { 3293 EFX_PHY_FEC_NONE = 0, 3294 EFX_PHY_FEC_BASER, 3295 EFX_PHY_FEC_RS 3296 } efx_phy_fec_type_t; 3297 3298 extern __checkReturn efx_rc_t 3299 efx_phy_fec_type_get( 3300 __in efx_nic_t *enp, 3301 __out efx_phy_fec_type_t *typep); 3302 3303 typedef struct efx_phy_link_state_s { 3304 uint32_t epls_adv_cap_mask; 3305 uint32_t epls_lp_cap_mask; 3306 uint32_t epls_ld_cap_mask; 3307 unsigned int epls_fcntl; 3308 efx_phy_fec_type_t epls_fec; 3309 efx_link_mode_t epls_link_mode; 3310 } efx_phy_link_state_t; 3311 3312 extern __checkReturn efx_rc_t 3313 efx_phy_link_state_get( 3314 __in efx_nic_t *enp, 3315 __out efx_phy_link_state_t *eplsp); 3316 3317 3318 #ifdef __cplusplus 3319 } 3320 #endif 3321 3322 #endif /* _SYS_EFX_H */ 3323