1 /*- 2 * Copyright (c) 2006-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EFX_H 34 #define _SYS_EFX_H 35 36 #include "efsys.h" 37 #include "efx_phy_ids.h" 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 #define EFX_STATIC_ASSERT(_cond) \ 44 ((void)sizeof(char[(_cond) ? 1 : -1])) 45 46 #define EFX_ARRAY_SIZE(_array) \ 47 (sizeof(_array) / sizeof((_array)[0])) 48 49 #define EFX_FIELD_OFFSET(_type, _field) \ 50 ((size_t) &(((_type *)0)->_field)) 51 52 /* Return codes */ 53 54 typedef __success(return == 0) int efx_rc_t; 55 56 57 /* Chip families */ 58 59 typedef enum efx_family_e { 60 EFX_FAMILY_INVALID, 61 EFX_FAMILY_FALCON, 62 EFX_FAMILY_SIENA, 63 EFX_FAMILY_HUNTINGTON, 64 EFX_FAMILY_NTYPES 65 } efx_family_t; 66 67 extern __checkReturn efx_rc_t 68 efx_family( 69 __in uint16_t venid, 70 __in uint16_t devid, 71 __out efx_family_t *efp); 72 73 extern __checkReturn efx_rc_t 74 efx_infer_family( 75 __in efsys_bar_t *esbp, 76 __out efx_family_t *efp); 77 78 #define EFX_PCI_VENID_SFC 0x1924 79 80 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 81 82 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 83 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 84 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 85 86 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 87 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 88 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 89 90 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 91 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 92 93 94 #define EFX_MEM_BAR 2 95 96 /* Error codes */ 97 98 enum { 99 EFX_ERR_INVALID, 100 EFX_ERR_SRAM_OOB, 101 EFX_ERR_BUFID_DC_OOB, 102 EFX_ERR_MEM_PERR, 103 EFX_ERR_RBUF_OWN, 104 EFX_ERR_TBUF_OWN, 105 EFX_ERR_RDESQ_OWN, 106 EFX_ERR_TDESQ_OWN, 107 EFX_ERR_EVQ_OWN, 108 EFX_ERR_EVFF_OFLO, 109 EFX_ERR_ILL_ADDR, 110 EFX_ERR_SRAM_PERR, 111 EFX_ERR_NCODES 112 }; 113 114 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 115 extern __checkReturn uint32_t 116 efx_crc32_calculate( 117 __in uint32_t crc_init, 118 __in_ecount(length) uint8_t const *input, 119 __in int length); 120 121 122 /* Type prototypes */ 123 124 typedef struct efx_rxq_s efx_rxq_t; 125 126 /* NIC */ 127 128 typedef struct efx_nic_s efx_nic_t; 129 130 #define EFX_NIC_FUNC_PRIMARY 0x00000001 131 #define EFX_NIC_FUNC_LINKCTRL 0x00000002 132 #define EFX_NIC_FUNC_TRUSTED 0x00000004 133 134 135 extern __checkReturn efx_rc_t 136 efx_nic_create( 137 __in efx_family_t family, 138 __in efsys_identifier_t *esip, 139 __in efsys_bar_t *esbp, 140 __in efsys_lock_t *eslp, 141 __deref_out efx_nic_t **enpp); 142 143 extern __checkReturn efx_rc_t 144 efx_nic_probe( 145 __in efx_nic_t *enp); 146 147 #if EFSYS_OPT_PCIE_TUNE 148 149 extern __checkReturn efx_rc_t 150 efx_nic_pcie_tune( 151 __in efx_nic_t *enp, 152 unsigned int nlanes); 153 154 extern __checkReturn efx_rc_t 155 efx_nic_pcie_extended_sync( 156 __in efx_nic_t *enp); 157 158 #endif /* EFSYS_OPT_PCIE_TUNE */ 159 160 extern __checkReturn efx_rc_t 161 efx_nic_init( 162 __in efx_nic_t *enp); 163 164 extern __checkReturn efx_rc_t 165 efx_nic_reset( 166 __in efx_nic_t *enp); 167 168 #if EFSYS_OPT_DIAG 169 170 extern __checkReturn efx_rc_t 171 efx_nic_register_test( 172 __in efx_nic_t *enp); 173 174 #endif /* EFSYS_OPT_DIAG */ 175 176 extern void 177 efx_nic_fini( 178 __in efx_nic_t *enp); 179 180 extern void 181 efx_nic_unprobe( 182 __in efx_nic_t *enp); 183 184 extern void 185 efx_nic_destroy( 186 __in efx_nic_t *enp); 187 188 #if EFSYS_OPT_MCDI 189 190 #if EFSYS_OPT_HUNTINGTON 191 /* Huntington requires MCDIv2 commands */ 192 #define WITH_MCDI_V2 1 193 #endif 194 195 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 196 197 typedef enum efx_mcdi_exception_e { 198 EFX_MCDI_EXCEPTION_MC_REBOOT, 199 EFX_MCDI_EXCEPTION_MC_BADASSERT, 200 } efx_mcdi_exception_t; 201 202 #if EFSYS_OPT_MCDI_LOGGING 203 typedef enum efx_log_msg_e 204 { 205 EFX_LOG_INVALID, 206 EFX_LOG_MCDI_REQUEST, 207 EFX_LOG_MCDI_RESPONSE, 208 } efx_log_msg_t; 209 #endif /* EFSYS_OPT_MCDI_LOGGING */ 210 211 typedef struct efx_mcdi_transport_s { 212 void *emt_context; 213 efsys_mem_t *emt_dma_mem; 214 void (*emt_execute)(void *, efx_mcdi_req_t *); 215 void (*emt_ev_cpl)(void *); 216 void (*emt_exception)(void *, efx_mcdi_exception_t); 217 #if EFSYS_OPT_MCDI_LOGGING 218 void (*emt_logger)(void *, efx_log_msg_t, 219 void *, size_t, void *, size_t); 220 #endif /* EFSYS_OPT_MCDI_LOGGING */ 221 #if EFSYS_OPT_MCDI_PROXY_AUTH 222 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 223 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 224 } efx_mcdi_transport_t; 225 226 extern __checkReturn efx_rc_t 227 efx_mcdi_init( 228 __in efx_nic_t *enp, 229 __in const efx_mcdi_transport_t *mtp); 230 231 extern __checkReturn efx_rc_t 232 efx_mcdi_reboot( 233 __in efx_nic_t *enp); 234 235 void 236 efx_mcdi_new_epoch( 237 __in efx_nic_t *enp); 238 239 extern void 240 efx_mcdi_request_start( 241 __in efx_nic_t *enp, 242 __in efx_mcdi_req_t *emrp, 243 __in boolean_t ev_cpl); 244 245 extern __checkReturn boolean_t 246 efx_mcdi_request_poll( 247 __in efx_nic_t *enp); 248 249 extern __checkReturn boolean_t 250 efx_mcdi_request_abort( 251 __in efx_nic_t *enp); 252 253 extern void 254 efx_mcdi_fini( 255 __in efx_nic_t *enp); 256 257 #endif /* EFSYS_OPT_MCDI */ 258 259 /* INTR */ 260 261 #define EFX_NINTR_FALCON 64 262 #define EFX_NINTR_SIENA 1024 263 264 typedef enum efx_intr_type_e { 265 EFX_INTR_INVALID = 0, 266 EFX_INTR_LINE, 267 EFX_INTR_MESSAGE, 268 EFX_INTR_NTYPES 269 } efx_intr_type_t; 270 271 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 272 273 extern __checkReturn efx_rc_t 274 efx_intr_init( 275 __in efx_nic_t *enp, 276 __in efx_intr_type_t type, 277 __in efsys_mem_t *esmp); 278 279 extern void 280 efx_intr_enable( 281 __in efx_nic_t *enp); 282 283 extern void 284 efx_intr_disable( 285 __in efx_nic_t *enp); 286 287 extern void 288 efx_intr_disable_unlocked( 289 __in efx_nic_t *enp); 290 291 #define EFX_INTR_NEVQS 32 292 293 extern __checkReturn efx_rc_t 294 efx_intr_trigger( 295 __in efx_nic_t *enp, 296 __in unsigned int level); 297 298 extern void 299 efx_intr_status_line( 300 __in efx_nic_t *enp, 301 __out boolean_t *fatalp, 302 __out uint32_t *maskp); 303 304 extern void 305 efx_intr_status_message( 306 __in efx_nic_t *enp, 307 __in unsigned int message, 308 __out boolean_t *fatalp); 309 310 extern void 311 efx_intr_fatal( 312 __in efx_nic_t *enp); 313 314 extern void 315 efx_intr_fini( 316 __in efx_nic_t *enp); 317 318 /* MAC */ 319 320 #if EFSYS_OPT_MAC_STATS 321 322 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 323 typedef enum efx_mac_stat_e { 324 EFX_MAC_RX_OCTETS, 325 EFX_MAC_RX_PKTS, 326 EFX_MAC_RX_UNICST_PKTS, 327 EFX_MAC_RX_MULTICST_PKTS, 328 EFX_MAC_RX_BRDCST_PKTS, 329 EFX_MAC_RX_PAUSE_PKTS, 330 EFX_MAC_RX_LE_64_PKTS, 331 EFX_MAC_RX_65_TO_127_PKTS, 332 EFX_MAC_RX_128_TO_255_PKTS, 333 EFX_MAC_RX_256_TO_511_PKTS, 334 EFX_MAC_RX_512_TO_1023_PKTS, 335 EFX_MAC_RX_1024_TO_15XX_PKTS, 336 EFX_MAC_RX_GE_15XX_PKTS, 337 EFX_MAC_RX_ERRORS, 338 EFX_MAC_RX_FCS_ERRORS, 339 EFX_MAC_RX_DROP_EVENTS, 340 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 341 EFX_MAC_RX_SYMBOL_ERRORS, 342 EFX_MAC_RX_ALIGN_ERRORS, 343 EFX_MAC_RX_INTERNAL_ERRORS, 344 EFX_MAC_RX_JABBER_PKTS, 345 EFX_MAC_RX_LANE0_CHAR_ERR, 346 EFX_MAC_RX_LANE1_CHAR_ERR, 347 EFX_MAC_RX_LANE2_CHAR_ERR, 348 EFX_MAC_RX_LANE3_CHAR_ERR, 349 EFX_MAC_RX_LANE0_DISP_ERR, 350 EFX_MAC_RX_LANE1_DISP_ERR, 351 EFX_MAC_RX_LANE2_DISP_ERR, 352 EFX_MAC_RX_LANE3_DISP_ERR, 353 EFX_MAC_RX_MATCH_FAULT, 354 EFX_MAC_RX_NODESC_DROP_CNT, 355 EFX_MAC_TX_OCTETS, 356 EFX_MAC_TX_PKTS, 357 EFX_MAC_TX_UNICST_PKTS, 358 EFX_MAC_TX_MULTICST_PKTS, 359 EFX_MAC_TX_BRDCST_PKTS, 360 EFX_MAC_TX_PAUSE_PKTS, 361 EFX_MAC_TX_LE_64_PKTS, 362 EFX_MAC_TX_65_TO_127_PKTS, 363 EFX_MAC_TX_128_TO_255_PKTS, 364 EFX_MAC_TX_256_TO_511_PKTS, 365 EFX_MAC_TX_512_TO_1023_PKTS, 366 EFX_MAC_TX_1024_TO_15XX_PKTS, 367 EFX_MAC_TX_GE_15XX_PKTS, 368 EFX_MAC_TX_ERRORS, 369 EFX_MAC_TX_SGL_COL_PKTS, 370 EFX_MAC_TX_MULT_COL_PKTS, 371 EFX_MAC_TX_EX_COL_PKTS, 372 EFX_MAC_TX_LATE_COL_PKTS, 373 EFX_MAC_TX_DEF_PKTS, 374 EFX_MAC_TX_EX_DEF_PKTS, 375 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 376 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 377 EFX_MAC_PM_TRUNC_VFIFO_FULL, 378 EFX_MAC_PM_DISCARD_VFIFO_FULL, 379 EFX_MAC_PM_TRUNC_QBB, 380 EFX_MAC_PM_DISCARD_QBB, 381 EFX_MAC_PM_DISCARD_MAPPING, 382 EFX_MAC_RXDP_Q_DISABLED_PKTS, 383 EFX_MAC_RXDP_DI_DROPPED_PKTS, 384 EFX_MAC_RXDP_STREAMING_PKTS, 385 EFX_MAC_RXDP_HLB_FETCH, 386 EFX_MAC_RXDP_HLB_WAIT, 387 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 388 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 389 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 390 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 391 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 392 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 393 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 394 EFX_MAC_VADAPTER_RX_BAD_BYTES, 395 EFX_MAC_VADAPTER_RX_OVERFLOW, 396 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 397 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 398 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 399 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 400 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 401 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 402 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 403 EFX_MAC_VADAPTER_TX_BAD_BYTES, 404 EFX_MAC_VADAPTER_TX_OVERFLOW, 405 EFX_MAC_NSTATS 406 } efx_mac_stat_t; 407 408 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 409 410 #endif /* EFSYS_OPT_MAC_STATS */ 411 412 typedef enum efx_link_mode_e { 413 EFX_LINK_UNKNOWN = 0, 414 EFX_LINK_DOWN, 415 EFX_LINK_10HDX, 416 EFX_LINK_10FDX, 417 EFX_LINK_100HDX, 418 EFX_LINK_100FDX, 419 EFX_LINK_1000HDX, 420 EFX_LINK_1000FDX, 421 EFX_LINK_10000FDX, 422 EFX_LINK_40000FDX, 423 EFX_LINK_NMODES 424 } efx_link_mode_t; 425 426 #define EFX_MAC_ADDR_LEN 6 427 428 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01) 429 430 #define EFX_MAC_MULTICAST_LIST_MAX 256 431 432 #define EFX_MAC_SDU_MAX 9202 433 434 #define EFX_MAC_PDU(_sdu) \ 435 P2ROUNDUP(((_sdu) \ 436 + /* EtherII */ 14 \ 437 + /* VLAN */ 4 \ 438 + /* CRC */ 4 \ 439 + /* bug16011 */ 16), \ 440 (1 << 3)) 441 442 #define EFX_MAC_PDU_MIN 60 443 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 444 445 extern __checkReturn efx_rc_t 446 efx_mac_pdu_set( 447 __in efx_nic_t *enp, 448 __in size_t pdu); 449 450 extern __checkReturn efx_rc_t 451 efx_mac_addr_set( 452 __in efx_nic_t *enp, 453 __in uint8_t *addr); 454 455 extern __checkReturn efx_rc_t 456 efx_mac_filter_set( 457 __in efx_nic_t *enp, 458 __in boolean_t all_unicst, 459 __in boolean_t mulcst, 460 __in boolean_t all_mulcst, 461 __in boolean_t brdcst); 462 463 extern __checkReturn efx_rc_t 464 efx_mac_multicast_list_set( 465 __in efx_nic_t *enp, 466 __in_ecount(6*count) uint8_t const *addrs, 467 __in int count); 468 469 extern __checkReturn efx_rc_t 470 efx_mac_filter_default_rxq_set( 471 __in efx_nic_t *enp, 472 __in efx_rxq_t *erp, 473 __in boolean_t using_rss); 474 475 extern void 476 efx_mac_filter_default_rxq_clear( 477 __in efx_nic_t *enp); 478 479 extern __checkReturn efx_rc_t 480 efx_mac_drain( 481 __in efx_nic_t *enp, 482 __in boolean_t enabled); 483 484 extern __checkReturn efx_rc_t 485 efx_mac_up( 486 __in efx_nic_t *enp, 487 __out boolean_t *mac_upp); 488 489 #define EFX_FCNTL_RESPOND 0x00000001 490 #define EFX_FCNTL_GENERATE 0x00000002 491 492 extern __checkReturn efx_rc_t 493 efx_mac_fcntl_set( 494 __in efx_nic_t *enp, 495 __in unsigned int fcntl, 496 __in boolean_t autoneg); 497 498 extern void 499 efx_mac_fcntl_get( 500 __in efx_nic_t *enp, 501 __out unsigned int *fcntl_wantedp, 502 __out unsigned int *fcntl_linkp); 503 504 #define EFX_MAC_HASH_BITS (1 << 8) 505 506 extern __checkReturn efx_rc_t 507 efx_pktfilter_init( 508 __in efx_nic_t *enp); 509 510 extern void 511 efx_pktfilter_fini( 512 __in efx_nic_t *enp); 513 514 extern __checkReturn efx_rc_t 515 efx_pktfilter_set( 516 __in efx_nic_t *enp, 517 __in boolean_t unicst, 518 __in boolean_t brdcst); 519 520 extern __checkReturn efx_rc_t 521 efx_mac_hash_set( 522 __in efx_nic_t *enp, 523 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); 524 525 #if EFSYS_OPT_MCAST_FILTER_LIST 526 extern __checkReturn efx_rc_t 527 efx_pktfilter_mcast_list_set( 528 __in efx_nic_t *enp, 529 __in uint8_t const *addrs, 530 __in int count); 531 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */ 532 533 extern __checkReturn efx_rc_t 534 efx_pktfilter_mcast_all( 535 __in efx_nic_t *enp); 536 537 #if EFSYS_OPT_MAC_STATS 538 539 #if EFSYS_OPT_NAMES 540 541 extern __checkReturn const char * 542 efx_mac_stat_name( 543 __in efx_nic_t *enp, 544 __in unsigned int id); 545 546 #endif /* EFSYS_OPT_NAMES */ 547 548 #define EFX_MAC_STATS_SIZE 0x400 549 550 /* 551 * Upload mac statistics supported by the hardware into the given buffer. 552 * 553 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 554 * and page aligned. 555 * 556 * The hardware will only DMA statistics that it understands (of course). 557 * Drivers should not make any assumptions about which statistics are 558 * supported, especially when the statistics are generated by firmware. 559 * 560 * Thus, drivers should zero this buffer before use, so that not-understood 561 * statistics read back as zero. 562 */ 563 extern __checkReturn efx_rc_t 564 efx_mac_stats_upload( 565 __in efx_nic_t *enp, 566 __in efsys_mem_t *esmp); 567 568 extern __checkReturn efx_rc_t 569 efx_mac_stats_periodic( 570 __in efx_nic_t *enp, 571 __in efsys_mem_t *esmp, 572 __in uint16_t period_ms, 573 __in boolean_t events); 574 575 extern __checkReturn efx_rc_t 576 efx_mac_stats_update( 577 __in efx_nic_t *enp, 578 __in efsys_mem_t *esmp, 579 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 580 __inout_opt uint32_t *generationp); 581 582 #endif /* EFSYS_OPT_MAC_STATS */ 583 584 /* MON */ 585 586 typedef enum efx_mon_type_e { 587 EFX_MON_INVALID = 0, 588 EFX_MON_NULL, 589 EFX_MON_LM87, 590 EFX_MON_MAX6647, 591 EFX_MON_SFC90X0, 592 EFX_MON_SFC91X0, 593 EFX_MON_NTYPES 594 } efx_mon_type_t; 595 596 #if EFSYS_OPT_NAMES 597 598 extern const char * 599 efx_mon_name( 600 __in efx_nic_t *enp); 601 602 #endif /* EFSYS_OPT_NAMES */ 603 604 extern __checkReturn efx_rc_t 605 efx_mon_init( 606 __in efx_nic_t *enp); 607 608 #if EFSYS_OPT_MON_STATS 609 610 #define EFX_MON_STATS_PAGE_SIZE 0x100 611 #define EFX_MON_MASK_ELEMENT_SIZE 32 612 613 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */ 614 typedef enum efx_mon_stat_e { 615 EFX_MON_STAT_2_5V, 616 EFX_MON_STAT_VCCP1, 617 EFX_MON_STAT_VCC, 618 EFX_MON_STAT_5V, 619 EFX_MON_STAT_12V, 620 EFX_MON_STAT_VCCP2, 621 EFX_MON_STAT_EXT_TEMP, 622 EFX_MON_STAT_INT_TEMP, 623 EFX_MON_STAT_AIN1, 624 EFX_MON_STAT_AIN2, 625 EFX_MON_STAT_INT_COOLING, 626 EFX_MON_STAT_EXT_COOLING, 627 EFX_MON_STAT_1V, 628 EFX_MON_STAT_1_2V, 629 EFX_MON_STAT_1_8V, 630 EFX_MON_STAT_3_3V, 631 EFX_MON_STAT_1_2VA, 632 EFX_MON_STAT_VREF, 633 EFX_MON_STAT_VAOE, 634 EFX_MON_STAT_AOE_TEMP, 635 EFX_MON_STAT_PSU_AOE_TEMP, 636 EFX_MON_STAT_PSU_TEMP, 637 EFX_MON_STAT_FAN0, 638 EFX_MON_STAT_FAN1, 639 EFX_MON_STAT_FAN2, 640 EFX_MON_STAT_FAN3, 641 EFX_MON_STAT_FAN4, 642 EFX_MON_STAT_VAOE_IN, 643 EFX_MON_STAT_IAOE, 644 EFX_MON_STAT_IAOE_IN, 645 EFX_MON_STAT_NIC_POWER, 646 EFX_MON_STAT_0_9V, 647 EFX_MON_STAT_I0_9V, 648 EFX_MON_STAT_I1_2V, 649 EFX_MON_STAT_0_9V_ADC, 650 EFX_MON_STAT_INT_TEMP2, 651 EFX_MON_STAT_VREG_TEMP, 652 EFX_MON_STAT_VREG_0_9V_TEMP, 653 EFX_MON_STAT_VREG_1_2V_TEMP, 654 EFX_MON_STAT_INT_VPTAT, 655 EFX_MON_STAT_INT_ADC_TEMP, 656 EFX_MON_STAT_EXT_VPTAT, 657 EFX_MON_STAT_EXT_ADC_TEMP, 658 EFX_MON_STAT_AMBIENT_TEMP, 659 EFX_MON_STAT_AIRFLOW, 660 EFX_MON_STAT_VDD08D_VSS08D_CSR, 661 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 662 EFX_MON_STAT_HOTPOINT_TEMP, 663 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 664 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 665 EFX_MON_STAT_MUM_VCC, 666 EFX_MON_STAT_0V9_A, 667 EFX_MON_STAT_I0V9_A, 668 EFX_MON_STAT_0V9_A_TEMP, 669 EFX_MON_STAT_0V9_B, 670 EFX_MON_STAT_I0V9_B, 671 EFX_MON_STAT_0V9_B_TEMP, 672 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 673 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 674 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 675 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 676 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 677 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 678 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 679 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 680 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 681 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 682 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 683 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 684 EFX_MON_NSTATS 685 } efx_mon_stat_t; 686 687 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 688 689 typedef enum efx_mon_stat_state_e { 690 EFX_MON_STAT_STATE_OK = 0, 691 EFX_MON_STAT_STATE_WARNING = 1, 692 EFX_MON_STAT_STATE_FATAL = 2, 693 EFX_MON_STAT_STATE_BROKEN = 3, 694 EFX_MON_STAT_STATE_NO_READING = 4, 695 } efx_mon_stat_state_t; 696 697 typedef struct efx_mon_stat_value_s { 698 uint16_t emsv_value; 699 uint16_t emsv_state; 700 } efx_mon_stat_value_t; 701 702 #if EFSYS_OPT_NAMES 703 704 extern const char * 705 efx_mon_stat_name( 706 __in efx_nic_t *enp, 707 __in efx_mon_stat_t id); 708 709 #endif /* EFSYS_OPT_NAMES */ 710 711 extern __checkReturn efx_rc_t 712 efx_mon_stats_update( 713 __in efx_nic_t *enp, 714 __in efsys_mem_t *esmp, 715 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 716 717 #endif /* EFSYS_OPT_MON_STATS */ 718 719 extern void 720 efx_mon_fini( 721 __in efx_nic_t *enp); 722 723 /* PHY */ 724 725 #define PMA_PMD_MMD 1 726 #define PCS_MMD 3 727 #define PHY_XS_MMD 4 728 #define DTE_XS_MMD 5 729 #define AN_MMD 7 730 #define CL22EXT_MMD 29 731 732 #define MAXMMD ((1 << 5) - 1) 733 734 extern __checkReturn efx_rc_t 735 efx_phy_verify( 736 __in efx_nic_t *enp); 737 738 #if EFSYS_OPT_PHY_LED_CONTROL 739 740 typedef enum efx_phy_led_mode_e { 741 EFX_PHY_LED_DEFAULT = 0, 742 EFX_PHY_LED_OFF, 743 EFX_PHY_LED_ON, 744 EFX_PHY_LED_FLASH, 745 EFX_PHY_LED_NMODES 746 } efx_phy_led_mode_t; 747 748 extern __checkReturn efx_rc_t 749 efx_phy_led_set( 750 __in efx_nic_t *enp, 751 __in efx_phy_led_mode_t mode); 752 753 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 754 755 extern __checkReturn efx_rc_t 756 efx_port_init( 757 __in efx_nic_t *enp); 758 759 #if EFSYS_OPT_LOOPBACK 760 761 typedef enum efx_loopback_type_e { 762 EFX_LOOPBACK_OFF = 0, 763 EFX_LOOPBACK_DATA = 1, 764 EFX_LOOPBACK_GMAC = 2, 765 EFX_LOOPBACK_XGMII = 3, 766 EFX_LOOPBACK_XGXS = 4, 767 EFX_LOOPBACK_XAUI = 5, 768 EFX_LOOPBACK_GMII = 6, 769 EFX_LOOPBACK_SGMII = 7, 770 EFX_LOOPBACK_XGBR = 8, 771 EFX_LOOPBACK_XFI = 9, 772 EFX_LOOPBACK_XAUI_FAR = 10, 773 EFX_LOOPBACK_GMII_FAR = 11, 774 EFX_LOOPBACK_SGMII_FAR = 12, 775 EFX_LOOPBACK_XFI_FAR = 13, 776 EFX_LOOPBACK_GPHY = 14, 777 EFX_LOOPBACK_PHY_XS = 15, 778 EFX_LOOPBACK_PCS = 16, 779 EFX_LOOPBACK_PMA_PMD = 17, 780 EFX_LOOPBACK_XPORT = 18, 781 EFX_LOOPBACK_XGMII_WS = 19, 782 EFX_LOOPBACK_XAUI_WS = 20, 783 EFX_LOOPBACK_XAUI_WS_FAR = 21, 784 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 785 EFX_LOOPBACK_GMII_WS = 23, 786 EFX_LOOPBACK_XFI_WS = 24, 787 EFX_LOOPBACK_XFI_WS_FAR = 25, 788 EFX_LOOPBACK_PHYXS_WS = 26, 789 EFX_LOOPBACK_PMA_INT = 27, 790 EFX_LOOPBACK_SD_NEAR = 28, 791 EFX_LOOPBACK_SD_FAR = 29, 792 EFX_LOOPBACK_PMA_INT_WS = 30, 793 EFX_LOOPBACK_SD_FEP2_WS = 31, 794 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 795 EFX_LOOPBACK_SD_FEP_WS = 33, 796 EFX_LOOPBACK_SD_FES_WS = 34, 797 EFX_LOOPBACK_NTYPES 798 } efx_loopback_type_t; 799 800 typedef enum efx_loopback_kind_e { 801 EFX_LOOPBACK_KIND_OFF = 0, 802 EFX_LOOPBACK_KIND_ALL, 803 EFX_LOOPBACK_KIND_MAC, 804 EFX_LOOPBACK_KIND_PHY, 805 EFX_LOOPBACK_NKINDS 806 } efx_loopback_kind_t; 807 808 extern void 809 efx_loopback_mask( 810 __in efx_loopback_kind_t loopback_kind, 811 __out efx_qword_t *maskp); 812 813 extern __checkReturn efx_rc_t 814 efx_port_loopback_set( 815 __in efx_nic_t *enp, 816 __in efx_link_mode_t link_mode, 817 __in efx_loopback_type_t type); 818 819 #if EFSYS_OPT_NAMES 820 821 extern __checkReturn const char * 822 efx_loopback_type_name( 823 __in efx_nic_t *enp, 824 __in efx_loopback_type_t type); 825 826 #endif /* EFSYS_OPT_NAMES */ 827 828 #endif /* EFSYS_OPT_LOOPBACK */ 829 830 extern __checkReturn efx_rc_t 831 efx_port_poll( 832 __in efx_nic_t *enp, 833 __out_opt efx_link_mode_t *link_modep); 834 835 extern void 836 efx_port_fini( 837 __in efx_nic_t *enp); 838 839 typedef enum efx_phy_cap_type_e { 840 EFX_PHY_CAP_INVALID = 0, 841 EFX_PHY_CAP_10HDX, 842 EFX_PHY_CAP_10FDX, 843 EFX_PHY_CAP_100HDX, 844 EFX_PHY_CAP_100FDX, 845 EFX_PHY_CAP_1000HDX, 846 EFX_PHY_CAP_1000FDX, 847 EFX_PHY_CAP_10000FDX, 848 EFX_PHY_CAP_PAUSE, 849 EFX_PHY_CAP_ASYM, 850 EFX_PHY_CAP_AN, 851 EFX_PHY_CAP_40000FDX, 852 EFX_PHY_CAP_NTYPES 853 } efx_phy_cap_type_t; 854 855 856 #define EFX_PHY_CAP_CURRENT 0x00000000 857 #define EFX_PHY_CAP_DEFAULT 0x00000001 858 #define EFX_PHY_CAP_PERM 0x00000002 859 860 extern void 861 efx_phy_adv_cap_get( 862 __in efx_nic_t *enp, 863 __in uint32_t flag, 864 __out uint32_t *maskp); 865 866 extern __checkReturn efx_rc_t 867 efx_phy_adv_cap_set( 868 __in efx_nic_t *enp, 869 __in uint32_t mask); 870 871 extern void 872 efx_phy_lp_cap_get( 873 __in efx_nic_t *enp, 874 __out uint32_t *maskp); 875 876 extern __checkReturn efx_rc_t 877 efx_phy_oui_get( 878 __in efx_nic_t *enp, 879 __out uint32_t *ouip); 880 881 typedef enum efx_phy_media_type_e { 882 EFX_PHY_MEDIA_INVALID = 0, 883 EFX_PHY_MEDIA_XAUI, 884 EFX_PHY_MEDIA_CX4, 885 EFX_PHY_MEDIA_KX4, 886 EFX_PHY_MEDIA_XFP, 887 EFX_PHY_MEDIA_SFP_PLUS, 888 EFX_PHY_MEDIA_BASE_T, 889 EFX_PHY_MEDIA_QSFP_PLUS, 890 EFX_PHY_MEDIA_NTYPES 891 } efx_phy_media_type_t; 892 893 /* Get the type of medium currently used. If the board has ports for 894 * modules, a module is present, and we recognise the media type of 895 * the module, then this will be the media type of the module. 896 * Otherwise it will be the media type of the port. 897 */ 898 extern void 899 efx_phy_media_type_get( 900 __in efx_nic_t *enp, 901 __out efx_phy_media_type_t *typep); 902 903 #if EFSYS_OPT_PHY_STATS 904 905 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 906 typedef enum efx_phy_stat_e { 907 EFX_PHY_STAT_OUI, 908 EFX_PHY_STAT_PMA_PMD_LINK_UP, 909 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 910 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 911 EFX_PHY_STAT_PMA_PMD_REV_A, 912 EFX_PHY_STAT_PMA_PMD_REV_B, 913 EFX_PHY_STAT_PMA_PMD_REV_C, 914 EFX_PHY_STAT_PMA_PMD_REV_D, 915 EFX_PHY_STAT_PCS_LINK_UP, 916 EFX_PHY_STAT_PCS_RX_FAULT, 917 EFX_PHY_STAT_PCS_TX_FAULT, 918 EFX_PHY_STAT_PCS_BER, 919 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 920 EFX_PHY_STAT_PHY_XS_LINK_UP, 921 EFX_PHY_STAT_PHY_XS_RX_FAULT, 922 EFX_PHY_STAT_PHY_XS_TX_FAULT, 923 EFX_PHY_STAT_PHY_XS_ALIGN, 924 EFX_PHY_STAT_PHY_XS_SYNC_A, 925 EFX_PHY_STAT_PHY_XS_SYNC_B, 926 EFX_PHY_STAT_PHY_XS_SYNC_C, 927 EFX_PHY_STAT_PHY_XS_SYNC_D, 928 EFX_PHY_STAT_AN_LINK_UP, 929 EFX_PHY_STAT_AN_MASTER, 930 EFX_PHY_STAT_AN_LOCAL_RX_OK, 931 EFX_PHY_STAT_AN_REMOTE_RX_OK, 932 EFX_PHY_STAT_CL22EXT_LINK_UP, 933 EFX_PHY_STAT_SNR_A, 934 EFX_PHY_STAT_SNR_B, 935 EFX_PHY_STAT_SNR_C, 936 EFX_PHY_STAT_SNR_D, 937 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 938 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 939 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 940 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 941 EFX_PHY_STAT_AN_COMPLETE, 942 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 943 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 944 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 945 EFX_PHY_STAT_PCS_FW_VERSION_0, 946 EFX_PHY_STAT_PCS_FW_VERSION_1, 947 EFX_PHY_STAT_PCS_FW_VERSION_2, 948 EFX_PHY_STAT_PCS_FW_VERSION_3, 949 EFX_PHY_STAT_PCS_FW_BUILD_YY, 950 EFX_PHY_STAT_PCS_FW_BUILD_MM, 951 EFX_PHY_STAT_PCS_FW_BUILD_DD, 952 EFX_PHY_STAT_PCS_OP_MODE, 953 EFX_PHY_NSTATS 954 } efx_phy_stat_t; 955 956 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 957 958 #if EFSYS_OPT_NAMES 959 960 extern const char * 961 efx_phy_stat_name( 962 __in efx_nic_t *enp, 963 __in efx_phy_stat_t stat); 964 965 #endif /* EFSYS_OPT_NAMES */ 966 967 #define EFX_PHY_STATS_SIZE 0x100 968 969 extern __checkReturn efx_rc_t 970 efx_phy_stats_update( 971 __in efx_nic_t *enp, 972 __in efsys_mem_t *esmp, 973 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 974 975 #endif /* EFSYS_OPT_PHY_STATS */ 976 977 #if EFSYS_OPT_PHY_PROPS 978 979 #if EFSYS_OPT_NAMES 980 981 extern const char * 982 efx_phy_prop_name( 983 __in efx_nic_t *enp, 984 __in unsigned int id); 985 986 #endif /* EFSYS_OPT_NAMES */ 987 988 #define EFX_PHY_PROP_DEFAULT 0x00000001 989 990 extern __checkReturn efx_rc_t 991 efx_phy_prop_get( 992 __in efx_nic_t *enp, 993 __in unsigned int id, 994 __in uint32_t flags, 995 __out uint32_t *valp); 996 997 extern __checkReturn efx_rc_t 998 efx_phy_prop_set( 999 __in efx_nic_t *enp, 1000 __in unsigned int id, 1001 __in uint32_t val); 1002 1003 #endif /* EFSYS_OPT_PHY_PROPS */ 1004 1005 #if EFSYS_OPT_BIST 1006 1007 typedef enum efx_bist_type_e { 1008 EFX_BIST_TYPE_UNKNOWN, 1009 EFX_BIST_TYPE_PHY_NORMAL, 1010 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1011 EFX_BIST_TYPE_PHY_CABLE_LONG, 1012 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1013 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/ 1014 EFX_BIST_TYPE_REG, /* Test the register memories */ 1015 EFX_BIST_TYPE_NTYPES, 1016 } efx_bist_type_t; 1017 1018 typedef enum efx_bist_result_e { 1019 EFX_BIST_RESULT_UNKNOWN, 1020 EFX_BIST_RESULT_RUNNING, 1021 EFX_BIST_RESULT_PASSED, 1022 EFX_BIST_RESULT_FAILED, 1023 } efx_bist_result_t; 1024 1025 typedef enum efx_phy_cable_status_e { 1026 EFX_PHY_CABLE_STATUS_OK, 1027 EFX_PHY_CABLE_STATUS_INVALID, 1028 EFX_PHY_CABLE_STATUS_OPEN, 1029 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1030 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1031 EFX_PHY_CABLE_STATUS_BUSY, 1032 } efx_phy_cable_status_t; 1033 1034 typedef enum efx_bist_value_e { 1035 EFX_BIST_PHY_CABLE_LENGTH_A, 1036 EFX_BIST_PHY_CABLE_LENGTH_B, 1037 EFX_BIST_PHY_CABLE_LENGTH_C, 1038 EFX_BIST_PHY_CABLE_LENGTH_D, 1039 EFX_BIST_PHY_CABLE_STATUS_A, 1040 EFX_BIST_PHY_CABLE_STATUS_B, 1041 EFX_BIST_PHY_CABLE_STATUS_C, 1042 EFX_BIST_PHY_CABLE_STATUS_D, 1043 EFX_BIST_FAULT_CODE, 1044 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1045 * response. */ 1046 EFX_BIST_MEM_TEST, 1047 EFX_BIST_MEM_ADDR, 1048 EFX_BIST_MEM_BUS, 1049 EFX_BIST_MEM_EXPECT, 1050 EFX_BIST_MEM_ACTUAL, 1051 EFX_BIST_MEM_ECC, 1052 EFX_BIST_MEM_ECC_PARITY, 1053 EFX_BIST_MEM_ECC_FATAL, 1054 EFX_BIST_NVALUES, 1055 } efx_bist_value_t; 1056 1057 extern __checkReturn efx_rc_t 1058 efx_bist_enable_offline( 1059 __in efx_nic_t *enp); 1060 1061 extern __checkReturn efx_rc_t 1062 efx_bist_start( 1063 __in efx_nic_t *enp, 1064 __in efx_bist_type_t type); 1065 1066 extern __checkReturn efx_rc_t 1067 efx_bist_poll( 1068 __in efx_nic_t *enp, 1069 __in efx_bist_type_t type, 1070 __out efx_bist_result_t *resultp, 1071 __out_opt uint32_t *value_maskp, 1072 __out_ecount_opt(count) unsigned long *valuesp, 1073 __in size_t count); 1074 1075 extern void 1076 efx_bist_stop( 1077 __in efx_nic_t *enp, 1078 __in efx_bist_type_t type); 1079 1080 #endif /* EFSYS_OPT_BIST */ 1081 1082 #define EFX_FEATURE_IPV6 0x00000001 1083 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1084 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1085 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1086 #define EFX_FEATURE_WOL 0x00000010 1087 #define EFX_FEATURE_MCDI 0x00000020 1088 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1089 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1090 #define EFX_FEATURE_TURBO 0x00000100 1091 #define EFX_FEATURE_MCDI_DMA 0x00000200 1092 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1093 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1094 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1095 1096 typedef struct efx_nic_cfg_s { 1097 uint32_t enc_board_type; 1098 uint32_t enc_phy_type; 1099 #if EFSYS_OPT_NAMES 1100 char enc_phy_name[21]; 1101 #endif 1102 char enc_phy_revision[21]; 1103 efx_mon_type_t enc_mon_type; 1104 #if EFSYS_OPT_MON_STATS 1105 uint32_t enc_mon_stat_dma_buf_size; 1106 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1107 #endif 1108 unsigned int enc_features; 1109 uint8_t enc_mac_addr[6]; 1110 uint8_t enc_port; /* PHY port number */ 1111 uint32_t enc_func_flags; 1112 uint32_t enc_intr_vec_base; 1113 uint32_t enc_intr_limit; 1114 uint32_t enc_evq_limit; 1115 uint32_t enc_txq_limit; 1116 uint32_t enc_rxq_limit; 1117 uint32_t enc_buftbl_limit; 1118 uint32_t enc_piobuf_limit; 1119 uint32_t enc_piobuf_size; 1120 uint32_t enc_evq_timer_quantum_ns; 1121 uint32_t enc_evq_timer_max_us; 1122 uint32_t enc_clk_mult; 1123 uint32_t enc_rx_prefix_size; 1124 uint32_t enc_rx_buf_align_start; 1125 uint32_t enc_rx_buf_align_end; 1126 #if EFSYS_OPT_LOOPBACK 1127 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1128 #endif /* EFSYS_OPT_LOOPBACK */ 1129 #if EFSYS_OPT_PHY_FLAGS 1130 uint32_t enc_phy_flags_mask; 1131 #endif /* EFSYS_OPT_PHY_FLAGS */ 1132 #if EFSYS_OPT_PHY_LED_CONTROL 1133 uint32_t enc_led_mask; 1134 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1135 #if EFSYS_OPT_PHY_STATS 1136 uint64_t enc_phy_stat_mask; 1137 #endif /* EFSYS_OPT_PHY_STATS */ 1138 #if EFSYS_OPT_PHY_PROPS 1139 unsigned int enc_phy_nprops; 1140 #endif /* EFSYS_OPT_PHY_PROPS */ 1141 #if EFSYS_OPT_SIENA 1142 uint8_t enc_mcdi_mdio_channel; 1143 #if EFSYS_OPT_PHY_STATS 1144 uint32_t enc_mcdi_phy_stat_mask; 1145 #endif /* EFSYS_OPT_PHY_STATS */ 1146 #endif /* EFSYS_OPT_SIENA */ 1147 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) 1148 #if EFSYS_OPT_MON_STATS 1149 uint32_t *enc_mcdi_sensor_maskp; 1150 uint32_t enc_mcdi_sensor_mask_size; 1151 #endif /* EFSYS_OPT_MON_STATS */ 1152 #endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */ 1153 #if EFSYS_OPT_BIST 1154 uint32_t enc_bist_mask; 1155 #endif /* EFSYS_OPT_BIST */ 1156 #if EFSYS_OPT_HUNTINGTON 1157 uint32_t enc_pf; 1158 uint32_t enc_vf; 1159 uint32_t enc_privilege_mask; 1160 #endif /* EFSYS_OPT_HUNTINGTON */ 1161 boolean_t enc_bug26807_workaround; 1162 boolean_t enc_bug35388_workaround; 1163 boolean_t enc_bug41750_workaround; 1164 boolean_t enc_rx_batching_enabled; 1165 /* Maximum number of descriptors completed in an rx event. */ 1166 uint32_t enc_rx_batch_max; 1167 /* Number of rx descriptors the hardware requires for a push. */ 1168 uint32_t enc_rx_push_align; 1169 /* 1170 * Maximum number of bytes into the packet the TCP header can start for 1171 * the hardware to apply TSO packet edits. 1172 */ 1173 uint32_t enc_tx_tso_tcp_header_offset_limit; 1174 boolean_t enc_fw_assisted_tso_enabled; 1175 boolean_t enc_hw_tx_insert_vlan_enabled; 1176 /* Datapath firmware vadapter/vport/vswitch support */ 1177 boolean_t enc_datapath_cap_evb; 1178 boolean_t enc_rx_disable_scatter_supported; 1179 boolean_t enc_allow_set_mac_with_installed_filters; 1180 /* External port identifier */ 1181 uint8_t enc_external_port; 1182 uint32_t enc_mcdi_max_payload_length; 1183 } efx_nic_cfg_t; 1184 1185 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1186 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1187 1188 #define EFX_PCI_FUNCTION(_encp) \ 1189 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1190 1191 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1192 1193 extern const efx_nic_cfg_t * 1194 efx_nic_cfg_get( 1195 __in efx_nic_t *enp); 1196 1197 /* Driver resource limits (minimum required/maximum usable). */ 1198 typedef struct efx_drv_limits_s 1199 { 1200 uint32_t edl_min_evq_count; 1201 uint32_t edl_max_evq_count; 1202 1203 uint32_t edl_min_rxq_count; 1204 uint32_t edl_max_rxq_count; 1205 1206 uint32_t edl_min_txq_count; 1207 uint32_t edl_max_txq_count; 1208 1209 /* PIO blocks (sub-allocated from piobuf) */ 1210 uint32_t edl_min_pio_alloc_size; 1211 uint32_t edl_max_pio_alloc_count; 1212 } efx_drv_limits_t; 1213 1214 extern __checkReturn efx_rc_t 1215 efx_nic_set_drv_limits( 1216 __inout efx_nic_t *enp, 1217 __in efx_drv_limits_t *edlp); 1218 1219 typedef enum efx_nic_region_e { 1220 EFX_REGION_VI, /* Memory BAR UC mapping */ 1221 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1222 } efx_nic_region_t; 1223 1224 extern __checkReturn efx_rc_t 1225 efx_nic_get_bar_region( 1226 __in efx_nic_t *enp, 1227 __in efx_nic_region_t region, 1228 __out uint32_t *offsetp, 1229 __out size_t *sizep); 1230 1231 extern __checkReturn efx_rc_t 1232 efx_nic_get_vi_pool( 1233 __in efx_nic_t *enp, 1234 __out uint32_t *evq_countp, 1235 __out uint32_t *rxq_countp, 1236 __out uint32_t *txq_countp); 1237 1238 1239 #if EFSYS_OPT_VPD 1240 1241 typedef enum efx_vpd_tag_e { 1242 EFX_VPD_ID = 0x02, 1243 EFX_VPD_END = 0x0f, 1244 EFX_VPD_RO = 0x10, 1245 EFX_VPD_RW = 0x11, 1246 } efx_vpd_tag_t; 1247 1248 typedef uint16_t efx_vpd_keyword_t; 1249 1250 typedef struct efx_vpd_value_s { 1251 efx_vpd_tag_t evv_tag; 1252 efx_vpd_keyword_t evv_keyword; 1253 uint8_t evv_length; 1254 uint8_t evv_value[0x100]; 1255 } efx_vpd_value_t; 1256 1257 1258 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1259 1260 extern __checkReturn efx_rc_t 1261 efx_vpd_init( 1262 __in efx_nic_t *enp); 1263 1264 extern __checkReturn efx_rc_t 1265 efx_vpd_size( 1266 __in efx_nic_t *enp, 1267 __out size_t *sizep); 1268 1269 extern __checkReturn efx_rc_t 1270 efx_vpd_read( 1271 __in efx_nic_t *enp, 1272 __out_bcount(size) caddr_t data, 1273 __in size_t size); 1274 1275 extern __checkReturn efx_rc_t 1276 efx_vpd_verify( 1277 __in efx_nic_t *enp, 1278 __in_bcount(size) caddr_t data, 1279 __in size_t size); 1280 1281 extern __checkReturn efx_rc_t 1282 efx_vpd_reinit( 1283 __in efx_nic_t *enp, 1284 __in_bcount(size) caddr_t data, 1285 __in size_t size); 1286 1287 extern __checkReturn efx_rc_t 1288 efx_vpd_get( 1289 __in efx_nic_t *enp, 1290 __in_bcount(size) caddr_t data, 1291 __in size_t size, 1292 __inout efx_vpd_value_t *evvp); 1293 1294 extern __checkReturn efx_rc_t 1295 efx_vpd_set( 1296 __in efx_nic_t *enp, 1297 __inout_bcount(size) caddr_t data, 1298 __in size_t size, 1299 __in efx_vpd_value_t *evvp); 1300 1301 extern __checkReturn efx_rc_t 1302 efx_vpd_next( 1303 __in efx_nic_t *enp, 1304 __inout_bcount(size) caddr_t data, 1305 __in size_t size, 1306 __out efx_vpd_value_t *evvp, 1307 __inout unsigned int *contp); 1308 1309 extern __checkReturn efx_rc_t 1310 efx_vpd_write( 1311 __in efx_nic_t *enp, 1312 __in_bcount(size) caddr_t data, 1313 __in size_t size); 1314 1315 extern void 1316 efx_vpd_fini( 1317 __in efx_nic_t *enp); 1318 1319 #endif /* EFSYS_OPT_VPD */ 1320 1321 /* NVRAM */ 1322 1323 #if EFSYS_OPT_NVRAM 1324 1325 typedef enum efx_nvram_type_e { 1326 EFX_NVRAM_INVALID = 0, 1327 EFX_NVRAM_BOOTROM, 1328 EFX_NVRAM_BOOTROM_CFG, 1329 EFX_NVRAM_MC_FIRMWARE, 1330 EFX_NVRAM_MC_GOLDEN, 1331 EFX_NVRAM_PHY, 1332 EFX_NVRAM_NULLPHY, 1333 EFX_NVRAM_FPGA, 1334 EFX_NVRAM_FCFW, 1335 EFX_NVRAM_CPLD, 1336 EFX_NVRAM_FPGA_BACKUP, 1337 EFX_NVRAM_DYNAMIC_CFG, 1338 EFX_NVRAM_NTYPES, 1339 } efx_nvram_type_t; 1340 1341 extern __checkReturn efx_rc_t 1342 efx_nvram_init( 1343 __in efx_nic_t *enp); 1344 1345 #if EFSYS_OPT_DIAG 1346 1347 extern __checkReturn efx_rc_t 1348 efx_nvram_test( 1349 __in efx_nic_t *enp); 1350 1351 #endif /* EFSYS_OPT_DIAG */ 1352 1353 extern __checkReturn efx_rc_t 1354 efx_nvram_size( 1355 __in efx_nic_t *enp, 1356 __in efx_nvram_type_t type, 1357 __out size_t *sizep); 1358 1359 extern __checkReturn efx_rc_t 1360 efx_nvram_rw_start( 1361 __in efx_nic_t *enp, 1362 __in efx_nvram_type_t type, 1363 __out_opt size_t *pref_chunkp); 1364 1365 extern void 1366 efx_nvram_rw_finish( 1367 __in efx_nic_t *enp, 1368 __in efx_nvram_type_t type); 1369 1370 extern __checkReturn efx_rc_t 1371 efx_nvram_get_version( 1372 __in efx_nic_t *enp, 1373 __in efx_nvram_type_t type, 1374 __out uint32_t *subtypep, 1375 __out_ecount(4) uint16_t version[4]); 1376 1377 extern __checkReturn efx_rc_t 1378 efx_nvram_read_chunk( 1379 __in efx_nic_t *enp, 1380 __in efx_nvram_type_t type, 1381 __in unsigned int offset, 1382 __out_bcount(size) caddr_t data, 1383 __in size_t size); 1384 1385 extern __checkReturn efx_rc_t 1386 efx_nvram_set_version( 1387 __in efx_nic_t *enp, 1388 __in efx_nvram_type_t type, 1389 __in_ecount(4) uint16_t version[4]); 1390 1391 /* Validate contents of TLV formatted partition */ 1392 extern __checkReturn efx_rc_t 1393 efx_nvram_tlv_validate( 1394 __in efx_nic_t *enp, 1395 __in uint32_t partn, 1396 __in_bcount(partn_size) caddr_t partn_data, 1397 __in size_t partn_size); 1398 1399 extern __checkReturn efx_rc_t 1400 efx_nvram_erase( 1401 __in efx_nic_t *enp, 1402 __in efx_nvram_type_t type); 1403 1404 extern __checkReturn efx_rc_t 1405 efx_nvram_write_chunk( 1406 __in efx_nic_t *enp, 1407 __in efx_nvram_type_t type, 1408 __in unsigned int offset, 1409 __in_bcount(size) caddr_t data, 1410 __in size_t size); 1411 1412 extern void 1413 efx_nvram_fini( 1414 __in efx_nic_t *enp); 1415 1416 #endif /* EFSYS_OPT_NVRAM */ 1417 1418 #if EFSYS_OPT_BOOTCFG 1419 1420 extern efx_rc_t 1421 efx_bootcfg_read( 1422 __in efx_nic_t *enp, 1423 __out_bcount(size) caddr_t data, 1424 __in size_t size); 1425 1426 extern efx_rc_t 1427 efx_bootcfg_write( 1428 __in efx_nic_t *enp, 1429 __in_bcount(size) caddr_t data, 1430 __in size_t size); 1431 1432 #endif /* EFSYS_OPT_BOOTCFG */ 1433 1434 #if EFSYS_OPT_WOL 1435 1436 typedef enum efx_wol_type_e { 1437 EFX_WOL_TYPE_INVALID, 1438 EFX_WOL_TYPE_MAGIC, 1439 EFX_WOL_TYPE_BITMAP, 1440 EFX_WOL_TYPE_LINK, 1441 EFX_WOL_NTYPES, 1442 } efx_wol_type_t; 1443 1444 typedef enum efx_lightsout_offload_type_e { 1445 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1446 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1447 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1448 } efx_lightsout_offload_type_t; 1449 1450 #define EFX_WOL_BITMAP_MASK_SIZE (48) 1451 #define EFX_WOL_BITMAP_VALUE_SIZE (128) 1452 1453 typedef union efx_wol_param_u { 1454 struct { 1455 uint8_t mac_addr[6]; 1456 } ewp_magic; 1457 struct { 1458 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1459 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1460 uint8_t value_len; 1461 } ewp_bitmap; 1462 } efx_wol_param_t; 1463 1464 typedef union efx_lightsout_offload_param_u { 1465 struct { 1466 uint8_t mac_addr[6]; 1467 uint32_t ip; 1468 } elop_arp; 1469 struct { 1470 uint8_t mac_addr[6]; 1471 uint32_t solicited_node[4]; 1472 uint32_t ip[4]; 1473 } elop_ns; 1474 } efx_lightsout_offload_param_t; 1475 1476 extern __checkReturn efx_rc_t 1477 efx_wol_init( 1478 __in efx_nic_t *enp); 1479 1480 extern __checkReturn efx_rc_t 1481 efx_wol_filter_clear( 1482 __in efx_nic_t *enp); 1483 1484 extern __checkReturn efx_rc_t 1485 efx_wol_filter_add( 1486 __in efx_nic_t *enp, 1487 __in efx_wol_type_t type, 1488 __in efx_wol_param_t *paramp, 1489 __out uint32_t *filter_idp); 1490 1491 extern __checkReturn efx_rc_t 1492 efx_wol_filter_remove( 1493 __in efx_nic_t *enp, 1494 __in uint32_t filter_id); 1495 1496 extern __checkReturn efx_rc_t 1497 efx_lightsout_offload_add( 1498 __in efx_nic_t *enp, 1499 __in efx_lightsout_offload_type_t type, 1500 __in efx_lightsout_offload_param_t *paramp, 1501 __out uint32_t *filter_idp); 1502 1503 extern __checkReturn efx_rc_t 1504 efx_lightsout_offload_remove( 1505 __in efx_nic_t *enp, 1506 __in efx_lightsout_offload_type_t type, 1507 __in uint32_t filter_id); 1508 1509 extern void 1510 efx_wol_fini( 1511 __in efx_nic_t *enp); 1512 1513 #endif /* EFSYS_OPT_WOL */ 1514 1515 #if EFSYS_OPT_DIAG 1516 1517 typedef enum efx_pattern_type_t { 1518 EFX_PATTERN_BYTE_INCREMENT = 0, 1519 EFX_PATTERN_ALL_THE_SAME, 1520 EFX_PATTERN_BIT_ALTERNATE, 1521 EFX_PATTERN_BYTE_ALTERNATE, 1522 EFX_PATTERN_BYTE_CHANGING, 1523 EFX_PATTERN_BIT_SWEEP, 1524 EFX_PATTERN_NTYPES 1525 } efx_pattern_type_t; 1526 1527 typedef void 1528 (*efx_sram_pattern_fn_t)( 1529 __in size_t row, 1530 __in boolean_t negate, 1531 __out efx_qword_t *eqp); 1532 1533 extern __checkReturn efx_rc_t 1534 efx_sram_test( 1535 __in efx_nic_t *enp, 1536 __in efx_pattern_type_t type); 1537 1538 #endif /* EFSYS_OPT_DIAG */ 1539 1540 extern __checkReturn efx_rc_t 1541 efx_sram_buf_tbl_set( 1542 __in efx_nic_t *enp, 1543 __in uint32_t id, 1544 __in efsys_mem_t *esmp, 1545 __in size_t n); 1546 1547 extern void 1548 efx_sram_buf_tbl_clear( 1549 __in efx_nic_t *enp, 1550 __in uint32_t id, 1551 __in size_t n); 1552 1553 #define EFX_BUF_TBL_SIZE 0x20000 1554 1555 #define EFX_BUF_SIZE 4096 1556 1557 /* EV */ 1558 1559 typedef struct efx_evq_s efx_evq_t; 1560 1561 #if EFSYS_OPT_QSTATS 1562 1563 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1564 typedef enum efx_ev_qstat_e { 1565 EV_ALL, 1566 EV_RX, 1567 EV_RX_OK, 1568 EV_RX_FRM_TRUNC, 1569 EV_RX_TOBE_DISC, 1570 EV_RX_PAUSE_FRM_ERR, 1571 EV_RX_BUF_OWNER_ID_ERR, 1572 EV_RX_IPV4_HDR_CHKSUM_ERR, 1573 EV_RX_TCP_UDP_CHKSUM_ERR, 1574 EV_RX_ETH_CRC_ERR, 1575 EV_RX_IP_FRAG_ERR, 1576 EV_RX_MCAST_PKT, 1577 EV_RX_MCAST_HASH_MATCH, 1578 EV_RX_TCP_IPV4, 1579 EV_RX_TCP_IPV6, 1580 EV_RX_UDP_IPV4, 1581 EV_RX_UDP_IPV6, 1582 EV_RX_OTHER_IPV4, 1583 EV_RX_OTHER_IPV6, 1584 EV_RX_NON_IP, 1585 EV_RX_BATCH, 1586 EV_TX, 1587 EV_TX_WQ_FF_FULL, 1588 EV_TX_PKT_ERR, 1589 EV_TX_PKT_TOO_BIG, 1590 EV_TX_UNEXPECTED, 1591 EV_GLOBAL, 1592 EV_GLOBAL_MNT, 1593 EV_DRIVER, 1594 EV_DRIVER_SRM_UPD_DONE, 1595 EV_DRIVER_TX_DESCQ_FLS_DONE, 1596 EV_DRIVER_RX_DESCQ_FLS_DONE, 1597 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1598 EV_DRIVER_RX_DSC_ERROR, 1599 EV_DRIVER_TX_DSC_ERROR, 1600 EV_DRV_GEN, 1601 EV_MCDI_RESPONSE, 1602 EV_NQSTATS 1603 } efx_ev_qstat_t; 1604 1605 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1606 1607 #endif /* EFSYS_OPT_QSTATS */ 1608 1609 extern __checkReturn efx_rc_t 1610 efx_ev_init( 1611 __in efx_nic_t *enp); 1612 1613 extern void 1614 efx_ev_fini( 1615 __in efx_nic_t *enp); 1616 1617 #define EFX_EVQ_MAXNEVS 32768 1618 #define EFX_EVQ_MINNEVS 512 1619 1620 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1621 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1622 1623 extern __checkReturn efx_rc_t 1624 efx_ev_qcreate( 1625 __in efx_nic_t *enp, 1626 __in unsigned int index, 1627 __in efsys_mem_t *esmp, 1628 __in size_t n, 1629 __in uint32_t id, 1630 __deref_out efx_evq_t **eepp); 1631 1632 extern void 1633 efx_ev_qpost( 1634 __in efx_evq_t *eep, 1635 __in uint16_t data); 1636 1637 typedef __checkReturn boolean_t 1638 (*efx_initialized_ev_t)( 1639 __in_opt void *arg); 1640 1641 #define EFX_PKT_UNICAST 0x0004 1642 #define EFX_PKT_START 0x0008 1643 1644 #define EFX_PKT_VLAN_TAGGED 0x0010 1645 #define EFX_CKSUM_TCPUDP 0x0020 1646 #define EFX_CKSUM_IPV4 0x0040 1647 #define EFX_PKT_CONT 0x0080 1648 1649 #define EFX_CHECK_VLAN 0x0100 1650 #define EFX_PKT_TCP 0x0200 1651 #define EFX_PKT_UDP 0x0400 1652 #define EFX_PKT_IPV4 0x0800 1653 1654 #define EFX_PKT_IPV6 0x1000 1655 #define EFX_PKT_PREFIX_LEN 0x2000 1656 #define EFX_ADDR_MISMATCH 0x4000 1657 #define EFX_DISCARD 0x8000 1658 1659 #define EFX_EV_RX_NLABELS 32 1660 #define EFX_EV_TX_NLABELS 32 1661 1662 typedef __checkReturn boolean_t 1663 (*efx_rx_ev_t)( 1664 __in_opt void *arg, 1665 __in uint32_t label, 1666 __in uint32_t id, 1667 __in uint32_t size, 1668 __in uint16_t flags); 1669 1670 typedef __checkReturn boolean_t 1671 (*efx_tx_ev_t)( 1672 __in_opt void *arg, 1673 __in uint32_t label, 1674 __in uint32_t id); 1675 1676 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1677 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1678 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1679 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1680 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1681 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1682 #define EFX_EXCEPTION_RX_ERROR 0x00000007 1683 #define EFX_EXCEPTION_TX_ERROR 0x00000008 1684 #define EFX_EXCEPTION_EV_ERROR 0x00000009 1685 1686 typedef __checkReturn boolean_t 1687 (*efx_exception_ev_t)( 1688 __in_opt void *arg, 1689 __in uint32_t label, 1690 __in uint32_t data); 1691 1692 typedef __checkReturn boolean_t 1693 (*efx_rxq_flush_done_ev_t)( 1694 __in_opt void *arg, 1695 __in uint32_t rxq_index); 1696 1697 typedef __checkReturn boolean_t 1698 (*efx_rxq_flush_failed_ev_t)( 1699 __in_opt void *arg, 1700 __in uint32_t rxq_index); 1701 1702 typedef __checkReturn boolean_t 1703 (*efx_txq_flush_done_ev_t)( 1704 __in_opt void *arg, 1705 __in uint32_t txq_index); 1706 1707 typedef __checkReturn boolean_t 1708 (*efx_software_ev_t)( 1709 __in_opt void *arg, 1710 __in uint16_t magic); 1711 1712 typedef __checkReturn boolean_t 1713 (*efx_sram_ev_t)( 1714 __in_opt void *arg, 1715 __in uint32_t code); 1716 1717 #define EFX_SRAM_CLEAR 0 1718 #define EFX_SRAM_UPDATE 1 1719 #define EFX_SRAM_ILLEGAL_CLEAR 2 1720 1721 typedef __checkReturn boolean_t 1722 (*efx_wake_up_ev_t)( 1723 __in_opt void *arg, 1724 __in uint32_t label); 1725 1726 typedef __checkReturn boolean_t 1727 (*efx_timer_ev_t)( 1728 __in_opt void *arg, 1729 __in uint32_t label); 1730 1731 typedef __checkReturn boolean_t 1732 (*efx_link_change_ev_t)( 1733 __in_opt void *arg, 1734 __in efx_link_mode_t link_mode); 1735 1736 #if EFSYS_OPT_MON_STATS 1737 1738 typedef __checkReturn boolean_t 1739 (*efx_monitor_ev_t)( 1740 __in_opt void *arg, 1741 __in efx_mon_stat_t id, 1742 __in efx_mon_stat_value_t value); 1743 1744 #endif /* EFSYS_OPT_MON_STATS */ 1745 1746 #if EFSYS_OPT_MAC_STATS 1747 1748 typedef __checkReturn boolean_t 1749 (*efx_mac_stats_ev_t)( 1750 __in_opt void *arg, 1751 __in uint32_t generation 1752 ); 1753 1754 #endif /* EFSYS_OPT_MAC_STATS */ 1755 1756 typedef struct efx_ev_callbacks_s { 1757 efx_initialized_ev_t eec_initialized; 1758 efx_rx_ev_t eec_rx; 1759 efx_tx_ev_t eec_tx; 1760 efx_exception_ev_t eec_exception; 1761 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1762 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1763 efx_txq_flush_done_ev_t eec_txq_flush_done; 1764 efx_software_ev_t eec_software; 1765 efx_sram_ev_t eec_sram; 1766 efx_wake_up_ev_t eec_wake_up; 1767 efx_timer_ev_t eec_timer; 1768 efx_link_change_ev_t eec_link_change; 1769 #if EFSYS_OPT_MON_STATS 1770 efx_monitor_ev_t eec_monitor; 1771 #endif /* EFSYS_OPT_MON_STATS */ 1772 #if EFSYS_OPT_MAC_STATS 1773 efx_mac_stats_ev_t eec_mac_stats; 1774 #endif /* EFSYS_OPT_MAC_STATS */ 1775 } efx_ev_callbacks_t; 1776 1777 extern __checkReturn boolean_t 1778 efx_ev_qpending( 1779 __in efx_evq_t *eep, 1780 __in unsigned int count); 1781 1782 #if EFSYS_OPT_EV_PREFETCH 1783 1784 extern void 1785 efx_ev_qprefetch( 1786 __in efx_evq_t *eep, 1787 __in unsigned int count); 1788 1789 #endif /* EFSYS_OPT_EV_PREFETCH */ 1790 1791 extern void 1792 efx_ev_qpoll( 1793 __in efx_evq_t *eep, 1794 __inout unsigned int *countp, 1795 __in const efx_ev_callbacks_t *eecp, 1796 __in_opt void *arg); 1797 1798 extern __checkReturn efx_rc_t 1799 efx_ev_qmoderate( 1800 __in efx_evq_t *eep, 1801 __in unsigned int us); 1802 1803 extern __checkReturn efx_rc_t 1804 efx_ev_qprime( 1805 __in efx_evq_t *eep, 1806 __in unsigned int count); 1807 1808 #if EFSYS_OPT_QSTATS 1809 1810 #if EFSYS_OPT_NAMES 1811 1812 extern const char * 1813 efx_ev_qstat_name( 1814 __in efx_nic_t *enp, 1815 __in unsigned int id); 1816 1817 #endif /* EFSYS_OPT_NAMES */ 1818 1819 extern void 1820 efx_ev_qstats_update( 1821 __in efx_evq_t *eep, 1822 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1823 1824 #endif /* EFSYS_OPT_QSTATS */ 1825 1826 extern void 1827 efx_ev_qdestroy( 1828 __in efx_evq_t *eep); 1829 1830 /* RX */ 1831 1832 extern __checkReturn efx_rc_t 1833 efx_rx_init( 1834 __inout efx_nic_t *enp); 1835 1836 extern void 1837 efx_rx_fini( 1838 __in efx_nic_t *enp); 1839 1840 #if EFSYS_OPT_RX_HDR_SPLIT 1841 __checkReturn efx_rc_t 1842 efx_rx_hdr_split_enable( 1843 __in efx_nic_t *enp, 1844 __in unsigned int hdr_buf_size, 1845 __in unsigned int pld_buf_size); 1846 1847 #endif /* EFSYS_OPT_RX_HDR_SPLIT */ 1848 1849 #if EFSYS_OPT_RX_SCATTER 1850 __checkReturn efx_rc_t 1851 efx_rx_scatter_enable( 1852 __in efx_nic_t *enp, 1853 __in unsigned int buf_size); 1854 #endif /* EFSYS_OPT_RX_SCATTER */ 1855 1856 #if EFSYS_OPT_RX_SCALE 1857 1858 typedef enum efx_rx_hash_alg_e { 1859 EFX_RX_HASHALG_LFSR = 0, 1860 EFX_RX_HASHALG_TOEPLITZ 1861 } efx_rx_hash_alg_t; 1862 1863 typedef enum efx_rx_hash_type_e { 1864 EFX_RX_HASH_IPV4 = 0, 1865 EFX_RX_HASH_TCPIPV4, 1866 EFX_RX_HASH_IPV6, 1867 EFX_RX_HASH_TCPIPV6, 1868 } efx_rx_hash_type_t; 1869 1870 typedef enum efx_rx_hash_support_e { 1871 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1872 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1873 } efx_rx_hash_support_t; 1874 1875 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1876 #define EFX_MAXRSS 64 /* RX indirection entry range */ 1877 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1878 1879 typedef enum efx_rx_scale_support_e { 1880 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */ 1881 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1882 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1883 } efx_rx_scale_support_t; 1884 1885 extern __checkReturn efx_rc_t 1886 efx_rx_hash_support_get( 1887 __in efx_nic_t *enp, 1888 __out efx_rx_hash_support_t *supportp); 1889 1890 1891 extern __checkReturn efx_rc_t 1892 efx_rx_scale_support_get( 1893 __in efx_nic_t *enp, 1894 __out efx_rx_scale_support_t *supportp); 1895 1896 extern __checkReturn efx_rc_t 1897 efx_rx_scale_mode_set( 1898 __in efx_nic_t *enp, 1899 __in efx_rx_hash_alg_t alg, 1900 __in efx_rx_hash_type_t type, 1901 __in boolean_t insert); 1902 1903 extern __checkReturn efx_rc_t 1904 efx_rx_scale_tbl_set( 1905 __in efx_nic_t *enp, 1906 __in_ecount(n) unsigned int *table, 1907 __in size_t n); 1908 1909 extern __checkReturn efx_rc_t 1910 efx_rx_scale_key_set( 1911 __in efx_nic_t *enp, 1912 __in_ecount(n) uint8_t *key, 1913 __in size_t n); 1914 1915 extern uint32_t 1916 efx_psuedo_hdr_hash_get( 1917 __in efx_nic_t *enp, 1918 __in efx_rx_hash_alg_t func, 1919 __in uint8_t *buffer); 1920 1921 #endif /* EFSYS_OPT_RX_SCALE */ 1922 1923 extern __checkReturn efx_rc_t 1924 efx_psuedo_hdr_pkt_length_get( 1925 __in efx_nic_t *enp, 1926 __in uint8_t *buffer, 1927 __out uint16_t *pkt_lengthp); 1928 1929 #define EFX_RXQ_MAXNDESCS 4096 1930 #define EFX_RXQ_MINNDESCS 512 1931 1932 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1933 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1934 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1935 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 1936 1937 typedef enum efx_rxq_type_e { 1938 EFX_RXQ_TYPE_DEFAULT, 1939 EFX_RXQ_TYPE_SPLIT_HEADER, 1940 EFX_RXQ_TYPE_SPLIT_PAYLOAD, 1941 EFX_RXQ_TYPE_SCATTER, 1942 EFX_RXQ_NTYPES 1943 } efx_rxq_type_t; 1944 1945 extern __checkReturn efx_rc_t 1946 efx_rx_qcreate( 1947 __in efx_nic_t *enp, 1948 __in unsigned int index, 1949 __in unsigned int label, 1950 __in efx_rxq_type_t type, 1951 __in efsys_mem_t *esmp, 1952 __in size_t n, 1953 __in uint32_t id, 1954 __in efx_evq_t *eep, 1955 __deref_out efx_rxq_t **erpp); 1956 1957 typedef struct efx_buffer_s { 1958 efsys_dma_addr_t eb_addr; 1959 size_t eb_size; 1960 boolean_t eb_eop; 1961 } efx_buffer_t; 1962 1963 typedef struct efx_desc_s { 1964 efx_qword_t ed_eq; 1965 } efx_desc_t; 1966 1967 extern void 1968 efx_rx_qpost( 1969 __in efx_rxq_t *erp, 1970 __in_ecount(n) efsys_dma_addr_t *addrp, 1971 __in size_t size, 1972 __in unsigned int n, 1973 __in unsigned int completed, 1974 __in unsigned int added); 1975 1976 extern void 1977 efx_rx_qpush( 1978 __in efx_rxq_t *erp, 1979 __in unsigned int added, 1980 __inout unsigned int *pushedp); 1981 1982 extern __checkReturn efx_rc_t 1983 efx_rx_qflush( 1984 __in efx_rxq_t *erp); 1985 1986 extern void 1987 efx_rx_qenable( 1988 __in efx_rxq_t *erp); 1989 1990 extern void 1991 efx_rx_qdestroy( 1992 __in efx_rxq_t *erp); 1993 1994 /* TX */ 1995 1996 typedef struct efx_txq_s efx_txq_t; 1997 1998 #if EFSYS_OPT_QSTATS 1999 2000 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2001 typedef enum efx_tx_qstat_e { 2002 TX_POST, 2003 TX_POST_PIO, 2004 TX_NQSTATS 2005 } efx_tx_qstat_t; 2006 2007 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2008 2009 #endif /* EFSYS_OPT_QSTATS */ 2010 2011 extern __checkReturn efx_rc_t 2012 efx_tx_init( 2013 __in efx_nic_t *enp); 2014 2015 extern void 2016 efx_tx_fini( 2017 __in efx_nic_t *enp); 2018 2019 #define EFX_BUG35388_WORKAROUND(_encp) \ 2020 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0)) 2021 2022 #define EFX_TXQ_MAXNDESCS(_encp) \ 2023 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096) 2024 2025 #define EFX_TXQ_MINNDESCS 512 2026 2027 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2028 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2029 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2030 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2031 2032 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2033 2034 #define EFX_TXQ_CKSUM_IPV4 0x0001 2035 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2036 2037 extern __checkReturn efx_rc_t 2038 efx_tx_qcreate( 2039 __in efx_nic_t *enp, 2040 __in unsigned int index, 2041 __in unsigned int label, 2042 __in efsys_mem_t *esmp, 2043 __in size_t n, 2044 __in uint32_t id, 2045 __in uint16_t flags, 2046 __in efx_evq_t *eep, 2047 __deref_out efx_txq_t **etpp, 2048 __out unsigned int *addedp); 2049 2050 extern __checkReturn efx_rc_t 2051 efx_tx_qpost( 2052 __in efx_txq_t *etp, 2053 __in_ecount(n) efx_buffer_t *eb, 2054 __in unsigned int n, 2055 __in unsigned int completed, 2056 __inout unsigned int *addedp); 2057 2058 extern __checkReturn efx_rc_t 2059 efx_tx_qpace( 2060 __in efx_txq_t *etp, 2061 __in unsigned int ns); 2062 2063 extern void 2064 efx_tx_qpush( 2065 __in efx_txq_t *etp, 2066 __in unsigned int added, 2067 __in unsigned int pushed); 2068 2069 extern __checkReturn efx_rc_t 2070 efx_tx_qflush( 2071 __in efx_txq_t *etp); 2072 2073 extern void 2074 efx_tx_qenable( 2075 __in efx_txq_t *etp); 2076 2077 extern __checkReturn efx_rc_t 2078 efx_tx_qpio_enable( 2079 __in efx_txq_t *etp); 2080 2081 extern void 2082 efx_tx_qpio_disable( 2083 __in efx_txq_t *etp); 2084 2085 extern __checkReturn efx_rc_t 2086 efx_tx_qpio_write( 2087 __in efx_txq_t *etp, 2088 __in_ecount(buf_length) uint8_t *buffer, 2089 __in size_t buf_length, 2090 __in size_t pio_buf_offset); 2091 2092 extern __checkReturn efx_rc_t 2093 efx_tx_qpio_post( 2094 __in efx_txq_t *etp, 2095 __in size_t pkt_length, 2096 __in unsigned int completed, 2097 __inout unsigned int *addedp); 2098 2099 extern __checkReturn efx_rc_t 2100 efx_tx_qdesc_post( 2101 __in efx_txq_t *etp, 2102 __in_ecount(n) efx_desc_t *ed, 2103 __in unsigned int n, 2104 __in unsigned int completed, 2105 __inout unsigned int *addedp); 2106 2107 extern void 2108 efx_tx_qdesc_dma_create( 2109 __in efx_txq_t *etp, 2110 __in efsys_dma_addr_t addr, 2111 __in size_t size, 2112 __in boolean_t eop, 2113 __out efx_desc_t *edp); 2114 2115 extern void 2116 efx_tx_qdesc_tso_create( 2117 __in efx_txq_t *etp, 2118 __in uint16_t ipv4_id, 2119 __in uint32_t tcp_seq, 2120 __in uint8_t tcp_flags, 2121 __out efx_desc_t *edp); 2122 2123 extern void 2124 efx_tx_qdesc_vlantci_create( 2125 __in efx_txq_t *etp, 2126 __in uint16_t tci, 2127 __out efx_desc_t *edp); 2128 2129 #if EFSYS_OPT_QSTATS 2130 2131 #if EFSYS_OPT_NAMES 2132 2133 extern const char * 2134 efx_tx_qstat_name( 2135 __in efx_nic_t *etp, 2136 __in unsigned int id); 2137 2138 #endif /* EFSYS_OPT_NAMES */ 2139 2140 extern void 2141 efx_tx_qstats_update( 2142 __in efx_txq_t *etp, 2143 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2144 2145 #endif /* EFSYS_OPT_QSTATS */ 2146 2147 extern void 2148 efx_tx_qdestroy( 2149 __in efx_txq_t *etp); 2150 2151 2152 /* FILTER */ 2153 2154 #if EFSYS_OPT_FILTER 2155 2156 #define EFX_ETHER_TYPE_IPV4 0x0800 2157 #define EFX_ETHER_TYPE_IPV6 0x86DD 2158 2159 #define EFX_IPPROTO_TCP 6 2160 #define EFX_IPPROTO_UDP 17 2161 2162 typedef enum efx_filter_flag_e { 2163 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 2164 * multiple queues */ 2165 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 2166 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter 2167 * (priority EFX_FILTER_PRI_AUTO). 2168 * May only be set by the filter 2169 * implementation for each type. 2170 * A removal request will 2171 * restore the automatic filter 2172 * in its place. */ 2173 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */ 2174 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */ 2175 } efx_filter_flag_t; 2176 2177 typedef enum efx_filter_match_flags_e { 2178 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host 2179 * address */ 2180 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host 2181 * address */ 2182 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */ 2183 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */ 2184 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */ 2185 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */ 2186 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */ 2187 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */ 2188 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */ 2189 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport 2190 * protocol */ 2191 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address 2192 * I/G bit. Used for RX default 2193 * unicast and multicast/ 2194 * broadcast filters. */ 2195 } efx_filter_match_flags_t; 2196 2197 typedef enum efx_filter_priority_s { 2198 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2199 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2200 * address list or hardware 2201 * requirements. This may only be used 2202 * by the filter implementation for 2203 * each NIC type. */ 2204 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2205 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2206 * client (e.g. SR-IOV, HyperV VMQ etc.) 2207 */ 2208 } efx_filter_priority_t; 2209 2210 /* 2211 * FIXME: All these fields are assumed to be in little-endian byte order. 2212 * It may be better for some to be big-endian. See bug42804. 2213 */ 2214 2215 typedef struct efx_filter_spec_s { 2216 uint32_t efs_match_flags:12; 2217 uint32_t efs_priority:2; 2218 uint32_t efs_flags:6; 2219 uint32_t efs_dmaq_id:12; 2220 uint32_t efs_rss_context; 2221 uint16_t efs_outer_vid; 2222 uint16_t efs_inner_vid; 2223 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2224 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2225 uint16_t efs_ether_type; 2226 uint8_t efs_ip_proto; 2227 uint16_t efs_loc_port; 2228 uint16_t efs_rem_port; 2229 efx_oword_t efs_rem_host; 2230 efx_oword_t efs_loc_host; 2231 } efx_filter_spec_t; 2232 2233 2234 /* Default values for use in filter specifications */ 2235 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff 2236 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2237 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2238 2239 extern __checkReturn efx_rc_t 2240 efx_filter_init( 2241 __in efx_nic_t *enp); 2242 2243 extern void 2244 efx_filter_fini( 2245 __in efx_nic_t *enp); 2246 2247 extern __checkReturn efx_rc_t 2248 efx_filter_insert( 2249 __in efx_nic_t *enp, 2250 __inout efx_filter_spec_t *spec); 2251 2252 extern __checkReturn efx_rc_t 2253 efx_filter_remove( 2254 __in efx_nic_t *enp, 2255 __inout efx_filter_spec_t *spec); 2256 2257 extern __checkReturn efx_rc_t 2258 efx_filter_restore( 2259 __in efx_nic_t *enp); 2260 2261 extern __checkReturn efx_rc_t 2262 efx_filter_supported_filters( 2263 __in efx_nic_t *enp, 2264 __out uint32_t *list, 2265 __out size_t *length); 2266 2267 extern void 2268 efx_filter_spec_init_rx( 2269 __inout efx_filter_spec_t *spec, 2270 __in efx_filter_priority_t priority, 2271 __in efx_filter_flag_t flags, 2272 __in efx_rxq_t *erp); 2273 2274 extern void 2275 efx_filter_spec_init_tx( 2276 __inout efx_filter_spec_t *spec, 2277 __in efx_txq_t *etp); 2278 2279 extern __checkReturn efx_rc_t 2280 efx_filter_spec_set_ipv4_local( 2281 __inout efx_filter_spec_t *spec, 2282 __in uint8_t proto, 2283 __in uint32_t host, 2284 __in uint16_t port); 2285 2286 extern __checkReturn efx_rc_t 2287 efx_filter_spec_set_ipv4_full( 2288 __inout efx_filter_spec_t *spec, 2289 __in uint8_t proto, 2290 __in uint32_t lhost, 2291 __in uint16_t lport, 2292 __in uint32_t rhost, 2293 __in uint16_t rport); 2294 2295 extern __checkReturn efx_rc_t 2296 efx_filter_spec_set_eth_local( 2297 __inout efx_filter_spec_t *spec, 2298 __in uint16_t vid, 2299 __in const uint8_t *addr); 2300 2301 extern __checkReturn efx_rc_t 2302 efx_filter_spec_set_uc_def( 2303 __inout efx_filter_spec_t *spec); 2304 2305 extern __checkReturn efx_rc_t 2306 efx_filter_spec_set_mc_def( 2307 __inout efx_filter_spec_t *spec); 2308 2309 #endif /* EFSYS_OPT_FILTER */ 2310 2311 /* HASH */ 2312 2313 extern __checkReturn uint32_t 2314 efx_hash_dwords( 2315 __in_ecount(count) uint32_t const *input, 2316 __in size_t count, 2317 __in uint32_t init); 2318 2319 extern __checkReturn uint32_t 2320 efx_hash_bytes( 2321 __in_ecount(length) uint8_t const *input, 2322 __in size_t length, 2323 __in uint32_t init); 2324 2325 2326 #ifdef __cplusplus 2327 } 2328 #endif 2329 2330 #endif /* _SYS_EFX_H */ 2331