1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_H 36 #define _SYS_EFX_H 37 38 #include "efsys.h" 39 #include "efx_check.h" 40 #include "efx_phy_ids.h" 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #define EFX_STATIC_ASSERT(_cond) \ 47 ((void)sizeof (char[(_cond) ? 1 : -1])) 48 49 #define EFX_ARRAY_SIZE(_array) \ 50 (sizeof (_array) / sizeof ((_array)[0])) 51 52 #define EFX_FIELD_OFFSET(_type, _field) \ 53 ((size_t)&(((_type *)0)->_field)) 54 55 /* The macro expands divider twice */ 56 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 57 58 /* Return codes */ 59 60 typedef __success(return == 0) int efx_rc_t; 61 62 63 /* Chip families */ 64 65 typedef enum efx_family_e { 66 EFX_FAMILY_INVALID, 67 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 68 EFX_FAMILY_SIENA, 69 EFX_FAMILY_HUNTINGTON, 70 EFX_FAMILY_MEDFORD, 71 EFX_FAMILY_NTYPES 72 } efx_family_t; 73 74 extern __checkReturn efx_rc_t 75 efx_family( 76 __in uint16_t venid, 77 __in uint16_t devid, 78 __out efx_family_t *efp); 79 80 81 #define EFX_PCI_VENID_SFC 0x1924 82 83 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 84 85 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 86 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 87 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 88 89 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 90 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 91 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 92 93 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 94 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 95 96 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 97 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 98 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 99 100 #define EFX_MEM_BAR 2 101 102 /* Error codes */ 103 104 enum { 105 EFX_ERR_INVALID, 106 EFX_ERR_SRAM_OOB, 107 EFX_ERR_BUFID_DC_OOB, 108 EFX_ERR_MEM_PERR, 109 EFX_ERR_RBUF_OWN, 110 EFX_ERR_TBUF_OWN, 111 EFX_ERR_RDESQ_OWN, 112 EFX_ERR_TDESQ_OWN, 113 EFX_ERR_EVQ_OWN, 114 EFX_ERR_EVFF_OFLO, 115 EFX_ERR_ILL_ADDR, 116 EFX_ERR_SRAM_PERR, 117 EFX_ERR_NCODES 118 }; 119 120 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 121 extern __checkReturn uint32_t 122 efx_crc32_calculate( 123 __in uint32_t crc_init, 124 __in_ecount(length) uint8_t const *input, 125 __in int length); 126 127 128 /* Type prototypes */ 129 130 typedef struct efx_rxq_s efx_rxq_t; 131 132 /* NIC */ 133 134 typedef struct efx_nic_s efx_nic_t; 135 136 extern __checkReturn efx_rc_t 137 efx_nic_create( 138 __in efx_family_t family, 139 __in efsys_identifier_t *esip, 140 __in efsys_bar_t *esbp, 141 __in efsys_lock_t *eslp, 142 __deref_out efx_nic_t **enpp); 143 144 extern __checkReturn efx_rc_t 145 efx_nic_probe( 146 __in efx_nic_t *enp); 147 148 extern __checkReturn efx_rc_t 149 efx_nic_init( 150 __in efx_nic_t *enp); 151 152 extern __checkReturn efx_rc_t 153 efx_nic_reset( 154 __in efx_nic_t *enp); 155 156 #if EFSYS_OPT_DIAG 157 158 extern __checkReturn efx_rc_t 159 efx_nic_register_test( 160 __in efx_nic_t *enp); 161 162 #endif /* EFSYS_OPT_DIAG */ 163 164 extern void 165 efx_nic_fini( 166 __in efx_nic_t *enp); 167 168 extern void 169 efx_nic_unprobe( 170 __in efx_nic_t *enp); 171 172 extern void 173 efx_nic_destroy( 174 __in efx_nic_t *enp); 175 176 #define EFX_PCIE_LINK_SPEED_GEN1 1 177 #define EFX_PCIE_LINK_SPEED_GEN2 2 178 #define EFX_PCIE_LINK_SPEED_GEN3 3 179 180 typedef enum efx_pcie_link_performance_e { 181 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 182 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 184 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 185 } efx_pcie_link_performance_t; 186 187 extern __checkReturn efx_rc_t 188 efx_nic_calculate_pcie_link_bandwidth( 189 __in uint32_t pcie_link_width, 190 __in uint32_t pcie_link_gen, 191 __out uint32_t *bandwidth_mbpsp); 192 193 extern __checkReturn efx_rc_t 194 efx_nic_check_pcie_link_speed( 195 __in efx_nic_t *enp, 196 __in uint32_t pcie_link_width, 197 __in uint32_t pcie_link_gen, 198 __out efx_pcie_link_performance_t *resultp); 199 200 #if EFSYS_OPT_MCDI 201 202 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 203 /* Huntington and Medford require MCDIv2 commands */ 204 #define WITH_MCDI_V2 1 205 #endif 206 207 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 208 209 typedef enum efx_mcdi_exception_e { 210 EFX_MCDI_EXCEPTION_MC_REBOOT, 211 EFX_MCDI_EXCEPTION_MC_BADASSERT, 212 } efx_mcdi_exception_t; 213 214 #if EFSYS_OPT_MCDI_LOGGING 215 typedef enum efx_log_msg_e { 216 EFX_LOG_INVALID, 217 EFX_LOG_MCDI_REQUEST, 218 EFX_LOG_MCDI_RESPONSE, 219 } efx_log_msg_t; 220 #endif /* EFSYS_OPT_MCDI_LOGGING */ 221 222 typedef struct efx_mcdi_transport_s { 223 void *emt_context; 224 efsys_mem_t *emt_dma_mem; 225 void (*emt_execute)(void *, efx_mcdi_req_t *); 226 void (*emt_ev_cpl)(void *); 227 void (*emt_exception)(void *, efx_mcdi_exception_t); 228 #if EFSYS_OPT_MCDI_LOGGING 229 void (*emt_logger)(void *, efx_log_msg_t, 230 void *, size_t, void *, size_t); 231 #endif /* EFSYS_OPT_MCDI_LOGGING */ 232 #if EFSYS_OPT_MCDI_PROXY_AUTH 233 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 234 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 235 } efx_mcdi_transport_t; 236 237 extern __checkReturn efx_rc_t 238 efx_mcdi_init( 239 __in efx_nic_t *enp, 240 __in const efx_mcdi_transport_t *mtp); 241 242 extern __checkReturn efx_rc_t 243 efx_mcdi_reboot( 244 __in efx_nic_t *enp); 245 246 void 247 efx_mcdi_new_epoch( 248 __in efx_nic_t *enp); 249 250 extern void 251 efx_mcdi_get_timeout( 252 __in efx_nic_t *enp, 253 __in efx_mcdi_req_t *emrp, 254 __out uint32_t *usec_timeoutp); 255 256 extern void 257 efx_mcdi_request_start( 258 __in efx_nic_t *enp, 259 __in efx_mcdi_req_t *emrp, 260 __in boolean_t ev_cpl); 261 262 extern __checkReturn boolean_t 263 efx_mcdi_request_poll( 264 __in efx_nic_t *enp); 265 266 extern __checkReturn boolean_t 267 efx_mcdi_request_abort( 268 __in efx_nic_t *enp); 269 270 extern void 271 efx_mcdi_fini( 272 __in efx_nic_t *enp); 273 274 #endif /* EFSYS_OPT_MCDI */ 275 276 /* INTR */ 277 278 #define EFX_NINTR_SIENA 1024 279 280 typedef enum efx_intr_type_e { 281 EFX_INTR_INVALID = 0, 282 EFX_INTR_LINE, 283 EFX_INTR_MESSAGE, 284 EFX_INTR_NTYPES 285 } efx_intr_type_t; 286 287 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 288 289 extern __checkReturn efx_rc_t 290 efx_intr_init( 291 __in efx_nic_t *enp, 292 __in efx_intr_type_t type, 293 __in efsys_mem_t *esmp); 294 295 extern void 296 efx_intr_enable( 297 __in efx_nic_t *enp); 298 299 extern void 300 efx_intr_disable( 301 __in efx_nic_t *enp); 302 303 extern void 304 efx_intr_disable_unlocked( 305 __in efx_nic_t *enp); 306 307 #define EFX_INTR_NEVQS 32 308 309 extern __checkReturn efx_rc_t 310 efx_intr_trigger( 311 __in efx_nic_t *enp, 312 __in unsigned int level); 313 314 extern void 315 efx_intr_status_line( 316 __in efx_nic_t *enp, 317 __out boolean_t *fatalp, 318 __out uint32_t *maskp); 319 320 extern void 321 efx_intr_status_message( 322 __in efx_nic_t *enp, 323 __in unsigned int message, 324 __out boolean_t *fatalp); 325 326 extern void 327 efx_intr_fatal( 328 __in efx_nic_t *enp); 329 330 extern void 331 efx_intr_fini( 332 __in efx_nic_t *enp); 333 334 /* MAC */ 335 336 #if EFSYS_OPT_MAC_STATS 337 338 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */ 339 typedef enum efx_mac_stat_e { 340 EFX_MAC_RX_OCTETS, 341 EFX_MAC_RX_PKTS, 342 EFX_MAC_RX_UNICST_PKTS, 343 EFX_MAC_RX_MULTICST_PKTS, 344 EFX_MAC_RX_BRDCST_PKTS, 345 EFX_MAC_RX_PAUSE_PKTS, 346 EFX_MAC_RX_LE_64_PKTS, 347 EFX_MAC_RX_65_TO_127_PKTS, 348 EFX_MAC_RX_128_TO_255_PKTS, 349 EFX_MAC_RX_256_TO_511_PKTS, 350 EFX_MAC_RX_512_TO_1023_PKTS, 351 EFX_MAC_RX_1024_TO_15XX_PKTS, 352 EFX_MAC_RX_GE_15XX_PKTS, 353 EFX_MAC_RX_ERRORS, 354 EFX_MAC_RX_FCS_ERRORS, 355 EFX_MAC_RX_DROP_EVENTS, 356 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 357 EFX_MAC_RX_SYMBOL_ERRORS, 358 EFX_MAC_RX_ALIGN_ERRORS, 359 EFX_MAC_RX_INTERNAL_ERRORS, 360 EFX_MAC_RX_JABBER_PKTS, 361 EFX_MAC_RX_LANE0_CHAR_ERR, 362 EFX_MAC_RX_LANE1_CHAR_ERR, 363 EFX_MAC_RX_LANE2_CHAR_ERR, 364 EFX_MAC_RX_LANE3_CHAR_ERR, 365 EFX_MAC_RX_LANE0_DISP_ERR, 366 EFX_MAC_RX_LANE1_DISP_ERR, 367 EFX_MAC_RX_LANE2_DISP_ERR, 368 EFX_MAC_RX_LANE3_DISP_ERR, 369 EFX_MAC_RX_MATCH_FAULT, 370 EFX_MAC_RX_NODESC_DROP_CNT, 371 EFX_MAC_TX_OCTETS, 372 EFX_MAC_TX_PKTS, 373 EFX_MAC_TX_UNICST_PKTS, 374 EFX_MAC_TX_MULTICST_PKTS, 375 EFX_MAC_TX_BRDCST_PKTS, 376 EFX_MAC_TX_PAUSE_PKTS, 377 EFX_MAC_TX_LE_64_PKTS, 378 EFX_MAC_TX_65_TO_127_PKTS, 379 EFX_MAC_TX_128_TO_255_PKTS, 380 EFX_MAC_TX_256_TO_511_PKTS, 381 EFX_MAC_TX_512_TO_1023_PKTS, 382 EFX_MAC_TX_1024_TO_15XX_PKTS, 383 EFX_MAC_TX_GE_15XX_PKTS, 384 EFX_MAC_TX_ERRORS, 385 EFX_MAC_TX_SGL_COL_PKTS, 386 EFX_MAC_TX_MULT_COL_PKTS, 387 EFX_MAC_TX_EX_COL_PKTS, 388 EFX_MAC_TX_LATE_COL_PKTS, 389 EFX_MAC_TX_DEF_PKTS, 390 EFX_MAC_TX_EX_DEF_PKTS, 391 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 392 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 393 EFX_MAC_PM_TRUNC_VFIFO_FULL, 394 EFX_MAC_PM_DISCARD_VFIFO_FULL, 395 EFX_MAC_PM_TRUNC_QBB, 396 EFX_MAC_PM_DISCARD_QBB, 397 EFX_MAC_PM_DISCARD_MAPPING, 398 EFX_MAC_RXDP_Q_DISABLED_PKTS, 399 EFX_MAC_RXDP_DI_DROPPED_PKTS, 400 EFX_MAC_RXDP_STREAMING_PKTS, 401 EFX_MAC_RXDP_HLB_FETCH, 402 EFX_MAC_RXDP_HLB_WAIT, 403 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 404 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 405 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 406 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 407 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 408 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 409 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 410 EFX_MAC_VADAPTER_RX_BAD_BYTES, 411 EFX_MAC_VADAPTER_RX_OVERFLOW, 412 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 413 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 414 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 415 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 416 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 417 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 418 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 419 EFX_MAC_VADAPTER_TX_BAD_BYTES, 420 EFX_MAC_VADAPTER_TX_OVERFLOW, 421 EFX_MAC_NSTATS 422 } efx_mac_stat_t; 423 424 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 425 426 #endif /* EFSYS_OPT_MAC_STATS */ 427 428 typedef enum efx_link_mode_e { 429 EFX_LINK_UNKNOWN = 0, 430 EFX_LINK_DOWN, 431 EFX_LINK_10HDX, 432 EFX_LINK_10FDX, 433 EFX_LINK_100HDX, 434 EFX_LINK_100FDX, 435 EFX_LINK_1000HDX, 436 EFX_LINK_1000FDX, 437 EFX_LINK_10000FDX, 438 EFX_LINK_40000FDX, 439 EFX_LINK_NMODES 440 } efx_link_mode_t; 441 442 #define EFX_MAC_ADDR_LEN 6 443 444 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 445 446 #define EFX_MAC_MULTICAST_LIST_MAX 256 447 448 #define EFX_MAC_SDU_MAX 9202 449 450 #define EFX_MAC_PDU_ADJUSTMENT \ 451 (/* EtherII */ 14 \ 452 + /* VLAN */ 4 \ 453 + /* CRC */ 4 \ 454 + /* bug16011 */ 16) \ 455 456 #define EFX_MAC_PDU(_sdu) \ 457 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 458 459 /* 460 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 461 * the SDU rounded up slightly. 462 */ 463 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 464 465 #define EFX_MAC_PDU_MIN 60 466 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 467 468 extern __checkReturn efx_rc_t 469 efx_mac_pdu_get( 470 __in efx_nic_t *enp, 471 __out size_t *pdu); 472 473 extern __checkReturn efx_rc_t 474 efx_mac_pdu_set( 475 __in efx_nic_t *enp, 476 __in size_t pdu); 477 478 extern __checkReturn efx_rc_t 479 efx_mac_addr_set( 480 __in efx_nic_t *enp, 481 __in uint8_t *addr); 482 483 extern __checkReturn efx_rc_t 484 efx_mac_filter_set( 485 __in efx_nic_t *enp, 486 __in boolean_t all_unicst, 487 __in boolean_t mulcst, 488 __in boolean_t all_mulcst, 489 __in boolean_t brdcst); 490 491 extern __checkReturn efx_rc_t 492 efx_mac_multicast_list_set( 493 __in efx_nic_t *enp, 494 __in_ecount(6*count) uint8_t const *addrs, 495 __in int count); 496 497 extern __checkReturn efx_rc_t 498 efx_mac_filter_default_rxq_set( 499 __in efx_nic_t *enp, 500 __in efx_rxq_t *erp, 501 __in boolean_t using_rss); 502 503 extern void 504 efx_mac_filter_default_rxq_clear( 505 __in efx_nic_t *enp); 506 507 extern __checkReturn efx_rc_t 508 efx_mac_drain( 509 __in efx_nic_t *enp, 510 __in boolean_t enabled); 511 512 extern __checkReturn efx_rc_t 513 efx_mac_up( 514 __in efx_nic_t *enp, 515 __out boolean_t *mac_upp); 516 517 #define EFX_FCNTL_RESPOND 0x00000001 518 #define EFX_FCNTL_GENERATE 0x00000002 519 520 extern __checkReturn efx_rc_t 521 efx_mac_fcntl_set( 522 __in efx_nic_t *enp, 523 __in unsigned int fcntl, 524 __in boolean_t autoneg); 525 526 extern void 527 efx_mac_fcntl_get( 528 __in efx_nic_t *enp, 529 __out unsigned int *fcntl_wantedp, 530 __out unsigned int *fcntl_linkp); 531 532 533 #if EFSYS_OPT_MAC_STATS 534 535 #if EFSYS_OPT_NAMES 536 537 extern __checkReturn const char * 538 efx_mac_stat_name( 539 __in efx_nic_t *enp, 540 __in unsigned int id); 541 542 #endif /* EFSYS_OPT_NAMES */ 543 544 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 545 546 #define EFX_MAC_STATS_MASK_NPAGES \ 547 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 548 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 549 550 /* 551 * Get mask of MAC statistics supported by the hardware. 552 * 553 * If mask_size is insufficient to return the mask, EINVAL error is 554 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 555 * (which is sizeof (uint32_t)) is sufficient. 556 */ 557 extern __checkReturn efx_rc_t 558 efx_mac_stats_get_mask( 559 __in efx_nic_t *enp, 560 __out_bcount(mask_size) uint32_t *maskp, 561 __in size_t mask_size); 562 563 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 564 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 565 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 566 567 #define EFX_MAC_STATS_SIZE 0x400 568 569 extern __checkReturn efx_rc_t 570 efx_mac_stats_clear( 571 __in efx_nic_t *enp); 572 573 /* 574 * Upload mac statistics supported by the hardware into the given buffer. 575 * 576 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 577 * and page aligned. 578 * 579 * The hardware will only DMA statistics that it understands (of course). 580 * Drivers should not make any assumptions about which statistics are 581 * supported, especially when the statistics are generated by firmware. 582 * 583 * Thus, drivers should zero this buffer before use, so that not-understood 584 * statistics read back as zero. 585 */ 586 extern __checkReturn efx_rc_t 587 efx_mac_stats_upload( 588 __in efx_nic_t *enp, 589 __in efsys_mem_t *esmp); 590 591 extern __checkReturn efx_rc_t 592 efx_mac_stats_periodic( 593 __in efx_nic_t *enp, 594 __in efsys_mem_t *esmp, 595 __in uint16_t period_ms, 596 __in boolean_t events); 597 598 extern __checkReturn efx_rc_t 599 efx_mac_stats_update( 600 __in efx_nic_t *enp, 601 __in efsys_mem_t *esmp, 602 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 603 __inout_opt uint32_t *generationp); 604 605 #endif /* EFSYS_OPT_MAC_STATS */ 606 607 /* MON */ 608 609 typedef enum efx_mon_type_e { 610 EFX_MON_INVALID = 0, 611 EFX_MON_SFC90X0, 612 EFX_MON_SFC91X0, 613 EFX_MON_SFC92X0, 614 EFX_MON_NTYPES 615 } efx_mon_type_t; 616 617 #if EFSYS_OPT_NAMES 618 619 extern const char * 620 efx_mon_name( 621 __in efx_nic_t *enp); 622 623 #endif /* EFSYS_OPT_NAMES */ 624 625 extern __checkReturn efx_rc_t 626 efx_mon_init( 627 __in efx_nic_t *enp); 628 629 #if EFSYS_OPT_MON_STATS 630 631 #define EFX_MON_STATS_PAGE_SIZE 0x100 632 #define EFX_MON_MASK_ELEMENT_SIZE 32 633 634 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock aa0233c80156308e */ 635 typedef enum efx_mon_stat_e { 636 EFX_MON_STAT_2_5V, 637 EFX_MON_STAT_VCCP1, 638 EFX_MON_STAT_VCC, 639 EFX_MON_STAT_5V, 640 EFX_MON_STAT_12V, 641 EFX_MON_STAT_VCCP2, 642 EFX_MON_STAT_EXT_TEMP, 643 EFX_MON_STAT_INT_TEMP, 644 EFX_MON_STAT_AIN1, 645 EFX_MON_STAT_AIN2, 646 EFX_MON_STAT_INT_COOLING, 647 EFX_MON_STAT_EXT_COOLING, 648 EFX_MON_STAT_1V, 649 EFX_MON_STAT_1_2V, 650 EFX_MON_STAT_1_8V, 651 EFX_MON_STAT_3_3V, 652 EFX_MON_STAT_1_2VA, 653 EFX_MON_STAT_VREF, 654 EFX_MON_STAT_VAOE, 655 EFX_MON_STAT_AOE_TEMP, 656 EFX_MON_STAT_PSU_AOE_TEMP, 657 EFX_MON_STAT_PSU_TEMP, 658 EFX_MON_STAT_FAN0, 659 EFX_MON_STAT_FAN1, 660 EFX_MON_STAT_FAN2, 661 EFX_MON_STAT_FAN3, 662 EFX_MON_STAT_FAN4, 663 EFX_MON_STAT_VAOE_IN, 664 EFX_MON_STAT_IAOE, 665 EFX_MON_STAT_IAOE_IN, 666 EFX_MON_STAT_NIC_POWER, 667 EFX_MON_STAT_0_9V, 668 EFX_MON_STAT_I0_9V, 669 EFX_MON_STAT_I1_2V, 670 EFX_MON_STAT_0_9V_ADC, 671 EFX_MON_STAT_INT_TEMP2, 672 EFX_MON_STAT_VREG_TEMP, 673 EFX_MON_STAT_VREG_0_9V_TEMP, 674 EFX_MON_STAT_VREG_1_2V_TEMP, 675 EFX_MON_STAT_INT_VPTAT, 676 EFX_MON_STAT_INT_ADC_TEMP, 677 EFX_MON_STAT_EXT_VPTAT, 678 EFX_MON_STAT_EXT_ADC_TEMP, 679 EFX_MON_STAT_AMBIENT_TEMP, 680 EFX_MON_STAT_AIRFLOW, 681 EFX_MON_STAT_VDD08D_VSS08D_CSR, 682 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 683 EFX_MON_STAT_HOTPOINT_TEMP, 684 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0, 685 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1, 686 EFX_MON_STAT_MUM_VCC, 687 EFX_MON_STAT_0V9_A, 688 EFX_MON_STAT_I0V9_A, 689 EFX_MON_STAT_0V9_A_TEMP, 690 EFX_MON_STAT_0V9_B, 691 EFX_MON_STAT_I0V9_B, 692 EFX_MON_STAT_0V9_B_TEMP, 693 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 694 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC, 695 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 696 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC, 697 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 698 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 699 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC, 700 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC, 701 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 702 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 703 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, 704 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, 705 EFX_MON_STAT_SODIMM_VOUT, 706 EFX_MON_STAT_SODIMM_0_TEMP, 707 EFX_MON_STAT_SODIMM_1_TEMP, 708 EFX_MON_STAT_PHY0_VCC, 709 EFX_MON_STAT_PHY1_VCC, 710 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 711 EFX_MON_STAT_BOARD_FRONT_TEMP, 712 EFX_MON_STAT_BOARD_BACK_TEMP, 713 EFX_MON_STAT_I1V8, 714 EFX_MON_STAT_I2V5, 715 EFX_MON_NSTATS 716 } efx_mon_stat_t; 717 718 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 719 720 typedef enum efx_mon_stat_state_e { 721 EFX_MON_STAT_STATE_OK = 0, 722 EFX_MON_STAT_STATE_WARNING = 1, 723 EFX_MON_STAT_STATE_FATAL = 2, 724 EFX_MON_STAT_STATE_BROKEN = 3, 725 EFX_MON_STAT_STATE_NO_READING = 4, 726 } efx_mon_stat_state_t; 727 728 typedef struct efx_mon_stat_value_s { 729 uint16_t emsv_value; 730 uint16_t emsv_state; 731 } efx_mon_stat_value_t; 732 733 #if EFSYS_OPT_NAMES 734 735 extern const char * 736 efx_mon_stat_name( 737 __in efx_nic_t *enp, 738 __in efx_mon_stat_t id); 739 740 #endif /* EFSYS_OPT_NAMES */ 741 742 extern __checkReturn efx_rc_t 743 efx_mon_stats_update( 744 __in efx_nic_t *enp, 745 __in efsys_mem_t *esmp, 746 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 747 748 #endif /* EFSYS_OPT_MON_STATS */ 749 750 extern void 751 efx_mon_fini( 752 __in efx_nic_t *enp); 753 754 /* PHY */ 755 756 extern __checkReturn efx_rc_t 757 efx_phy_verify( 758 __in efx_nic_t *enp); 759 760 #if EFSYS_OPT_PHY_LED_CONTROL 761 762 typedef enum efx_phy_led_mode_e { 763 EFX_PHY_LED_DEFAULT = 0, 764 EFX_PHY_LED_OFF, 765 EFX_PHY_LED_ON, 766 EFX_PHY_LED_FLASH, 767 EFX_PHY_LED_NMODES 768 } efx_phy_led_mode_t; 769 770 extern __checkReturn efx_rc_t 771 efx_phy_led_set( 772 __in efx_nic_t *enp, 773 __in efx_phy_led_mode_t mode); 774 775 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 776 777 extern __checkReturn efx_rc_t 778 efx_port_init( 779 __in efx_nic_t *enp); 780 781 #if EFSYS_OPT_LOOPBACK 782 783 typedef enum efx_loopback_type_e { 784 EFX_LOOPBACK_OFF = 0, 785 EFX_LOOPBACK_DATA = 1, 786 EFX_LOOPBACK_GMAC = 2, 787 EFX_LOOPBACK_XGMII = 3, 788 EFX_LOOPBACK_XGXS = 4, 789 EFX_LOOPBACK_XAUI = 5, 790 EFX_LOOPBACK_GMII = 6, 791 EFX_LOOPBACK_SGMII = 7, 792 EFX_LOOPBACK_XGBR = 8, 793 EFX_LOOPBACK_XFI = 9, 794 EFX_LOOPBACK_XAUI_FAR = 10, 795 EFX_LOOPBACK_GMII_FAR = 11, 796 EFX_LOOPBACK_SGMII_FAR = 12, 797 EFX_LOOPBACK_XFI_FAR = 13, 798 EFX_LOOPBACK_GPHY = 14, 799 EFX_LOOPBACK_PHY_XS = 15, 800 EFX_LOOPBACK_PCS = 16, 801 EFX_LOOPBACK_PMA_PMD = 17, 802 EFX_LOOPBACK_XPORT = 18, 803 EFX_LOOPBACK_XGMII_WS = 19, 804 EFX_LOOPBACK_XAUI_WS = 20, 805 EFX_LOOPBACK_XAUI_WS_FAR = 21, 806 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 807 EFX_LOOPBACK_GMII_WS = 23, 808 EFX_LOOPBACK_XFI_WS = 24, 809 EFX_LOOPBACK_XFI_WS_FAR = 25, 810 EFX_LOOPBACK_PHYXS_WS = 26, 811 EFX_LOOPBACK_PMA_INT = 27, 812 EFX_LOOPBACK_SD_NEAR = 28, 813 EFX_LOOPBACK_SD_FAR = 29, 814 EFX_LOOPBACK_PMA_INT_WS = 30, 815 EFX_LOOPBACK_SD_FEP2_WS = 31, 816 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 817 EFX_LOOPBACK_SD_FEP_WS = 33, 818 EFX_LOOPBACK_SD_FES_WS = 34, 819 EFX_LOOPBACK_NTYPES 820 } efx_loopback_type_t; 821 822 typedef enum efx_loopback_kind_e { 823 EFX_LOOPBACK_KIND_OFF = 0, 824 EFX_LOOPBACK_KIND_ALL, 825 EFX_LOOPBACK_KIND_MAC, 826 EFX_LOOPBACK_KIND_PHY, 827 EFX_LOOPBACK_NKINDS 828 } efx_loopback_kind_t; 829 830 extern void 831 efx_loopback_mask( 832 __in efx_loopback_kind_t loopback_kind, 833 __out efx_qword_t *maskp); 834 835 extern __checkReturn efx_rc_t 836 efx_port_loopback_set( 837 __in efx_nic_t *enp, 838 __in efx_link_mode_t link_mode, 839 __in efx_loopback_type_t type); 840 841 #if EFSYS_OPT_NAMES 842 843 extern __checkReturn const char * 844 efx_loopback_type_name( 845 __in efx_nic_t *enp, 846 __in efx_loopback_type_t type); 847 848 #endif /* EFSYS_OPT_NAMES */ 849 850 #endif /* EFSYS_OPT_LOOPBACK */ 851 852 extern __checkReturn efx_rc_t 853 efx_port_poll( 854 __in efx_nic_t *enp, 855 __out_opt efx_link_mode_t *link_modep); 856 857 extern void 858 efx_port_fini( 859 __in efx_nic_t *enp); 860 861 typedef enum efx_phy_cap_type_e { 862 EFX_PHY_CAP_INVALID = 0, 863 EFX_PHY_CAP_10HDX, 864 EFX_PHY_CAP_10FDX, 865 EFX_PHY_CAP_100HDX, 866 EFX_PHY_CAP_100FDX, 867 EFX_PHY_CAP_1000HDX, 868 EFX_PHY_CAP_1000FDX, 869 EFX_PHY_CAP_10000FDX, 870 EFX_PHY_CAP_PAUSE, 871 EFX_PHY_CAP_ASYM, 872 EFX_PHY_CAP_AN, 873 EFX_PHY_CAP_40000FDX, 874 EFX_PHY_CAP_NTYPES 875 } efx_phy_cap_type_t; 876 877 878 #define EFX_PHY_CAP_CURRENT 0x00000000 879 #define EFX_PHY_CAP_DEFAULT 0x00000001 880 #define EFX_PHY_CAP_PERM 0x00000002 881 882 extern void 883 efx_phy_adv_cap_get( 884 __in efx_nic_t *enp, 885 __in uint32_t flag, 886 __out uint32_t *maskp); 887 888 extern __checkReturn efx_rc_t 889 efx_phy_adv_cap_set( 890 __in efx_nic_t *enp, 891 __in uint32_t mask); 892 893 extern void 894 efx_phy_lp_cap_get( 895 __in efx_nic_t *enp, 896 __out uint32_t *maskp); 897 898 extern __checkReturn efx_rc_t 899 efx_phy_oui_get( 900 __in efx_nic_t *enp, 901 __out uint32_t *ouip); 902 903 typedef enum efx_phy_media_type_e { 904 EFX_PHY_MEDIA_INVALID = 0, 905 EFX_PHY_MEDIA_XAUI, 906 EFX_PHY_MEDIA_CX4, 907 EFX_PHY_MEDIA_KX4, 908 EFX_PHY_MEDIA_XFP, 909 EFX_PHY_MEDIA_SFP_PLUS, 910 EFX_PHY_MEDIA_BASE_T, 911 EFX_PHY_MEDIA_QSFP_PLUS, 912 EFX_PHY_MEDIA_NTYPES 913 } efx_phy_media_type_t; 914 915 /* 916 * Get the type of medium currently used. If the board has ports for 917 * modules, a module is present, and we recognise the media type of 918 * the module, then this will be the media type of the module. 919 * Otherwise it will be the media type of the port. 920 */ 921 extern void 922 efx_phy_media_type_get( 923 __in efx_nic_t *enp, 924 __out efx_phy_media_type_t *typep); 925 926 extern __checkReturn efx_rc_t 927 efx_phy_module_get_info( 928 __in efx_nic_t *enp, 929 __in uint8_t dev_addr, 930 __in uint8_t offset, 931 __in uint8_t len, 932 __out_bcount(len) uint8_t *data); 933 934 #if EFSYS_OPT_PHY_STATS 935 936 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 937 typedef enum efx_phy_stat_e { 938 EFX_PHY_STAT_OUI, 939 EFX_PHY_STAT_PMA_PMD_LINK_UP, 940 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 941 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 942 EFX_PHY_STAT_PMA_PMD_REV_A, 943 EFX_PHY_STAT_PMA_PMD_REV_B, 944 EFX_PHY_STAT_PMA_PMD_REV_C, 945 EFX_PHY_STAT_PMA_PMD_REV_D, 946 EFX_PHY_STAT_PCS_LINK_UP, 947 EFX_PHY_STAT_PCS_RX_FAULT, 948 EFX_PHY_STAT_PCS_TX_FAULT, 949 EFX_PHY_STAT_PCS_BER, 950 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 951 EFX_PHY_STAT_PHY_XS_LINK_UP, 952 EFX_PHY_STAT_PHY_XS_RX_FAULT, 953 EFX_PHY_STAT_PHY_XS_TX_FAULT, 954 EFX_PHY_STAT_PHY_XS_ALIGN, 955 EFX_PHY_STAT_PHY_XS_SYNC_A, 956 EFX_PHY_STAT_PHY_XS_SYNC_B, 957 EFX_PHY_STAT_PHY_XS_SYNC_C, 958 EFX_PHY_STAT_PHY_XS_SYNC_D, 959 EFX_PHY_STAT_AN_LINK_UP, 960 EFX_PHY_STAT_AN_MASTER, 961 EFX_PHY_STAT_AN_LOCAL_RX_OK, 962 EFX_PHY_STAT_AN_REMOTE_RX_OK, 963 EFX_PHY_STAT_CL22EXT_LINK_UP, 964 EFX_PHY_STAT_SNR_A, 965 EFX_PHY_STAT_SNR_B, 966 EFX_PHY_STAT_SNR_C, 967 EFX_PHY_STAT_SNR_D, 968 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 969 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 970 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 971 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 972 EFX_PHY_STAT_AN_COMPLETE, 973 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 974 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 975 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 976 EFX_PHY_STAT_PCS_FW_VERSION_0, 977 EFX_PHY_STAT_PCS_FW_VERSION_1, 978 EFX_PHY_STAT_PCS_FW_VERSION_2, 979 EFX_PHY_STAT_PCS_FW_VERSION_3, 980 EFX_PHY_STAT_PCS_FW_BUILD_YY, 981 EFX_PHY_STAT_PCS_FW_BUILD_MM, 982 EFX_PHY_STAT_PCS_FW_BUILD_DD, 983 EFX_PHY_STAT_PCS_OP_MODE, 984 EFX_PHY_NSTATS 985 } efx_phy_stat_t; 986 987 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 988 989 #if EFSYS_OPT_NAMES 990 991 extern const char * 992 efx_phy_stat_name( 993 __in efx_nic_t *enp, 994 __in efx_phy_stat_t stat); 995 996 #endif /* EFSYS_OPT_NAMES */ 997 998 #define EFX_PHY_STATS_SIZE 0x100 999 1000 extern __checkReturn efx_rc_t 1001 efx_phy_stats_update( 1002 __in efx_nic_t *enp, 1003 __in efsys_mem_t *esmp, 1004 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1005 1006 #endif /* EFSYS_OPT_PHY_STATS */ 1007 1008 1009 #if EFSYS_OPT_BIST 1010 1011 typedef enum efx_bist_type_e { 1012 EFX_BIST_TYPE_UNKNOWN, 1013 EFX_BIST_TYPE_PHY_NORMAL, 1014 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1015 EFX_BIST_TYPE_PHY_CABLE_LONG, 1016 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1017 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1018 EFX_BIST_TYPE_REG, /* Test the register memories */ 1019 EFX_BIST_TYPE_NTYPES, 1020 } efx_bist_type_t; 1021 1022 typedef enum efx_bist_result_e { 1023 EFX_BIST_RESULT_UNKNOWN, 1024 EFX_BIST_RESULT_RUNNING, 1025 EFX_BIST_RESULT_PASSED, 1026 EFX_BIST_RESULT_FAILED, 1027 } efx_bist_result_t; 1028 1029 typedef enum efx_phy_cable_status_e { 1030 EFX_PHY_CABLE_STATUS_OK, 1031 EFX_PHY_CABLE_STATUS_INVALID, 1032 EFX_PHY_CABLE_STATUS_OPEN, 1033 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1034 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1035 EFX_PHY_CABLE_STATUS_BUSY, 1036 } efx_phy_cable_status_t; 1037 1038 typedef enum efx_bist_value_e { 1039 EFX_BIST_PHY_CABLE_LENGTH_A, 1040 EFX_BIST_PHY_CABLE_LENGTH_B, 1041 EFX_BIST_PHY_CABLE_LENGTH_C, 1042 EFX_BIST_PHY_CABLE_LENGTH_D, 1043 EFX_BIST_PHY_CABLE_STATUS_A, 1044 EFX_BIST_PHY_CABLE_STATUS_B, 1045 EFX_BIST_PHY_CABLE_STATUS_C, 1046 EFX_BIST_PHY_CABLE_STATUS_D, 1047 EFX_BIST_FAULT_CODE, 1048 /* 1049 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1050 * response. 1051 */ 1052 EFX_BIST_MEM_TEST, 1053 EFX_BIST_MEM_ADDR, 1054 EFX_BIST_MEM_BUS, 1055 EFX_BIST_MEM_EXPECT, 1056 EFX_BIST_MEM_ACTUAL, 1057 EFX_BIST_MEM_ECC, 1058 EFX_BIST_MEM_ECC_PARITY, 1059 EFX_BIST_MEM_ECC_FATAL, 1060 EFX_BIST_NVALUES, 1061 } efx_bist_value_t; 1062 1063 extern __checkReturn efx_rc_t 1064 efx_bist_enable_offline( 1065 __in efx_nic_t *enp); 1066 1067 extern __checkReturn efx_rc_t 1068 efx_bist_start( 1069 __in efx_nic_t *enp, 1070 __in efx_bist_type_t type); 1071 1072 extern __checkReturn efx_rc_t 1073 efx_bist_poll( 1074 __in efx_nic_t *enp, 1075 __in efx_bist_type_t type, 1076 __out efx_bist_result_t *resultp, 1077 __out_opt uint32_t *value_maskp, 1078 __out_ecount_opt(count) unsigned long *valuesp, 1079 __in size_t count); 1080 1081 extern void 1082 efx_bist_stop( 1083 __in efx_nic_t *enp, 1084 __in efx_bist_type_t type); 1085 1086 #endif /* EFSYS_OPT_BIST */ 1087 1088 #define EFX_FEATURE_IPV6 0x00000001 1089 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1090 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1091 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1092 #define EFX_FEATURE_MCDI 0x00000020 1093 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1094 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1095 #define EFX_FEATURE_TURBO 0x00000100 1096 #define EFX_FEATURE_MCDI_DMA 0x00000200 1097 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1098 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1099 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1100 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1101 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1102 1103 typedef enum efx_tunnel_protocol_e { 1104 EFX_TUNNEL_PROTOCOL_NONE = 0, 1105 EFX_TUNNEL_PROTOCOL_VXLAN, 1106 EFX_TUNNEL_PROTOCOL_GENEVE, 1107 EFX_TUNNEL_PROTOCOL_NVGRE, 1108 EFX_TUNNEL_NPROTOS 1109 } efx_tunnel_protocol_t; 1110 1111 typedef struct efx_nic_cfg_s { 1112 uint32_t enc_board_type; 1113 uint32_t enc_phy_type; 1114 #if EFSYS_OPT_NAMES 1115 char enc_phy_name[21]; 1116 #endif 1117 char enc_phy_revision[21]; 1118 efx_mon_type_t enc_mon_type; 1119 #if EFSYS_OPT_MON_STATS 1120 uint32_t enc_mon_stat_dma_buf_size; 1121 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1122 #endif 1123 unsigned int enc_features; 1124 uint8_t enc_mac_addr[6]; 1125 uint8_t enc_port; /* PHY port number */ 1126 uint32_t enc_intr_vec_base; 1127 uint32_t enc_intr_limit; 1128 uint32_t enc_evq_limit; 1129 uint32_t enc_txq_limit; 1130 uint32_t enc_rxq_limit; 1131 uint32_t enc_txq_max_ndescs; 1132 uint32_t enc_buftbl_limit; 1133 uint32_t enc_piobuf_limit; 1134 uint32_t enc_piobuf_size; 1135 uint32_t enc_piobuf_min_alloc_size; 1136 uint32_t enc_evq_timer_quantum_ns; 1137 uint32_t enc_evq_timer_max_us; 1138 uint32_t enc_clk_mult; 1139 uint32_t enc_rx_prefix_size; 1140 uint32_t enc_rx_buf_align_start; 1141 uint32_t enc_rx_buf_align_end; 1142 uint32_t enc_rx_scale_max_exclusive_contexts; 1143 #if EFSYS_OPT_LOOPBACK 1144 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1145 #endif /* EFSYS_OPT_LOOPBACK */ 1146 #if EFSYS_OPT_PHY_FLAGS 1147 uint32_t enc_phy_flags_mask; 1148 #endif /* EFSYS_OPT_PHY_FLAGS */ 1149 #if EFSYS_OPT_PHY_LED_CONTROL 1150 uint32_t enc_led_mask; 1151 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1152 #if EFSYS_OPT_PHY_STATS 1153 uint64_t enc_phy_stat_mask; 1154 #endif /* EFSYS_OPT_PHY_STATS */ 1155 #if EFSYS_OPT_MCDI 1156 uint8_t enc_mcdi_mdio_channel; 1157 #if EFSYS_OPT_PHY_STATS 1158 uint32_t enc_mcdi_phy_stat_mask; 1159 #endif /* EFSYS_OPT_PHY_STATS */ 1160 #if EFSYS_OPT_MON_STATS 1161 uint32_t *enc_mcdi_sensor_maskp; 1162 uint32_t enc_mcdi_sensor_mask_size; 1163 #endif /* EFSYS_OPT_MON_STATS */ 1164 #endif /* EFSYS_OPT_MCDI */ 1165 #if EFSYS_OPT_BIST 1166 uint32_t enc_bist_mask; 1167 #endif /* EFSYS_OPT_BIST */ 1168 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 1169 uint32_t enc_pf; 1170 uint32_t enc_vf; 1171 uint32_t enc_privilege_mask; 1172 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 1173 boolean_t enc_bug26807_workaround; 1174 boolean_t enc_bug35388_workaround; 1175 boolean_t enc_bug41750_workaround; 1176 boolean_t enc_bug61265_workaround; 1177 boolean_t enc_rx_batching_enabled; 1178 /* Maximum number of descriptors completed in an rx event. */ 1179 uint32_t enc_rx_batch_max; 1180 /* Number of rx descriptors the hardware requires for a push. */ 1181 uint32_t enc_rx_push_align; 1182 /* Maximum amount of data in DMA descriptor */ 1183 uint32_t enc_tx_dma_desc_size_max; 1184 /* 1185 * Boundary which DMA descriptor data must not cross or 0 if no 1186 * limitation. 1187 */ 1188 uint32_t enc_tx_dma_desc_boundary; 1189 /* 1190 * Maximum number of bytes into the packet the TCP header can start for 1191 * the hardware to apply TSO packet edits. 1192 */ 1193 uint32_t enc_tx_tso_tcp_header_offset_limit; 1194 boolean_t enc_fw_assisted_tso_enabled; 1195 boolean_t enc_fw_assisted_tso_v2_enabled; 1196 /* Number of TSO contexts on the NIC (FATSOv2) */ 1197 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1198 boolean_t enc_hw_tx_insert_vlan_enabled; 1199 /* Number of PFs on the NIC */ 1200 uint32_t enc_hw_pf_count; 1201 /* Datapath firmware vadapter/vport/vswitch support */ 1202 boolean_t enc_datapath_cap_evb; 1203 boolean_t enc_rx_disable_scatter_supported; 1204 boolean_t enc_allow_set_mac_with_installed_filters; 1205 boolean_t enc_enhanced_set_mac_supported; 1206 boolean_t enc_init_evq_v2_supported; 1207 boolean_t enc_rx_packed_stream_supported; 1208 boolean_t enc_rx_var_packed_stream_supported; 1209 boolean_t enc_pm_and_rxdp_counters; 1210 boolean_t enc_mac_stats_40g_tx_size_bins; 1211 uint32_t enc_tunnel_encapsulations_supported; 1212 /* External port identifier */ 1213 uint8_t enc_external_port; 1214 uint32_t enc_mcdi_max_payload_length; 1215 /* VPD may be per-PF or global */ 1216 boolean_t enc_vpd_is_global; 1217 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1218 uint32_t enc_required_pcie_bandwidth_mbps; 1219 uint32_t enc_max_pcie_link_gen; 1220 /* Firmware verifies integrity of NVRAM updates */ 1221 uint32_t enc_nvram_update_verify_result_supported; 1222 } efx_nic_cfg_t; 1223 1224 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1225 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1226 1227 #define EFX_PCI_FUNCTION(_encp) \ 1228 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1229 1230 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1231 1232 extern const efx_nic_cfg_t * 1233 efx_nic_cfg_get( 1234 __in efx_nic_t *enp); 1235 1236 typedef struct efx_nic_fw_info_s { 1237 /* Basic FW version information */ 1238 uint16_t enfi_mc_fw_version[4]; 1239 /* 1240 * If datapath capabilities can be detected, 1241 * additional FW information is to be shown 1242 */ 1243 boolean_t enfi_dpcpu_fw_ids_valid; 1244 /* Rx and Tx datapath CPU FW IDs */ 1245 uint16_t enfi_rx_dpcpu_fw_id; 1246 uint16_t enfi_tx_dpcpu_fw_id; 1247 } efx_nic_fw_info_t; 1248 1249 extern __checkReturn efx_rc_t 1250 efx_nic_get_fw_version( 1251 __in efx_nic_t *enp, 1252 __out efx_nic_fw_info_t *enfip); 1253 1254 /* Driver resource limits (minimum required/maximum usable). */ 1255 typedef struct efx_drv_limits_s { 1256 uint32_t edl_min_evq_count; 1257 uint32_t edl_max_evq_count; 1258 1259 uint32_t edl_min_rxq_count; 1260 uint32_t edl_max_rxq_count; 1261 1262 uint32_t edl_min_txq_count; 1263 uint32_t edl_max_txq_count; 1264 1265 /* PIO blocks (sub-allocated from piobuf) */ 1266 uint32_t edl_min_pio_alloc_size; 1267 uint32_t edl_max_pio_alloc_count; 1268 } efx_drv_limits_t; 1269 1270 extern __checkReturn efx_rc_t 1271 efx_nic_set_drv_limits( 1272 __inout efx_nic_t *enp, 1273 __in efx_drv_limits_t *edlp); 1274 1275 typedef enum efx_nic_region_e { 1276 EFX_REGION_VI, /* Memory BAR UC mapping */ 1277 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1278 } efx_nic_region_t; 1279 1280 extern __checkReturn efx_rc_t 1281 efx_nic_get_bar_region( 1282 __in efx_nic_t *enp, 1283 __in efx_nic_region_t region, 1284 __out uint32_t *offsetp, 1285 __out size_t *sizep); 1286 1287 extern __checkReturn efx_rc_t 1288 efx_nic_get_vi_pool( 1289 __in efx_nic_t *enp, 1290 __out uint32_t *evq_countp, 1291 __out uint32_t *rxq_countp, 1292 __out uint32_t *txq_countp); 1293 1294 1295 #if EFSYS_OPT_VPD 1296 1297 typedef enum efx_vpd_tag_e { 1298 EFX_VPD_ID = 0x02, 1299 EFX_VPD_END = 0x0f, 1300 EFX_VPD_RO = 0x10, 1301 EFX_VPD_RW = 0x11, 1302 } efx_vpd_tag_t; 1303 1304 typedef uint16_t efx_vpd_keyword_t; 1305 1306 typedef struct efx_vpd_value_s { 1307 efx_vpd_tag_t evv_tag; 1308 efx_vpd_keyword_t evv_keyword; 1309 uint8_t evv_length; 1310 uint8_t evv_value[0x100]; 1311 } efx_vpd_value_t; 1312 1313 1314 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1315 1316 extern __checkReturn efx_rc_t 1317 efx_vpd_init( 1318 __in efx_nic_t *enp); 1319 1320 extern __checkReturn efx_rc_t 1321 efx_vpd_size( 1322 __in efx_nic_t *enp, 1323 __out size_t *sizep); 1324 1325 extern __checkReturn efx_rc_t 1326 efx_vpd_read( 1327 __in efx_nic_t *enp, 1328 __out_bcount(size) caddr_t data, 1329 __in size_t size); 1330 1331 extern __checkReturn efx_rc_t 1332 efx_vpd_verify( 1333 __in efx_nic_t *enp, 1334 __in_bcount(size) caddr_t data, 1335 __in size_t size); 1336 1337 extern __checkReturn efx_rc_t 1338 efx_vpd_reinit( 1339 __in efx_nic_t *enp, 1340 __in_bcount(size) caddr_t data, 1341 __in size_t size); 1342 1343 extern __checkReturn efx_rc_t 1344 efx_vpd_get( 1345 __in efx_nic_t *enp, 1346 __in_bcount(size) caddr_t data, 1347 __in size_t size, 1348 __inout efx_vpd_value_t *evvp); 1349 1350 extern __checkReturn efx_rc_t 1351 efx_vpd_set( 1352 __in efx_nic_t *enp, 1353 __inout_bcount(size) caddr_t data, 1354 __in size_t size, 1355 __in efx_vpd_value_t *evvp); 1356 1357 extern __checkReturn efx_rc_t 1358 efx_vpd_next( 1359 __in efx_nic_t *enp, 1360 __inout_bcount(size) caddr_t data, 1361 __in size_t size, 1362 __out efx_vpd_value_t *evvp, 1363 __inout unsigned int *contp); 1364 1365 extern __checkReturn efx_rc_t 1366 efx_vpd_write( 1367 __in efx_nic_t *enp, 1368 __in_bcount(size) caddr_t data, 1369 __in size_t size); 1370 1371 extern void 1372 efx_vpd_fini( 1373 __in efx_nic_t *enp); 1374 1375 #endif /* EFSYS_OPT_VPD */ 1376 1377 /* NVRAM */ 1378 1379 #if EFSYS_OPT_NVRAM 1380 1381 typedef enum efx_nvram_type_e { 1382 EFX_NVRAM_INVALID = 0, 1383 EFX_NVRAM_BOOTROM, 1384 EFX_NVRAM_BOOTROM_CFG, 1385 EFX_NVRAM_MC_FIRMWARE, 1386 EFX_NVRAM_MC_GOLDEN, 1387 EFX_NVRAM_PHY, 1388 EFX_NVRAM_NULLPHY, 1389 EFX_NVRAM_FPGA, 1390 EFX_NVRAM_FCFW, 1391 EFX_NVRAM_CPLD, 1392 EFX_NVRAM_FPGA_BACKUP, 1393 EFX_NVRAM_DYNAMIC_CFG, 1394 EFX_NVRAM_LICENSE, 1395 EFX_NVRAM_UEFIROM, 1396 EFX_NVRAM_MUM_FIRMWARE, 1397 EFX_NVRAM_NTYPES, 1398 } efx_nvram_type_t; 1399 1400 extern __checkReturn efx_rc_t 1401 efx_nvram_init( 1402 __in efx_nic_t *enp); 1403 1404 #if EFSYS_OPT_DIAG 1405 1406 extern __checkReturn efx_rc_t 1407 efx_nvram_test( 1408 __in efx_nic_t *enp); 1409 1410 #endif /* EFSYS_OPT_DIAG */ 1411 1412 extern __checkReturn efx_rc_t 1413 efx_nvram_size( 1414 __in efx_nic_t *enp, 1415 __in efx_nvram_type_t type, 1416 __out size_t *sizep); 1417 1418 extern __checkReturn efx_rc_t 1419 efx_nvram_rw_start( 1420 __in efx_nic_t *enp, 1421 __in efx_nvram_type_t type, 1422 __out_opt size_t *pref_chunkp); 1423 1424 extern __checkReturn efx_rc_t 1425 efx_nvram_rw_finish( 1426 __in efx_nic_t *enp, 1427 __in efx_nvram_type_t type, 1428 __out_opt uint32_t *verify_resultp); 1429 1430 extern __checkReturn efx_rc_t 1431 efx_nvram_get_version( 1432 __in efx_nic_t *enp, 1433 __in efx_nvram_type_t type, 1434 __out uint32_t *subtypep, 1435 __out_ecount(4) uint16_t version[4]); 1436 1437 extern __checkReturn efx_rc_t 1438 efx_nvram_read_chunk( 1439 __in efx_nic_t *enp, 1440 __in efx_nvram_type_t type, 1441 __in unsigned int offset, 1442 __out_bcount(size) caddr_t data, 1443 __in size_t size); 1444 1445 extern __checkReturn efx_rc_t 1446 efx_nvram_read_backup( 1447 __in efx_nic_t *enp, 1448 __in efx_nvram_type_t type, 1449 __in unsigned int offset, 1450 __out_bcount(size) caddr_t data, 1451 __in size_t size); 1452 1453 extern __checkReturn efx_rc_t 1454 efx_nvram_set_version( 1455 __in efx_nic_t *enp, 1456 __in efx_nvram_type_t type, 1457 __in_ecount(4) uint16_t version[4]); 1458 1459 extern __checkReturn efx_rc_t 1460 efx_nvram_validate( 1461 __in efx_nic_t *enp, 1462 __in efx_nvram_type_t type, 1463 __in_bcount(partn_size) caddr_t partn_data, 1464 __in size_t partn_size); 1465 1466 extern __checkReturn efx_rc_t 1467 efx_nvram_erase( 1468 __in efx_nic_t *enp, 1469 __in efx_nvram_type_t type); 1470 1471 extern __checkReturn efx_rc_t 1472 efx_nvram_write_chunk( 1473 __in efx_nic_t *enp, 1474 __in efx_nvram_type_t type, 1475 __in unsigned int offset, 1476 __in_bcount(size) caddr_t data, 1477 __in size_t size); 1478 1479 extern void 1480 efx_nvram_fini( 1481 __in efx_nic_t *enp); 1482 1483 #endif /* EFSYS_OPT_NVRAM */ 1484 1485 #if EFSYS_OPT_BOOTCFG 1486 1487 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1488 extern __checkReturn efx_rc_t 1489 efx_bootcfg_sector_info( 1490 __in efx_nic_t *enp, 1491 __in uint32_t pf, 1492 __out_opt uint32_t *sector_countp, 1493 __out size_t *offsetp, 1494 __out size_t *max_sizep); 1495 1496 /* 1497 * Copy bootcfg sector data to a target buffer which may differ in size. 1498 * Optionally corrects format errors in source buffer. 1499 */ 1500 extern efx_rc_t 1501 efx_bootcfg_copy_sector( 1502 __in efx_nic_t *enp, 1503 __inout_bcount(sector_length) 1504 uint8_t *sector, 1505 __in size_t sector_length, 1506 __out_bcount(data_size) uint8_t *data, 1507 __in size_t data_size, 1508 __in boolean_t handle_format_errors); 1509 1510 extern efx_rc_t 1511 efx_bootcfg_read( 1512 __in efx_nic_t *enp, 1513 __out_bcount(size) uint8_t *data, 1514 __in size_t size); 1515 1516 extern efx_rc_t 1517 efx_bootcfg_write( 1518 __in efx_nic_t *enp, 1519 __in_bcount(size) uint8_t *data, 1520 __in size_t size); 1521 1522 #endif /* EFSYS_OPT_BOOTCFG */ 1523 1524 #if EFSYS_OPT_DIAG 1525 1526 typedef enum efx_pattern_type_t { 1527 EFX_PATTERN_BYTE_INCREMENT = 0, 1528 EFX_PATTERN_ALL_THE_SAME, 1529 EFX_PATTERN_BIT_ALTERNATE, 1530 EFX_PATTERN_BYTE_ALTERNATE, 1531 EFX_PATTERN_BYTE_CHANGING, 1532 EFX_PATTERN_BIT_SWEEP, 1533 EFX_PATTERN_NTYPES 1534 } efx_pattern_type_t; 1535 1536 typedef void 1537 (*efx_sram_pattern_fn_t)( 1538 __in size_t row, 1539 __in boolean_t negate, 1540 __out efx_qword_t *eqp); 1541 1542 extern __checkReturn efx_rc_t 1543 efx_sram_test( 1544 __in efx_nic_t *enp, 1545 __in efx_pattern_type_t type); 1546 1547 #endif /* EFSYS_OPT_DIAG */ 1548 1549 extern __checkReturn efx_rc_t 1550 efx_sram_buf_tbl_set( 1551 __in efx_nic_t *enp, 1552 __in uint32_t id, 1553 __in efsys_mem_t *esmp, 1554 __in size_t n); 1555 1556 extern void 1557 efx_sram_buf_tbl_clear( 1558 __in efx_nic_t *enp, 1559 __in uint32_t id, 1560 __in size_t n); 1561 1562 #define EFX_BUF_TBL_SIZE 0x20000 1563 1564 #define EFX_BUF_SIZE 4096 1565 1566 /* EV */ 1567 1568 typedef struct efx_evq_s efx_evq_t; 1569 1570 #if EFSYS_OPT_QSTATS 1571 1572 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1573 typedef enum efx_ev_qstat_e { 1574 EV_ALL, 1575 EV_RX, 1576 EV_RX_OK, 1577 EV_RX_FRM_TRUNC, 1578 EV_RX_TOBE_DISC, 1579 EV_RX_PAUSE_FRM_ERR, 1580 EV_RX_BUF_OWNER_ID_ERR, 1581 EV_RX_IPV4_HDR_CHKSUM_ERR, 1582 EV_RX_TCP_UDP_CHKSUM_ERR, 1583 EV_RX_ETH_CRC_ERR, 1584 EV_RX_IP_FRAG_ERR, 1585 EV_RX_MCAST_PKT, 1586 EV_RX_MCAST_HASH_MATCH, 1587 EV_RX_TCP_IPV4, 1588 EV_RX_TCP_IPV6, 1589 EV_RX_UDP_IPV4, 1590 EV_RX_UDP_IPV6, 1591 EV_RX_OTHER_IPV4, 1592 EV_RX_OTHER_IPV6, 1593 EV_RX_NON_IP, 1594 EV_RX_BATCH, 1595 EV_TX, 1596 EV_TX_WQ_FF_FULL, 1597 EV_TX_PKT_ERR, 1598 EV_TX_PKT_TOO_BIG, 1599 EV_TX_UNEXPECTED, 1600 EV_GLOBAL, 1601 EV_GLOBAL_MNT, 1602 EV_DRIVER, 1603 EV_DRIVER_SRM_UPD_DONE, 1604 EV_DRIVER_TX_DESCQ_FLS_DONE, 1605 EV_DRIVER_RX_DESCQ_FLS_DONE, 1606 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1607 EV_DRIVER_RX_DSC_ERROR, 1608 EV_DRIVER_TX_DSC_ERROR, 1609 EV_DRV_GEN, 1610 EV_MCDI_RESPONSE, 1611 EV_NQSTATS 1612 } efx_ev_qstat_t; 1613 1614 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1615 1616 #endif /* EFSYS_OPT_QSTATS */ 1617 1618 extern __checkReturn efx_rc_t 1619 efx_ev_init( 1620 __in efx_nic_t *enp); 1621 1622 extern void 1623 efx_ev_fini( 1624 __in efx_nic_t *enp); 1625 1626 #define EFX_EVQ_MAXNEVS 32768 1627 #define EFX_EVQ_MINNEVS 512 1628 1629 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1630 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1631 1632 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 1633 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 1634 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 1635 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 1636 1637 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 1638 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 1639 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 1640 1641 extern __checkReturn efx_rc_t 1642 efx_ev_qcreate( 1643 __in efx_nic_t *enp, 1644 __in unsigned int index, 1645 __in efsys_mem_t *esmp, 1646 __in size_t ndescs, 1647 __in uint32_t id, 1648 __in uint32_t us, 1649 __in uint32_t flags, 1650 __deref_out efx_evq_t **eepp); 1651 1652 extern void 1653 efx_ev_qpost( 1654 __in efx_evq_t *eep, 1655 __in uint16_t data); 1656 1657 typedef __checkReturn boolean_t 1658 (*efx_initialized_ev_t)( 1659 __in_opt void *arg); 1660 1661 #define EFX_PKT_UNICAST 0x0004 1662 #define EFX_PKT_START 0x0008 1663 1664 #define EFX_PKT_VLAN_TAGGED 0x0010 1665 #define EFX_CKSUM_TCPUDP 0x0020 1666 #define EFX_CKSUM_IPV4 0x0040 1667 #define EFX_PKT_CONT 0x0080 1668 1669 #define EFX_CHECK_VLAN 0x0100 1670 #define EFX_PKT_TCP 0x0200 1671 #define EFX_PKT_UDP 0x0400 1672 #define EFX_PKT_IPV4 0x0800 1673 1674 #define EFX_PKT_IPV6 0x1000 1675 #define EFX_PKT_PREFIX_LEN 0x2000 1676 #define EFX_ADDR_MISMATCH 0x4000 1677 #define EFX_DISCARD 0x8000 1678 1679 /* 1680 * The following flags are used only for packed stream 1681 * mode. The values for the flags are reused to fit into 16 bit, 1682 * since EFX_PKT_START and EFX_PKT_CONT are never used in 1683 * packed stream mode 1684 */ 1685 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 1686 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 1687 1688 1689 #define EFX_EV_RX_NLABELS 32 1690 #define EFX_EV_TX_NLABELS 32 1691 1692 typedef __checkReturn boolean_t 1693 (*efx_rx_ev_t)( 1694 __in_opt void *arg, 1695 __in uint32_t label, 1696 __in uint32_t id, 1697 __in uint32_t size, 1698 __in uint16_t flags); 1699 1700 #if EFSYS_OPT_RX_PACKED_STREAM 1701 1702 /* 1703 * Packed stream mode is documented in SF-112241-TC. 1704 * The general idea is that, instead of putting each incoming 1705 * packet into a separate buffer which is specified in a RX 1706 * descriptor, a large buffer is provided to the hardware and 1707 * packets are put there in a continuous stream. 1708 * The main advantage of such an approach is that RX queue refilling 1709 * happens much less frequently. 1710 */ 1711 1712 typedef __checkReturn boolean_t 1713 (*efx_rx_ps_ev_t)( 1714 __in_opt void *arg, 1715 __in uint32_t label, 1716 __in uint32_t id, 1717 __in uint32_t pkt_count, 1718 __in uint16_t flags); 1719 1720 #endif 1721 1722 typedef __checkReturn boolean_t 1723 (*efx_tx_ev_t)( 1724 __in_opt void *arg, 1725 __in uint32_t label, 1726 __in uint32_t id); 1727 1728 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1729 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1730 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1731 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1732 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1733 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1734 #define EFX_EXCEPTION_RX_ERROR 0x00000007 1735 #define EFX_EXCEPTION_TX_ERROR 0x00000008 1736 #define EFX_EXCEPTION_EV_ERROR 0x00000009 1737 1738 typedef __checkReturn boolean_t 1739 (*efx_exception_ev_t)( 1740 __in_opt void *arg, 1741 __in uint32_t label, 1742 __in uint32_t data); 1743 1744 typedef __checkReturn boolean_t 1745 (*efx_rxq_flush_done_ev_t)( 1746 __in_opt void *arg, 1747 __in uint32_t rxq_index); 1748 1749 typedef __checkReturn boolean_t 1750 (*efx_rxq_flush_failed_ev_t)( 1751 __in_opt void *arg, 1752 __in uint32_t rxq_index); 1753 1754 typedef __checkReturn boolean_t 1755 (*efx_txq_flush_done_ev_t)( 1756 __in_opt void *arg, 1757 __in uint32_t txq_index); 1758 1759 typedef __checkReturn boolean_t 1760 (*efx_software_ev_t)( 1761 __in_opt void *arg, 1762 __in uint16_t magic); 1763 1764 typedef __checkReturn boolean_t 1765 (*efx_sram_ev_t)( 1766 __in_opt void *arg, 1767 __in uint32_t code); 1768 1769 #define EFX_SRAM_CLEAR 0 1770 #define EFX_SRAM_UPDATE 1 1771 #define EFX_SRAM_ILLEGAL_CLEAR 2 1772 1773 typedef __checkReturn boolean_t 1774 (*efx_wake_up_ev_t)( 1775 __in_opt void *arg, 1776 __in uint32_t label); 1777 1778 typedef __checkReturn boolean_t 1779 (*efx_timer_ev_t)( 1780 __in_opt void *arg, 1781 __in uint32_t label); 1782 1783 typedef __checkReturn boolean_t 1784 (*efx_link_change_ev_t)( 1785 __in_opt void *arg, 1786 __in efx_link_mode_t link_mode); 1787 1788 #if EFSYS_OPT_MON_STATS 1789 1790 typedef __checkReturn boolean_t 1791 (*efx_monitor_ev_t)( 1792 __in_opt void *arg, 1793 __in efx_mon_stat_t id, 1794 __in efx_mon_stat_value_t value); 1795 1796 #endif /* EFSYS_OPT_MON_STATS */ 1797 1798 #if EFSYS_OPT_MAC_STATS 1799 1800 typedef __checkReturn boolean_t 1801 (*efx_mac_stats_ev_t)( 1802 __in_opt void *arg, 1803 __in uint32_t generation); 1804 1805 #endif /* EFSYS_OPT_MAC_STATS */ 1806 1807 typedef struct efx_ev_callbacks_s { 1808 efx_initialized_ev_t eec_initialized; 1809 efx_rx_ev_t eec_rx; 1810 #if EFSYS_OPT_RX_PACKED_STREAM 1811 efx_rx_ps_ev_t eec_rx_ps; 1812 #endif 1813 efx_tx_ev_t eec_tx; 1814 efx_exception_ev_t eec_exception; 1815 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1816 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1817 efx_txq_flush_done_ev_t eec_txq_flush_done; 1818 efx_software_ev_t eec_software; 1819 efx_sram_ev_t eec_sram; 1820 efx_wake_up_ev_t eec_wake_up; 1821 efx_timer_ev_t eec_timer; 1822 efx_link_change_ev_t eec_link_change; 1823 #if EFSYS_OPT_MON_STATS 1824 efx_monitor_ev_t eec_monitor; 1825 #endif /* EFSYS_OPT_MON_STATS */ 1826 #if EFSYS_OPT_MAC_STATS 1827 efx_mac_stats_ev_t eec_mac_stats; 1828 #endif /* EFSYS_OPT_MAC_STATS */ 1829 } efx_ev_callbacks_t; 1830 1831 extern __checkReturn boolean_t 1832 efx_ev_qpending( 1833 __in efx_evq_t *eep, 1834 __in unsigned int count); 1835 1836 #if EFSYS_OPT_EV_PREFETCH 1837 1838 extern void 1839 efx_ev_qprefetch( 1840 __in efx_evq_t *eep, 1841 __in unsigned int count); 1842 1843 #endif /* EFSYS_OPT_EV_PREFETCH */ 1844 1845 extern void 1846 efx_ev_qpoll( 1847 __in efx_evq_t *eep, 1848 __inout unsigned int *countp, 1849 __in const efx_ev_callbacks_t *eecp, 1850 __in_opt void *arg); 1851 1852 extern __checkReturn efx_rc_t 1853 efx_ev_usecs_to_ticks( 1854 __in efx_nic_t *enp, 1855 __in unsigned int usecs, 1856 __out unsigned int *ticksp); 1857 1858 extern __checkReturn efx_rc_t 1859 efx_ev_qmoderate( 1860 __in efx_evq_t *eep, 1861 __in unsigned int us); 1862 1863 extern __checkReturn efx_rc_t 1864 efx_ev_qprime( 1865 __in efx_evq_t *eep, 1866 __in unsigned int count); 1867 1868 #if EFSYS_OPT_QSTATS 1869 1870 #if EFSYS_OPT_NAMES 1871 1872 extern const char * 1873 efx_ev_qstat_name( 1874 __in efx_nic_t *enp, 1875 __in unsigned int id); 1876 1877 #endif /* EFSYS_OPT_NAMES */ 1878 1879 extern void 1880 efx_ev_qstats_update( 1881 __in efx_evq_t *eep, 1882 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1883 1884 #endif /* EFSYS_OPT_QSTATS */ 1885 1886 extern void 1887 efx_ev_qdestroy( 1888 __in efx_evq_t *eep); 1889 1890 /* RX */ 1891 1892 extern __checkReturn efx_rc_t 1893 efx_rx_init( 1894 __inout efx_nic_t *enp); 1895 1896 extern void 1897 efx_rx_fini( 1898 __in efx_nic_t *enp); 1899 1900 #if EFSYS_OPT_RX_SCATTER 1901 __checkReturn efx_rc_t 1902 efx_rx_scatter_enable( 1903 __in efx_nic_t *enp, 1904 __in unsigned int buf_size); 1905 #endif /* EFSYS_OPT_RX_SCATTER */ 1906 1907 /* Handle to represent use of the default RSS context. */ 1908 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 1909 1910 #if EFSYS_OPT_RX_SCALE 1911 1912 typedef enum efx_rx_hash_alg_e { 1913 EFX_RX_HASHALG_LFSR = 0, 1914 EFX_RX_HASHALG_TOEPLITZ 1915 } efx_rx_hash_alg_t; 1916 1917 #define EFX_RX_HASH_IPV4 (1U << 0) 1918 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 1919 #define EFX_RX_HASH_IPV6 (1U << 2) 1920 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 1921 1922 typedef unsigned int efx_rx_hash_type_t; 1923 1924 typedef enum efx_rx_hash_support_e { 1925 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 1926 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 1927 } efx_rx_hash_support_t; 1928 1929 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 1930 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1931 #define EFX_MAXRSS 64 /* RX indirection entry range */ 1932 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1933 1934 typedef enum efx_rx_scale_context_type_e { 1935 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 1936 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 1937 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 1938 } efx_rx_scale_context_type_t; 1939 1940 extern __checkReturn efx_rc_t 1941 efx_rx_hash_default_support_get( 1942 __in efx_nic_t *enp, 1943 __out efx_rx_hash_support_t *supportp); 1944 1945 1946 extern __checkReturn efx_rc_t 1947 efx_rx_scale_default_support_get( 1948 __in efx_nic_t *enp, 1949 __out efx_rx_scale_context_type_t *typep); 1950 1951 extern __checkReturn efx_rc_t 1952 efx_rx_scale_context_alloc( 1953 __in efx_nic_t *enp, 1954 __in efx_rx_scale_context_type_t type, 1955 __in uint32_t num_queues, 1956 __out uint32_t *rss_contextp); 1957 1958 extern __checkReturn efx_rc_t 1959 efx_rx_scale_context_free( 1960 __in efx_nic_t *enp, 1961 __in uint32_t rss_context); 1962 1963 extern __checkReturn efx_rc_t 1964 efx_rx_scale_mode_set( 1965 __in efx_nic_t *enp, 1966 __in uint32_t rss_context, 1967 __in efx_rx_hash_alg_t alg, 1968 __in efx_rx_hash_type_t type, 1969 __in boolean_t insert); 1970 1971 extern __checkReturn efx_rc_t 1972 efx_rx_scale_tbl_set( 1973 __in efx_nic_t *enp, 1974 __in uint32_t rss_context, 1975 __in_ecount(n) unsigned int *table, 1976 __in size_t n); 1977 1978 extern __checkReturn efx_rc_t 1979 efx_rx_scale_key_set( 1980 __in efx_nic_t *enp, 1981 __in uint32_t rss_context, 1982 __in_ecount(n) uint8_t *key, 1983 __in size_t n); 1984 1985 extern __checkReturn uint32_t 1986 efx_pseudo_hdr_hash_get( 1987 __in efx_rxq_t *erp, 1988 __in efx_rx_hash_alg_t func, 1989 __in uint8_t *buffer); 1990 1991 #endif /* EFSYS_OPT_RX_SCALE */ 1992 1993 extern __checkReturn efx_rc_t 1994 efx_pseudo_hdr_pkt_length_get( 1995 __in efx_rxq_t *erp, 1996 __in uint8_t *buffer, 1997 __out uint16_t *pkt_lengthp); 1998 1999 #define EFX_RXQ_MAXNDESCS 4096 2000 #define EFX_RXQ_MINNDESCS 512 2001 2002 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2003 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2004 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2005 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2006 2007 typedef enum efx_rxq_type_e { 2008 EFX_RXQ_TYPE_DEFAULT, 2009 EFX_RXQ_TYPE_PACKED_STREAM, 2010 EFX_RXQ_NTYPES 2011 } efx_rxq_type_t; 2012 2013 /* 2014 * Dummy flag to be used instead of 0 to make it clear that the argument 2015 * is receive queue flags. 2016 */ 2017 #define EFX_RXQ_FLAG_NONE 0x0 2018 #define EFX_RXQ_FLAG_SCATTER 0x1 2019 /* 2020 * If tunnels are supported and Rx event can provide information about 2021 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2022 * full-feature firmware variant running), outer classes are requested by 2023 * default. However, if the driver supports tunnels, the flag allows to 2024 * request inner classes which are required to be able to interpret inner 2025 * Rx checksum offload results. 2026 */ 2027 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2028 2029 extern __checkReturn efx_rc_t 2030 efx_rx_qcreate( 2031 __in efx_nic_t *enp, 2032 __in unsigned int index, 2033 __in unsigned int label, 2034 __in efx_rxq_type_t type, 2035 __in efsys_mem_t *esmp, 2036 __in size_t ndescs, 2037 __in uint32_t id, 2038 __in unsigned int flags, 2039 __in efx_evq_t *eep, 2040 __deref_out efx_rxq_t **erpp); 2041 2042 #if EFSYS_OPT_RX_PACKED_STREAM 2043 2044 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2045 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2046 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2047 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2048 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2049 2050 extern __checkReturn efx_rc_t 2051 efx_rx_qcreate_packed_stream( 2052 __in efx_nic_t *enp, 2053 __in unsigned int index, 2054 __in unsigned int label, 2055 __in uint32_t ps_buf_size, 2056 __in efsys_mem_t *esmp, 2057 __in size_t ndescs, 2058 __in efx_evq_t *eep, 2059 __deref_out efx_rxq_t **erpp); 2060 2061 #endif 2062 2063 typedef struct efx_buffer_s { 2064 efsys_dma_addr_t eb_addr; 2065 size_t eb_size; 2066 boolean_t eb_eop; 2067 } efx_buffer_t; 2068 2069 typedef struct efx_desc_s { 2070 efx_qword_t ed_eq; 2071 } efx_desc_t; 2072 2073 extern void 2074 efx_rx_qpost( 2075 __in efx_rxq_t *erp, 2076 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 2077 __in size_t size, 2078 __in unsigned int ndescs, 2079 __in unsigned int completed, 2080 __in unsigned int added); 2081 2082 extern void 2083 efx_rx_qpush( 2084 __in efx_rxq_t *erp, 2085 __in unsigned int added, 2086 __inout unsigned int *pushedp); 2087 2088 #if EFSYS_OPT_RX_PACKED_STREAM 2089 2090 extern void 2091 efx_rx_qpush_ps_credits( 2092 __in efx_rxq_t *erp); 2093 2094 extern __checkReturn uint8_t * 2095 efx_rx_qps_packet_info( 2096 __in efx_rxq_t *erp, 2097 __in uint8_t *buffer, 2098 __in uint32_t buffer_length, 2099 __in uint32_t current_offset, 2100 __out uint16_t *lengthp, 2101 __out uint32_t *next_offsetp, 2102 __out uint32_t *timestamp); 2103 #endif 2104 2105 extern __checkReturn efx_rc_t 2106 efx_rx_qflush( 2107 __in efx_rxq_t *erp); 2108 2109 extern void 2110 efx_rx_qenable( 2111 __in efx_rxq_t *erp); 2112 2113 extern void 2114 efx_rx_qdestroy( 2115 __in efx_rxq_t *erp); 2116 2117 /* TX */ 2118 2119 typedef struct efx_txq_s efx_txq_t; 2120 2121 #if EFSYS_OPT_QSTATS 2122 2123 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2124 typedef enum efx_tx_qstat_e { 2125 TX_POST, 2126 TX_POST_PIO, 2127 TX_NQSTATS 2128 } efx_tx_qstat_t; 2129 2130 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2131 2132 #endif /* EFSYS_OPT_QSTATS */ 2133 2134 extern __checkReturn efx_rc_t 2135 efx_tx_init( 2136 __in efx_nic_t *enp); 2137 2138 extern void 2139 efx_tx_fini( 2140 __in efx_nic_t *enp); 2141 2142 #define EFX_TXQ_MINNDESCS 512 2143 2144 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2145 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2146 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2147 2148 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2149 2150 #define EFX_TXQ_CKSUM_IPV4 0x0001 2151 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 2152 #define EFX_TXQ_FATSOV2 0x0004 2153 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2154 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2155 2156 extern __checkReturn efx_rc_t 2157 efx_tx_qcreate( 2158 __in efx_nic_t *enp, 2159 __in unsigned int index, 2160 __in unsigned int label, 2161 __in efsys_mem_t *esmp, 2162 __in size_t n, 2163 __in uint32_t id, 2164 __in uint16_t flags, 2165 __in efx_evq_t *eep, 2166 __deref_out efx_txq_t **etpp, 2167 __out unsigned int *addedp); 2168 2169 extern __checkReturn efx_rc_t 2170 efx_tx_qpost( 2171 __in efx_txq_t *etp, 2172 __in_ecount(ndescs) efx_buffer_t *eb, 2173 __in unsigned int ndescs, 2174 __in unsigned int completed, 2175 __inout unsigned int *addedp); 2176 2177 extern __checkReturn efx_rc_t 2178 efx_tx_qpace( 2179 __in efx_txq_t *etp, 2180 __in unsigned int ns); 2181 2182 extern void 2183 efx_tx_qpush( 2184 __in efx_txq_t *etp, 2185 __in unsigned int added, 2186 __in unsigned int pushed); 2187 2188 extern __checkReturn efx_rc_t 2189 efx_tx_qflush( 2190 __in efx_txq_t *etp); 2191 2192 extern void 2193 efx_tx_qenable( 2194 __in efx_txq_t *etp); 2195 2196 extern __checkReturn efx_rc_t 2197 efx_tx_qpio_enable( 2198 __in efx_txq_t *etp); 2199 2200 extern void 2201 efx_tx_qpio_disable( 2202 __in efx_txq_t *etp); 2203 2204 extern __checkReturn efx_rc_t 2205 efx_tx_qpio_write( 2206 __in efx_txq_t *etp, 2207 __in_ecount(buf_length) uint8_t *buffer, 2208 __in size_t buf_length, 2209 __in size_t pio_buf_offset); 2210 2211 extern __checkReturn efx_rc_t 2212 efx_tx_qpio_post( 2213 __in efx_txq_t *etp, 2214 __in size_t pkt_length, 2215 __in unsigned int completed, 2216 __inout unsigned int *addedp); 2217 2218 extern __checkReturn efx_rc_t 2219 efx_tx_qdesc_post( 2220 __in efx_txq_t *etp, 2221 __in_ecount(n) efx_desc_t *ed, 2222 __in unsigned int n, 2223 __in unsigned int completed, 2224 __inout unsigned int *addedp); 2225 2226 extern void 2227 efx_tx_qdesc_dma_create( 2228 __in efx_txq_t *etp, 2229 __in efsys_dma_addr_t addr, 2230 __in size_t size, 2231 __in boolean_t eop, 2232 __out efx_desc_t *edp); 2233 2234 extern void 2235 efx_tx_qdesc_tso_create( 2236 __in efx_txq_t *etp, 2237 __in uint16_t ipv4_id, 2238 __in uint32_t tcp_seq, 2239 __in uint8_t tcp_flags, 2240 __out efx_desc_t *edp); 2241 2242 /* Number of FATSOv2 option descriptors */ 2243 #define EFX_TX_FATSOV2_OPT_NDESCS 2 2244 2245 /* Maximum number of DMA segments per TSO packet (not superframe) */ 2246 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2247 2248 extern void 2249 efx_tx_qdesc_tso2_create( 2250 __in efx_txq_t *etp, 2251 __in uint16_t ipv4_id, 2252 __in uint32_t tcp_seq, 2253 __in uint16_t tcp_mss, 2254 __out_ecount(count) efx_desc_t *edp, 2255 __in int count); 2256 2257 extern void 2258 efx_tx_qdesc_vlantci_create( 2259 __in efx_txq_t *etp, 2260 __in uint16_t tci, 2261 __out efx_desc_t *edp); 2262 2263 #if EFSYS_OPT_QSTATS 2264 2265 #if EFSYS_OPT_NAMES 2266 2267 extern const char * 2268 efx_tx_qstat_name( 2269 __in efx_nic_t *etp, 2270 __in unsigned int id); 2271 2272 #endif /* EFSYS_OPT_NAMES */ 2273 2274 extern void 2275 efx_tx_qstats_update( 2276 __in efx_txq_t *etp, 2277 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2278 2279 #endif /* EFSYS_OPT_QSTATS */ 2280 2281 extern void 2282 efx_tx_qdestroy( 2283 __in efx_txq_t *etp); 2284 2285 2286 /* FILTER */ 2287 2288 #if EFSYS_OPT_FILTER 2289 2290 #define EFX_ETHER_TYPE_IPV4 0x0800 2291 #define EFX_ETHER_TYPE_IPV6 0x86DD 2292 2293 #define EFX_IPPROTO_TCP 6 2294 #define EFX_IPPROTO_UDP 17 2295 #define EFX_IPPROTO_GRE 47 2296 2297 /* Use RSS to spread across multiple queues */ 2298 #define EFX_FILTER_FLAG_RX_RSS 0x01 2299 /* Enable RX scatter */ 2300 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 2301 /* 2302 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2303 * May only be set by the filter implementation for each type. 2304 * A removal request will restore the automatic filter in its place. 2305 */ 2306 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2307 /* Filter is for RX */ 2308 #define EFX_FILTER_FLAG_RX 0x08 2309 /* Filter is for TX */ 2310 #define EFX_FILTER_FLAG_TX 0x10 2311 2312 typedef uint8_t efx_filter_flags_t; 2313 2314 /* 2315 * Flags which specify the fields to match on. The values are the same as in the 2316 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 2317 */ 2318 2319 /* Match by remote IP host address */ 2320 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 2321 /* Match by local IP host address */ 2322 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 2323 /* Match by remote MAC address */ 2324 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 2325 /* Match by remote TCP/UDP port */ 2326 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 2327 /* Match by remote TCP/UDP port */ 2328 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 2329 /* Match by local TCP/UDP port */ 2330 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 2331 /* Match by Ether-type */ 2332 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 2333 /* Match by inner VLAN ID */ 2334 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 2335 /* Match by outer VLAN ID */ 2336 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 2337 /* Match by IP transport protocol */ 2338 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 2339 /* For encapsulated packets, match all multicast inner frames */ 2340 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 2341 /* For encapsulated packets, match all unicast inner frames */ 2342 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 2343 /* Match otherwise-unmatched multicast and broadcast packets */ 2344 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 2345 /* Match otherwise-unmatched unicast packets */ 2346 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 2347 2348 typedef uint32_t efx_filter_match_flags_t; 2349 2350 typedef enum efx_filter_priority_s { 2351 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2352 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2353 * address list or hardware 2354 * requirements. This may only be used 2355 * by the filter implementation for 2356 * each NIC type. */ 2357 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2358 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2359 * client (e.g. SR-IOV, HyperV VMQ etc.) 2360 */ 2361 } efx_filter_priority_t; 2362 2363 /* 2364 * FIXME: All these fields are assumed to be in little-endian byte order. 2365 * It may be better for some to be big-endian. See bug42804. 2366 */ 2367 2368 typedef struct efx_filter_spec_s { 2369 efx_filter_match_flags_t efs_match_flags; 2370 uint8_t efs_priority; 2371 efx_filter_flags_t efs_flags; 2372 uint16_t efs_dmaq_id; 2373 uint32_t efs_rss_context; 2374 uint16_t efs_outer_vid; 2375 uint16_t efs_inner_vid; 2376 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2377 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2378 uint16_t efs_ether_type; 2379 uint8_t efs_ip_proto; 2380 efx_tunnel_protocol_t efs_encap_type; 2381 uint16_t efs_loc_port; 2382 uint16_t efs_rem_port; 2383 efx_oword_t efs_rem_host; 2384 efx_oword_t efs_loc_host; 2385 } efx_filter_spec_t; 2386 2387 2388 /* Default values for use in filter specifications */ 2389 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2390 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2391 2392 extern __checkReturn efx_rc_t 2393 efx_filter_init( 2394 __in efx_nic_t *enp); 2395 2396 extern void 2397 efx_filter_fini( 2398 __in efx_nic_t *enp); 2399 2400 extern __checkReturn efx_rc_t 2401 efx_filter_insert( 2402 __in efx_nic_t *enp, 2403 __inout efx_filter_spec_t *spec); 2404 2405 extern __checkReturn efx_rc_t 2406 efx_filter_remove( 2407 __in efx_nic_t *enp, 2408 __inout efx_filter_spec_t *spec); 2409 2410 extern __checkReturn efx_rc_t 2411 efx_filter_restore( 2412 __in efx_nic_t *enp); 2413 2414 extern __checkReturn efx_rc_t 2415 efx_filter_supported_filters( 2416 __in efx_nic_t *enp, 2417 __out_ecount(buffer_length) uint32_t *buffer, 2418 __in size_t buffer_length, 2419 __out size_t *list_lengthp); 2420 2421 extern void 2422 efx_filter_spec_init_rx( 2423 __out efx_filter_spec_t *spec, 2424 __in efx_filter_priority_t priority, 2425 __in efx_filter_flags_t flags, 2426 __in efx_rxq_t *erp); 2427 2428 extern void 2429 efx_filter_spec_init_tx( 2430 __out efx_filter_spec_t *spec, 2431 __in efx_txq_t *etp); 2432 2433 extern __checkReturn efx_rc_t 2434 efx_filter_spec_set_ipv4_local( 2435 __inout efx_filter_spec_t *spec, 2436 __in uint8_t proto, 2437 __in uint32_t host, 2438 __in uint16_t port); 2439 2440 extern __checkReturn efx_rc_t 2441 efx_filter_spec_set_ipv4_full( 2442 __inout efx_filter_spec_t *spec, 2443 __in uint8_t proto, 2444 __in uint32_t lhost, 2445 __in uint16_t lport, 2446 __in uint32_t rhost, 2447 __in uint16_t rport); 2448 2449 extern __checkReturn efx_rc_t 2450 efx_filter_spec_set_eth_local( 2451 __inout efx_filter_spec_t *spec, 2452 __in uint16_t vid, 2453 __in const uint8_t *addr); 2454 2455 extern void 2456 efx_filter_spec_set_ether_type( 2457 __inout efx_filter_spec_t *spec, 2458 __in uint16_t ether_type); 2459 2460 extern __checkReturn efx_rc_t 2461 efx_filter_spec_set_uc_def( 2462 __inout efx_filter_spec_t *spec); 2463 2464 extern __checkReturn efx_rc_t 2465 efx_filter_spec_set_mc_def( 2466 __inout efx_filter_spec_t *spec); 2467 2468 typedef enum efx_filter_inner_frame_match_e { 2469 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 2470 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 2471 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 2472 } efx_filter_inner_frame_match_t; 2473 2474 extern __checkReturn efx_rc_t 2475 efx_filter_spec_set_encap_type( 2476 __inout efx_filter_spec_t *spec, 2477 __in efx_tunnel_protocol_t encap_type, 2478 __in efx_filter_inner_frame_match_t inner_frame_match); 2479 2480 #if EFSYS_OPT_RX_SCALE 2481 extern __checkReturn efx_rc_t 2482 efx_filter_spec_set_rss_context( 2483 __inout efx_filter_spec_t *spec, 2484 __in uint32_t rss_context); 2485 #endif 2486 #endif /* EFSYS_OPT_FILTER */ 2487 2488 /* HASH */ 2489 2490 extern __checkReturn uint32_t 2491 efx_hash_dwords( 2492 __in_ecount(count) uint32_t const *input, 2493 __in size_t count, 2494 __in uint32_t init); 2495 2496 extern __checkReturn uint32_t 2497 efx_hash_bytes( 2498 __in_ecount(length) uint8_t const *input, 2499 __in size_t length, 2500 __in uint32_t init); 2501 2502 #if EFSYS_OPT_LICENSING 2503 2504 /* LICENSING */ 2505 2506 typedef struct efx_key_stats_s { 2507 uint32_t eks_valid; 2508 uint32_t eks_invalid; 2509 uint32_t eks_blacklisted; 2510 uint32_t eks_unverifiable; 2511 uint32_t eks_wrong_node; 2512 uint32_t eks_licensed_apps_lo; 2513 uint32_t eks_licensed_apps_hi; 2514 uint32_t eks_licensed_features_lo; 2515 uint32_t eks_licensed_features_hi; 2516 } efx_key_stats_t; 2517 2518 extern __checkReturn efx_rc_t 2519 efx_lic_init( 2520 __in efx_nic_t *enp); 2521 2522 extern void 2523 efx_lic_fini( 2524 __in efx_nic_t *enp); 2525 2526 extern __checkReturn boolean_t 2527 efx_lic_check_support( 2528 __in efx_nic_t *enp); 2529 2530 extern __checkReturn efx_rc_t 2531 efx_lic_update_licenses( 2532 __in efx_nic_t *enp); 2533 2534 extern __checkReturn efx_rc_t 2535 efx_lic_get_key_stats( 2536 __in efx_nic_t *enp, 2537 __out efx_key_stats_t *ksp); 2538 2539 extern __checkReturn efx_rc_t 2540 efx_lic_app_state( 2541 __in efx_nic_t *enp, 2542 __in uint64_t app_id, 2543 __out boolean_t *licensedp); 2544 2545 extern __checkReturn efx_rc_t 2546 efx_lic_get_id( 2547 __in efx_nic_t *enp, 2548 __in size_t buffer_size, 2549 __out uint32_t *typep, 2550 __out size_t *lengthp, 2551 __out_opt uint8_t *bufferp); 2552 2553 2554 extern __checkReturn efx_rc_t 2555 efx_lic_find_start( 2556 __in efx_nic_t *enp, 2557 __in_bcount(buffer_size) 2558 caddr_t bufferp, 2559 __in size_t buffer_size, 2560 __out uint32_t *startp); 2561 2562 extern __checkReturn efx_rc_t 2563 efx_lic_find_end( 2564 __in efx_nic_t *enp, 2565 __in_bcount(buffer_size) 2566 caddr_t bufferp, 2567 __in size_t buffer_size, 2568 __in uint32_t offset, 2569 __out uint32_t *endp); 2570 2571 extern __checkReturn __success(return != B_FALSE) boolean_t 2572 efx_lic_find_key( 2573 __in efx_nic_t *enp, 2574 __in_bcount(buffer_size) 2575 caddr_t bufferp, 2576 __in size_t buffer_size, 2577 __in uint32_t offset, 2578 __out uint32_t *startp, 2579 __out uint32_t *lengthp); 2580 2581 extern __checkReturn __success(return != B_FALSE) boolean_t 2582 efx_lic_validate_key( 2583 __in efx_nic_t *enp, 2584 __in_bcount(length) caddr_t keyp, 2585 __in uint32_t length); 2586 2587 extern __checkReturn efx_rc_t 2588 efx_lic_read_key( 2589 __in efx_nic_t *enp, 2590 __in_bcount(buffer_size) 2591 caddr_t bufferp, 2592 __in size_t buffer_size, 2593 __in uint32_t offset, 2594 __in uint32_t length, 2595 __out_bcount_part(key_max_size, *lengthp) 2596 caddr_t keyp, 2597 __in size_t key_max_size, 2598 __out uint32_t *lengthp); 2599 2600 extern __checkReturn efx_rc_t 2601 efx_lic_write_key( 2602 __in efx_nic_t *enp, 2603 __in_bcount(buffer_size) 2604 caddr_t bufferp, 2605 __in size_t buffer_size, 2606 __in uint32_t offset, 2607 __in_bcount(length) caddr_t keyp, 2608 __in uint32_t length, 2609 __out uint32_t *lengthp); 2610 2611 __checkReturn efx_rc_t 2612 efx_lic_delete_key( 2613 __in efx_nic_t *enp, 2614 __in_bcount(buffer_size) 2615 caddr_t bufferp, 2616 __in size_t buffer_size, 2617 __in uint32_t offset, 2618 __in uint32_t length, 2619 __in uint32_t end, 2620 __out uint32_t *deltap); 2621 2622 extern __checkReturn efx_rc_t 2623 efx_lic_create_partition( 2624 __in efx_nic_t *enp, 2625 __in_bcount(buffer_size) 2626 caddr_t bufferp, 2627 __in size_t buffer_size); 2628 2629 extern __checkReturn efx_rc_t 2630 efx_lic_finish_partition( 2631 __in efx_nic_t *enp, 2632 __in_bcount(buffer_size) 2633 caddr_t bufferp, 2634 __in size_t buffer_size); 2635 2636 #endif /* EFSYS_OPT_LICENSING */ 2637 2638 2639 2640 #ifdef __cplusplus 2641 } 2642 #endif 2643 2644 #endif /* _SYS_EFX_H */ 2645