xref: /freebsd/sys/dev/sfxge/common/ef10_tx.c (revision 8f87df16d414c7b09739ba95030e1e5650207b73)
1 /*-
2  * Copyright (c) 2012-2016 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include "efx.h"
35 #include "efx_impl.h"
36 
37 
38 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
39 
40 #if EFSYS_OPT_QSTATS
41 #define	EFX_TX_QSTAT_INCR(_etp, _stat)					\
42 	do {								\
43 		(_etp)->et_stat[_stat]++;				\
44 	_NOTE(CONSTANTCONDITION)					\
45 	} while (B_FALSE)
46 #else
47 #define	EFX_TX_QSTAT_INCR(_etp, _stat)
48 #endif
49 
50 static	__checkReturn	efx_rc_t
51 efx_mcdi_init_txq(
52 	__in		efx_nic_t *enp,
53 	__in		uint32_t size,
54 	__in		uint32_t target_evq,
55 	__in		uint32_t label,
56 	__in		uint32_t instance,
57 	__in		uint16_t flags,
58 	__in		efsys_mem_t *esmp)
59 {
60 	efx_mcdi_req_t req;
61 	uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
62 			    MC_CMD_INIT_TXQ_OUT_LEN)];
63 	efx_qword_t *dma_addr;
64 	uint64_t addr;
65 	int npages;
66 	int i;
67 	efx_rc_t rc;
68 
69 	EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
70 	    EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg)));
71 
72 	npages = EFX_TXQ_NBUFS(size);
73 	if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
74 		rc = EINVAL;
75 		goto fail1;
76 	}
77 
78 	(void) memset(payload, 0, sizeof (payload));
79 	req.emr_cmd = MC_CMD_INIT_TXQ;
80 	req.emr_in_buf = payload;
81 	req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
82 	req.emr_out_buf = payload;
83 	req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
84 
85 	MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
86 	MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
87 	MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
88 	MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
89 
90 	MCDI_IN_POPULATE_DWORD_7(req, INIT_TXQ_IN_FLAGS,
91 	    INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
92 	    INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
93 	    (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
94 	    INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
95 	    (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
96 	    INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
97 	    INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
98 	    INIT_TXQ_IN_CRC_MODE, 0,
99 	    INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
100 
101 	MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
102 	MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
103 
104 	dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
105 	addr = EFSYS_MEM_ADDR(esmp);
106 
107 	for (i = 0; i < npages; i++) {
108 		EFX_POPULATE_QWORD_2(*dma_addr,
109 		    EFX_DWORD_1, (uint32_t)(addr >> 32),
110 		    EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
111 
112 		dma_addr++;
113 		addr += EFX_BUF_SIZE;
114 	}
115 
116 	efx_mcdi_execute(enp, &req);
117 
118 	if (req.emr_rc != 0) {
119 		rc = req.emr_rc;
120 		goto fail2;
121 	}
122 
123 	return (0);
124 
125 fail2:
126 	EFSYS_PROBE(fail2);
127 fail1:
128 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
129 
130 	return (rc);
131 }
132 
133 static	__checkReturn	efx_rc_t
134 efx_mcdi_fini_txq(
135 	__in		efx_nic_t *enp,
136 	__in		uint32_t instance)
137 {
138 	efx_mcdi_req_t req;
139 	uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
140 			    MC_CMD_FINI_TXQ_OUT_LEN)];
141 	efx_rc_t rc;
142 
143 	(void) memset(payload, 0, sizeof (payload));
144 	req.emr_cmd = MC_CMD_FINI_TXQ;
145 	req.emr_in_buf = payload;
146 	req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
147 	req.emr_out_buf = payload;
148 	req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
149 
150 	MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
151 
152 	efx_mcdi_execute_quiet(enp, &req);
153 
154 	if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) {
155 		rc = req.emr_rc;
156 		goto fail1;
157 	}
158 
159 	return (0);
160 
161 fail1:
162 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
163 
164 	return (rc);
165 }
166 
167 	__checkReturn	efx_rc_t
168 ef10_tx_init(
169 	__in		efx_nic_t *enp)
170 {
171 	_NOTE(ARGUNUSED(enp))
172 	return (0);
173 }
174 
175 			void
176 ef10_tx_fini(
177 	__in		efx_nic_t *enp)
178 {
179 	_NOTE(ARGUNUSED(enp))
180 }
181 
182 	__checkReturn	efx_rc_t
183 ef10_tx_qcreate(
184 	__in		efx_nic_t *enp,
185 	__in		unsigned int index,
186 	__in		unsigned int label,
187 	__in		efsys_mem_t *esmp,
188 	__in		size_t n,
189 	__in		uint32_t id,
190 	__in		uint16_t flags,
191 	__in		efx_evq_t *eep,
192 	__in		efx_txq_t *etp,
193 	__out		unsigned int *addedp)
194 {
195 	efx_qword_t desc;
196 	efx_rc_t rc;
197 
198 	_NOTE(ARGUNUSED(id))
199 
200 	if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
201 	    esmp)) != 0)
202 		goto fail1;
203 
204 	/*
205 	 * A previous user of this TX queue may have written a descriptor to the
206 	 * TX push collector, but not pushed the doorbell (e.g. after a crash).
207 	 * The next doorbell write would then push the stale descriptor.
208 	 *
209 	 * Ensure the (per network port) TX push collector is cleared by writing
210 	 * a no-op TX option descriptor. See bug29981 for details.
211 	 */
212 	*addedp = 1;
213 	EFX_POPULATE_QWORD_4(desc,
214 	    ESF_DZ_TX_DESC_IS_OPT, 1,
215 	    ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
216 	    ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
217 	    (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
218 	    ESF_DZ_TX_OPTION_IP_CSUM,
219 	    (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
220 
221 	EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
222 	ef10_tx_qpush(etp, *addedp, 0);
223 
224 	return (0);
225 
226 fail1:
227 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
228 
229 	return (rc);
230 }
231 
232 		void
233 ef10_tx_qdestroy(
234 	__in	efx_txq_t *etp)
235 {
236 	/* FIXME */
237 	_NOTE(ARGUNUSED(etp))
238 	/* FIXME */
239 }
240 
241 	__checkReturn	efx_rc_t
242 ef10_tx_qpio_enable(
243 	__in		efx_txq_t *etp)
244 {
245 	efx_nic_t *enp = etp->et_enp;
246 	efx_piobuf_handle_t handle;
247 	efx_rc_t rc;
248 
249 	if (etp->et_pio_size != 0) {
250 		rc = EALREADY;
251 		goto fail1;
252 	}
253 
254 	/* Sub-allocate a PIO block from a piobuf */
255 	if ((rc = ef10_nic_pio_alloc(enp,
256 		    &etp->et_pio_bufnum,
257 		    &handle,
258 		    &etp->et_pio_blknum,
259 		    &etp->et_pio_offset,
260 		    &etp->et_pio_size)) != 0) {
261 		goto fail2;
262 	}
263 	EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
264 
265 	/* Link the piobuf to this TXQ */
266 	if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
267 		goto fail3;
268 	}
269 
270 	/*
271 	 * et_pio_offset is the offset of the sub-allocated block within the
272 	 * hardware PIO buffer. It is used as the buffer address in the PIO
273 	 * option descriptor.
274 	 *
275 	 * et_pio_write_offset is the offset of the sub-allocated block from the
276 	 * start of the write-combined memory mapping, and is used for writing
277 	 * data into the PIO buffer.
278 	 */
279 	etp->et_pio_write_offset =
280 	    (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
281 	    ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
282 
283 	return (0);
284 
285 fail3:
286 	EFSYS_PROBE(fail3);
287 	ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
288 	etp->et_pio_size = 0;
289 fail2:
290 	EFSYS_PROBE(fail2);
291 fail1:
292 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
293 
294 	return (rc);
295 }
296 
297 			void
298 ef10_tx_qpio_disable(
299 	__in		efx_txq_t *etp)
300 {
301 	efx_nic_t *enp = etp->et_enp;
302 
303 	if (etp->et_pio_size != 0) {
304 		/* Unlink the piobuf from this TXQ */
305 		ef10_nic_pio_unlink(enp, etp->et_index);
306 
307 		/* Free the sub-allocated PIO block */
308 		ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
309 		etp->et_pio_size = 0;
310 		etp->et_pio_write_offset = 0;
311 	}
312 }
313 
314 	__checkReturn	efx_rc_t
315 ef10_tx_qpio_write(
316 	__in			efx_txq_t *etp,
317 	__in_ecount(length)	uint8_t *buffer,
318 	__in			size_t length,
319 	__in			size_t offset)
320 {
321 	efx_nic_t *enp = etp->et_enp;
322 	efsys_bar_t *esbp = enp->en_esbp;
323 	uint32_t write_offset;
324 	uint32_t write_offset_limit;
325 	efx_qword_t *eqp;
326 	efx_rc_t rc;
327 
328 	EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
329 
330 	if (etp->et_pio_size == 0) {
331 		rc = ENOENT;
332 		goto fail1;
333 	}
334 	if (offset + length > etp->et_pio_size)	{
335 		rc = ENOSPC;
336 		goto fail2;
337 	}
338 
339 	/*
340 	 * Writes to PIO buffers must be 64 bit aligned, and multiples of
341 	 * 64 bits.
342 	 */
343 	write_offset = etp->et_pio_write_offset + offset;
344 	write_offset_limit = write_offset + length;
345 	eqp = (efx_qword_t *)buffer;
346 	while (write_offset < write_offset_limit) {
347 		EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
348 		eqp++;
349 		write_offset += sizeof (efx_qword_t);
350 	}
351 
352 	return (0);
353 
354 fail2:
355 	EFSYS_PROBE(fail2);
356 fail1:
357 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
358 
359 	return (rc);
360 }
361 
362 	__checkReturn	efx_rc_t
363 ef10_tx_qpio_post(
364 	__in			efx_txq_t *etp,
365 	__in			size_t pkt_length,
366 	__in			unsigned int completed,
367 	__inout			unsigned int *addedp)
368 {
369 	efx_qword_t pio_desc;
370 	unsigned int id;
371 	size_t offset;
372 	unsigned int added = *addedp;
373 	efx_rc_t rc;
374 
375 
376 	if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
377 		rc = ENOSPC;
378 		goto fail1;
379 	}
380 
381 	if (etp->et_pio_size == 0) {
382 		rc = ENOENT;
383 		goto fail2;
384 	}
385 
386 	id = added++ & etp->et_mask;
387 	offset = id * sizeof (efx_qword_t);
388 
389 	EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
390 		    unsigned int, id, uint32_t, etp->et_pio_offset,
391 		    size_t, pkt_length);
392 
393 	EFX_POPULATE_QWORD_5(pio_desc,
394 			ESF_DZ_TX_DESC_IS_OPT, 1,
395 			ESF_DZ_TX_OPTION_TYPE, 1,
396 			ESF_DZ_TX_PIO_CONT, 0,
397 			ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
398 			ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
399 
400 	EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
401 
402 	EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
403 
404 	*addedp = added;
405 	return (0);
406 
407 fail2:
408 	EFSYS_PROBE(fail2);
409 fail1:
410 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
411 
412 	return (rc);
413 }
414 
415 	__checkReturn	efx_rc_t
416 ef10_tx_qpost(
417 	__in		efx_txq_t *etp,
418 	__in_ecount(n)	efx_buffer_t *eb,
419 	__in		unsigned int n,
420 	__in		unsigned int completed,
421 	__inout		unsigned int *addedp)
422 {
423 	unsigned int added = *addedp;
424 	unsigned int i;
425 	efx_rc_t rc;
426 
427 	if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
428 		rc = ENOSPC;
429 		goto fail1;
430 	}
431 
432 	for (i = 0; i < n; i++) {
433 		efx_buffer_t *ebp = &eb[i];
434 		efsys_dma_addr_t addr = ebp->eb_addr;
435 		size_t size = ebp->eb_size;
436 		boolean_t eop = ebp->eb_eop;
437 		unsigned int id;
438 		size_t offset;
439 		efx_qword_t qword;
440 
441 		/* Fragments must not span 4k boundaries. */
442 		EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
443 
444 		id = added++ & etp->et_mask;
445 		offset = id * sizeof (efx_qword_t);
446 
447 		EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
448 		    unsigned int, id, efsys_dma_addr_t, addr,
449 		    size_t, size, boolean_t, eop);
450 
451 		EFX_POPULATE_QWORD_5(qword,
452 		    ESF_DZ_TX_KER_TYPE, 0,
453 		    ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
454 		    ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
455 		    ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
456 		    ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
457 
458 		EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
459 	}
460 
461 	EFX_TX_QSTAT_INCR(etp, TX_POST);
462 
463 	*addedp = added;
464 	return (0);
465 
466 fail1:
467 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
468 
469 	return (rc);
470 }
471 
472 /*
473  * This improves performance by, when possible, pushing a TX descriptor at the
474  * same time as the doorbell. The descriptor must be added to the TXQ, so that
475  * can be used if the hardware decides not to use the pushed descriptor.
476  */
477 			void
478 ef10_tx_qpush(
479 	__in		efx_txq_t *etp,
480 	__in		unsigned int added,
481 	__in		unsigned int pushed)
482 {
483 	efx_nic_t *enp = etp->et_enp;
484 	unsigned int wptr;
485 	unsigned int id;
486 	size_t offset;
487 	efx_qword_t desc;
488 	efx_oword_t oword;
489 
490 	wptr = added & etp->et_mask;
491 	id = pushed & etp->et_mask;
492 	offset = id * sizeof (efx_qword_t);
493 
494 	EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
495 
496 	/*
497 	 * SF Bug 65776: TSO option descriptors cannot be pushed if pacer bypass
498 	 * is enabled on the event queue this transmit queue is attached to.
499 	 *
500 	 * To ensure the code is safe, it is easiest to simply test the type of
501 	 * the descriptor to push, and only push it is if it not a TSO option
502 	 * descriptor.
503 	 */
504 	if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
505 	    (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
506 	    ESE_DZ_TX_OPTION_DESC_TSO)) {
507 		/* Push the descriptor and update the wptr. */
508 		EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
509 		    ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
510 		    ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
511 
512 		/* Ensure ordering of memory (descriptors) and PIO (doorbell) */
513 		EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
514 					    wptr, id);
515 		EFSYS_PIO_WRITE_BARRIER();
516 		EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
517 					    etp->et_index, &oword);
518 	} else {
519 		efx_dword_t dword;
520 
521 		/*
522 		 * Only update the wptr. This is signalled to the hardware by
523 		 * only writing one DWORD of the doorbell register.
524 		 */
525 		EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
526 		dword = oword.eo_dword[2];
527 
528 		/* Ensure ordering of memory (descriptors) and PIO (doorbell) */
529 		EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
530 					    wptr, id);
531 		EFSYS_PIO_WRITE_BARRIER();
532 		EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
533 				    etp->et_index, &dword, B_FALSE);
534 	}
535 }
536 
537 	__checkReturn	efx_rc_t
538 ef10_tx_qdesc_post(
539 	__in		efx_txq_t *etp,
540 	__in_ecount(n)	efx_desc_t *ed,
541 	__in		unsigned int n,
542 	__in		unsigned int completed,
543 	__inout		unsigned int *addedp)
544 {
545 	unsigned int added = *addedp;
546 	unsigned int i;
547 	efx_rc_t rc;
548 
549 	if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
550 		rc = ENOSPC;
551 		goto fail1;
552 	}
553 
554 	for (i = 0; i < n; i++) {
555 		efx_desc_t *edp = &ed[i];
556 		unsigned int id;
557 		size_t offset;
558 
559 		id = added++ & etp->et_mask;
560 		offset = id * sizeof (efx_desc_t);
561 
562 		EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
563 	}
564 
565 	EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
566 		    unsigned int, added, unsigned int, n);
567 
568 	EFX_TX_QSTAT_INCR(etp, TX_POST);
569 
570 	*addedp = added;
571 	return (0);
572 
573 fail1:
574 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
575 
576 	return (rc);
577 }
578 
579 	void
580 ef10_tx_qdesc_dma_create(
581 	__in	efx_txq_t *etp,
582 	__in	efsys_dma_addr_t addr,
583 	__in	size_t size,
584 	__in	boolean_t eop,
585 	__out	efx_desc_t *edp)
586 {
587 	/* Fragments must not span 4k boundaries. */
588 	EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
589 
590 	EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
591 		    efsys_dma_addr_t, addr,
592 		    size_t, size, boolean_t, eop);
593 
594 	EFX_POPULATE_QWORD_5(edp->ed_eq,
595 		    ESF_DZ_TX_KER_TYPE, 0,
596 		    ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
597 		    ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
598 		    ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
599 		    ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
600 }
601 
602 	void
603 ef10_tx_qdesc_tso_create(
604 	__in	efx_txq_t *etp,
605 	__in	uint16_t ipv4_id,
606 	__in	uint32_t tcp_seq,
607 	__in	uint8_t  tcp_flags,
608 	__out	efx_desc_t *edp)
609 {
610 	EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
611 		    uint16_t, ipv4_id, uint32_t, tcp_seq,
612 		    uint8_t, tcp_flags);
613 
614 	EFX_POPULATE_QWORD_5(edp->ed_eq,
615 			    ESF_DZ_TX_DESC_IS_OPT, 1,
616 			    ESF_DZ_TX_OPTION_TYPE,
617 			    ESE_DZ_TX_OPTION_DESC_TSO,
618 			    ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
619 			    ESF_DZ_TX_TSO_IP_ID, ipv4_id,
620 			    ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
621 }
622 
623 	void
624 ef10_tx_qdesc_tso2_create(
625 	__in			efx_txq_t *etp,
626 	__in			uint16_t ipv4_id,
627 	__in			uint32_t tcp_seq,
628 	__in			uint16_t tcp_mss,
629 	__out_ecount(count)	efx_desc_t *edp,
630 	__in			int count)
631 {
632 	EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
633 		    uint16_t, ipv4_id, uint32_t, tcp_seq,
634 		    uint16_t, tcp_mss);
635 
636 	EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
637 
638 	EFX_POPULATE_QWORD_5(edp[0].ed_eq,
639 			    ESF_DZ_TX_DESC_IS_OPT, 1,
640 			    ESF_DZ_TX_OPTION_TYPE,
641 			    ESE_DZ_TX_OPTION_DESC_TSO,
642 			    ESF_DZ_TX_TSO_OPTION_TYPE,
643 			    ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
644 			    ESF_DZ_TX_TSO_IP_ID, ipv4_id,
645 			    ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
646 	EFX_POPULATE_QWORD_4(edp[1].ed_eq,
647 			    ESF_DZ_TX_DESC_IS_OPT, 1,
648 			    ESF_DZ_TX_OPTION_TYPE,
649 			    ESE_DZ_TX_OPTION_DESC_TSO,
650 			    ESF_DZ_TX_TSO_OPTION_TYPE,
651 			    ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
652 			    ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
653 }
654 
655 	void
656 ef10_tx_qdesc_vlantci_create(
657 	__in	efx_txq_t *etp,
658 	__in	uint16_t  tci,
659 	__out	efx_desc_t *edp)
660 {
661 	EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
662 		    uint16_t, tci);
663 
664 	EFX_POPULATE_QWORD_4(edp->ed_eq,
665 			    ESF_DZ_TX_DESC_IS_OPT, 1,
666 			    ESF_DZ_TX_OPTION_TYPE,
667 			    ESE_DZ_TX_OPTION_DESC_VLAN,
668 			    ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
669 			    ESF_DZ_TX_VLAN_TAG1, tci);
670 }
671 
672 
673 	__checkReturn	efx_rc_t
674 ef10_tx_qpace(
675 	__in		efx_txq_t *etp,
676 	__in		unsigned int ns)
677 {
678 	efx_rc_t rc;
679 
680 	/* FIXME */
681 	_NOTE(ARGUNUSED(etp, ns))
682 	_NOTE(CONSTANTCONDITION)
683 	if (B_FALSE) {
684 		rc = ENOTSUP;
685 		goto fail1;
686 	}
687 	/* FIXME */
688 
689 	return (0);
690 
691 fail1:
692 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
693 
694 	return (rc);
695 }
696 
697 	__checkReturn	efx_rc_t
698 ef10_tx_qflush(
699 	__in		efx_txq_t *etp)
700 {
701 	efx_nic_t *enp = etp->et_enp;
702 	efx_rc_t rc;
703 
704 	if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
705 		goto fail1;
706 
707 	return (0);
708 
709 fail1:
710 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
711 
712 	return (rc);
713 }
714 
715 			void
716 ef10_tx_qenable(
717 	__in		efx_txq_t *etp)
718 {
719 	/* FIXME */
720 	_NOTE(ARGUNUSED(etp))
721 	/* FIXME */
722 }
723 
724 #if EFSYS_OPT_QSTATS
725 			void
726 ef10_tx_qstats_update(
727 	__in				efx_txq_t *etp,
728 	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat)
729 {
730 	unsigned int id;
731 
732 	for (id = 0; id < TX_NQSTATS; id++) {
733 		efsys_stat_t *essp = &stat[id];
734 
735 		EFSYS_STAT_INCR(essp, etp->et_stat[id]);
736 		etp->et_stat[id] = 0;
737 	}
738 }
739 
740 #endif /* EFSYS_OPT_QSTATS */
741 
742 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
743