1 /*- 2 * Copyright (c) 2012-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* These structures define the layouts for the TLV items stored in static and 34 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). 35 * 36 * They contain the same sort of information that was kept in the 37 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures 38 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for 39 * Siena. 40 * 41 * These are used directly by the MC and should also be usable directly on host 42 * systems which are little-endian and do not do strange things with structure 43 * padding. (Big-endian host systems will require some byte-swapping.) 44 * 45 * ----- 46 * 47 * Please refer to SF-108797-SW for a general overview of the TLV partition 48 * format. 49 * 50 * ----- 51 * 52 * The current tag IDs have a general structure: with the exception of the 53 * special values defined in the document, they are of the form 0xLTTTNNNN, 54 * where: 55 * 56 * - L is a location, indicating where this tag is expected to be found: 57 * 0: static configuration 58 * 1: dynamic configuration 59 * 2: firmware internal use 60 * 3: license partition 61 * 62 * - TTT is a type, which is just a unique value. The same type value 63 * might appear in both locations, indicating a relationship between 64 * the items (e.g. static and dynamic VPD below). 65 * 66 * - NNNN is an index of some form. Some item types are per-port, some 67 * are per-PF, some are per-partition-type. 68 * 69 * ----- 70 * 71 * As with the previous Siena structures, each structure here is laid out 72 * carefully: values are aligned to their natural boundary, with explicit 73 * padding fields added where necessary. (No, technically this does not 74 * absolutely guarantee portability. But, in practice, compilers are generally 75 * sensible enough not to introduce completely pointless padding, and it works 76 * well enough.) 77 */ 78 79 80 #ifndef CI_MGMT_TLV_LAYOUT_H 81 #define CI_MGMT_TLV_LAYOUT_H 82 83 84 /* ---------------------------------------------------------------------------- 85 * General structure (defined by SF-108797-SW) 86 * ---------------------------------------------------------------------------- 87 */ 88 89 90 /* The "end" tag. 91 * 92 * (Note that this is *not* followed by length or value fields: anything after 93 * the tag itself is irrelevant.) 94 */ 95 96 #define TLV_TAG_END (0xEEEEEEEE) 97 98 99 /* Other special reserved tag values. 100 */ 101 102 #define TLV_TAG_SKIP (0x00000000) 103 #define TLV_TAG_INVALID (0xFFFFFFFF) 104 105 106 /* TLV partition header. 107 * 108 * In a TLV partition, this must be the first item in the sequence, at offset 109 * 0. 110 */ 111 112 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) 113 114 struct tlv_partition_header { 115 uint32_t tag; 116 uint32_t length; 117 uint16_t type_id; 118 /* 0 indicates the default segment (always located at offset 0), while other values 119 * are for RFID-selectable presets that should immediately follow the default segment. 120 * The default segment may also have preset > 0, which means that it is a preset 121 * selected through an RFID command and copied by FW to the location at offset 0. */ 122 uint16_t preset; 123 uint32_t generation; 124 uint32_t total_length; 125 }; 126 127 128 /* TLV partition trailer. 129 * 130 * In a TLV partition, this must be the last item in the sequence, immediately 131 * preceding the TLV_TAG_END word. 132 */ 133 134 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57) 135 136 struct tlv_partition_trailer { 137 uint32_t tag; 138 uint32_t length; 139 uint32_t generation; 140 uint32_t checksum; 141 }; 142 143 144 /* Appendable TLV partition header. 145 * 146 * In an appendable TLV partition, this must be the first item in the sequence, 147 * at offset 0. (Note that, unlike the configuration partitions, there is no 148 * trailer before the TLV_TAG_END word.) 149 */ 150 151 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) 152 153 struct tlv_appendable_partition_header { 154 uint32_t tag; 155 uint32_t length; 156 uint16_t type_id; 157 uint16_t reserved; 158 }; 159 160 161 /* ---------------------------------------------------------------------------- 162 * Configuration items 163 * ---------------------------------------------------------------------------- 164 */ 165 166 167 /* NIC global capabilities. 168 */ 169 170 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) 171 172 struct tlv_global_capabilities { 173 uint32_t tag; 174 uint32_t length; 175 uint32_t flags; 176 }; 177 178 179 /* Siena-style per-port MAC address allocation. 180 * 181 * There are <count> addresses, starting at <base_address> and incrementing 182 * by adding <stride> to the low-order byte(s). 183 * 184 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool 185 * of contiguous MAC addresses for the firmware to allocate as it sees fit.) 186 */ 187 188 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) 189 190 struct tlv_port_mac { 191 uint32_t tag; 192 uint32_t length; 193 uint8_t base_address[6]; 194 uint16_t reserved; 195 uint16_t count; 196 uint16_t stride; 197 }; 198 199 200 /* Static VPD. 201 * 202 * This is the portion of VPD which is set at manufacturing time and not 203 * expected to change. It is formatted as a standard PCI VPD block. There are 204 * global and per-pf TLVs for this, the global TLV is new for Medford and is 205 * used in preference to the per-pf TLV. 206 */ 207 208 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) 209 210 struct tlv_pf_static_vpd { 211 uint32_t tag; 212 uint32_t length; 213 uint8_t bytes[]; 214 }; 215 216 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) 217 218 struct tlv_global_static_vpd { 219 uint32_t tag; 220 uint32_t length; 221 uint8_t bytes[]; 222 }; 223 224 225 /* Dynamic VPD. 226 * 227 * This is the portion of VPD which may be changed (e.g. by firmware updates). 228 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs 229 * for this, the global TLV is new for Medford and is used in preference to the 230 * per-pf TLV. 231 */ 232 233 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) 234 235 struct tlv_pf_dynamic_vpd { 236 uint32_t tag; 237 uint32_t length; 238 uint8_t bytes[]; 239 }; 240 241 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) 242 243 struct tlv_global_dynamic_vpd { 244 uint32_t tag; 245 uint32_t length; 246 uint8_t bytes[]; 247 }; 248 249 250 /* "DBI" PCI config space changes. 251 * 252 * This is a set of edits made to the default PCI config space values before 253 * the device is allowed to enumerate. There are global and per-pf TLVs for 254 * this, the global TLV is new for Medford and is used in preference to the 255 * per-pf TLV. 256 */ 257 258 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) 259 260 struct tlv_pf_dbi { 261 uint32_t tag; 262 uint32_t length; 263 struct { 264 uint16_t addr; 265 uint16_t byte_enables; 266 uint32_t value; 267 } items[]; 268 }; 269 270 271 #define TLV_TAG_GLOBAL_DBI (0x00210000) 272 273 struct tlv_global_dbi { 274 uint32_t tag; 275 uint32_t length; 276 struct { 277 uint16_t addr; 278 uint16_t byte_enables; 279 uint32_t value; 280 } items[]; 281 }; 282 283 284 /* Partition subtype codes. 285 * 286 * A subtype may optionally be stored for each type of partition present in 287 * the NVRAM. For example, this may be used to allow a generic firmware update 288 * utility to select a specific variant of firmware for a specific variant of 289 * board. 290 * 291 * The description[] field is an optional string which is returned in the 292 * MC_CMD_NVRAM_METADATA response if present. 293 */ 294 295 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) 296 297 struct tlv_partition_subtype { 298 uint32_t tag; 299 uint32_t length; 300 uint32_t subtype; 301 uint8_t description[]; 302 }; 303 304 305 /* Partition version codes. 306 * 307 * A version may optionally be stored for each type of partition present in 308 * the NVRAM. This provides a standard way of tracking the currently stored 309 * version of each of the various component images. 310 */ 311 312 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) 313 314 struct tlv_partition_version { 315 uint32_t tag; 316 uint32_t length; 317 uint16_t version_w; 318 uint16_t version_x; 319 uint16_t version_y; 320 uint16_t version_z; 321 }; 322 323 /* Global PCIe configuration */ 324 325 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) 326 327 struct tlv_pcie_config { 328 uint32_t tag; 329 uint32_t length; 330 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ 331 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 332 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 333 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 334 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ 335 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ 336 }; 337 338 /* Per-PF configuration. Note that not all these fields are necessarily useful 339 * as the apertures are constrained by the BIU settings (the one case we do 340 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can 341 * tidy things up later */ 342 343 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) 344 345 struct tlv_per_pf_pcie_config { 346 uint32_t tag; 347 uint32_t length; 348 uint8_t vfs_total; 349 uint8_t port_allocation; 350 uint16_t vectors_per_pf; 351 uint16_t vectors_per_vf; 352 uint8_t pf_bar0_aperture; 353 uint8_t pf_bar2_aperture; 354 uint8_t vf_bar0_aperture; 355 uint8_t vf_base; 356 uint16_t supp_pagesz; 357 uint16_t msix_vec_base; 358 }; 359 360 361 /* Development ONLY. This is a single TLV tag for all the gubbins 362 * that can be set through the MC command-line other than the PCIe 363 * settings. This is a temporary measure. */ 364 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ 365 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS 366 367 struct tlv_tmp_gubbins { 368 uint32_t tag; 369 uint32_t length; 370 /* Consumed by dpcpu.c */ 371 uint64_t tx0_tags; /* Bitmap */ 372 uint64_t tx1_tags; /* Bitmap */ 373 uint64_t dl_tags; /* Bitmap */ 374 uint32_t flags; 375 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ 376 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ 377 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ 378 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ 379 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ 380 /* Consumed by features.c */ 381 uint32_t dut_features; /* All 1s -> leave alone */ 382 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ 383 /* Consumed by clocks_hunt.c */ 384 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ 385 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */ 386 int8_t rx_dc_size; /* -1 -> leave alone */ 387 int8_t tx_dc_size; 388 int16_t num_q_allocs; 389 }; 390 391 /* Global port configuration 392 * 393 * This is now deprecated in favour of a platform-provided default 394 * and dynamic config override via tlv_global_port_options. 395 */ 396 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) 397 398 struct tlv_global_port_config { 399 uint32_t tag; 400 uint32_t length; 401 uint32_t ports_per_core; 402 uint32_t max_port_speed; 403 }; 404 405 406 /* Firmware options. 407 * 408 * This is intended for user-configurable selection of optional firmware 409 * features and variants. 410 * 411 * Initially, this consists only of the satellite CPU firmware variant 412 * selection, but this tag could be extended in the future (using the 413 * tag length to determine whether additional fields are present). 414 */ 415 416 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) 417 418 struct tlv_firmware_options { 419 uint32_t tag; 420 uint32_t length; 421 uint32_t firmware_variant; 422 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) 423 424 /* These are the values for overriding the driver's choice; the definitions 425 * are taken from MCDI so that they don't get out of step. Include 426 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if 427 * you need to use these constants. 428 */ 429 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED 430 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY 431 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM 432 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE 433 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ 434 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 435 }; 436 437 /* Voltage settings 438 * 439 * Intended for boards with A0 silicon where the core voltage may 440 * need tweaking. Most likely set once when the pass voltage is 441 * determined. */ 442 443 #define TLV_TAG_0V9_SETTINGS (0x000c0000) 444 445 struct tlv_0v9_settings { 446 uint32_t tag; 447 uint32_t length; 448 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ 449 #define TLV_TAG_0V9_REQUIRES_FAN (1) 450 uint16_t target_voltage; /* In millivolts */ 451 /* Since the limits are meant to be centred to the target (and must at least 452 * contain it) they need setting as well. */ 453 uint16_t warn_low; /* In millivolts */ 454 uint16_t warn_high; /* In millivolts */ 455 uint16_t panic_low; /* In millivolts */ 456 uint16_t panic_high; /* In millivolts */ 457 }; 458 459 460 /* Clock configuration */ 461 462 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ 463 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG 464 465 struct tlv_clock_config { 466 uint32_t tag; 467 uint32_t length; 468 uint16_t clk_sys; /* MHz */ 469 uint16_t clk_dpcpu; /* MHz */ 470 uint16_t clk_icore; /* MHz */ 471 uint16_t clk_pcs; /* MHz */ 472 }; 473 474 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) 475 476 struct tlv_clock_config_medford { 477 uint32_t tag; 478 uint32_t length; 479 uint16_t clk_sys; /* MHz */ 480 uint16_t clk_mc; /* MHz */ 481 uint16_t clk_rmon; /* MHz */ 482 uint16_t clk_vswitch; /* MHz */ 483 uint16_t clk_dpcpu; /* MHz */ 484 uint16_t clk_pcs; /* MHz */ 485 }; 486 487 488 /* EF10-style global pool of MAC addresses. 489 * 490 * There are <count> addresses, starting at <base_address>, which are 491 * contiguous. Firmware is responsible for allocating addresses from this 492 * pool to ports / PFs as appropriate. 493 */ 494 495 #define TLV_TAG_GLOBAL_MAC (0x000e0000) 496 497 struct tlv_global_mac { 498 uint32_t tag; 499 uint32_t length; 500 uint8_t base_address[6]; 501 uint16_t reserved1; 502 uint16_t count; 503 uint16_t reserved2; 504 }; 505 506 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ 507 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET 508 509 /* The target value for the 0v9 power rail measured on-chip at the 510 * analogue test bus */ 511 struct tlv_0v9_atb_target { 512 uint32_t tag; 513 uint32_t length; 514 uint16_t millivolts; 515 uint16_t reserved; 516 }; 517 518 /* Global PCIe configuration, second revision. This represents the visible PFs 519 * by a bitmap rather than having the number of the highest visible one. As such 520 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG 521 * can and it should be used in place of that tag in future (but compatibility with 522 * the old tag will be left in the firmware indefinitely). */ 523 524 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) 525 526 struct tlv_pcie_config_r2 { 527 uint32_t tag; 528 uint32_t length; 529 uint16_t visible_pfs; /**< Bitmap of visible PFs */ 530 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 531 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 532 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 533 }; 534 535 /* Dynamic port mode. 536 * 537 * Allows selecting alternate port configuration for platforms that support it 538 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the 539 * number of externally visible ports (and, hence, PF to port mapping), so must 540 * be done at boot time. 541 * 542 * This tag supercedes tlv_global_port_config. 543 */ 544 545 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) 546 547 struct tlv_global_port_mode { 548 uint32_t tag; 549 uint32_t length; 550 uint32_t port_mode; 551 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ 552 #define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */ 553 #define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */ 554 #define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */ 555 #define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */ 556 #define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */ 557 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */ 558 #define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */ 559 #define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */ 560 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */ 561 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2 562 }; 563 564 /* Type of the v-switch created implicitly by the firmware */ 565 566 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) 567 568 struct tlv_vswitch_type { 569 uint32_t tag; 570 uint32_t length; 571 uint32_t vswitch_type; 572 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ 573 #define TLV_VSWITCH_TYPE_NONE (0) 574 #define TLV_VSWITCH_TYPE_VLAN (1) 575 #define TLV_VSWITCH_TYPE_VEB (2) 576 #define TLV_VSWITCH_TYPE_VEPA (3) 577 #define TLV_VSWITCH_TYPE_MUX (4) 578 #define TLV_VSWITCH_TYPE_TEST (5) 579 }; 580 581 /* A VLAN tag for the v-port created implicitly by the firmware */ 582 583 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) 584 585 struct tlv_vport_vlan_tag { 586 uint32_t tag; 587 uint32_t length; 588 uint32_t vlan_tag; 589 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ 590 }; 591 592 /* Offset to be applied to the 0v9 setting, wherever it came from */ 593 594 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000) 595 596 struct tlv_0v9_atb_offset { 597 uint32_t tag; 598 uint32_t length; 599 int16_t offset_millivolts; 600 uint16_t reserved; 601 }; 602 603 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). 604 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. 605 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while 606 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: 607 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ 608 609 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ 610 611 struct tlv_privilege_mask { /* legacy structure - do not use */ 612 uint32_t tag; 613 uint32_t length; 614 uint32_t privilege_mask; 615 }; 616 617 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) 618 619 struct tlv_privilege_mask_add { 620 uint32_t tag; 621 uint32_t length; 622 uint32_t privilege_mask_add; 623 }; 624 625 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) 626 627 struct tlv_privilege_mask_rem { 628 uint32_t tag; 629 uint32_t length; 630 uint32_t privilege_mask_rem; 631 }; 632 633 /* Additional privileges given to all PFs. 634 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 635 636 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) 637 638 struct tlv_privilege_mask_add_all_pfs { 639 uint32_t tag; 640 uint32_t length; 641 uint32_t privilege_mask_add; 642 }; 643 644 /* Additional privileges given to a selected PF. 645 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 646 647 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) 648 649 struct tlv_privilege_mask_add_single_pf { 650 uint32_t tag; 651 uint32_t length; 652 uint32_t privilege_mask_add; 653 }; 654 655 /* Turning on/off the PFIOV mode. 656 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ 657 658 #define TLV_TAG_PFIOV(port) (0x10170000 + (port)) 659 660 struct tlv_pfiov { 661 uint32_t tag; 662 uint32_t length; 663 uint32_t pfiov; 664 #define TLV_PFIOV_OFF (0) /* Default */ 665 #define TLV_PFIOV_ON (1) 666 }; 667 668 /* Multicast filter chaining mode selection. 669 * 670 * When enabled, multicast packets are delivered to all recipients of all 671 * matching multicast filters, with the exception that IP multicast filters 672 * will steal traffic from MAC multicast filters on a per-function basis. 673 * (New behaviour.) 674 * 675 * When disabled, multicast packets will always be delivered only to the 676 * recipients of the highest priority matching multicast filter. 677 * (Legacy behaviour.) 678 * 679 * The DEFAULT mode (which is the same as the tag not being present at all) 680 * is equivalent to ENABLED in production builds, and DISABLED in eftest 681 * builds. 682 * 683 * This option is intended to provide run-time control over this feature 684 * while it is being stabilised and may be withdrawn at some point in the 685 * future; the new behaviour is intended to become the standard behaviour. 686 */ 687 688 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) 689 690 struct tlv_mcast_filter_chaining { 691 uint32_t tag; 692 uint32_t length; 693 uint32_t mode; 694 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) 695 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0) 696 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1) 697 }; 698 699 /* Pacer rate limit per PF */ 700 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) 701 702 struct tlv_rate_limit { 703 uint32_t tag; 704 uint32_t length; 705 uint32_t rate_mbps; 706 }; 707 708 /* OCSD Enable/Disable 709 * 710 * This setting allows OCSD to be disabled. This is a requirement for HP 711 * servers to support PCI passthrough for virtualization. 712 * 713 * The DEFAULT mode (which is the same as the tag not being present) is 714 * equivalent to ENABLED. 715 * 716 * This option is not used by the MCFW, and is entirely handled by the various 717 * drivers that support OCSD, by reading the setting before they attempt 718 * to enable OCSD. 719 * 720 * bit0: OCSD Disabled/Enabled 721 */ 722 723 #define TLV_TAG_OCSD (0x101C0000) 724 725 struct tlv_ocsd { 726 uint32_t tag; 727 uint32_t length; 728 uint32_t mode; 729 #define TLV_OCSD_DISABLED 0 730 #define TLV_OCSD_ENABLED 1 /* Default */ 731 }; 732 733 /* Descriptor cache config. 734 * 735 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also 736 * sets the total number of VIs. When the number of VIs is reduced VIs are taken 737 * away from the highest numbered port first, so a vi_count of 1024 means 1024 738 * VIs on the first port and 0 on the second (on a Torino). 739 */ 740 741 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) 742 743 struct tlv_descriptor_cache_config { 744 uint32_t tag; 745 uint32_t length; 746 uint8_t rx_desc_cache_size; 747 uint8_t tx_desc_cache_size; 748 uint16_t vi_count; 749 }; 750 #define TLV_DESC_CACHE_DEFAULT (0xff) 751 #define TLV_VI_COUNT_DEFAULT (0xffff) 752 753 /* RX event merging config (read batching). 754 * 755 * Sets the global maximum number of events for the merging bins, and the 756 * global timeout configuration for the bins. 757 */ 758 759 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) 760 761 struct tlv_rx_event_merging_config { 762 uint32_t tag; 763 uint32_t length; 764 uint32_t max_events; 765 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 766 uint32_t timeout_ns; 767 }; 768 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7 769 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740 770 771 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000) 772 struct tlv_pcie_link_settings { 773 uint32_t tag; 774 uint32_t length; 775 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */ 776 uint16_t width; /* Number of lanes */ 777 }; 778 779 /* TX event merging config. 780 * 781 * Sets the global maximum number of events for the merging bins, and the 782 * global timeout configuration for the bins, and the global timeout for 783 * empty queues. 784 */ 785 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000) 786 struct tlv_tx_event_merging_config { 787 uint32_t tag; 788 uint32_t length; 789 uint32_t max_events; 790 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 791 uint32_t timeout_ns; 792 uint32_t qempty_timeout_ns; /* Medford only */ 793 }; 794 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7 795 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 1400 796 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT 700 797 798 /* Tx vFIFO Low latency configuration 799 * 800 * To keep the desired booting behaviour for the switch, it just requires to 801 * know if the low latency mode is enabled. 802 */ 803 804 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10220000) 805 struct tlv_tx_vfifo_ull_mode { 806 uint32_t tag; 807 uint32_t length; 808 uint8_t mode; 809 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0 810 }; 811 812 #define TLV_TAG_LICENSE (0x30800000) 813 814 typedef struct tlv_license { 815 uint32_t tag; 816 uint32_t length; 817 uint8_t data[]; 818 } tlv_license_t; 819 820 /* TSA NIC IP address configuration 821 * 822 * Sets the TSA NIC IP address statically via configuration tool or dynamically 823 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop) 824 * 825 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 826 * be moved to a private partition during TSA development. It is not used in any 827 * released code yet. 828 */ 829 830 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) 831 832 #define TLV_TSAN_IP_MODE_STATIC (0) 833 #define TLV_TSAN_IP_MODE_DHCP (1) 834 #define TLV_TSAN_IP_MODE_SNOOP (2) 835 typedef struct tlv_tsan_config { 836 uint32_t tag; 837 uint32_t length; 838 uint32_t mode; 839 uint32_t ip; 840 uint32_t netmask; 841 uint32_t gateway; 842 uint32_t port; 843 uint32_t bind_retry; 844 uint32_t bind_bkout; 845 } tlv_tsan_config_t; 846 847 /* TSA Controller IP address configuration 848 * 849 * Sets the TSA Controller IP address statically via configuration tool 850 * 851 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 852 * be moved to a private partition during TSA development. It is not used in any 853 * released code yet. 854 */ 855 856 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) 857 858 #define TLV_MAX_TSACS (4) 859 typedef struct tlv_tsac_config { 860 uint32_t tag; 861 uint32_t length; 862 uint32_t num_tsacs; 863 uint32_t ip[TLV_MAX_TSACS]; 864 uint32_t port[TLV_MAX_TSACS]; 865 } tlv_tsac_config_t; 866 867 /* Binding ticket 868 * 869 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC 870 * and the TSA Controller 871 * 872 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 873 * be moved to a private partition during TSA development. It is not used in any 874 * released code yet. 875 */ 876 877 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) 878 879 typedef struct tlv_binding_ticket { 880 uint32_t tag; 881 uint32_t length; 882 uint8_t bytes[]; 883 } tlv_binding_ticket_t; 884 885 /* Solarflare private key 886 * 887 * Sets the Solareflare private key used for signing during the binding process 888 * 889 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 890 * be moved to a private partition during TSA development. It is not used in any 891 * released code yet. 892 */ 893 894 #define TLV_TAG_TMP_PIK_SF (0x10250000) 895 896 typedef struct tlv_pik_sf { 897 uint32_t tag; 898 uint32_t length; 899 uint8_t bytes[]; 900 } tlv_pik_sf_t; 901 902 /* CA root certificate 903 * 904 * Sets the CA root certificate used for TSA Controller verfication during 905 * TLS connection setup between the TSA NIC and the TSA Controller 906 * 907 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 908 * be moved to a private partition during TSA development. It is not used in any 909 * released code yet. 910 */ 911 912 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) 913 914 typedef struct tlv_ca_root_cert { 915 uint32_t tag; 916 uint32_t length; 917 uint8_t bytes[]; 918 } tlv_ca_root_cert_t; 919 920 #endif /* CI_MGMT_TLV_LAYOUT_H */ 921