1 /*- 2 * Copyright (c) 2012-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* These structures define the layouts for the TLV items stored in static and 34 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). 35 * 36 * They contain the same sort of information that was kept in the 37 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures 38 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for 39 * Siena. 40 * 41 * These are used directly by the MC and should also be usable directly on host 42 * systems which are little-endian and do not do strange things with structure 43 * padding. (Big-endian host systems will require some byte-swapping.) 44 * 45 * ----- 46 * 47 * Please refer to SF-108797-SW for a general overview of the TLV partition 48 * format. 49 * 50 * ----- 51 * 52 * The current tag IDs have a general structure: with the exception of the 53 * special values defined in the document, they are of the form 0xLTTTNNNN, 54 * where: 55 * 56 * - L is a location, indicating where this tag is expected to be found: 57 * 0 for static configuration, or 1 for dynamic configuration. Other 58 * values are reserved. 59 * 60 * - TTT is a type, which is just a unique value. The same type value 61 * might appear in both locations, indicating a relationship between 62 * the items (e.g. static and dynamic VPD below). 63 * 64 * - NNNN is an index of some form. Some item types are per-port, some 65 * are per-PF, some are per-partition-type. 66 * 67 * ----- 68 * 69 * As with the previous Siena structures, each structure here is laid out 70 * carefully: values are aligned to their natural boundary, with explicit 71 * padding fields added where necessary. (No, technically this does not 72 * absolutely guarantee portability. But, in practice, compilers are generally 73 * sensible enough not to introduce completely pointless padding, and it works 74 * well enough.) 75 */ 76 77 78 #ifndef CI_MGMT_TLV_LAYOUT_H 79 #define CI_MGMT_TLV_LAYOUT_H 80 81 82 /* ---------------------------------------------------------------------------- 83 * General structure (defined by SF-108797-SW) 84 * ---------------------------------------------------------------------------- 85 */ 86 87 88 /* The "end" tag. 89 * 90 * (Note that this is *not* followed by length or value fields: anything after 91 * the tag itself is irrelevant.) 92 */ 93 94 #define TLV_TAG_END (0xEEEEEEEE) 95 96 97 /* Other special reserved tag values. 98 */ 99 100 #define TLV_TAG_SKIP (0x00000000) 101 #define TLV_TAG_INVALID (0xFFFFFFFF) 102 103 104 /* TLV partition header. 105 * 106 * In a TLV partition, this must be the first item in the sequence, at offset 107 * 0. 108 */ 109 110 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) 111 112 struct tlv_partition_header { 113 uint32_t tag; 114 uint32_t length; 115 uint16_t type_id; 116 uint16_t reserved; 117 uint32_t generation; 118 uint32_t total_length; 119 }; 120 121 122 /* TLV partition trailer. 123 * 124 * In a TLV partition, this must be the last item in the sequence, immediately 125 * preceding the TLV_TAG_END word. 126 */ 127 128 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57) 129 130 struct tlv_partition_trailer { 131 uint32_t tag; 132 uint32_t length; 133 uint32_t generation; 134 uint32_t checksum; 135 }; 136 137 138 /* Appendable TLV partition header. 139 * 140 * In an appendable TLV partition, this must be the first item in the sequence, 141 * at offset 0. (Note that, unlike the configuration partitions, there is no 142 * trailer before the TLV_TAG_END word.) 143 */ 144 145 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) 146 147 struct tlv_appendable_partition_header { 148 uint32_t tag; 149 uint32_t length; 150 uint16_t type_id; 151 uint16_t reserved; 152 }; 153 154 155 /* ---------------------------------------------------------------------------- 156 * Configuration items 157 * ---------------------------------------------------------------------------- 158 */ 159 160 161 /* NIC global capabilities. 162 */ 163 164 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) 165 166 struct tlv_global_capabilities { 167 uint32_t tag; 168 uint32_t length; 169 uint32_t flags; 170 }; 171 172 173 /* Siena-style per-port MAC address allocation. 174 * 175 * There are <count> addresses, starting at <base_address> and incrementing 176 * by adding <stride> to the low-order byte(s). 177 * 178 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool 179 * of contiguous MAC addresses for the firmware to allocate as it sees fit.) 180 */ 181 182 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) 183 184 struct tlv_port_mac { 185 uint32_t tag; 186 uint32_t length; 187 uint8_t base_address[6]; 188 uint16_t reserved; 189 uint16_t count; 190 uint16_t stride; 191 }; 192 193 194 /* Static VPD. 195 * 196 * This is the portion of VPD which is set at manufacturing time and not 197 * expected to change. It is formatted as a standard PCI VPD block. There are 198 * global and per-pf TLVs for this, the global TLV is new for Medford and is 199 * used in preference to the per-pf TLV. 200 */ 201 202 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) 203 204 struct tlv_pf_static_vpd { 205 uint32_t tag; 206 uint32_t length; 207 uint8_t bytes[]; 208 }; 209 210 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) 211 212 struct tlv_global_static_vpd { 213 uint32_t tag; 214 uint32_t length; 215 uint8_t bytes[]; 216 }; 217 218 219 /* Dynamic VPD. 220 * 221 * This is the portion of VPD which may be changed (e.g. by firmware updates). 222 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs 223 * for this, the global TLV is new for Medford and is used in preference to the 224 * per-pf TLV. 225 */ 226 227 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) 228 229 struct tlv_pf_dynamic_vpd { 230 uint32_t tag; 231 uint32_t length; 232 uint8_t bytes[]; 233 }; 234 235 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) 236 237 struct tlv_global_dynamic_vpd { 238 uint32_t tag; 239 uint32_t length; 240 uint8_t bytes[]; 241 }; 242 243 244 /* "DBI" PCI config space changes. 245 * 246 * This is a set of edits made to the default PCI config space values before 247 * the device is allowed to enumerate. There are global and per-pf TLVs for 248 * this, the global TLV is new for Medford and is used in preference to the 249 * per-pf TLV. 250 */ 251 252 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) 253 254 struct tlv_pf_dbi { 255 uint32_t tag; 256 uint32_t length; 257 struct { 258 uint16_t addr; 259 uint16_t byte_enables; 260 uint32_t value; 261 } items[]; 262 }; 263 264 265 #define TLV_TAG_GLOBAL_DBI (0x00210000) 266 267 struct tlv_global_dbi { 268 uint32_t tag; 269 uint32_t length; 270 struct { 271 uint16_t addr; 272 uint16_t byte_enables; 273 uint32_t value; 274 } items[]; 275 }; 276 277 278 /* Partition subtype codes. 279 * 280 * A subtype may optionally be stored for each type of partition present in 281 * the NVRAM. For example, this may be used to allow a generic firmware update 282 * utility to select a specific variant of firmware for a specific variant of 283 * board. 284 * 285 * The description[] field is an optional string which is returned in the 286 * MC_CMD_NVRAM_METADATA response if present. 287 */ 288 289 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) 290 291 struct tlv_partition_subtype { 292 uint32_t tag; 293 uint32_t length; 294 uint32_t subtype; 295 uint8_t description[]; 296 }; 297 298 299 /* Partition version codes. 300 * 301 * A version may optionally be stored for each type of partition present in 302 * the NVRAM. This provides a standard way of tracking the currently stored 303 * version of each of the various component images. 304 */ 305 306 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) 307 308 struct tlv_partition_version { 309 uint32_t tag; 310 uint32_t length; 311 uint16_t version_w; 312 uint16_t version_x; 313 uint16_t version_y; 314 uint16_t version_z; 315 }; 316 317 /* Global PCIe configuration */ 318 319 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) 320 321 struct tlv_pcie_config { 322 uint32_t tag; 323 uint32_t length; 324 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ 325 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 326 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 327 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 328 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ 329 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ 330 }; 331 332 /* Per-PF configuration. Note that not all these fields are necessarily useful 333 * as the apertures are constrained by the BIU settings (the one case we do 334 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can 335 * tidy things up later */ 336 337 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) 338 339 struct tlv_per_pf_pcie_config { 340 uint32_t tag; 341 uint32_t length; 342 uint8_t vfs_total; 343 uint8_t port_allocation; 344 uint16_t vectors_per_pf; 345 uint16_t vectors_per_vf; 346 uint8_t pf_bar0_aperture; 347 uint8_t pf_bar2_aperture; 348 uint8_t vf_bar0_aperture; 349 uint8_t vf_base; 350 uint16_t supp_pagesz; 351 uint16_t msix_vec_base; 352 }; 353 354 355 /* Development ONLY. This is a single TLV tag for all the gubbins 356 * that can be set through the MC command-line other than the PCIe 357 * settings. This is a temporary measure. */ 358 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ 359 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS 360 361 struct tlv_tmp_gubbins { 362 uint32_t tag; 363 uint32_t length; 364 /* Consumed by dpcpu.c */ 365 uint64_t tx0_tags; /* Bitmap */ 366 uint64_t tx1_tags; /* Bitmap */ 367 uint64_t dl_tags; /* Bitmap */ 368 uint32_t flags; 369 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ 370 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ 371 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ 372 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ 373 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ 374 /* Consumed by features.c */ 375 uint32_t dut_features; /* All 1s -> leave alone */ 376 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ 377 /* Consumed by clocks_hunt.c */ 378 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ 379 /* Consumed by sram.c */ 380 int8_t rx_dc_size; /* -1 -> leave alone */ 381 int8_t tx_dc_size; 382 int16_t num_q_allocs; 383 }; 384 385 /* Global port configuration 386 * 387 * This is now deprecated in favour of a platform-provided default 388 * and dynamic config override via tlv_global_port_options. 389 */ 390 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) 391 392 struct tlv_global_port_config { 393 uint32_t tag; 394 uint32_t length; 395 uint32_t ports_per_core; 396 uint32_t max_port_speed; 397 }; 398 399 400 /* Firmware options. 401 * 402 * This is intended for user-configurable selection of optional firmware 403 * features and variants. 404 * 405 * Initially, this consists only of the satellite CPU firmware variant 406 * selection, but this tag could be extended in the future (using the 407 * tag length to determine whether additional fields are present). 408 */ 409 410 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) 411 412 struct tlv_firmware_options { 413 uint32_t tag; 414 uint32_t length; 415 uint32_t firmware_variant; 416 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) 417 418 /* These are the values for overriding the driver's choice; the definitions 419 * are taken from MCDI so that they don't get out of step. Include 420 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if 421 * you need to use these constants. 422 */ 423 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED 424 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY 425 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM 426 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE 427 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ 428 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 429 }; 430 431 /* Voltage settings 432 * 433 * Intended for boards with A0 silicon where the core voltage may 434 * need tweaking. Most likely set once when the pass voltage is 435 * determined. */ 436 437 #define TLV_TAG_0V9_SETTINGS (0x000c0000) 438 439 struct tlv_0v9_settings { 440 uint32_t tag; 441 uint32_t length; 442 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ 443 #define TLV_TAG_0V9_REQUIRES_FAN (1) 444 uint16_t target_voltage; /* In millivolts */ 445 /* Since the limits are meant to be centred to the target (and must at least 446 * contain it) they need setting as well. */ 447 uint16_t warn_low; /* In millivolts */ 448 uint16_t warn_high; /* In millivolts */ 449 uint16_t panic_low; /* In millivolts */ 450 uint16_t panic_high; /* In millivolts */ 451 }; 452 453 454 /* Clock configuration */ 455 456 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ 457 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG 458 459 struct tlv_clock_config { 460 uint32_t tag; 461 uint32_t length; 462 uint16_t clk_sys; /* MHz */ 463 uint16_t clk_dpcpu; /* MHz */ 464 uint16_t clk_icore; /* MHz */ 465 uint16_t clk_pcs; /* MHz */ 466 }; 467 468 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) 469 470 struct tlv_clock_config_medford { 471 uint32_t tag; 472 uint32_t length; 473 uint16_t clk_sys; /* MHz */ 474 uint16_t clk_mc; /* MHz */ 475 uint16_t clk_rmon; /* MHz */ 476 uint16_t clk_vswitch; /* MHz */ 477 uint16_t clk_dpcpu; /* MHz */ 478 uint16_t clk_pcs; /* MHz */ 479 }; 480 481 482 /* EF10-style global pool of MAC addresses. 483 * 484 * There are <count> addresses, starting at <base_address>, which are 485 * contiguous. Firmware is responsible for allocating addresses from this 486 * pool to ports / PFs as appropriate. 487 */ 488 489 #define TLV_TAG_GLOBAL_MAC (0x000e0000) 490 491 struct tlv_global_mac { 492 uint32_t tag; 493 uint32_t length; 494 uint8_t base_address[6]; 495 uint16_t reserved1; 496 uint16_t count; 497 uint16_t reserved2; 498 }; 499 500 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ 501 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET 502 503 /* The target value for the 0v9 power rail measured on-chip at the 504 * analogue test bus */ 505 struct tlv_0v9_atb_target { 506 uint32_t tag; 507 uint32_t length; 508 uint16_t millivolts; 509 uint16_t reserved; 510 }; 511 512 /* Global PCIe configuration, second revision. This represents the visible PFs 513 * by a bitmap rather than having the number of the highest visible one. As such 514 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG 515 * can and it should be used in place of that tag in future (but compatibility with 516 * the old tag will be left in the firmware indefinitely). */ 517 518 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) 519 520 struct tlv_pcie_config_r2 { 521 uint32_t tag; 522 uint32_t length; 523 uint16_t visible_pfs; /**< Bitmap of visible PFs */ 524 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 525 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 526 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 527 }; 528 529 /* Dynamic port mode. 530 * 531 * Allows selecting alternate port configuration for platforms that support it 532 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the 533 * number of externally visible ports (and, hence, PF to port mapping), so must 534 * be done at boot time. 535 * 536 * This tag supercedes tlv_global_port_config. 537 */ 538 539 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) 540 541 struct tlv_global_port_mode { 542 uint32_t tag; 543 uint32_t length; 544 uint32_t port_mode; 545 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ 546 #define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */ 547 #define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */ 548 #define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */ 549 #define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */ 550 #define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */ 551 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */ 552 #define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */ 553 #define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */ 554 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */ 555 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2 556 }; 557 558 /* Type of the v-switch created implicitly by the firmware */ 559 560 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) 561 562 struct tlv_vswitch_type { 563 uint32_t tag; 564 uint32_t length; 565 uint32_t vswitch_type; 566 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ 567 #define TLV_VSWITCH_TYPE_NONE (0) 568 #define TLV_VSWITCH_TYPE_VLAN (1) 569 #define TLV_VSWITCH_TYPE_VEB (2) 570 #define TLV_VSWITCH_TYPE_VEPA (3) 571 #define TLV_VSWITCH_TYPE_MUX (4) 572 #define TLV_VSWITCH_TYPE_TEST (5) 573 }; 574 575 /* A VLAN tag for the v-port created implicitly by the firmware */ 576 577 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) 578 579 struct tlv_vport_vlan_tag { 580 uint32_t tag; 581 uint32_t length; 582 uint32_t vlan_tag; 583 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ 584 }; 585 586 /* Offset to be applied to the 0v9 setting, wherever it came from */ 587 588 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000) 589 590 struct tlv_0v9_atb_offset { 591 uint32_t tag; 592 uint32_t length; 593 int16_t offset_millivolts; 594 uint16_t reserved; 595 }; 596 597 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). 598 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. 599 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while 600 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: 601 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ 602 603 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ 604 605 struct tlv_privilege_mask { /* legacy structure - do not use */ 606 uint32_t tag; 607 uint32_t length; 608 uint32_t privilege_mask; 609 }; 610 611 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) 612 613 struct tlv_privilege_mask_add { 614 uint32_t tag; 615 uint32_t length; 616 uint32_t privilege_mask_add; 617 }; 618 619 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) 620 621 struct tlv_privilege_mask_rem { 622 uint32_t tag; 623 uint32_t length; 624 uint32_t privilege_mask_rem; 625 }; 626 627 /* Additional privileges given to all PFs. 628 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 629 630 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) 631 632 struct tlv_privilege_mask_add_all_pfs { 633 uint32_t tag; 634 uint32_t length; 635 uint32_t privilege_mask_add; 636 }; 637 638 /* Additional privileges given to a selected PF. 639 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 640 641 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) 642 643 struct tlv_privilege_mask_add_single_pf { 644 uint32_t tag; 645 uint32_t length; 646 uint32_t privilege_mask_add; 647 }; 648 649 /* Turning on/off the PFIOV mode. 650 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ 651 652 #define TLV_TAG_PFIOV(port) (0x10170000 + (port)) 653 654 struct tlv_pfiov { 655 uint32_t tag; 656 uint32_t length; 657 uint32_t pfiov; 658 #define TLV_PFIOV_OFF (0) /* Default */ 659 #define TLV_PFIOV_ON (1) 660 }; 661 662 /* Multicast filter chaining mode selection. 663 * 664 * When enabled, multicast packets are delivered to all recipients of all 665 * matching multicast filters, with the exception that IP multicast filters 666 * will steal traffic from MAC multicast filters on a per-function basis. 667 * (New behaviour.) 668 * 669 * When disabled, multicast packets will always be delivered only to the 670 * recipients of the highest priority matching multicast filter. 671 * (Legacy behaviour.) 672 * 673 * The DEFAULT mode (which is the same as the tag not being present at all) 674 * is equivalent to ENABLED in production builds, and DISABLED in eftest 675 * builds. 676 * 677 * This option is intended to provide run-time control over this feature 678 * while it is being stabilised and may be withdrawn at some point in the 679 * future; the new behaviour is intended to become the standard behaviour. 680 */ 681 682 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) 683 684 struct tlv_mcast_filter_chaining { 685 uint32_t tag; 686 uint32_t length; 687 uint32_t mode; 688 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) 689 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0) 690 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1) 691 }; 692 693 694 /* Pacer rate limit per PF */ 695 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) 696 697 struct tlv_rate_limit { 698 uint32_t tag; 699 uint32_t length; 700 uint32_t rate_mbps; 701 }; 702 703 704 /* OCSD Enable/Disable 705 * 706 * This setting allows OCSD to be disabled. This is a requirement for HP 707 * servers to support PCI passthrough for virtualization. 708 * 709 * The DEFAULT mode (which is the same as the tag not being present) is 710 * equivalent to ENABLED. 711 * 712 * This option is not used by the MCFW, and is entirely handled by the various 713 * drivers that support OCSD, by reading the setting before they attempt 714 * to enable OCSD. 715 * 716 * bit0: OCSD Disabled/Enabled 717 */ 718 719 #define TLV_TAG_OCSD (0x101C0000) 720 721 struct tlv_ocsd { 722 uint32_t tag; 723 uint32_t length; 724 uint32_t mode; 725 #define TLV_OCSD_DISABLED 0 726 #define TLV_OCSD_ENABLED 1 /* Default */ 727 }; 728 729 /* Descriptor cache config. 730 * 731 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also 732 * sets the total number of VIs. When the number of VIs is reduced VIs are taken 733 * away from the highest numbered port first, so a vi_count of 1024 means 1024 734 * VIs on the first port and 0 on the second (on a Torino). 735 */ 736 737 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) 738 739 struct tlv_descriptor_cache_config { 740 uint32_t tag; 741 uint32_t length; 742 uint8_t rx_desc_cache_size; 743 uint8_t tx_desc_cache_size; 744 uint16_t vi_count; 745 }; 746 #define TLV_DESC_CACHE_DEFAULT (0xff) 747 #define TLV_VI_COUNT_DEFAULT (0xffff) 748 749 /* RX event merging config (read batching). 750 * 751 * Sets the global maximum number of events for the merging bins, and the 752 * global timeout configuration for the bins. 753 */ 754 755 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) 756 757 struct tlv_rx_event_merging_config { 758 uint32_t tag; 759 uint32_t length; 760 uint32_t max_events; 761 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 762 uint32_t timeout_ns; 763 }; 764 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7 765 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740 766 767 #endif /* CI_MGMT_TLV_LAYOUT_H */ 768