1 /*- 2 * Copyright (c) 2012-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 /* 32 * This is NOT the original source file. Do NOT edit it. 33 * To update the tlv layout, please edit the copy in 34 * the sfregistry repo and then, in that repo, 35 * "make tlv_headers" or "make export" to 36 * regenerate and export all types of headers. 37 */ 38 39 /* These structures define the layouts for the TLV items stored in static and 40 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). 41 * 42 * They contain the same sort of information that was kept in the 43 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures 44 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for 45 * Siena. 46 * 47 * These are used directly by the MC and should also be usable directly on host 48 * systems which are little-endian and do not do strange things with structure 49 * padding. (Big-endian host systems will require some byte-swapping.) 50 * 51 * ----- 52 * 53 * Please refer to SF-108797-SW for a general overview of the TLV partition 54 * format. 55 * 56 * ----- 57 * 58 * The current tag IDs have a general structure: with the exception of the 59 * special values defined in the document, they are of the form 0xLTTTNNNN, 60 * where: 61 * 62 * - L is a location, indicating where this tag is expected to be found: 63 * 0: static configuration 64 * 1: dynamic configuration 65 * 2: firmware internal use 66 * 3: license partition 67 * 4: tsa configuration 68 * 69 * - TTT is a type, which is just a unique value. The same type value 70 * might appear in both locations, indicating a relationship between 71 * the items (e.g. static and dynamic VPD below). 72 * 73 * - NNNN is an index of some form. Some item types are per-port, some 74 * are per-PF, some are per-partition-type. 75 * 76 * ----- 77 * 78 * As with the previous Siena structures, each structure here is laid out 79 * carefully: values are aligned to their natural boundary, with explicit 80 * padding fields added where necessary. (No, technically this does not 81 * absolutely guarantee portability. But, in practice, compilers are generally 82 * sensible enough not to introduce completely pointless padding, and it works 83 * well enough.) 84 */ 85 86 #ifndef CI_MGMT_TLV_LAYOUT_H 87 #define CI_MGMT_TLV_LAYOUT_H 88 89 /* ---------------------------------------------------------------------------- 90 * General structure (defined by SF-108797-SW) 91 * ---------------------------------------------------------------------------- 92 */ 93 94 /* The "end" tag. 95 * 96 * (Note that this is *not* followed by length or value fields: anything after 97 * the tag itself is irrelevant.) 98 */ 99 100 #define TLV_TAG_END (0xEEEEEEEE) 101 102 /* Other special reserved tag values. 103 */ 104 105 #define TLV_TAG_SKIP (0x00000000) 106 #define TLV_TAG_INVALID (0xFFFFFFFF) 107 108 /* TLV partition header. 109 * 110 * In a TLV partition, this must be the first item in the sequence, at offset 111 * 0. 112 */ 113 114 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) 115 116 struct tlv_partition_header { 117 uint32_t tag; 118 uint32_t length; 119 uint16_t type_id; 120 /* 0 indicates the default segment (always located at offset 0), while other values 121 * are for RFID-selectable presets that should immediately follow the default segment. 122 * The default segment may also have preset > 0, which means that it is a preset 123 * selected through an RFID command and copied by FW to the location at offset 0. */ 124 uint16_t preset; 125 uint32_t generation; 126 uint32_t total_length; 127 }; 128 129 /* TLV partition trailer. 130 * 131 * In a TLV partition, this must be the last item in the sequence, immediately 132 * preceding the TLV_TAG_END word. 133 */ 134 135 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57) 136 137 struct tlv_partition_trailer { 138 uint32_t tag; 139 uint32_t length; 140 uint32_t generation; 141 uint32_t checksum; 142 }; 143 144 /* Appendable TLV partition header. 145 * 146 * In an appendable TLV partition, this must be the first item in the sequence, 147 * at offset 0. (Note that, unlike the configuration partitions, there is no 148 * trailer before the TLV_TAG_END word.) 149 */ 150 151 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) 152 153 struct tlv_appendable_partition_header { 154 uint32_t tag; 155 uint32_t length; 156 uint16_t type_id; 157 uint16_t reserved; 158 }; 159 160 /* ---------------------------------------------------------------------------- 161 * Configuration items 162 * ---------------------------------------------------------------------------- 163 */ 164 165 /* NIC global capabilities. 166 */ 167 168 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) 169 170 struct tlv_global_capabilities { 171 uint32_t tag; 172 uint32_t length; 173 uint32_t flags; 174 }; 175 176 /* Siena-style per-port MAC address allocation. 177 * 178 * There are <count> addresses, starting at <base_address> and incrementing 179 * by adding <stride> to the low-order byte(s). 180 * 181 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool 182 * of contiguous MAC addresses for the firmware to allocate as it sees fit.) 183 */ 184 185 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) 186 187 struct tlv_port_mac { 188 uint32_t tag; 189 uint32_t length; 190 uint8_t base_address[6]; 191 uint16_t reserved; 192 uint16_t count; 193 uint16_t stride; 194 }; 195 196 /* Static VPD. 197 * 198 * This is the portion of VPD which is set at manufacturing time and not 199 * expected to change. It is formatted as a standard PCI VPD block. There are 200 * global and per-pf TLVs for this, the global TLV is new for Medford and is 201 * used in preference to the per-pf TLV. 202 */ 203 204 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) 205 206 struct tlv_pf_static_vpd { 207 uint32_t tag; 208 uint32_t length; 209 uint8_t bytes[]; 210 }; 211 212 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) 213 214 struct tlv_global_static_vpd { 215 uint32_t tag; 216 uint32_t length; 217 uint8_t bytes[]; 218 }; 219 220 /* Dynamic VPD. 221 * 222 * This is the portion of VPD which may be changed (e.g. by firmware updates). 223 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs 224 * for this, the global TLV is new for Medford and is used in preference to the 225 * per-pf TLV. 226 */ 227 228 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) 229 230 struct tlv_pf_dynamic_vpd { 231 uint32_t tag; 232 uint32_t length; 233 uint8_t bytes[]; 234 }; 235 236 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) 237 238 struct tlv_global_dynamic_vpd { 239 uint32_t tag; 240 uint32_t length; 241 uint8_t bytes[]; 242 }; 243 244 /* "DBI" PCI config space changes. 245 * 246 * This is a set of edits made to the default PCI config space values before 247 * the device is allowed to enumerate. There are global and per-pf TLVs for 248 * this, the global TLV is new for Medford and is used in preference to the 249 * per-pf TLV. 250 */ 251 252 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) 253 254 struct tlv_pf_dbi { 255 uint32_t tag; 256 uint32_t length; 257 struct { 258 uint16_t addr; 259 uint16_t byte_enables; 260 uint32_t value; 261 } items[]; 262 }; 263 264 #define TLV_TAG_GLOBAL_DBI (0x00210000) 265 266 struct tlv_global_dbi { 267 uint32_t tag; 268 uint32_t length; 269 struct { 270 uint16_t addr; 271 uint16_t byte_enables; 272 uint32_t value; 273 } items[]; 274 }; 275 276 /* Partition subtype codes. 277 * 278 * A subtype may optionally be stored for each type of partition present in 279 * the NVRAM. For example, this may be used to allow a generic firmware update 280 * utility to select a specific variant of firmware for a specific variant of 281 * board. 282 * 283 * The description[] field is an optional string which is returned in the 284 * MC_CMD_NVRAM_METADATA response if present. 285 */ 286 287 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) 288 289 struct tlv_partition_subtype { 290 uint32_t tag; 291 uint32_t length; 292 uint32_t subtype; 293 uint8_t description[]; 294 }; 295 296 /* Partition version codes. 297 * 298 * A version may optionally be stored for each type of partition present in 299 * the NVRAM. This provides a standard way of tracking the currently stored 300 * version of each of the various component images. 301 */ 302 303 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) 304 305 struct tlv_partition_version { 306 uint32_t tag; 307 uint32_t length; 308 uint16_t version_w; 309 uint16_t version_x; 310 uint16_t version_y; 311 uint16_t version_z; 312 }; 313 314 /* Global PCIe configuration */ 315 316 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) 317 318 struct tlv_pcie_config { 319 uint32_t tag; 320 uint32_t length; 321 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ 322 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 323 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 324 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 325 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ 326 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ 327 }; 328 329 /* Per-PF configuration. Note that not all these fields are necessarily useful 330 * as the apertures are constrained by the BIU settings (the one case we do 331 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can 332 * tidy things up later */ 333 334 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) 335 336 struct tlv_per_pf_pcie_config { 337 uint32_t tag; 338 uint32_t length; 339 uint8_t vfs_total; 340 uint8_t port_allocation; 341 uint16_t vectors_per_pf; 342 uint16_t vectors_per_vf; 343 uint8_t pf_bar0_aperture; 344 uint8_t pf_bar2_aperture; 345 uint8_t vf_bar0_aperture; 346 uint8_t vf_base; 347 uint16_t supp_pagesz; 348 uint16_t msix_vec_base; 349 }; 350 351 /* Development ONLY. This is a single TLV tag for all the gubbins 352 * that can be set through the MC command-line other than the PCIe 353 * settings. This is a temporary measure. */ 354 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ 355 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS 356 357 struct tlv_tmp_gubbins { 358 uint32_t tag; 359 uint32_t length; 360 /* Consumed by dpcpu.c */ 361 uint64_t tx0_tags; /* Bitmap */ 362 uint64_t tx1_tags; /* Bitmap */ 363 uint64_t dl_tags; /* Bitmap */ 364 uint32_t flags; 365 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ 366 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ 367 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ 368 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ 369 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ 370 /* Consumed by features.c */ 371 uint32_t dut_features; /* All 1s -> leave alone */ 372 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ 373 /* Consumed by clocks_hunt.c */ 374 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ 375 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */ 376 int8_t rx_dc_size; /* -1 -> leave alone */ 377 int8_t tx_dc_size; 378 int16_t num_q_allocs; 379 }; 380 381 /* Global port configuration 382 * 383 * This is now deprecated in favour of a platform-provided default 384 * and dynamic config override via tlv_global_port_options. 385 */ 386 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) 387 388 struct tlv_global_port_config { 389 uint32_t tag; 390 uint32_t length; 391 uint32_t ports_per_core; 392 uint32_t max_port_speed; 393 }; 394 395 /* Firmware options. 396 * 397 * This is intended for user-configurable selection of optional firmware 398 * features and variants. 399 * 400 * Initially, this consists only of the satellite CPU firmware variant 401 * selection, but this tag could be extended in the future (using the 402 * tag length to determine whether additional fields are present). 403 */ 404 405 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) 406 407 struct tlv_firmware_options { 408 uint32_t tag; 409 uint32_t length; 410 uint32_t firmware_variant; 411 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) 412 413 /* These are the values for overriding the driver's choice; the definitions 414 * are taken from MCDI so that they don't get out of step. Include 415 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if 416 * you need to use these constants. 417 */ 418 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED 419 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY 420 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM 421 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE 422 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ 423 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 424 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE 425 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK 426 #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP 427 }; 428 429 /* Voltage settings 430 * 431 * Intended for boards with A0 silicon where the core voltage may 432 * need tweaking. Most likely set once when the pass voltage is 433 * determined. */ 434 435 #define TLV_TAG_0V9_SETTINGS (0x000c0000) 436 437 struct tlv_0v9_settings { 438 uint32_t tag; 439 uint32_t length; 440 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ 441 #define TLV_TAG_0V9_REQUIRES_FAN (1) 442 uint16_t target_voltage; /* In millivolts */ 443 /* Since the limits are meant to be centred to the target (and must at least 444 * contain it) they need setting as well. */ 445 uint16_t warn_low; /* In millivolts */ 446 uint16_t warn_high; /* In millivolts */ 447 uint16_t panic_low; /* In millivolts */ 448 uint16_t panic_high; /* In millivolts */ 449 }; 450 451 /* Clock configuration */ 452 453 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ 454 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG 455 456 struct tlv_clock_config { 457 uint32_t tag; 458 uint32_t length; 459 uint16_t clk_sys; /* MHz */ 460 uint16_t clk_dpcpu; /* MHz */ 461 uint16_t clk_icore; /* MHz */ 462 uint16_t clk_pcs; /* MHz */ 463 }; 464 465 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) 466 467 struct tlv_clock_config_medford { 468 uint32_t tag; 469 uint32_t length; 470 uint16_t clk_sys; /* MHz */ 471 uint16_t clk_mc; /* MHz */ 472 uint16_t clk_rmon; /* MHz */ 473 uint16_t clk_vswitch; /* MHz */ 474 uint16_t clk_dpcpu; /* MHz */ 475 uint16_t clk_pcs; /* MHz */ 476 }; 477 478 /* EF10-style global pool of MAC addresses. 479 * 480 * There are <count> addresses, starting at <base_address>, which are 481 * contiguous. Firmware is responsible for allocating addresses from this 482 * pool to ports / PFs as appropriate. 483 */ 484 485 #define TLV_TAG_GLOBAL_MAC (0x000e0000) 486 487 struct tlv_global_mac { 488 uint32_t tag; 489 uint32_t length; 490 uint8_t base_address[6]; 491 uint16_t reserved1; 492 uint16_t count; 493 uint16_t reserved2; 494 }; 495 496 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ 497 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET 498 499 /* The target value for the 0v9 power rail measured on-chip at the 500 * analogue test bus */ 501 struct tlv_0v9_atb_target { 502 uint32_t tag; 503 uint32_t length; 504 uint16_t millivolts; 505 uint16_t reserved; 506 }; 507 508 /* Factory settings for amplitude calibration of the PCIE TX serdes */ 509 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000) 510 struct tlv_pcie_tx_amp_config { 511 uint32_t tag; 512 uint32_t length; 513 uint8_t quad_tx_imp2k[4]; 514 uint8_t quad_tx_imp50[4]; 515 uint8_t lane_amp[16]; 516 }; 517 518 /* Global PCIe configuration, second revision. This represents the visible PFs 519 * by a bitmap rather than having the number of the highest visible one. As such 520 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG 521 * can and it should be used in place of that tag in future (but compatibility with 522 * the old tag will be left in the firmware indefinitely). */ 523 524 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) 525 526 struct tlv_pcie_config_r2 { 527 uint32_t tag; 528 uint32_t length; 529 uint16_t visible_pfs; /**< Bitmap of visible PFs */ 530 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 531 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 532 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 533 }; 534 535 /* Dynamic port mode. 536 * 537 * Allows selecting alternate port configuration for platforms that support it 538 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the 539 * number of externally visible ports (and, hence, PF to port mapping), so must 540 * be done at boot time. 541 * 542 * Port mode naming convention is 543 * 544 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width] 545 * 546 * Port lane width determines the capabilities (speeds) of the ports, subject 547 * to architecture capabilities (e.g. 25G support) and switch bandwidth 548 * constraints: 549 * - single lane ports can do 25G/10G/1G 550 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane) 551 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes) 552 553 * This tag supercedes tlv_global_port_config. 554 */ 555 556 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) 557 558 struct tlv_global_port_mode { 559 uint32_t tag; 560 uint32_t length; 561 uint32_t port_mode; 562 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ 563 564 /* Huntington port modes */ 565 #define TLV_PORT_MODE_10G (0) 566 #define TLV_PORT_MODE_40G (1) 567 #define TLV_PORT_MODE_10G_10G (2) 568 #define TLV_PORT_MODE_40G_40G (3) 569 #define TLV_PORT_MODE_10G_10G_10G_10G (4) 570 #define TLV_PORT_MODE_40G_10G_10G (6) 571 #define TLV_PORT_MODE_10G_10G_40G (7) 572 573 /* Medford (and later) port modes */ 574 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */ 575 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */ 576 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */ 577 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */ 578 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */ 579 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */ 580 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */ 581 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */ 582 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */ 583 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */ 584 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */ 585 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */ 586 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */ 587 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */ 588 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */ 589 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */ 590 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */ 591 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */ 592 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */ 593 594 /* Snapper-only Medford2 port modes. 595 * These modes are eftest only, to allow snapper explicit 596 * selection between multi-channel and LLPCS. In production, 597 * this selection is automatic and outside world should not 598 * care about LLPCS. 599 */ 600 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */ 601 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */ 602 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */ 603 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */ 604 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */ 605 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */ 606 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL 607 608 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */ 609 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) 610 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) 611 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) 612 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) 613 614 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL 615 }; 616 617 /* Type of the v-switch created implicitly by the firmware */ 618 619 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) 620 621 struct tlv_vswitch_type { 622 uint32_t tag; 623 uint32_t length; 624 uint32_t vswitch_type; 625 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ 626 #define TLV_VSWITCH_TYPE_NONE (0) 627 #define TLV_VSWITCH_TYPE_VLAN (1) 628 #define TLV_VSWITCH_TYPE_VEB (2) 629 #define TLV_VSWITCH_TYPE_VEPA (3) 630 #define TLV_VSWITCH_TYPE_MUX (4) 631 #define TLV_VSWITCH_TYPE_TEST (5) 632 }; 633 634 /* A VLAN tag for the v-port created implicitly by the firmware */ 635 636 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) 637 638 struct tlv_vport_vlan_tag { 639 uint32_t tag; 640 uint32_t length; 641 uint32_t vlan_tag; 642 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ 643 }; 644 645 /* Offset to be applied to the 0v9 setting, wherever it came from */ 646 647 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000) 648 649 struct tlv_0v9_atb_offset { 650 uint32_t tag; 651 uint32_t length; 652 int16_t offset_millivolts; 653 uint16_t reserved; 654 }; 655 656 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). 657 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. 658 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while 659 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: 660 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ 661 662 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ 663 664 struct tlv_privilege_mask { /* legacy structure - do not use */ 665 uint32_t tag; 666 uint32_t length; 667 uint32_t privilege_mask; 668 }; 669 670 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) 671 672 struct tlv_privilege_mask_add { 673 uint32_t tag; 674 uint32_t length; 675 uint32_t privilege_mask_add; 676 }; 677 678 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) 679 680 struct tlv_privilege_mask_rem { 681 uint32_t tag; 682 uint32_t length; 683 uint32_t privilege_mask_rem; 684 }; 685 686 /* Additional privileges given to all PFs. 687 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 688 689 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) 690 691 struct tlv_privilege_mask_add_all_pfs { 692 uint32_t tag; 693 uint32_t length; 694 uint32_t privilege_mask_add; 695 }; 696 697 /* Additional privileges given to a selected PF. 698 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 699 700 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) 701 702 struct tlv_privilege_mask_add_single_pf { 703 uint32_t tag; 704 uint32_t length; 705 uint32_t privilege_mask_add; 706 }; 707 708 /* Turning on/off the PFIOV mode. 709 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ 710 711 #define TLV_TAG_PFIOV(port) (0x10170000 + (port)) 712 713 struct tlv_pfiov { 714 uint32_t tag; 715 uint32_t length; 716 uint32_t pfiov; 717 #define TLV_PFIOV_OFF (0) /* Default */ 718 #define TLV_PFIOV_ON (1) 719 }; 720 721 /* Multicast filter chaining mode selection. 722 * 723 * When enabled, multicast packets are delivered to all recipients of all 724 * matching multicast filters, with the exception that IP multicast filters 725 * will steal traffic from MAC multicast filters on a per-function basis. 726 * (New behaviour.) 727 * 728 * When disabled, multicast packets will always be delivered only to the 729 * recipients of the highest priority matching multicast filter. 730 * (Legacy behaviour.) 731 * 732 * The DEFAULT mode (which is the same as the tag not being present at all) 733 * is equivalent to ENABLED in production builds, and DISABLED in eftest 734 * builds. 735 * 736 * This option is intended to provide run-time control over this feature 737 * while it is being stabilised and may be withdrawn at some point in the 738 * future; the new behaviour is intended to become the standard behaviour. 739 */ 740 741 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) 742 743 struct tlv_mcast_filter_chaining { 744 uint32_t tag; 745 uint32_t length; 746 uint32_t mode; 747 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) 748 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0) 749 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1) 750 }; 751 752 /* Pacer rate limit per PF */ 753 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) 754 755 struct tlv_rate_limit { 756 uint32_t tag; 757 uint32_t length; 758 uint32_t rate_mbps; 759 }; 760 761 /* OCSD Enable/Disable 762 * 763 * This setting allows OCSD to be disabled. This is a requirement for HP 764 * servers to support PCI passthrough for virtualization. 765 * 766 * The DEFAULT mode (which is the same as the tag not being present) is 767 * equivalent to ENABLED. 768 * 769 * This option is not used by the MCFW, and is entirely handled by the various 770 * drivers that support OCSD, by reading the setting before they attempt 771 * to enable OCSD. 772 * 773 * bit0: OCSD Disabled/Enabled 774 */ 775 776 #define TLV_TAG_OCSD (0x101C0000) 777 778 struct tlv_ocsd { 779 uint32_t tag; 780 uint32_t length; 781 uint32_t mode; 782 #define TLV_OCSD_DISABLED 0 783 #define TLV_OCSD_ENABLED 1 /* Default */ 784 }; 785 786 /* Descriptor cache config. 787 * 788 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also 789 * sets the total number of VIs. When the number of VIs is reduced VIs are taken 790 * away from the highest numbered port first, so a vi_count of 1024 means 1024 791 * VIs on the first port and 0 on the second (on a Torino). 792 */ 793 794 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) 795 796 struct tlv_descriptor_cache_config { 797 uint32_t tag; 798 uint32_t length; 799 uint8_t rx_desc_cache_size; 800 uint8_t tx_desc_cache_size; 801 uint16_t vi_count; 802 }; 803 #define TLV_DESC_CACHE_DEFAULT (0xff) 804 #define TLV_VI_COUNT_DEFAULT (0xffff) 805 806 /* RX event merging config (read batching). 807 * 808 * Sets the global maximum number of events for the merging bins, and the 809 * global timeout configuration for the bins. 810 */ 811 812 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) 813 814 struct tlv_rx_event_merging_config { 815 uint32_t tag; 816 uint32_t length; 817 uint32_t max_events; 818 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 819 uint32_t timeout_ns; 820 }; 821 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) 822 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) 823 824 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000) 825 struct tlv_pcie_link_settings { 826 uint32_t tag; 827 uint32_t length; 828 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */ 829 uint16_t width; /* Number of lanes */ 830 }; 831 832 /* TX event merging config. 833 * 834 * Sets the global maximum number of events for the merging bins, and the 835 * global timeout configuration for the bins, and the global timeout for 836 * empty queues. 837 */ 838 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000) 839 struct tlv_tx_event_merging_config { 840 uint32_t tag; 841 uint32_t length; 842 uint32_t max_events; 843 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 844 uint32_t timeout_ns; 845 uint32_t qempty_timeout_ns; /* Medford only */ 846 }; 847 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) 848 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) 849 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff) 850 851 #define TLV_TAG_LICENSE (0x30800000) 852 853 typedef struct tlv_license { 854 uint32_t tag; 855 uint32_t length; 856 uint8_t data[]; 857 } tlv_license_t; 858 859 /* TSA NIC IP address configuration (DEPRECATED) 860 * 861 * Sets the TSA NIC IP address statically via configuration tool or dynamically 862 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop) 863 * 864 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 865 * be moved to a private partition during TSA development. It is not used in any 866 * released code yet. 867 */ 868 869 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */ 870 871 #define TLV_TSAN_IP_MODE_STATIC (0) 872 #define TLV_TSAN_IP_MODE_DHCP (1) 873 #define TLV_TSAN_IP_MODE_SNOOP (2) 874 typedef struct tlv_tsan_config { 875 uint32_t tag; 876 uint32_t length; 877 uint32_t mode; 878 uint32_t ip; 879 uint32_t netmask; 880 uint32_t gateway; 881 uint32_t port; 882 uint32_t bind_retry; /* DEPRECATED */ 883 uint32_t bind_bkout; /* DEPRECATED */ 884 } tlv_tsan_config_t; 885 886 /* TSA Controller IP address configuration (DEPRECATED) 887 * 888 * Sets the TSA Controller IP address statically via configuration tool 889 * 890 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 891 * be moved to a private partition during TSA development. It is not used in any 892 * released code yet. 893 */ 894 895 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */ 896 897 #define TLV_MAX_TSACS (4) 898 typedef struct tlv_tsac_config { 899 uint32_t tag; 900 uint32_t length; 901 uint32_t num_tsacs; 902 uint32_t ip[TLV_MAX_TSACS]; 903 uint32_t port[TLV_MAX_TSACS]; 904 } tlv_tsac_config_t; 905 906 /* Binding ticket (DEPRECATED) 907 * 908 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC 909 * and the TSA Controller 910 * 911 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 912 * be moved to a private partition during TSA development. It is not used in any 913 * released code yet. 914 */ 915 916 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */ 917 918 typedef struct tlv_binding_ticket { 919 uint32_t tag; 920 uint32_t length; 921 uint8_t bytes[]; 922 } tlv_binding_ticket_t; 923 924 /* Solarflare private key (DEPRECATED) 925 * 926 * Sets the Solareflare private key used for signing during the binding process 927 * 928 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 929 * be moved to a private partition during TSA development. It is not used in any 930 * released code yet. 931 */ 932 933 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */ 934 935 typedef struct tlv_pik_sf { 936 uint32_t tag; 937 uint32_t length; 938 uint8_t bytes[]; 939 } tlv_pik_sf_t; 940 941 /* CA root certificate (DEPRECATED) 942 * 943 * Sets the CA root certificate used for TSA Controller verfication during 944 * TLS connection setup between the TSA NIC and the TSA Controller 945 * 946 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 947 * be moved to a private partition during TSA development. It is not used in any 948 * released code yet. 949 */ 950 951 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */ 952 953 typedef struct tlv_ca_root_cert { 954 uint32_t tag; 955 uint32_t length; 956 uint8_t bytes[]; 957 } tlv_ca_root_cert_t; 958 959 /* Tx vFIFO Low latency configuration 960 * 961 * To keep the desired booting behaviour for the switch, it just requires to 962 * know if the low latency mode is enabled. 963 */ 964 965 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000) 966 struct tlv_tx_vfifo_ull_mode { 967 uint32_t tag; 968 uint32_t length; 969 uint8_t mode; 970 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0 971 }; 972 973 /* BIU mode 974 * 975 * Medford2 tag for selecting VI window decode (see values below) 976 */ 977 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000) 978 struct tlv_biu_vi_window_mode { 979 uint32_t tag; 980 uint32_t length; 981 uint8_t mode; 982 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */ 983 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */ 984 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */ 985 }; 986 987 /* FastPD mode 988 * 989 * Medford2 tag for configuring the FastPD mode (see values below) 990 */ 991 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port)) 992 struct tlv_fastpd_mode { 993 uint32_t tag; 994 uint32_t length; 995 uint8_t mode; 996 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */ 997 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */ 998 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */ 999 }; 1000 1001 /* L3xUDP datapath firmware UDP port configuration 1002 * 1003 * Sets the list of UDP ports on which the encapsulation will be handled. 1004 * The number of ports in the list is implied by the length of the TLV item. 1005 */ 1006 #define TLV_TAG_L3XUDP_PORTS (0x102a0000) 1007 struct tlv_l3xudp_ports { 1008 uint32_t tag; 1009 uint32_t length; 1010 uint16_t ports[]; 1011 #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16 1012 }; 1013 1014 #endif /* CI_MGMT_TLV_LAYOUT_H */ 1015