1 /*- 2 * Copyright (c) 2012-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * This is NOT the original source file. Do NOT edit it. 35 * To update the tlv layout, please edit the copy in 36 * the sfregistry repo and then, in that repo, 37 * "make tlv_headers" or "make export" to 38 * regenerate and export all types of headers. 39 */ 40 41 /* These structures define the layouts for the TLV items stored in static and 42 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.). 43 * 44 * They contain the same sort of information that was kept in the 45 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures 46 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for 47 * Siena. 48 * 49 * These are used directly by the MC and should also be usable directly on host 50 * systems which are little-endian and do not do strange things with structure 51 * padding. (Big-endian host systems will require some byte-swapping.) 52 * 53 * ----- 54 * 55 * Please refer to SF-108797-SW for a general overview of the TLV partition 56 * format. 57 * 58 * ----- 59 * 60 * The current tag IDs have a general structure: with the exception of the 61 * special values defined in the document, they are of the form 0xLTTTNNNN, 62 * where: 63 * 64 * - L is a location, indicating where this tag is expected to be found: 65 * 0: static configuration 66 * 1: dynamic configuration 67 * 2: firmware internal use 68 * 3: license partition 69 * 4: tsa configuration 70 * 71 * - TTT is a type, which is just a unique value. The same type value 72 * might appear in both locations, indicating a relationship between 73 * the items (e.g. static and dynamic VPD below). 74 * 75 * - NNNN is an index of some form. Some item types are per-port, some 76 * are per-PF, some are per-partition-type. 77 * 78 * ----- 79 * 80 * As with the previous Siena structures, each structure here is laid out 81 * carefully: values are aligned to their natural boundary, with explicit 82 * padding fields added where necessary. (No, technically this does not 83 * absolutely guarantee portability. But, in practice, compilers are generally 84 * sensible enough not to introduce completely pointless padding, and it works 85 * well enough.) 86 */ 87 88 89 #ifndef CI_MGMT_TLV_LAYOUT_H 90 #define CI_MGMT_TLV_LAYOUT_H 91 92 93 /* ---------------------------------------------------------------------------- 94 * General structure (defined by SF-108797-SW) 95 * ---------------------------------------------------------------------------- 96 */ 97 98 99 /* The "end" tag. 100 * 101 * (Note that this is *not* followed by length or value fields: anything after 102 * the tag itself is irrelevant.) 103 */ 104 105 #define TLV_TAG_END (0xEEEEEEEE) 106 107 108 /* Other special reserved tag values. 109 */ 110 111 #define TLV_TAG_SKIP (0x00000000) 112 #define TLV_TAG_INVALID (0xFFFFFFFF) 113 114 115 /* TLV partition header. 116 * 117 * In a TLV partition, this must be the first item in the sequence, at offset 118 * 0. 119 */ 120 121 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A) 122 123 struct tlv_partition_header { 124 uint32_t tag; 125 uint32_t length; 126 uint16_t type_id; 127 /* 0 indicates the default segment (always located at offset 0), while other values 128 * are for RFID-selectable presets that should immediately follow the default segment. 129 * The default segment may also have preset > 0, which means that it is a preset 130 * selected through an RFID command and copied by FW to the location at offset 0. */ 131 uint16_t preset; 132 uint32_t generation; 133 uint32_t total_length; 134 }; 135 136 137 /* TLV partition trailer. 138 * 139 * In a TLV partition, this must be the last item in the sequence, immediately 140 * preceding the TLV_TAG_END word. 141 */ 142 143 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57) 144 145 struct tlv_partition_trailer { 146 uint32_t tag; 147 uint32_t length; 148 uint32_t generation; 149 uint32_t checksum; 150 }; 151 152 153 /* Appendable TLV partition header. 154 * 155 * In an appendable TLV partition, this must be the first item in the sequence, 156 * at offset 0. (Note that, unlike the configuration partitions, there is no 157 * trailer before the TLV_TAG_END word.) 158 */ 159 160 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7) 161 162 struct tlv_appendable_partition_header { 163 uint32_t tag; 164 uint32_t length; 165 uint16_t type_id; 166 uint16_t reserved; 167 }; 168 169 170 /* ---------------------------------------------------------------------------- 171 * Configuration items 172 * ---------------------------------------------------------------------------- 173 */ 174 175 176 /* NIC global capabilities. 177 */ 178 179 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000) 180 181 struct tlv_global_capabilities { 182 uint32_t tag; 183 uint32_t length; 184 uint32_t flags; 185 }; 186 187 188 /* Siena-style per-port MAC address allocation. 189 * 190 * There are <count> addresses, starting at <base_address> and incrementing 191 * by adding <stride> to the low-order byte(s). 192 * 193 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool 194 * of contiguous MAC addresses for the firmware to allocate as it sees fit.) 195 */ 196 197 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) 198 199 struct tlv_port_mac { 200 uint32_t tag; 201 uint32_t length; 202 uint8_t base_address[6]; 203 uint16_t reserved; 204 uint16_t count; 205 uint16_t stride; 206 }; 207 208 209 /* Static VPD. 210 * 211 * This is the portion of VPD which is set at manufacturing time and not 212 * expected to change. It is formatted as a standard PCI VPD block. There are 213 * global and per-pf TLVs for this, the global TLV is new for Medford and is 214 * used in preference to the per-pf TLV. 215 */ 216 217 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) 218 219 struct tlv_pf_static_vpd { 220 uint32_t tag; 221 uint32_t length; 222 uint8_t bytes[]; 223 }; 224 225 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) 226 227 struct tlv_global_static_vpd { 228 uint32_t tag; 229 uint32_t length; 230 uint8_t bytes[]; 231 }; 232 233 234 /* Dynamic VPD. 235 * 236 * This is the portion of VPD which may be changed (e.g. by firmware updates). 237 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs 238 * for this, the global TLV is new for Medford and is used in preference to the 239 * per-pf TLV. 240 */ 241 242 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) 243 244 struct tlv_pf_dynamic_vpd { 245 uint32_t tag; 246 uint32_t length; 247 uint8_t bytes[]; 248 }; 249 250 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) 251 252 struct tlv_global_dynamic_vpd { 253 uint32_t tag; 254 uint32_t length; 255 uint8_t bytes[]; 256 }; 257 258 259 /* "DBI" PCI config space changes. 260 * 261 * This is a set of edits made to the default PCI config space values before 262 * the device is allowed to enumerate. There are global and per-pf TLVs for 263 * this, the global TLV is new for Medford and is used in preference to the 264 * per-pf TLV. 265 */ 266 267 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) 268 269 struct tlv_pf_dbi { 270 uint32_t tag; 271 uint32_t length; 272 struct { 273 uint16_t addr; 274 uint16_t byte_enables; 275 uint32_t value; 276 } items[]; 277 }; 278 279 280 #define TLV_TAG_GLOBAL_DBI (0x00210000) 281 282 struct tlv_global_dbi { 283 uint32_t tag; 284 uint32_t length; 285 struct { 286 uint16_t addr; 287 uint16_t byte_enables; 288 uint32_t value; 289 } items[]; 290 }; 291 292 293 /* Partition subtype codes. 294 * 295 * A subtype may optionally be stored for each type of partition present in 296 * the NVRAM. For example, this may be used to allow a generic firmware update 297 * utility to select a specific variant of firmware for a specific variant of 298 * board. 299 * 300 * The description[] field is an optional string which is returned in the 301 * MC_CMD_NVRAM_METADATA response if present. 302 */ 303 304 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) 305 306 struct tlv_partition_subtype { 307 uint32_t tag; 308 uint32_t length; 309 uint32_t subtype; 310 uint8_t description[]; 311 }; 312 313 314 /* Partition version codes. 315 * 316 * A version may optionally be stored for each type of partition present in 317 * the NVRAM. This provides a standard way of tracking the currently stored 318 * version of each of the various component images. 319 */ 320 321 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type)) 322 323 struct tlv_partition_version { 324 uint32_t tag; 325 uint32_t length; 326 uint16_t version_w; 327 uint16_t version_x; 328 uint16_t version_y; 329 uint16_t version_z; 330 }; 331 332 /* Global PCIe configuration */ 333 334 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000) 335 336 struct tlv_pcie_config { 337 uint32_t tag; 338 uint32_t length; 339 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ 340 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 341 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 342 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 343 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ 344 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ 345 }; 346 347 /* Per-PF configuration. Note that not all these fields are necessarily useful 348 * as the apertures are constrained by the BIU settings (the one case we do 349 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can 350 * tidy things up later */ 351 352 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) 353 354 struct tlv_per_pf_pcie_config { 355 uint32_t tag; 356 uint32_t length; 357 uint8_t vfs_total; 358 uint8_t port_allocation; 359 uint16_t vectors_per_pf; 360 uint16_t vectors_per_vf; 361 uint8_t pf_bar0_aperture; 362 uint8_t pf_bar2_aperture; 363 uint8_t vf_bar0_aperture; 364 uint8_t vf_base; 365 uint16_t supp_pagesz; 366 uint16_t msix_vec_base; 367 }; 368 369 370 /* Development ONLY. This is a single TLV tag for all the gubbins 371 * that can be set through the MC command-line other than the PCIe 372 * settings. This is a temporary measure. */ 373 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ 374 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS 375 376 struct tlv_tmp_gubbins { 377 uint32_t tag; 378 uint32_t length; 379 /* Consumed by dpcpu.c */ 380 uint64_t tx0_tags; /* Bitmap */ 381 uint64_t tx1_tags; /* Bitmap */ 382 uint64_t dl_tags; /* Bitmap */ 383 uint32_t flags; 384 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ 385 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ 386 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ 387 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ 388 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */ 389 /* Consumed by features.c */ 390 uint32_t dut_features; /* All 1s -> leave alone */ 391 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */ 392 /* Consumed by clocks_hunt.c */ 393 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */ 394 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */ 395 int8_t rx_dc_size; /* -1 -> leave alone */ 396 int8_t tx_dc_size; 397 int16_t num_q_allocs; 398 }; 399 400 /* Global port configuration 401 * 402 * This is now deprecated in favour of a platform-provided default 403 * and dynamic config override via tlv_global_port_options. 404 */ 405 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000) 406 407 struct tlv_global_port_config { 408 uint32_t tag; 409 uint32_t length; 410 uint32_t ports_per_core; 411 uint32_t max_port_speed; 412 }; 413 414 415 /* Firmware options. 416 * 417 * This is intended for user-configurable selection of optional firmware 418 * features and variants. 419 * 420 * Initially, this consists only of the satellite CPU firmware variant 421 * selection, but this tag could be extended in the future (using the 422 * tag length to determine whether additional fields are present). 423 */ 424 425 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000) 426 427 struct tlv_firmware_options { 428 uint32_t tag; 429 uint32_t length; 430 uint32_t firmware_variant; 431 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff) 432 433 /* These are the values for overriding the driver's choice; the definitions 434 * are taken from MCDI so that they don't get out of step. Include 435 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if 436 * you need to use these constants. 437 */ 438 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED 439 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY 440 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM 441 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE 442 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \ 443 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 444 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE 445 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK 446 #define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP 447 }; 448 449 /* Voltage settings 450 * 451 * Intended for boards with A0 silicon where the core voltage may 452 * need tweaking. Most likely set once when the pass voltage is 453 * determined. */ 454 455 #define TLV_TAG_0V9_SETTINGS (0x000c0000) 456 457 struct tlv_0v9_settings { 458 uint32_t tag; 459 uint32_t length; 460 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ 461 #define TLV_TAG_0V9_REQUIRES_FAN (1) 462 uint16_t target_voltage; /* In millivolts */ 463 /* Since the limits are meant to be centred to the target (and must at least 464 * contain it) they need setting as well. */ 465 uint16_t warn_low; /* In millivolts */ 466 uint16_t warn_high; /* In millivolts */ 467 uint16_t panic_low; /* In millivolts */ 468 uint16_t panic_high; /* In millivolts */ 469 }; 470 471 472 /* Clock configuration */ 473 474 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ 475 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG 476 477 struct tlv_clock_config { 478 uint32_t tag; 479 uint32_t length; 480 uint16_t clk_sys; /* MHz */ 481 uint16_t clk_dpcpu; /* MHz */ 482 uint16_t clk_icore; /* MHz */ 483 uint16_t clk_pcs; /* MHz */ 484 }; 485 486 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000) 487 488 struct tlv_clock_config_medford { 489 uint32_t tag; 490 uint32_t length; 491 uint16_t clk_sys; /* MHz */ 492 uint16_t clk_mc; /* MHz */ 493 uint16_t clk_rmon; /* MHz */ 494 uint16_t clk_vswitch; /* MHz */ 495 uint16_t clk_dpcpu; /* MHz */ 496 uint16_t clk_pcs; /* MHz */ 497 }; 498 499 500 /* EF10-style global pool of MAC addresses. 501 * 502 * There are <count> addresses, starting at <base_address>, which are 503 * contiguous. Firmware is responsible for allocating addresses from this 504 * pool to ports / PFs as appropriate. 505 */ 506 507 #define TLV_TAG_GLOBAL_MAC (0x000e0000) 508 509 struct tlv_global_mac { 510 uint32_t tag; 511 uint32_t length; 512 uint8_t base_address[6]; 513 uint16_t reserved1; 514 uint16_t count; 515 uint16_t reserved2; 516 }; 517 518 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ 519 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET 520 521 /* The target value for the 0v9 power rail measured on-chip at the 522 * analogue test bus */ 523 struct tlv_0v9_atb_target { 524 uint32_t tag; 525 uint32_t length; 526 uint16_t millivolts; 527 uint16_t reserved; 528 }; 529 530 /* Factory settings for amplitude calibration of the PCIE TX serdes */ 531 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000) 532 struct tlv_pcie_tx_amp_config { 533 uint32_t tag; 534 uint32_t length; 535 uint8_t quad_tx_imp2k[4]; 536 uint8_t quad_tx_imp50[4]; 537 uint8_t lane_amp[16]; 538 }; 539 540 541 /* Global PCIe configuration, second revision. This represents the visible PFs 542 * by a bitmap rather than having the number of the highest visible one. As such 543 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG 544 * can and it should be used in place of that tag in future (but compatibility with 545 * the old tag will be left in the firmware indefinitely). */ 546 547 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000) 548 549 struct tlv_pcie_config_r2 { 550 uint32_t tag; 551 uint32_t length; 552 uint16_t visible_pfs; /**< Bitmap of visible PFs */ 553 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ 554 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ 555 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ 556 }; 557 558 /* Dynamic port mode. 559 * 560 * Allows selecting alternate port configuration for platforms that support it 561 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the 562 * number of externally visible ports (and, hence, PF to port mapping), so must 563 * be done at boot time. 564 * 565 * Port mode naming convention is 566 * 567 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width] 568 * 569 * Port lane width determines the capabilities (speeds) of the ports, subject 570 * to architecture capabilities (e.g. 25G support) and switch bandwidth 571 * constraints: 572 * - single lane ports can do 25G/10G/1G 573 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane) 574 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes) 575 576 * This tag supercedes tlv_global_port_config. 577 */ 578 579 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000) 580 581 struct tlv_global_port_mode { 582 uint32_t tag; 583 uint32_t length; 584 uint32_t port_mode; 585 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */ 586 587 /* Huntington port modes */ 588 #define TLV_PORT_MODE_10G (0) 589 #define TLV_PORT_MODE_40G (1) 590 #define TLV_PORT_MODE_10G_10G (2) 591 #define TLV_PORT_MODE_40G_40G (3) 592 #define TLV_PORT_MODE_10G_10G_10G_10G (4) 593 #define TLV_PORT_MODE_40G_10G_10G (6) 594 #define TLV_PORT_MODE_10G_10G_40G (7) 595 596 /* Medford (and later) port modes */ 597 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */ 598 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */ 599 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */ 600 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */ 601 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */ 602 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */ 603 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */ 604 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */ 605 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */ 606 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */ 607 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */ 608 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */ 609 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */ 610 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */ 611 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */ 612 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */ 613 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */ 614 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */ 615 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */ 616 617 /* Snapper-only Medford2 port modes. 618 * These modes are eftest only, to allow snapper explicit 619 * selection between multi-channel and LLPCS. In production, 620 * this selection is automatic and outside world should not 621 * care about LLPCS. 622 */ 623 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */ 624 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */ 625 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */ 626 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */ 627 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */ 628 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */ 629 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL 630 631 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */ 632 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) 633 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) 634 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) 635 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) 636 637 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL 638 }; 639 640 /* Type of the v-switch created implicitly by the firmware */ 641 642 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port)) 643 644 struct tlv_vswitch_type { 645 uint32_t tag; 646 uint32_t length; 647 uint32_t vswitch_type; 648 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */ 649 #define TLV_VSWITCH_TYPE_NONE (0) 650 #define TLV_VSWITCH_TYPE_VLAN (1) 651 #define TLV_VSWITCH_TYPE_VEB (2) 652 #define TLV_VSWITCH_TYPE_VEPA (3) 653 #define TLV_VSWITCH_TYPE_MUX (4) 654 #define TLV_VSWITCH_TYPE_TEST (5) 655 }; 656 657 /* A VLAN tag for the v-port created implicitly by the firmware */ 658 659 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) 660 661 struct tlv_vport_vlan_tag { 662 uint32_t tag; 663 uint32_t length; 664 uint32_t vlan_tag; 665 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */ 666 }; 667 668 /* Offset to be applied to the 0v9 setting, wherever it came from */ 669 670 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000) 671 672 struct tlv_0v9_atb_offset { 673 uint32_t tag; 674 uint32_t length; 675 int16_t offset_millivolts; 676 uint16_t reserved; 677 }; 678 679 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port). 680 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583. 681 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while 682 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default: 683 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */ 684 685 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */ 686 687 struct tlv_privilege_mask { /* legacy structure - do not use */ 688 uint32_t tag; 689 uint32_t length; 690 uint32_t privilege_mask; 691 }; 692 693 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000) 694 695 struct tlv_privilege_mask_add { 696 uint32_t tag; 697 uint32_t length; 698 uint32_t privilege_mask_add; 699 }; 700 701 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000) 702 703 struct tlv_privilege_mask_rem { 704 uint32_t tag; 705 uint32_t length; 706 uint32_t privilege_mask_rem; 707 }; 708 709 /* Additional privileges given to all PFs. 710 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 711 712 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000) 713 714 struct tlv_privilege_mask_add_all_pfs { 715 uint32_t tag; 716 uint32_t length; 717 uint32_t privilege_mask_add; 718 }; 719 720 /* Additional privileges given to a selected PF. 721 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */ 722 723 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) 724 725 struct tlv_privilege_mask_add_single_pf { 726 uint32_t tag; 727 uint32_t length; 728 uint32_t privilege_mask_add; 729 }; 730 731 /* Turning on/off the PFIOV mode. 732 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */ 733 734 #define TLV_TAG_PFIOV(port) (0x10170000 + (port)) 735 736 struct tlv_pfiov { 737 uint32_t tag; 738 uint32_t length; 739 uint32_t pfiov; 740 #define TLV_PFIOV_OFF (0) /* Default */ 741 #define TLV_PFIOV_ON (1) 742 }; 743 744 /* Multicast filter chaining mode selection. 745 * 746 * When enabled, multicast packets are delivered to all recipients of all 747 * matching multicast filters, with the exception that IP multicast filters 748 * will steal traffic from MAC multicast filters on a per-function basis. 749 * (New behaviour.) 750 * 751 * When disabled, multicast packets will always be delivered only to the 752 * recipients of the highest priority matching multicast filter. 753 * (Legacy behaviour.) 754 * 755 * The DEFAULT mode (which is the same as the tag not being present at all) 756 * is equivalent to ENABLED in production builds, and DISABLED in eftest 757 * builds. 758 * 759 * This option is intended to provide run-time control over this feature 760 * while it is being stabilised and may be withdrawn at some point in the 761 * future; the new behaviour is intended to become the standard behaviour. 762 */ 763 764 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000) 765 766 struct tlv_mcast_filter_chaining { 767 uint32_t tag; 768 uint32_t length; 769 uint32_t mode; 770 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff) 771 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0) 772 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1) 773 }; 774 775 /* Pacer rate limit per PF */ 776 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) 777 778 struct tlv_rate_limit { 779 uint32_t tag; 780 uint32_t length; 781 uint32_t rate_mbps; 782 }; 783 784 /* OCSD Enable/Disable 785 * 786 * This setting allows OCSD to be disabled. This is a requirement for HP 787 * servers to support PCI passthrough for virtualization. 788 * 789 * The DEFAULT mode (which is the same as the tag not being present) is 790 * equivalent to ENABLED. 791 * 792 * This option is not used by the MCFW, and is entirely handled by the various 793 * drivers that support OCSD, by reading the setting before they attempt 794 * to enable OCSD. 795 * 796 * bit0: OCSD Disabled/Enabled 797 */ 798 799 #define TLV_TAG_OCSD (0x101C0000) 800 801 struct tlv_ocsd { 802 uint32_t tag; 803 uint32_t length; 804 uint32_t mode; 805 #define TLV_OCSD_DISABLED 0 806 #define TLV_OCSD_ENABLED 1 /* Default */ 807 }; 808 809 /* Descriptor cache config. 810 * 811 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also 812 * sets the total number of VIs. When the number of VIs is reduced VIs are taken 813 * away from the highest numbered port first, so a vi_count of 1024 means 1024 814 * VIs on the first port and 0 on the second (on a Torino). 815 */ 816 817 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) 818 819 struct tlv_descriptor_cache_config { 820 uint32_t tag; 821 uint32_t length; 822 uint8_t rx_desc_cache_size; 823 uint8_t tx_desc_cache_size; 824 uint16_t vi_count; 825 }; 826 #define TLV_DESC_CACHE_DEFAULT (0xff) 827 #define TLV_VI_COUNT_DEFAULT (0xffff) 828 829 /* RX event merging config (read batching). 830 * 831 * Sets the global maximum number of events for the merging bins, and the 832 * global timeout configuration for the bins. 833 */ 834 835 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) 836 837 struct tlv_rx_event_merging_config { 838 uint32_t tag; 839 uint32_t length; 840 uint32_t max_events; 841 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 842 uint32_t timeout_ns; 843 }; 844 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) 845 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) 846 847 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000) 848 struct tlv_pcie_link_settings { 849 uint32_t tag; 850 uint32_t length; 851 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */ 852 uint16_t width; /* Number of lanes */ 853 }; 854 855 /* TX event merging config. 856 * 857 * Sets the global maximum number of events for the merging bins, and the 858 * global timeout configuration for the bins, and the global timeout for 859 * empty queues. 860 */ 861 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000) 862 struct tlv_tx_event_merging_config { 863 uint32_t tag; 864 uint32_t length; 865 uint32_t max_events; 866 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) 867 uint32_t timeout_ns; 868 uint32_t qempty_timeout_ns; /* Medford only */ 869 }; 870 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff) 871 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff) 872 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff) 873 874 #define TLV_TAG_LICENSE (0x30800000) 875 876 typedef struct tlv_license { 877 uint32_t tag; 878 uint32_t length; 879 uint8_t data[]; 880 } tlv_license_t; 881 882 /* TSA NIC IP address configuration (DEPRECATED) 883 * 884 * Sets the TSA NIC IP address statically via configuration tool or dynamically 885 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop) 886 * 887 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 888 * be moved to a private partition during TSA development. It is not used in any 889 * released code yet. 890 */ 891 892 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */ 893 894 #define TLV_TSAN_IP_MODE_STATIC (0) 895 #define TLV_TSAN_IP_MODE_DHCP (1) 896 #define TLV_TSAN_IP_MODE_SNOOP (2) 897 typedef struct tlv_tsan_config { 898 uint32_t tag; 899 uint32_t length; 900 uint32_t mode; 901 uint32_t ip; 902 uint32_t netmask; 903 uint32_t gateway; 904 uint32_t port; 905 uint32_t bind_retry; /* DEPRECATED */ 906 uint32_t bind_bkout; /* DEPRECATED */ 907 } tlv_tsan_config_t; 908 909 /* TSA Controller IP address configuration (DEPRECATED) 910 * 911 * Sets the TSA Controller IP address statically via configuration tool 912 * 913 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 914 * be moved to a private partition during TSA development. It is not used in any 915 * released code yet. 916 */ 917 918 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */ 919 920 #define TLV_MAX_TSACS (4) 921 typedef struct tlv_tsac_config { 922 uint32_t tag; 923 uint32_t length; 924 uint32_t num_tsacs; 925 uint32_t ip[TLV_MAX_TSACS]; 926 uint32_t port[TLV_MAX_TSACS]; 927 } tlv_tsac_config_t; 928 929 /* Binding ticket (DEPRECATED) 930 * 931 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC 932 * and the TSA Controller 933 * 934 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 935 * be moved to a private partition during TSA development. It is not used in any 936 * released code yet. 937 */ 938 939 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */ 940 941 typedef struct tlv_binding_ticket { 942 uint32_t tag; 943 uint32_t length; 944 uint8_t bytes[]; 945 } tlv_binding_ticket_t; 946 947 /* Solarflare private key (DEPRECATED) 948 * 949 * Sets the Solareflare private key used for signing during the binding process 950 * 951 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 952 * be moved to a private partition during TSA development. It is not used in any 953 * released code yet. 954 */ 955 956 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */ 957 958 typedef struct tlv_pik_sf { 959 uint32_t tag; 960 uint32_t length; 961 uint8_t bytes[]; 962 } tlv_pik_sf_t; 963 964 /* CA root certificate (DEPRECATED) 965 * 966 * Sets the CA root certificate used for TSA Controller verfication during 967 * TLS connection setup between the TSA NIC and the TSA Controller 968 * 969 * NOTE: This TAG is temporarily placed in the dynamic config partition and will 970 * be moved to a private partition during TSA development. It is not used in any 971 * released code yet. 972 */ 973 974 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */ 975 976 typedef struct tlv_ca_root_cert { 977 uint32_t tag; 978 uint32_t length; 979 uint8_t bytes[]; 980 } tlv_ca_root_cert_t; 981 982 /* Tx vFIFO Low latency configuration 983 * 984 * To keep the desired booting behaviour for the switch, it just requires to 985 * know if the low latency mode is enabled. 986 */ 987 988 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000) 989 struct tlv_tx_vfifo_ull_mode { 990 uint32_t tag; 991 uint32_t length; 992 uint8_t mode; 993 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0 994 }; 995 996 /* BIU mode 997 * 998 * Medford2 tag for selecting VI window decode (see values below) 999 */ 1000 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000) 1001 struct tlv_biu_vi_window_mode { 1002 uint32_t tag; 1003 uint32_t length; 1004 uint8_t mode; 1005 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */ 1006 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */ 1007 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */ 1008 }; 1009 1010 /* FastPD mode 1011 * 1012 * Medford2 tag for configuring the FastPD mode (see values below) 1013 */ 1014 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port)) 1015 struct tlv_fastpd_mode { 1016 uint32_t tag; 1017 uint32_t length; 1018 uint8_t mode; 1019 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */ 1020 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */ 1021 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */ 1022 }; 1023 1024 /* L3xUDP datapath firmware UDP port configuration 1025 * 1026 * Sets the list of UDP ports on which the encapsulation will be handled. 1027 * The number of ports in the list is implied by the length of the TLV item. 1028 */ 1029 #define TLV_TAG_L3XUDP_PORTS (0x102a0000) 1030 struct tlv_l3xudp_ports { 1031 uint32_t tag; 1032 uint32_t length; 1033 uint16_t ports[]; 1034 #define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16 1035 }; 1036 1037 #endif /* CI_MGMT_TLV_LAYOUT_H */ 1038