1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EF10_IMPL_H 34 #define _SYS_EF10_IMPL_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42 #elif EFSYS_OPT_HUNTINGTON 43 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44 #elif EFSYS_OPT_MEDFORD 45 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46 #endif 47 48 /* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53 #define EF10_NVRAM_CHUNK 0x80 54 55 /* 56 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned 57 * to an 8 descriptor boundary. 58 */ 59 #define EF10_RX_WPTR_ALIGN 8 60 61 /* 62 * Max byte offset into the packet the TCP header must start for the hardware 63 * to be able to parse the packet correctly. 64 */ 65 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 66 67 /* Invalid RSS context handle */ 68 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 69 70 71 /* EV */ 72 73 __checkReturn efx_rc_t 74 ef10_ev_init( 75 __in efx_nic_t *enp); 76 77 void 78 ef10_ev_fini( 79 __in efx_nic_t *enp); 80 81 __checkReturn efx_rc_t 82 ef10_ev_qcreate( 83 __in efx_nic_t *enp, 84 __in unsigned int index, 85 __in efsys_mem_t *esmp, 86 __in size_t ndescs, 87 __in uint32_t id, 88 __in uint32_t us, 89 __in uint32_t flags, 90 __in efx_evq_t *eep); 91 92 void 93 ef10_ev_qdestroy( 94 __in efx_evq_t *eep); 95 96 __checkReturn efx_rc_t 97 ef10_ev_qprime( 98 __in efx_evq_t *eep, 99 __in unsigned int count); 100 101 void 102 ef10_ev_qpost( 103 __in efx_evq_t *eep, 104 __in uint16_t data); 105 106 __checkReturn efx_rc_t 107 ef10_ev_qmoderate( 108 __in efx_evq_t *eep, 109 __in unsigned int us); 110 111 #if EFSYS_OPT_QSTATS 112 void 113 ef10_ev_qstats_update( 114 __in efx_evq_t *eep, 115 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 116 #endif /* EFSYS_OPT_QSTATS */ 117 118 void 119 ef10_ev_rxlabel_init( 120 __in efx_evq_t *eep, 121 __in efx_rxq_t *erp, 122 __in unsigned int label, 123 __in efx_rxq_type_t type); 124 125 void 126 ef10_ev_rxlabel_fini( 127 __in efx_evq_t *eep, 128 __in unsigned int label); 129 130 /* INTR */ 131 132 __checkReturn efx_rc_t 133 ef10_intr_init( 134 __in efx_nic_t *enp, 135 __in efx_intr_type_t type, 136 __in efsys_mem_t *esmp); 137 138 void 139 ef10_intr_enable( 140 __in efx_nic_t *enp); 141 142 void 143 ef10_intr_disable( 144 __in efx_nic_t *enp); 145 146 void 147 ef10_intr_disable_unlocked( 148 __in efx_nic_t *enp); 149 150 __checkReturn efx_rc_t 151 ef10_intr_trigger( 152 __in efx_nic_t *enp, 153 __in unsigned int level); 154 155 void 156 ef10_intr_status_line( 157 __in efx_nic_t *enp, 158 __out boolean_t *fatalp, 159 __out uint32_t *qmaskp); 160 161 void 162 ef10_intr_status_message( 163 __in efx_nic_t *enp, 164 __in unsigned int message, 165 __out boolean_t *fatalp); 166 167 void 168 ef10_intr_fatal( 169 __in efx_nic_t *enp); 170 void 171 ef10_intr_fini( 172 __in efx_nic_t *enp); 173 174 /* NIC */ 175 176 extern __checkReturn efx_rc_t 177 ef10_nic_probe( 178 __in efx_nic_t *enp); 179 180 extern __checkReturn efx_rc_t 181 ef10_nic_set_drv_limits( 182 __inout efx_nic_t *enp, 183 __in efx_drv_limits_t *edlp); 184 185 extern __checkReturn efx_rc_t 186 ef10_nic_get_vi_pool( 187 __in efx_nic_t *enp, 188 __out uint32_t *vi_countp); 189 190 extern __checkReturn efx_rc_t 191 ef10_nic_get_bar_region( 192 __in efx_nic_t *enp, 193 __in efx_nic_region_t region, 194 __out uint32_t *offsetp, 195 __out size_t *sizep); 196 197 extern __checkReturn efx_rc_t 198 ef10_nic_reset( 199 __in efx_nic_t *enp); 200 201 extern __checkReturn efx_rc_t 202 ef10_nic_init( 203 __in efx_nic_t *enp); 204 205 #if EFSYS_OPT_DIAG 206 207 extern __checkReturn efx_rc_t 208 ef10_nic_register_test( 209 __in efx_nic_t *enp); 210 211 #endif /* EFSYS_OPT_DIAG */ 212 213 extern void 214 ef10_nic_fini( 215 __in efx_nic_t *enp); 216 217 extern void 218 ef10_nic_unprobe( 219 __in efx_nic_t *enp); 220 221 222 /* MAC */ 223 224 extern __checkReturn efx_rc_t 225 ef10_mac_poll( 226 __in efx_nic_t *enp, 227 __out efx_link_mode_t *link_modep); 228 229 extern __checkReturn efx_rc_t 230 ef10_mac_up( 231 __in efx_nic_t *enp, 232 __out boolean_t *mac_upp); 233 234 extern __checkReturn efx_rc_t 235 ef10_mac_addr_set( 236 __in efx_nic_t *enp); 237 238 extern __checkReturn efx_rc_t 239 ef10_mac_pdu_set( 240 __in efx_nic_t *enp); 241 242 extern __checkReturn efx_rc_t 243 ef10_mac_pdu_get( 244 __in efx_nic_t *enp, 245 __out size_t *pdu); 246 247 extern __checkReturn efx_rc_t 248 ef10_mac_reconfigure( 249 __in efx_nic_t *enp); 250 251 extern __checkReturn efx_rc_t 252 ef10_mac_multicast_list_set( 253 __in efx_nic_t *enp); 254 255 extern __checkReturn efx_rc_t 256 ef10_mac_filter_default_rxq_set( 257 __in efx_nic_t *enp, 258 __in efx_rxq_t *erp, 259 __in boolean_t using_rss); 260 261 extern void 262 ef10_mac_filter_default_rxq_clear( 263 __in efx_nic_t *enp); 264 265 #if EFSYS_OPT_LOOPBACK 266 267 extern __checkReturn efx_rc_t 268 ef10_mac_loopback_set( 269 __in efx_nic_t *enp, 270 __in efx_link_mode_t link_mode, 271 __in efx_loopback_type_t loopback_type); 272 273 #endif /* EFSYS_OPT_LOOPBACK */ 274 275 #if EFSYS_OPT_MAC_STATS 276 277 extern __checkReturn efx_rc_t 278 ef10_mac_stats_get_mask( 279 __in efx_nic_t *enp, 280 __inout_bcount(mask_size) uint32_t *maskp, 281 __in size_t mask_size); 282 283 extern __checkReturn efx_rc_t 284 ef10_mac_stats_update( 285 __in efx_nic_t *enp, 286 __in efsys_mem_t *esmp, 287 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 288 __inout_opt uint32_t *generationp); 289 290 #endif /* EFSYS_OPT_MAC_STATS */ 291 292 293 /* MCDI */ 294 295 #if EFSYS_OPT_MCDI 296 297 extern __checkReturn efx_rc_t 298 ef10_mcdi_init( 299 __in efx_nic_t *enp, 300 __in const efx_mcdi_transport_t *mtp); 301 302 extern void 303 ef10_mcdi_fini( 304 __in efx_nic_t *enp); 305 306 extern void 307 ef10_mcdi_send_request( 308 __in efx_nic_t *enp, 309 __in_bcount(hdr_len) void *hdrp, 310 __in size_t hdr_len, 311 __in_bcount(sdu_len) void *sdup, 312 __in size_t sdu_len); 313 314 extern __checkReturn boolean_t 315 ef10_mcdi_poll_response( 316 __in efx_nic_t *enp); 317 318 extern void 319 ef10_mcdi_read_response( 320 __in efx_nic_t *enp, 321 __out_bcount(length) void *bufferp, 322 __in size_t offset, 323 __in size_t length); 324 325 extern efx_rc_t 326 ef10_mcdi_poll_reboot( 327 __in efx_nic_t *enp); 328 329 extern __checkReturn efx_rc_t 330 ef10_mcdi_feature_supported( 331 __in efx_nic_t *enp, 332 __in efx_mcdi_feature_id_t id, 333 __out boolean_t *supportedp); 334 335 extern void 336 ef10_mcdi_get_timeout( 337 __in efx_nic_t *enp, 338 __in efx_mcdi_req_t *emrp, 339 __out uint32_t *timeoutp); 340 341 #endif /* EFSYS_OPT_MCDI */ 342 343 /* NVRAM */ 344 345 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 346 347 extern __checkReturn efx_rc_t 348 ef10_nvram_buf_read_tlv( 349 __in efx_nic_t *enp, 350 __in_bcount(max_seg_size) caddr_t seg_data, 351 __in size_t max_seg_size, 352 __in uint32_t tag, 353 __deref_out_bcount_opt(*sizep) caddr_t *datap, 354 __out size_t *sizep); 355 356 extern __checkReturn efx_rc_t 357 ef10_nvram_buf_write_tlv( 358 __inout_bcount(partn_size) caddr_t partn_data, 359 __in size_t partn_size, 360 __in uint32_t tag, 361 __in_bcount(tag_size) caddr_t tag_data, 362 __in size_t tag_size, 363 __out size_t *total_lengthp); 364 365 extern __checkReturn efx_rc_t 366 ef10_nvram_partn_read_tlv( 367 __in efx_nic_t *enp, 368 __in uint32_t partn, 369 __in uint32_t tag, 370 __deref_out_bcount_opt(*sizep) caddr_t *datap, 371 __out size_t *sizep); 372 373 extern __checkReturn efx_rc_t 374 ef10_nvram_partn_write_tlv( 375 __in efx_nic_t *enp, 376 __in uint32_t partn, 377 __in uint32_t tag, 378 __in_bcount(size) caddr_t data, 379 __in size_t size); 380 381 extern __checkReturn efx_rc_t 382 ef10_nvram_partn_write_segment_tlv( 383 __in efx_nic_t *enp, 384 __in uint32_t partn, 385 __in uint32_t tag, 386 __in_bcount(size) caddr_t data, 387 __in size_t size, 388 __in boolean_t all_segments); 389 390 extern __checkReturn efx_rc_t 391 ef10_nvram_partn_lock( 392 __in efx_nic_t *enp, 393 __in uint32_t partn); 394 395 extern __checkReturn efx_rc_t 396 ef10_nvram_partn_unlock( 397 __in efx_nic_t *enp, 398 __in uint32_t partn, 399 __out_opt uint32_t *resultp); 400 401 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 402 403 #if EFSYS_OPT_NVRAM 404 405 #if EFSYS_OPT_DIAG 406 407 extern __checkReturn efx_rc_t 408 ef10_nvram_test( 409 __in efx_nic_t *enp); 410 411 #endif /* EFSYS_OPT_DIAG */ 412 413 extern __checkReturn efx_rc_t 414 ef10_nvram_type_to_partn( 415 __in efx_nic_t *enp, 416 __in efx_nvram_type_t type, 417 __out uint32_t *partnp); 418 419 extern __checkReturn efx_rc_t 420 ef10_nvram_partn_size( 421 __in efx_nic_t *enp, 422 __in uint32_t partn, 423 __out size_t *sizep); 424 425 extern __checkReturn efx_rc_t 426 ef10_nvram_partn_rw_start( 427 __in efx_nic_t *enp, 428 __in uint32_t partn, 429 __out size_t *chunk_sizep); 430 431 extern __checkReturn efx_rc_t 432 ef10_nvram_partn_read_mode( 433 __in efx_nic_t *enp, 434 __in uint32_t partn, 435 __in unsigned int offset, 436 __out_bcount(size) caddr_t data, 437 __in size_t size, 438 __in uint32_t mode); 439 440 extern __checkReturn efx_rc_t 441 ef10_nvram_partn_read( 442 __in efx_nic_t *enp, 443 __in uint32_t partn, 444 __in unsigned int offset, 445 __out_bcount(size) caddr_t data, 446 __in size_t size); 447 448 extern __checkReturn efx_rc_t 449 ef10_nvram_partn_read_backup( 450 __in efx_nic_t *enp, 451 __in uint32_t partn, 452 __in unsigned int offset, 453 __out_bcount(size) caddr_t data, 454 __in size_t size); 455 456 extern __checkReturn efx_rc_t 457 ef10_nvram_partn_erase( 458 __in efx_nic_t *enp, 459 __in uint32_t partn, 460 __in unsigned int offset, 461 __in size_t size); 462 463 extern __checkReturn efx_rc_t 464 ef10_nvram_partn_write( 465 __in efx_nic_t *enp, 466 __in uint32_t partn, 467 __in unsigned int offset, 468 __out_bcount(size) caddr_t data, 469 __in size_t size); 470 471 extern __checkReturn efx_rc_t 472 ef10_nvram_partn_rw_finish( 473 __in efx_nic_t *enp, 474 __in uint32_t partn, 475 __out_opt uint32_t *verify_resultp); 476 477 extern __checkReturn efx_rc_t 478 ef10_nvram_partn_get_version( 479 __in efx_nic_t *enp, 480 __in uint32_t partn, 481 __out uint32_t *subtypep, 482 __out_ecount(4) uint16_t version[4]); 483 484 extern __checkReturn efx_rc_t 485 ef10_nvram_partn_set_version( 486 __in efx_nic_t *enp, 487 __in uint32_t partn, 488 __in_ecount(4) uint16_t version[4]); 489 490 extern __checkReturn efx_rc_t 491 ef10_nvram_buffer_validate( 492 __in efx_nic_t *enp, 493 __in uint32_t partn, 494 __in_bcount(buffer_size) 495 caddr_t bufferp, 496 __in size_t buffer_size); 497 498 extern __checkReturn efx_rc_t 499 ef10_nvram_buffer_create( 500 __in efx_nic_t *enp, 501 __in uint16_t partn_type, 502 __in_bcount(buffer_size) 503 caddr_t bufferp, 504 __in size_t buffer_size); 505 506 extern __checkReturn efx_rc_t 507 ef10_nvram_buffer_find_item_start( 508 __in_bcount(buffer_size) 509 caddr_t bufferp, 510 __in size_t buffer_size, 511 __out uint32_t *startp); 512 513 extern __checkReturn efx_rc_t 514 ef10_nvram_buffer_find_end( 515 __in_bcount(buffer_size) 516 caddr_t bufferp, 517 __in size_t buffer_size, 518 __in uint32_t offset, 519 __out uint32_t *endp); 520 521 extern __checkReturn __success(return != B_FALSE) boolean_t 522 ef10_nvram_buffer_find_item( 523 __in_bcount(buffer_size) 524 caddr_t bufferp, 525 __in size_t buffer_size, 526 __in uint32_t offset, 527 __out uint32_t *startp, 528 __out uint32_t *lengthp); 529 530 extern __checkReturn efx_rc_t 531 ef10_nvram_buffer_get_item( 532 __in_bcount(buffer_size) 533 caddr_t bufferp, 534 __in size_t buffer_size, 535 __in uint32_t offset, 536 __in uint32_t length, 537 __out_bcount_part(item_max_size, *lengthp) 538 caddr_t itemp, 539 __in size_t item_max_size, 540 __out uint32_t *lengthp); 541 542 extern __checkReturn efx_rc_t 543 ef10_nvram_buffer_insert_item( 544 __in_bcount(buffer_size) 545 caddr_t bufferp, 546 __in size_t buffer_size, 547 __in uint32_t offset, 548 __in_bcount(length) caddr_t keyp, 549 __in uint32_t length, 550 __out uint32_t *lengthp); 551 552 extern __checkReturn efx_rc_t 553 ef10_nvram_buffer_delete_item( 554 __in_bcount(buffer_size) 555 caddr_t bufferp, 556 __in size_t buffer_size, 557 __in uint32_t offset, 558 __in uint32_t length, 559 __in uint32_t end); 560 561 extern __checkReturn efx_rc_t 562 ef10_nvram_buffer_finish( 563 __in_bcount(buffer_size) 564 caddr_t bufferp, 565 __in size_t buffer_size); 566 567 #endif /* EFSYS_OPT_NVRAM */ 568 569 570 /* PHY */ 571 572 typedef struct ef10_link_state_s { 573 uint32_t els_adv_cap_mask; 574 uint32_t els_lp_cap_mask; 575 unsigned int els_fcntl; 576 efx_link_mode_t els_link_mode; 577 #if EFSYS_OPT_LOOPBACK 578 efx_loopback_type_t els_loopback; 579 #endif 580 boolean_t els_mac_up; 581 } ef10_link_state_t; 582 583 extern void 584 ef10_phy_link_ev( 585 __in efx_nic_t *enp, 586 __in efx_qword_t *eqp, 587 __out efx_link_mode_t *link_modep); 588 589 extern __checkReturn efx_rc_t 590 ef10_phy_get_link( 591 __in efx_nic_t *enp, 592 __out ef10_link_state_t *elsp); 593 594 extern __checkReturn efx_rc_t 595 ef10_phy_power( 596 __in efx_nic_t *enp, 597 __in boolean_t on); 598 599 extern __checkReturn efx_rc_t 600 ef10_phy_reconfigure( 601 __in efx_nic_t *enp); 602 603 extern __checkReturn efx_rc_t 604 ef10_phy_verify( 605 __in efx_nic_t *enp); 606 607 extern __checkReturn efx_rc_t 608 ef10_phy_oui_get( 609 __in efx_nic_t *enp, 610 __out uint32_t *ouip); 611 612 #if EFSYS_OPT_PHY_STATS 613 614 extern __checkReturn efx_rc_t 615 ef10_phy_stats_update( 616 __in efx_nic_t *enp, 617 __in efsys_mem_t *esmp, 618 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 619 620 #endif /* EFSYS_OPT_PHY_STATS */ 621 622 #if EFSYS_OPT_BIST 623 624 extern __checkReturn efx_rc_t 625 ef10_bist_enable_offline( 626 __in efx_nic_t *enp); 627 628 extern __checkReturn efx_rc_t 629 ef10_bist_start( 630 __in efx_nic_t *enp, 631 __in efx_bist_type_t type); 632 633 extern __checkReturn efx_rc_t 634 ef10_bist_poll( 635 __in efx_nic_t *enp, 636 __in efx_bist_type_t type, 637 __out efx_bist_result_t *resultp, 638 __out_opt __drv_when(count > 0, __notnull) 639 uint32_t *value_maskp, 640 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 641 unsigned long *valuesp, 642 __in size_t count); 643 644 extern void 645 ef10_bist_stop( 646 __in efx_nic_t *enp, 647 __in efx_bist_type_t type); 648 649 #endif /* EFSYS_OPT_BIST */ 650 651 /* TX */ 652 653 extern __checkReturn efx_rc_t 654 ef10_tx_init( 655 __in efx_nic_t *enp); 656 657 extern void 658 ef10_tx_fini( 659 __in efx_nic_t *enp); 660 661 extern __checkReturn efx_rc_t 662 ef10_tx_qcreate( 663 __in efx_nic_t *enp, 664 __in unsigned int index, 665 __in unsigned int label, 666 __in efsys_mem_t *esmp, 667 __in size_t ndescs, 668 __in uint32_t id, 669 __in uint16_t flags, 670 __in efx_evq_t *eep, 671 __in efx_txq_t *etp, 672 __out unsigned int *addedp); 673 674 extern void 675 ef10_tx_qdestroy( 676 __in efx_txq_t *etp); 677 678 extern __checkReturn efx_rc_t 679 ef10_tx_qpost( 680 __in efx_txq_t *etp, 681 __in_ecount(ndescs) efx_buffer_t *ebp, 682 __in unsigned int ndescs, 683 __in unsigned int completed, 684 __inout unsigned int *addedp); 685 686 extern void 687 ef10_tx_qpush( 688 __in efx_txq_t *etp, 689 __in unsigned int added, 690 __in unsigned int pushed); 691 692 #if EFSYS_OPT_RX_PACKED_STREAM 693 extern void 694 ef10_rx_qpush_ps_credits( 695 __in efx_rxq_t *erp); 696 697 extern __checkReturn uint8_t * 698 ef10_rx_qps_packet_info( 699 __in efx_rxq_t *erp, 700 __in uint8_t *buffer, 701 __in uint32_t buffer_length, 702 __in uint32_t current_offset, 703 __out uint16_t *lengthp, 704 __out uint32_t *next_offsetp, 705 __out uint32_t *timestamp); 706 #endif 707 708 extern __checkReturn efx_rc_t 709 ef10_tx_qpace( 710 __in efx_txq_t *etp, 711 __in unsigned int ns); 712 713 extern __checkReturn efx_rc_t 714 ef10_tx_qflush( 715 __in efx_txq_t *etp); 716 717 extern void 718 ef10_tx_qenable( 719 __in efx_txq_t *etp); 720 721 extern __checkReturn efx_rc_t 722 ef10_tx_qpio_enable( 723 __in efx_txq_t *etp); 724 725 extern void 726 ef10_tx_qpio_disable( 727 __in efx_txq_t *etp); 728 729 extern __checkReturn efx_rc_t 730 ef10_tx_qpio_write( 731 __in efx_txq_t *etp, 732 __in_ecount(buf_length) uint8_t *buffer, 733 __in size_t buf_length, 734 __in size_t pio_buf_offset); 735 736 extern __checkReturn efx_rc_t 737 ef10_tx_qpio_post( 738 __in efx_txq_t *etp, 739 __in size_t pkt_length, 740 __in unsigned int completed, 741 __inout unsigned int *addedp); 742 743 extern __checkReturn efx_rc_t 744 ef10_tx_qdesc_post( 745 __in efx_txq_t *etp, 746 __in_ecount(n) efx_desc_t *ed, 747 __in unsigned int n, 748 __in unsigned int completed, 749 __inout unsigned int *addedp); 750 751 extern void 752 ef10_tx_qdesc_dma_create( 753 __in efx_txq_t *etp, 754 __in efsys_dma_addr_t addr, 755 __in size_t size, 756 __in boolean_t eop, 757 __out efx_desc_t *edp); 758 759 extern void 760 ef10_tx_qdesc_tso_create( 761 __in efx_txq_t *etp, 762 __in uint16_t ipv4_id, 763 __in uint32_t tcp_seq, 764 __in uint8_t tcp_flags, 765 __out efx_desc_t *edp); 766 767 extern void 768 ef10_tx_qdesc_tso2_create( 769 __in efx_txq_t *etp, 770 __in uint16_t ipv4_id, 771 __in uint32_t tcp_seq, 772 __in uint16_t tcp_mss, 773 __out_ecount(count) efx_desc_t *edp, 774 __in int count); 775 776 extern void 777 ef10_tx_qdesc_vlantci_create( 778 __in efx_txq_t *etp, 779 __in uint16_t vlan_tci, 780 __out efx_desc_t *edp); 781 782 783 #if EFSYS_OPT_QSTATS 784 785 extern void 786 ef10_tx_qstats_update( 787 __in efx_txq_t *etp, 788 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 789 790 #endif /* EFSYS_OPT_QSTATS */ 791 792 typedef uint32_t efx_piobuf_handle_t; 793 794 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1) 795 796 extern __checkReturn efx_rc_t 797 ef10_nic_pio_alloc( 798 __inout efx_nic_t *enp, 799 __out uint32_t *bufnump, 800 __out efx_piobuf_handle_t *handlep, 801 __out uint32_t *blknump, 802 __out uint32_t *offsetp, 803 __out size_t *sizep); 804 805 extern __checkReturn efx_rc_t 806 ef10_nic_pio_free( 807 __inout efx_nic_t *enp, 808 __in uint32_t bufnum, 809 __in uint32_t blknum); 810 811 extern __checkReturn efx_rc_t 812 ef10_nic_pio_link( 813 __inout efx_nic_t *enp, 814 __in uint32_t vi_index, 815 __in efx_piobuf_handle_t handle); 816 817 extern __checkReturn efx_rc_t 818 ef10_nic_pio_unlink( 819 __inout efx_nic_t *enp, 820 __in uint32_t vi_index); 821 822 823 /* VPD */ 824 825 #if EFSYS_OPT_VPD 826 827 extern __checkReturn efx_rc_t 828 ef10_vpd_init( 829 __in efx_nic_t *enp); 830 831 extern __checkReturn efx_rc_t 832 ef10_vpd_size( 833 __in efx_nic_t *enp, 834 __out size_t *sizep); 835 836 extern __checkReturn efx_rc_t 837 ef10_vpd_read( 838 __in efx_nic_t *enp, 839 __out_bcount(size) caddr_t data, 840 __in size_t size); 841 842 extern __checkReturn efx_rc_t 843 ef10_vpd_verify( 844 __in efx_nic_t *enp, 845 __in_bcount(size) caddr_t data, 846 __in size_t size); 847 848 extern __checkReturn efx_rc_t 849 ef10_vpd_reinit( 850 __in efx_nic_t *enp, 851 __in_bcount(size) caddr_t data, 852 __in size_t size); 853 854 extern __checkReturn efx_rc_t 855 ef10_vpd_get( 856 __in efx_nic_t *enp, 857 __in_bcount(size) caddr_t data, 858 __in size_t size, 859 __inout efx_vpd_value_t *evvp); 860 861 extern __checkReturn efx_rc_t 862 ef10_vpd_set( 863 __in efx_nic_t *enp, 864 __in_bcount(size) caddr_t data, 865 __in size_t size, 866 __in efx_vpd_value_t *evvp); 867 868 extern __checkReturn efx_rc_t 869 ef10_vpd_next( 870 __in efx_nic_t *enp, 871 __in_bcount(size) caddr_t data, 872 __in size_t size, 873 __out efx_vpd_value_t *evvp, 874 __inout unsigned int *contp); 875 876 extern __checkReturn efx_rc_t 877 ef10_vpd_write( 878 __in efx_nic_t *enp, 879 __in_bcount(size) caddr_t data, 880 __in size_t size); 881 882 extern void 883 ef10_vpd_fini( 884 __in efx_nic_t *enp); 885 886 #endif /* EFSYS_OPT_VPD */ 887 888 889 /* RX */ 890 891 extern __checkReturn efx_rc_t 892 ef10_rx_init( 893 __in efx_nic_t *enp); 894 895 #if EFSYS_OPT_RX_SCATTER 896 extern __checkReturn efx_rc_t 897 ef10_rx_scatter_enable( 898 __in efx_nic_t *enp, 899 __in unsigned int buf_size); 900 #endif /* EFSYS_OPT_RX_SCATTER */ 901 902 903 #if EFSYS_OPT_RX_SCALE 904 905 extern __checkReturn efx_rc_t 906 ef10_rx_scale_context_alloc( 907 __in efx_nic_t *enp, 908 __in efx_rx_scale_context_type_t type, 909 __in uint32_t num_queues, 910 __out uint32_t *rss_contextp); 911 912 extern __checkReturn efx_rc_t 913 ef10_rx_scale_context_free( 914 __in efx_nic_t *enp, 915 __in uint32_t rss_context); 916 917 extern __checkReturn efx_rc_t 918 ef10_rx_scale_mode_set( 919 __in efx_nic_t *enp, 920 __in uint32_t rss_context, 921 __in efx_rx_hash_alg_t alg, 922 __in efx_rx_hash_type_t type, 923 __in boolean_t insert); 924 925 extern __checkReturn efx_rc_t 926 ef10_rx_scale_key_set( 927 __in efx_nic_t *enp, 928 __in uint32_t rss_context, 929 __in_ecount(n) uint8_t *key, 930 __in size_t n); 931 932 extern __checkReturn efx_rc_t 933 ef10_rx_scale_tbl_set( 934 __in efx_nic_t *enp, 935 __in uint32_t rss_context, 936 __in_ecount(n) unsigned int *table, 937 __in size_t n); 938 939 extern __checkReturn uint32_t 940 ef10_rx_prefix_hash( 941 __in efx_nic_t *enp, 942 __in efx_rx_hash_alg_t func, 943 __in uint8_t *buffer); 944 945 #endif /* EFSYS_OPT_RX_SCALE */ 946 947 extern __checkReturn efx_rc_t 948 ef10_rx_prefix_pktlen( 949 __in efx_nic_t *enp, 950 __in uint8_t *buffer, 951 __out uint16_t *lengthp); 952 953 extern void 954 ef10_rx_qpost( 955 __in efx_rxq_t *erp, 956 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 957 __in size_t size, 958 __in unsigned int ndescs, 959 __in unsigned int completed, 960 __in unsigned int added); 961 962 extern void 963 ef10_rx_qpush( 964 __in efx_rxq_t *erp, 965 __in unsigned int added, 966 __inout unsigned int *pushedp); 967 968 extern __checkReturn efx_rc_t 969 ef10_rx_qflush( 970 __in efx_rxq_t *erp); 971 972 extern void 973 ef10_rx_qenable( 974 __in efx_rxq_t *erp); 975 976 extern __checkReturn efx_rc_t 977 ef10_rx_qcreate( 978 __in efx_nic_t *enp, 979 __in unsigned int index, 980 __in unsigned int label, 981 __in efx_rxq_type_t type, 982 __in uint32_t type_data, 983 __in efsys_mem_t *esmp, 984 __in size_t ndescs, 985 __in uint32_t id, 986 __in unsigned int flags, 987 __in efx_evq_t *eep, 988 __in efx_rxq_t *erp); 989 990 extern void 991 ef10_rx_qdestroy( 992 __in efx_rxq_t *erp); 993 994 extern void 995 ef10_rx_fini( 996 __in efx_nic_t *enp); 997 998 #if EFSYS_OPT_FILTER 999 1000 typedef struct ef10_filter_handle_s { 1001 uint32_t efh_lo; 1002 uint32_t efh_hi; 1003 } ef10_filter_handle_t; 1004 1005 typedef struct ef10_filter_entry_s { 1006 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 1007 ef10_filter_handle_t efe_handle; 1008 } ef10_filter_entry_t; 1009 1010 /* 1011 * BUSY flag indicates that an update is in progress. 1012 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 1013 */ 1014 #define EFX_EF10_FILTER_FLAG_BUSY 1U 1015 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 1016 #define EFX_EF10_FILTER_FLAGS 3U 1017 1018 /* 1019 * Size of the hash table used by the driver. Doesn't need to be the 1020 * same size as the hardware's table. 1021 */ 1022 #define EFX_EF10_FILTER_TBL_ROWS 8192 1023 1024 /* Only need to allow for one directed and one unknown unicast filter */ 1025 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 1026 1027 /* Allow for the broadcast address to be added to the multicast list */ 1028 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 1029 1030 /* 1031 * For encapsulated packets, there is one filter each for each combination of 1032 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or 1033 * multicast inner frames. 1034 */ 1035 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12 1036 1037 typedef struct ef10_filter_table_s { 1038 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 1039 efx_rxq_t *eft_default_rxq; 1040 boolean_t eft_using_rss; 1041 uint32_t eft_unicst_filter_indexes[ 1042 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 1043 uint32_t eft_unicst_filter_count; 1044 uint32_t eft_mulcst_filter_indexes[ 1045 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 1046 uint32_t eft_mulcst_filter_count; 1047 boolean_t eft_using_all_mulcst; 1048 uint32_t eft_encap_filter_indexes[ 1049 EFX_EF10_FILTER_ENCAP_FILTERS_MAX]; 1050 uint32_t eft_encap_filter_count; 1051 } ef10_filter_table_t; 1052 1053 __checkReturn efx_rc_t 1054 ef10_filter_init( 1055 __in efx_nic_t *enp); 1056 1057 void 1058 ef10_filter_fini( 1059 __in efx_nic_t *enp); 1060 1061 __checkReturn efx_rc_t 1062 ef10_filter_restore( 1063 __in efx_nic_t *enp); 1064 1065 __checkReturn efx_rc_t 1066 ef10_filter_add( 1067 __in efx_nic_t *enp, 1068 __inout efx_filter_spec_t *spec, 1069 __in boolean_t may_replace); 1070 1071 __checkReturn efx_rc_t 1072 ef10_filter_delete( 1073 __in efx_nic_t *enp, 1074 __inout efx_filter_spec_t *spec); 1075 1076 extern __checkReturn efx_rc_t 1077 ef10_filter_supported_filters( 1078 __in efx_nic_t *enp, 1079 __out_ecount(buffer_length) uint32_t *buffer, 1080 __in size_t buffer_length, 1081 __out size_t *list_lengthp); 1082 1083 extern __checkReturn efx_rc_t 1084 ef10_filter_reconfigure( 1085 __in efx_nic_t *enp, 1086 __in_ecount(6) uint8_t const *mac_addr, 1087 __in boolean_t all_unicst, 1088 __in boolean_t mulcst, 1089 __in boolean_t all_mulcst, 1090 __in boolean_t brdcst, 1091 __in_ecount(6*count) uint8_t const *addrs, 1092 __in uint32_t count); 1093 1094 extern void 1095 ef10_filter_get_default_rxq( 1096 __in efx_nic_t *enp, 1097 __out efx_rxq_t **erpp, 1098 __out boolean_t *using_rss); 1099 1100 extern void 1101 ef10_filter_default_rxq_set( 1102 __in efx_nic_t *enp, 1103 __in efx_rxq_t *erp, 1104 __in boolean_t using_rss); 1105 1106 extern void 1107 ef10_filter_default_rxq_clear( 1108 __in efx_nic_t *enp); 1109 1110 1111 #endif /* EFSYS_OPT_FILTER */ 1112 1113 extern __checkReturn efx_rc_t 1114 efx_mcdi_get_function_info( 1115 __in efx_nic_t *enp, 1116 __out uint32_t *pfp, 1117 __out_opt uint32_t *vfp); 1118 1119 extern __checkReturn efx_rc_t 1120 efx_mcdi_privilege_mask( 1121 __in efx_nic_t *enp, 1122 __in uint32_t pf, 1123 __in uint32_t vf, 1124 __out uint32_t *maskp); 1125 1126 extern __checkReturn efx_rc_t 1127 efx_mcdi_get_port_assignment( 1128 __in efx_nic_t *enp, 1129 __out uint32_t *portp); 1130 1131 extern __checkReturn efx_rc_t 1132 efx_mcdi_get_port_modes( 1133 __in efx_nic_t *enp, 1134 __out uint32_t *modesp, 1135 __out_opt uint32_t *current_modep); 1136 1137 extern __checkReturn efx_rc_t 1138 ef10_nic_get_port_mode_bandwidth( 1139 __in uint32_t port_mode, 1140 __out uint32_t *bandwidth_mbpsp); 1141 1142 extern __checkReturn efx_rc_t 1143 efx_mcdi_get_mac_address_pf( 1144 __in efx_nic_t *enp, 1145 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1146 1147 extern __checkReturn efx_rc_t 1148 efx_mcdi_get_mac_address_vf( 1149 __in efx_nic_t *enp, 1150 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1151 1152 extern __checkReturn efx_rc_t 1153 efx_mcdi_get_clock( 1154 __in efx_nic_t *enp, 1155 __out uint32_t *sys_freqp, 1156 __out uint32_t *dpcpu_freqp); 1157 1158 1159 extern __checkReturn efx_rc_t 1160 efx_mcdi_get_vector_cfg( 1161 __in efx_nic_t *enp, 1162 __out_opt uint32_t *vec_basep, 1163 __out_opt uint32_t *pf_nvecp, 1164 __out_opt uint32_t *vf_nvecp); 1165 1166 extern __checkReturn efx_rc_t 1167 ef10_get_datapath_caps( 1168 __in efx_nic_t *enp); 1169 1170 extern __checkReturn efx_rc_t 1171 ef10_get_privilege_mask( 1172 __in efx_nic_t *enp, 1173 __out uint32_t *maskp); 1174 1175 extern __checkReturn efx_rc_t 1176 ef10_external_port_mapping( 1177 __in efx_nic_t *enp, 1178 __in uint32_t port, 1179 __out uint8_t *external_portp); 1180 1181 #if EFSYS_OPT_RX_PACKED_STREAM 1182 1183 /* Data space per credit in packed stream mode */ 1184 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16) 1185 1186 /* 1187 * Received packets are always aligned at this boundary. Also there always 1188 * exists a gap of this size between packets. 1189 * (see SF-112241-TC, 4.5) 1190 */ 1191 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64 1192 1193 /* 1194 * Size of a pseudo-header prepended to received packets 1195 * in packed stream mode 1196 */ 1197 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8 1198 1199 /* Minimum space for packet in packed stream mode */ 1200 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \ 1201 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \ 1202 EFX_MAC_PDU_MIN + \ 1203 EFX_RX_PACKED_STREAM_ALIGNMENT, \ 1204 EFX_RX_PACKED_STREAM_ALIGNMENT) 1205 1206 /* Maximum number of credits */ 1207 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127 1208 1209 #endif /* EFSYS_OPT_RX_PACKED_STREAM */ 1210 1211 #ifdef __cplusplus 1212 } 1213 #endif 1214 1215 #endif /* _SYS_EF10_IMPL_H */ 1216