1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EF10_IMPL_H 34 #define _SYS_EF10_IMPL_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42 #elif EFSYS_OPT_HUNTINGTON 43 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44 #elif EFSYS_OPT_MEDFORD 45 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46 #endif 47 48 /* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53 #define EF10_NVRAM_CHUNK 0x80 54 55 /* Alignment requirement for value written to RX WPTR: 56 * the WPTR must be aligned to an 8 descriptor boundary 57 */ 58 #define EF10_RX_WPTR_ALIGN 8 59 60 /* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66 /* Invalid RSS context handle */ 67 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70 /* EV */ 71 72 __checkReturn efx_rc_t 73 ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77 ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81 ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in uint32_t us, 88 __in uint32_t flags, 89 __in efx_evq_t *eep); 90 91 void 92 ef10_ev_qdestroy( 93 __in efx_evq_t *eep); 94 95 __checkReturn efx_rc_t 96 ef10_ev_qprime( 97 __in efx_evq_t *eep, 98 __in unsigned int count); 99 100 void 101 ef10_ev_qpost( 102 __in efx_evq_t *eep, 103 __in uint16_t data); 104 105 __checkReturn efx_rc_t 106 ef10_ev_qmoderate( 107 __in efx_evq_t *eep, 108 __in unsigned int us); 109 110 #if EFSYS_OPT_QSTATS 111 void 112 ef10_ev_qstats_update( 113 __in efx_evq_t *eep, 114 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 115 #endif /* EFSYS_OPT_QSTATS */ 116 117 void 118 ef10_ev_rxlabel_init( 119 __in efx_evq_t *eep, 120 __in efx_rxq_t *erp, 121 __in unsigned int label); 122 123 void 124 ef10_ev_rxlabel_fini( 125 __in efx_evq_t *eep, 126 __in unsigned int label); 127 128 /* INTR */ 129 130 __checkReturn efx_rc_t 131 ef10_intr_init( 132 __in efx_nic_t *enp, 133 __in efx_intr_type_t type, 134 __in efsys_mem_t *esmp); 135 136 void 137 ef10_intr_enable( 138 __in efx_nic_t *enp); 139 140 void 141 ef10_intr_disable( 142 __in efx_nic_t *enp); 143 144 void 145 ef10_intr_disable_unlocked( 146 __in efx_nic_t *enp); 147 148 __checkReturn efx_rc_t 149 ef10_intr_trigger( 150 __in efx_nic_t *enp, 151 __in unsigned int level); 152 153 void 154 ef10_intr_status_line( 155 __in efx_nic_t *enp, 156 __out boolean_t *fatalp, 157 __out uint32_t *qmaskp); 158 159 void 160 ef10_intr_status_message( 161 __in efx_nic_t *enp, 162 __in unsigned int message, 163 __out boolean_t *fatalp); 164 165 void 166 ef10_intr_fatal( 167 __in efx_nic_t *enp); 168 void 169 ef10_intr_fini( 170 __in efx_nic_t *enp); 171 172 /* NIC */ 173 174 extern __checkReturn efx_rc_t 175 ef10_nic_probe( 176 __in efx_nic_t *enp); 177 178 extern __checkReturn efx_rc_t 179 ef10_nic_set_drv_limits( 180 __inout efx_nic_t *enp, 181 __in efx_drv_limits_t *edlp); 182 183 extern __checkReturn efx_rc_t 184 ef10_nic_get_vi_pool( 185 __in efx_nic_t *enp, 186 __out uint32_t *vi_countp); 187 188 extern __checkReturn efx_rc_t 189 ef10_nic_get_bar_region( 190 __in efx_nic_t *enp, 191 __in efx_nic_region_t region, 192 __out uint32_t *offsetp, 193 __out size_t *sizep); 194 195 extern __checkReturn efx_rc_t 196 ef10_nic_reset( 197 __in efx_nic_t *enp); 198 199 extern __checkReturn efx_rc_t 200 ef10_nic_init( 201 __in efx_nic_t *enp); 202 203 #if EFSYS_OPT_DIAG 204 205 extern __checkReturn efx_rc_t 206 ef10_nic_register_test( 207 __in efx_nic_t *enp); 208 209 #endif /* EFSYS_OPT_DIAG */ 210 211 extern void 212 ef10_nic_fini( 213 __in efx_nic_t *enp); 214 215 extern void 216 ef10_nic_unprobe( 217 __in efx_nic_t *enp); 218 219 220 /* MAC */ 221 222 extern __checkReturn efx_rc_t 223 ef10_mac_poll( 224 __in efx_nic_t *enp, 225 __out efx_link_mode_t *link_modep); 226 227 extern __checkReturn efx_rc_t 228 ef10_mac_up( 229 __in efx_nic_t *enp, 230 __out boolean_t *mac_upp); 231 232 extern __checkReturn efx_rc_t 233 ef10_mac_addr_set( 234 __in efx_nic_t *enp); 235 236 extern __checkReturn efx_rc_t 237 ef10_mac_pdu_set( 238 __in efx_nic_t *enp); 239 240 extern __checkReturn efx_rc_t 241 ef10_mac_pdu_get( 242 __in efx_nic_t *enp, 243 __out size_t *pdu); 244 245 extern __checkReturn efx_rc_t 246 ef10_mac_reconfigure( 247 __in efx_nic_t *enp); 248 249 extern __checkReturn efx_rc_t 250 ef10_mac_multicast_list_set( 251 __in efx_nic_t *enp); 252 253 extern __checkReturn efx_rc_t 254 ef10_mac_filter_default_rxq_set( 255 __in efx_nic_t *enp, 256 __in efx_rxq_t *erp, 257 __in boolean_t using_rss); 258 259 extern void 260 ef10_mac_filter_default_rxq_clear( 261 __in efx_nic_t *enp); 262 263 #if EFSYS_OPT_LOOPBACK 264 265 extern __checkReturn efx_rc_t 266 ef10_mac_loopback_set( 267 __in efx_nic_t *enp, 268 __in efx_link_mode_t link_mode, 269 __in efx_loopback_type_t loopback_type); 270 271 #endif /* EFSYS_OPT_LOOPBACK */ 272 273 #if EFSYS_OPT_MAC_STATS 274 275 extern __checkReturn efx_rc_t 276 ef10_mac_stats_get_mask( 277 __in efx_nic_t *enp, 278 __inout_bcount(mask_size) uint32_t *maskp, 279 __in size_t mask_size); 280 281 extern __checkReturn efx_rc_t 282 ef10_mac_stats_update( 283 __in efx_nic_t *enp, 284 __in efsys_mem_t *esmp, 285 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 286 __inout_opt uint32_t *generationp); 287 288 #endif /* EFSYS_OPT_MAC_STATS */ 289 290 291 /* MCDI */ 292 293 #if EFSYS_OPT_MCDI 294 295 extern __checkReturn efx_rc_t 296 ef10_mcdi_init( 297 __in efx_nic_t *enp, 298 __in const efx_mcdi_transport_t *mtp); 299 300 extern void 301 ef10_mcdi_fini( 302 __in efx_nic_t *enp); 303 304 extern void 305 ef10_mcdi_send_request( 306 __in efx_nic_t *enp, 307 __in_bcount(hdr_len) void *hdrp, 308 __in size_t hdr_len, 309 __in_bcount(sdu_len) void *sdup, 310 __in size_t sdu_len); 311 312 extern __checkReturn boolean_t 313 ef10_mcdi_poll_response( 314 __in efx_nic_t *enp); 315 316 extern void 317 ef10_mcdi_read_response( 318 __in efx_nic_t *enp, 319 __out_bcount(length) void *bufferp, 320 __in size_t offset, 321 __in size_t length); 322 323 extern efx_rc_t 324 ef10_mcdi_poll_reboot( 325 __in efx_nic_t *enp); 326 327 extern __checkReturn efx_rc_t 328 ef10_mcdi_feature_supported( 329 __in efx_nic_t *enp, 330 __in efx_mcdi_feature_id_t id, 331 __out boolean_t *supportedp); 332 333 extern void 334 ef10_mcdi_get_timeout( 335 __in efx_nic_t *enp, 336 __in efx_mcdi_req_t *emrp, 337 __out uint32_t *timeoutp); 338 339 #endif /* EFSYS_OPT_MCDI */ 340 341 /* NVRAM */ 342 343 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 344 345 extern __checkReturn efx_rc_t 346 ef10_nvram_buf_read_tlv( 347 __in efx_nic_t *enp, 348 __in_bcount(max_seg_size) caddr_t seg_data, 349 __in size_t max_seg_size, 350 __in uint32_t tag, 351 __deref_out_bcount_opt(*sizep) caddr_t *datap, 352 __out size_t *sizep); 353 354 extern __checkReturn efx_rc_t 355 ef10_nvram_buf_write_tlv( 356 __inout_bcount(partn_size) caddr_t partn_data, 357 __in size_t partn_size, 358 __in uint32_t tag, 359 __in_bcount(tag_size) caddr_t tag_data, 360 __in size_t tag_size, 361 __out size_t *total_lengthp); 362 363 extern __checkReturn efx_rc_t 364 ef10_nvram_partn_read_tlv( 365 __in efx_nic_t *enp, 366 __in uint32_t partn, 367 __in uint32_t tag, 368 __deref_out_bcount_opt(*sizep) caddr_t *datap, 369 __out size_t *sizep); 370 371 extern __checkReturn efx_rc_t 372 ef10_nvram_partn_write_tlv( 373 __in efx_nic_t *enp, 374 __in uint32_t partn, 375 __in uint32_t tag, 376 __in_bcount(size) caddr_t data, 377 __in size_t size); 378 379 extern __checkReturn efx_rc_t 380 ef10_nvram_partn_write_segment_tlv( 381 __in efx_nic_t *enp, 382 __in uint32_t partn, 383 __in uint32_t tag, 384 __in_bcount(size) caddr_t data, 385 __in size_t size, 386 __in boolean_t all_segments); 387 388 extern __checkReturn efx_rc_t 389 ef10_nvram_partn_lock( 390 __in efx_nic_t *enp, 391 __in uint32_t partn); 392 393 extern __checkReturn efx_rc_t 394 ef10_nvram_partn_unlock( 395 __in efx_nic_t *enp, 396 __in uint32_t partn, 397 __out_opt uint32_t *resultp); 398 399 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 400 401 #if EFSYS_OPT_NVRAM 402 403 #if EFSYS_OPT_DIAG 404 405 extern __checkReturn efx_rc_t 406 ef10_nvram_test( 407 __in efx_nic_t *enp); 408 409 #endif /* EFSYS_OPT_DIAG */ 410 411 extern __checkReturn efx_rc_t 412 ef10_nvram_type_to_partn( 413 __in efx_nic_t *enp, 414 __in efx_nvram_type_t type, 415 __out uint32_t *partnp); 416 417 extern __checkReturn efx_rc_t 418 ef10_nvram_partn_size( 419 __in efx_nic_t *enp, 420 __in uint32_t partn, 421 __out size_t *sizep); 422 423 extern __checkReturn efx_rc_t 424 ef10_nvram_partn_rw_start( 425 __in efx_nic_t *enp, 426 __in uint32_t partn, 427 __out size_t *chunk_sizep); 428 429 extern __checkReturn efx_rc_t 430 ef10_nvram_partn_read_mode( 431 __in efx_nic_t *enp, 432 __in uint32_t partn, 433 __in unsigned int offset, 434 __out_bcount(size) caddr_t data, 435 __in size_t size, 436 __in uint32_t mode); 437 438 extern __checkReturn efx_rc_t 439 ef10_nvram_partn_read( 440 __in efx_nic_t *enp, 441 __in uint32_t partn, 442 __in unsigned int offset, 443 __out_bcount(size) caddr_t data, 444 __in size_t size); 445 446 extern __checkReturn efx_rc_t 447 ef10_nvram_partn_erase( 448 __in efx_nic_t *enp, 449 __in uint32_t partn, 450 __in unsigned int offset, 451 __in size_t size); 452 453 extern __checkReturn efx_rc_t 454 ef10_nvram_partn_write( 455 __in efx_nic_t *enp, 456 __in uint32_t partn, 457 __in unsigned int offset, 458 __out_bcount(size) caddr_t data, 459 __in size_t size); 460 461 extern __checkReturn efx_rc_t 462 ef10_nvram_partn_rw_finish( 463 __in efx_nic_t *enp, 464 __in uint32_t partn); 465 466 extern __checkReturn efx_rc_t 467 ef10_nvram_partn_get_version( 468 __in efx_nic_t *enp, 469 __in uint32_t partn, 470 __out uint32_t *subtypep, 471 __out_ecount(4) uint16_t version[4]); 472 473 extern __checkReturn efx_rc_t 474 ef10_nvram_partn_set_version( 475 __in efx_nic_t *enp, 476 __in uint32_t partn, 477 __in_ecount(4) uint16_t version[4]); 478 479 extern __checkReturn efx_rc_t 480 ef10_nvram_buffer_validate( 481 __in efx_nic_t *enp, 482 __in uint32_t partn, 483 __in_bcount(buffer_size) 484 caddr_t bufferp, 485 __in size_t buffer_size); 486 487 extern __checkReturn efx_rc_t 488 ef10_nvram_buffer_create( 489 __in efx_nic_t *enp, 490 __in uint16_t partn_type, 491 __in_bcount(buffer_size) 492 caddr_t bufferp, 493 __in size_t buffer_size); 494 495 extern __checkReturn efx_rc_t 496 ef10_nvram_buffer_find_item_start( 497 __in_bcount(buffer_size) 498 caddr_t bufferp, 499 __in size_t buffer_size, 500 __out uint32_t *startp 501 ); 502 503 extern __checkReturn efx_rc_t 504 ef10_nvram_buffer_find_end( 505 __in_bcount(buffer_size) 506 caddr_t bufferp, 507 __in size_t buffer_size, 508 __in uint32_t offset, 509 __out uint32_t *endp 510 ); 511 512 extern __checkReturn __success(return != B_FALSE) boolean_t 513 ef10_nvram_buffer_find_item( 514 __in_bcount(buffer_size) 515 caddr_t bufferp, 516 __in size_t buffer_size, 517 __in uint32_t offset, 518 __out uint32_t *startp, 519 __out uint32_t *lengthp 520 ); 521 522 extern __checkReturn efx_rc_t 523 ef10_nvram_buffer_get_item( 524 __in_bcount(buffer_size) 525 caddr_t bufferp, 526 __in size_t buffer_size, 527 __in uint32_t offset, 528 __in uint32_t length, 529 __out_bcount_part(item_max_size, *lengthp) 530 caddr_t itemp, 531 __in size_t item_max_size, 532 __out uint32_t *lengthp 533 ); 534 535 extern __checkReturn efx_rc_t 536 ef10_nvram_buffer_insert_item( 537 __in_bcount(buffer_size) 538 caddr_t bufferp, 539 __in size_t buffer_size, 540 __in uint32_t offset, 541 __in_bcount(length) caddr_t keyp, 542 __in uint32_t length, 543 __out uint32_t *lengthp 544 ); 545 546 extern __checkReturn efx_rc_t 547 ef10_nvram_buffer_delete_item( 548 __in_bcount(buffer_size) 549 caddr_t bufferp, 550 __in size_t buffer_size, 551 __in uint32_t offset, 552 __in uint32_t length, 553 __in uint32_t end 554 ); 555 556 extern __checkReturn efx_rc_t 557 ef10_nvram_buffer_finish( 558 __in_bcount(buffer_size) 559 caddr_t bufferp, 560 __in size_t buffer_size 561 ); 562 563 #endif /* EFSYS_OPT_NVRAM */ 564 565 566 /* PHY */ 567 568 typedef struct ef10_link_state_s { 569 uint32_t els_adv_cap_mask; 570 uint32_t els_lp_cap_mask; 571 unsigned int els_fcntl; 572 efx_link_mode_t els_link_mode; 573 #if EFSYS_OPT_LOOPBACK 574 efx_loopback_type_t els_loopback; 575 #endif 576 boolean_t els_mac_up; 577 } ef10_link_state_t; 578 579 extern void 580 ef10_phy_link_ev( 581 __in efx_nic_t *enp, 582 __in efx_qword_t *eqp, 583 __out efx_link_mode_t *link_modep); 584 585 extern __checkReturn efx_rc_t 586 ef10_phy_get_link( 587 __in efx_nic_t *enp, 588 __out ef10_link_state_t *elsp); 589 590 extern __checkReturn efx_rc_t 591 ef10_phy_power( 592 __in efx_nic_t *enp, 593 __in boolean_t on); 594 595 extern __checkReturn efx_rc_t 596 ef10_phy_reconfigure( 597 __in efx_nic_t *enp); 598 599 extern __checkReturn efx_rc_t 600 ef10_phy_verify( 601 __in efx_nic_t *enp); 602 603 extern __checkReturn efx_rc_t 604 ef10_phy_oui_get( 605 __in efx_nic_t *enp, 606 __out uint32_t *ouip); 607 608 #if EFSYS_OPT_PHY_STATS 609 610 extern __checkReturn efx_rc_t 611 ef10_phy_stats_update( 612 __in efx_nic_t *enp, 613 __in efsys_mem_t *esmp, 614 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 615 616 #endif /* EFSYS_OPT_PHY_STATS */ 617 618 #if EFSYS_OPT_BIST 619 620 extern __checkReturn efx_rc_t 621 ef10_bist_enable_offline( 622 __in efx_nic_t *enp); 623 624 extern __checkReturn efx_rc_t 625 ef10_bist_start( 626 __in efx_nic_t *enp, 627 __in efx_bist_type_t type); 628 629 extern __checkReturn efx_rc_t 630 ef10_bist_poll( 631 __in efx_nic_t *enp, 632 __in efx_bist_type_t type, 633 __out efx_bist_result_t *resultp, 634 __out_opt __drv_when(count > 0, __notnull) 635 uint32_t *value_maskp, 636 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 637 unsigned long *valuesp, 638 __in size_t count); 639 640 extern void 641 ef10_bist_stop( 642 __in efx_nic_t *enp, 643 __in efx_bist_type_t type); 644 645 #endif /* EFSYS_OPT_BIST */ 646 647 /* TX */ 648 649 extern __checkReturn efx_rc_t 650 ef10_tx_init( 651 __in efx_nic_t *enp); 652 653 extern void 654 ef10_tx_fini( 655 __in efx_nic_t *enp); 656 657 extern __checkReturn efx_rc_t 658 ef10_tx_qcreate( 659 __in efx_nic_t *enp, 660 __in unsigned int index, 661 __in unsigned int label, 662 __in efsys_mem_t *esmp, 663 __in size_t n, 664 __in uint32_t id, 665 __in uint16_t flags, 666 __in efx_evq_t *eep, 667 __in efx_txq_t *etp, 668 __out unsigned int *addedp); 669 670 extern void 671 ef10_tx_qdestroy( 672 __in efx_txq_t *etp); 673 674 extern __checkReturn efx_rc_t 675 ef10_tx_qpost( 676 __in efx_txq_t *etp, 677 __in_ecount(n) efx_buffer_t *eb, 678 __in unsigned int n, 679 __in unsigned int completed, 680 __inout unsigned int *addedp); 681 682 extern void 683 ef10_tx_qpush( 684 __in efx_txq_t *etp, 685 __in unsigned int added, 686 __in unsigned int pushed); 687 688 extern __checkReturn efx_rc_t 689 ef10_tx_qpace( 690 __in efx_txq_t *etp, 691 __in unsigned int ns); 692 693 extern __checkReturn efx_rc_t 694 ef10_tx_qflush( 695 __in efx_txq_t *etp); 696 697 extern void 698 ef10_tx_qenable( 699 __in efx_txq_t *etp); 700 701 extern __checkReturn efx_rc_t 702 ef10_tx_qpio_enable( 703 __in efx_txq_t *etp); 704 705 extern void 706 ef10_tx_qpio_disable( 707 __in efx_txq_t *etp); 708 709 extern __checkReturn efx_rc_t 710 ef10_tx_qpio_write( 711 __in efx_txq_t *etp, 712 __in_ecount(buf_length) uint8_t *buffer, 713 __in size_t buf_length, 714 __in size_t pio_buf_offset); 715 716 extern __checkReturn efx_rc_t 717 ef10_tx_qpio_post( 718 __in efx_txq_t *etp, 719 __in size_t pkt_length, 720 __in unsigned int completed, 721 __inout unsigned int *addedp); 722 723 extern __checkReturn efx_rc_t 724 ef10_tx_qdesc_post( 725 __in efx_txq_t *etp, 726 __in_ecount(n) efx_desc_t *ed, 727 __in unsigned int n, 728 __in unsigned int completed, 729 __inout unsigned int *addedp); 730 731 extern void 732 ef10_tx_qdesc_dma_create( 733 __in efx_txq_t *etp, 734 __in efsys_dma_addr_t addr, 735 __in size_t size, 736 __in boolean_t eop, 737 __out efx_desc_t *edp); 738 739 extern void 740 ef10_tx_qdesc_tso_create( 741 __in efx_txq_t *etp, 742 __in uint16_t ipv4_id, 743 __in uint32_t tcp_seq, 744 __in uint8_t tcp_flags, 745 __out efx_desc_t *edp); 746 747 extern void 748 ef10_tx_qdesc_tso2_create( 749 __in efx_txq_t *etp, 750 __in uint16_t ipv4_id, 751 __in uint32_t tcp_seq, 752 __in uint16_t tcp_mss, 753 __out_ecount(count) efx_desc_t *edp, 754 __in int count); 755 756 extern void 757 ef10_tx_qdesc_vlantci_create( 758 __in efx_txq_t *etp, 759 __in uint16_t vlan_tci, 760 __out efx_desc_t *edp); 761 762 763 #if EFSYS_OPT_QSTATS 764 765 extern void 766 ef10_tx_qstats_update( 767 __in efx_txq_t *etp, 768 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 769 770 #endif /* EFSYS_OPT_QSTATS */ 771 772 typedef uint32_t efx_piobuf_handle_t; 773 774 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 775 776 extern __checkReturn efx_rc_t 777 ef10_nic_pio_alloc( 778 __inout efx_nic_t *enp, 779 __out uint32_t *bufnump, 780 __out efx_piobuf_handle_t *handlep, 781 __out uint32_t *blknump, 782 __out uint32_t *offsetp, 783 __out size_t *sizep); 784 785 extern __checkReturn efx_rc_t 786 ef10_nic_pio_free( 787 __inout efx_nic_t *enp, 788 __in uint32_t bufnum, 789 __in uint32_t blknum); 790 791 extern __checkReturn efx_rc_t 792 ef10_nic_pio_link( 793 __inout efx_nic_t *enp, 794 __in uint32_t vi_index, 795 __in efx_piobuf_handle_t handle); 796 797 extern __checkReturn efx_rc_t 798 ef10_nic_pio_unlink( 799 __inout efx_nic_t *enp, 800 __in uint32_t vi_index); 801 802 803 /* VPD */ 804 805 #if EFSYS_OPT_VPD 806 807 extern __checkReturn efx_rc_t 808 ef10_vpd_init( 809 __in efx_nic_t *enp); 810 811 extern __checkReturn efx_rc_t 812 ef10_vpd_size( 813 __in efx_nic_t *enp, 814 __out size_t *sizep); 815 816 extern __checkReturn efx_rc_t 817 ef10_vpd_read( 818 __in efx_nic_t *enp, 819 __out_bcount(size) caddr_t data, 820 __in size_t size); 821 822 extern __checkReturn efx_rc_t 823 ef10_vpd_verify( 824 __in efx_nic_t *enp, 825 __in_bcount(size) caddr_t data, 826 __in size_t size); 827 828 extern __checkReturn efx_rc_t 829 ef10_vpd_reinit( 830 __in efx_nic_t *enp, 831 __in_bcount(size) caddr_t data, 832 __in size_t size); 833 834 extern __checkReturn efx_rc_t 835 ef10_vpd_get( 836 __in efx_nic_t *enp, 837 __in_bcount(size) caddr_t data, 838 __in size_t size, 839 __inout efx_vpd_value_t *evvp); 840 841 extern __checkReturn efx_rc_t 842 ef10_vpd_set( 843 __in efx_nic_t *enp, 844 __in_bcount(size) caddr_t data, 845 __in size_t size, 846 __in efx_vpd_value_t *evvp); 847 848 extern __checkReturn efx_rc_t 849 ef10_vpd_next( 850 __in efx_nic_t *enp, 851 __in_bcount(size) caddr_t data, 852 __in size_t size, 853 __out efx_vpd_value_t *evvp, 854 __inout unsigned int *contp); 855 856 extern __checkReturn efx_rc_t 857 ef10_vpd_write( 858 __in efx_nic_t *enp, 859 __in_bcount(size) caddr_t data, 860 __in size_t size); 861 862 extern void 863 ef10_vpd_fini( 864 __in efx_nic_t *enp); 865 866 #endif /* EFSYS_OPT_VPD */ 867 868 869 /* RX */ 870 871 extern __checkReturn efx_rc_t 872 ef10_rx_init( 873 __in efx_nic_t *enp); 874 875 #if EFSYS_OPT_RX_SCATTER 876 extern __checkReturn efx_rc_t 877 ef10_rx_scatter_enable( 878 __in efx_nic_t *enp, 879 __in unsigned int buf_size); 880 #endif /* EFSYS_OPT_RX_SCATTER */ 881 882 883 #if EFSYS_OPT_RX_SCALE 884 885 extern __checkReturn efx_rc_t 886 ef10_rx_scale_mode_set( 887 __in efx_nic_t *enp, 888 __in efx_rx_hash_alg_t alg, 889 __in efx_rx_hash_type_t type, 890 __in boolean_t insert); 891 892 extern __checkReturn efx_rc_t 893 ef10_rx_scale_key_set( 894 __in efx_nic_t *enp, 895 __in_ecount(n) uint8_t *key, 896 __in size_t n); 897 898 extern __checkReturn efx_rc_t 899 ef10_rx_scale_tbl_set( 900 __in efx_nic_t *enp, 901 __in_ecount(n) unsigned int *table, 902 __in size_t n); 903 904 extern __checkReturn uint32_t 905 ef10_rx_prefix_hash( 906 __in efx_nic_t *enp, 907 __in efx_rx_hash_alg_t func, 908 __in uint8_t *buffer); 909 910 #endif /* EFSYS_OPT_RX_SCALE */ 911 912 extern __checkReturn efx_rc_t 913 ef10_rx_prefix_pktlen( 914 __in efx_nic_t *enp, 915 __in uint8_t *buffer, 916 __out uint16_t *lengthp); 917 918 extern void 919 ef10_rx_qpost( 920 __in efx_rxq_t *erp, 921 __in_ecount(n) efsys_dma_addr_t *addrp, 922 __in size_t size, 923 __in unsigned int n, 924 __in unsigned int completed, 925 __in unsigned int added); 926 927 extern void 928 ef10_rx_qpush( 929 __in efx_rxq_t *erp, 930 __in unsigned int added, 931 __inout unsigned int *pushedp); 932 933 extern __checkReturn efx_rc_t 934 ef10_rx_qflush( 935 __in efx_rxq_t *erp); 936 937 extern void 938 ef10_rx_qenable( 939 __in efx_rxq_t *erp); 940 941 extern __checkReturn efx_rc_t 942 ef10_rx_qcreate( 943 __in efx_nic_t *enp, 944 __in unsigned int index, 945 __in unsigned int label, 946 __in efx_rxq_type_t type, 947 __in efsys_mem_t *esmp, 948 __in size_t n, 949 __in uint32_t id, 950 __in efx_evq_t *eep, 951 __in efx_rxq_t *erp); 952 953 extern void 954 ef10_rx_qdestroy( 955 __in efx_rxq_t *erp); 956 957 extern void 958 ef10_rx_fini( 959 __in efx_nic_t *enp); 960 961 #if EFSYS_OPT_FILTER 962 963 typedef struct ef10_filter_handle_s { 964 uint32_t efh_lo; 965 uint32_t efh_hi; 966 } ef10_filter_handle_t; 967 968 typedef struct ef10_filter_entry_s { 969 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 970 ef10_filter_handle_t efe_handle; 971 } ef10_filter_entry_t; 972 973 /* 974 * BUSY flag indicates that an update is in progress. 975 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 976 */ 977 #define EFX_EF10_FILTER_FLAG_BUSY 1U 978 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 979 #define EFX_EF10_FILTER_FLAGS 3U 980 981 /* 982 * Size of the hash table used by the driver. Doesn't need to be the 983 * same size as the hardware's table. 984 */ 985 #define EFX_EF10_FILTER_TBL_ROWS 8192 986 987 /* Only need to allow for one directed and one unknown unicast filter */ 988 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 989 990 /* Allow for the broadcast address to be added to the multicast list */ 991 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 992 993 typedef struct ef10_filter_table_s { 994 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 995 efx_rxq_t *eft_default_rxq; 996 boolean_t eft_using_rss; 997 uint32_t eft_unicst_filter_indexes[ 998 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 999 uint32_t eft_unicst_filter_count; 1000 uint32_t eft_mulcst_filter_indexes[ 1001 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 1002 uint32_t eft_mulcst_filter_count; 1003 boolean_t eft_using_all_mulcst; 1004 } ef10_filter_table_t; 1005 1006 __checkReturn efx_rc_t 1007 ef10_filter_init( 1008 __in efx_nic_t *enp); 1009 1010 void 1011 ef10_filter_fini( 1012 __in efx_nic_t *enp); 1013 1014 __checkReturn efx_rc_t 1015 ef10_filter_restore( 1016 __in efx_nic_t *enp); 1017 1018 __checkReturn efx_rc_t 1019 ef10_filter_add( 1020 __in efx_nic_t *enp, 1021 __inout efx_filter_spec_t *spec, 1022 __in boolean_t may_replace); 1023 1024 __checkReturn efx_rc_t 1025 ef10_filter_delete( 1026 __in efx_nic_t *enp, 1027 __inout efx_filter_spec_t *spec); 1028 1029 extern __checkReturn efx_rc_t 1030 ef10_filter_supported_filters( 1031 __in efx_nic_t *enp, 1032 __out_ecount(buffer_length) uint32_t *buffer, 1033 __in size_t buffer_length, 1034 __out size_t *list_lengthp); 1035 1036 extern __checkReturn efx_rc_t 1037 ef10_filter_reconfigure( 1038 __in efx_nic_t *enp, 1039 __in_ecount(6) uint8_t const *mac_addr, 1040 __in boolean_t all_unicst, 1041 __in boolean_t mulcst, 1042 __in boolean_t all_mulcst, 1043 __in boolean_t brdcst, 1044 __in_ecount(6*count) uint8_t const *addrs, 1045 __in uint32_t count); 1046 1047 extern void 1048 ef10_filter_get_default_rxq( 1049 __in efx_nic_t *enp, 1050 __out efx_rxq_t **erpp, 1051 __out boolean_t *using_rss); 1052 1053 extern void 1054 ef10_filter_default_rxq_set( 1055 __in efx_nic_t *enp, 1056 __in efx_rxq_t *erp, 1057 __in boolean_t using_rss); 1058 1059 extern void 1060 ef10_filter_default_rxq_clear( 1061 __in efx_nic_t *enp); 1062 1063 1064 #endif /* EFSYS_OPT_FILTER */ 1065 1066 extern __checkReturn efx_rc_t 1067 efx_mcdi_get_function_info( 1068 __in efx_nic_t *enp, 1069 __out uint32_t *pfp, 1070 __out_opt uint32_t *vfp); 1071 1072 extern __checkReturn efx_rc_t 1073 efx_mcdi_privilege_mask( 1074 __in efx_nic_t *enp, 1075 __in uint32_t pf, 1076 __in uint32_t vf, 1077 __out uint32_t *maskp); 1078 1079 extern __checkReturn efx_rc_t 1080 efx_mcdi_get_port_assignment( 1081 __in efx_nic_t *enp, 1082 __out uint32_t *portp); 1083 1084 extern __checkReturn efx_rc_t 1085 efx_mcdi_get_port_modes( 1086 __in efx_nic_t *enp, 1087 __out uint32_t *modesp, 1088 __out_opt uint32_t *current_modep); 1089 1090 extern __checkReturn efx_rc_t 1091 ef10_nic_get_port_mode_bandwidth( 1092 __in uint32_t port_mode, 1093 __out uint32_t *bandwidth_mbpsp); 1094 1095 extern __checkReturn efx_rc_t 1096 efx_mcdi_get_mac_address_pf( 1097 __in efx_nic_t *enp, 1098 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1099 1100 extern __checkReturn efx_rc_t 1101 efx_mcdi_get_mac_address_vf( 1102 __in efx_nic_t *enp, 1103 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1104 1105 extern __checkReturn efx_rc_t 1106 efx_mcdi_get_clock( 1107 __in efx_nic_t *enp, 1108 __out uint32_t *sys_freqp, 1109 __out uint32_t *dpcpu_freqp); 1110 1111 1112 extern __checkReturn efx_rc_t 1113 efx_mcdi_get_vector_cfg( 1114 __in efx_nic_t *enp, 1115 __out_opt uint32_t *vec_basep, 1116 __out_opt uint32_t *pf_nvecp, 1117 __out_opt uint32_t *vf_nvecp); 1118 1119 extern __checkReturn efx_rc_t 1120 ef10_get_datapath_caps( 1121 __in efx_nic_t *enp); 1122 1123 extern __checkReturn efx_rc_t 1124 ef10_get_privilege_mask( 1125 __in efx_nic_t *enp, 1126 __out uint32_t *maskp); 1127 1128 extern __checkReturn efx_rc_t 1129 ef10_external_port_mapping( 1130 __in efx_nic_t *enp, 1131 __in uint32_t port, 1132 __out uint8_t *external_portp); 1133 1134 1135 #ifdef __cplusplus 1136 } 1137 #endif 1138 1139 #endif /* _SYS_EF10_IMPL_H */ 1140