1 /*- 2 * Copyright (c) 2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EF10_IMPL_H 34 #define _SYS_EF10_IMPL_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) 41 #define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) 42 #elif EFSYS_OPT_HUNTINGTON 43 #define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS 44 #elif EFSYS_OPT_MEDFORD 45 #define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS 46 #endif 47 48 /* 49 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 50 * possibly be increased, or the write size reported by newer firmware used 51 * instead. 52 */ 53 #define EF10_NVRAM_CHUNK 0x80 54 55 /* Alignment requirement for value written to RX WPTR: 56 * the WPTR must be aligned to an 8 descriptor boundary 57 */ 58 #define EF10_RX_WPTR_ALIGN 8 59 60 /* 61 * Max byte offset into the packet the TCP header must start for the hardware 62 * to be able to parse the packet correctly. 63 */ 64 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 65 66 /* Invalid RSS context handle */ 67 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 68 69 70 /* EV */ 71 72 __checkReturn efx_rc_t 73 ef10_ev_init( 74 __in efx_nic_t *enp); 75 76 void 77 ef10_ev_fini( 78 __in efx_nic_t *enp); 79 80 __checkReturn efx_rc_t 81 ef10_ev_qcreate( 82 __in efx_nic_t *enp, 83 __in unsigned int index, 84 __in efsys_mem_t *esmp, 85 __in size_t n, 86 __in uint32_t id, 87 __in efx_evq_t *eep); 88 89 void 90 ef10_ev_qdestroy( 91 __in efx_evq_t *eep); 92 93 __checkReturn efx_rc_t 94 ef10_ev_qprime( 95 __in efx_evq_t *eep, 96 __in unsigned int count); 97 98 void 99 ef10_ev_qpost( 100 __in efx_evq_t *eep, 101 __in uint16_t data); 102 103 __checkReturn efx_rc_t 104 ef10_ev_qmoderate( 105 __in efx_evq_t *eep, 106 __in unsigned int us); 107 108 #if EFSYS_OPT_QSTATS 109 void 110 ef10_ev_qstats_update( 111 __in efx_evq_t *eep, 112 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 113 #endif /* EFSYS_OPT_QSTATS */ 114 115 void 116 ef10_ev_rxlabel_init( 117 __in efx_evq_t *eep, 118 __in efx_rxq_t *erp, 119 __in unsigned int label); 120 121 void 122 ef10_ev_rxlabel_fini( 123 __in efx_evq_t *eep, 124 __in unsigned int label); 125 126 /* INTR */ 127 128 __checkReturn efx_rc_t 129 ef10_intr_init( 130 __in efx_nic_t *enp, 131 __in efx_intr_type_t type, 132 __in efsys_mem_t *esmp); 133 134 void 135 ef10_intr_enable( 136 __in efx_nic_t *enp); 137 138 void 139 ef10_intr_disable( 140 __in efx_nic_t *enp); 141 142 void 143 ef10_intr_disable_unlocked( 144 __in efx_nic_t *enp); 145 146 __checkReturn efx_rc_t 147 ef10_intr_trigger( 148 __in efx_nic_t *enp, 149 __in unsigned int level); 150 151 void 152 ef10_intr_status_line( 153 __in efx_nic_t *enp, 154 __out boolean_t *fatalp, 155 __out uint32_t *qmaskp); 156 157 void 158 ef10_intr_status_message( 159 __in efx_nic_t *enp, 160 __in unsigned int message, 161 __out boolean_t *fatalp); 162 163 void 164 ef10_intr_fatal( 165 __in efx_nic_t *enp); 166 void 167 ef10_intr_fini( 168 __in efx_nic_t *enp); 169 170 /* NIC */ 171 172 extern __checkReturn efx_rc_t 173 ef10_nic_probe( 174 __in efx_nic_t *enp); 175 176 extern __checkReturn efx_rc_t 177 ef10_nic_set_drv_limits( 178 __inout efx_nic_t *enp, 179 __in efx_drv_limits_t *edlp); 180 181 extern __checkReturn efx_rc_t 182 ef10_nic_get_vi_pool( 183 __in efx_nic_t *enp, 184 __out uint32_t *vi_countp); 185 186 extern __checkReturn efx_rc_t 187 ef10_nic_get_bar_region( 188 __in efx_nic_t *enp, 189 __in efx_nic_region_t region, 190 __out uint32_t *offsetp, 191 __out size_t *sizep); 192 193 extern __checkReturn efx_rc_t 194 ef10_nic_reset( 195 __in efx_nic_t *enp); 196 197 extern __checkReturn efx_rc_t 198 ef10_nic_init( 199 __in efx_nic_t *enp); 200 201 #if EFSYS_OPT_DIAG 202 203 extern __checkReturn efx_rc_t 204 ef10_nic_register_test( 205 __in efx_nic_t *enp); 206 207 #endif /* EFSYS_OPT_DIAG */ 208 209 extern void 210 ef10_nic_fini( 211 __in efx_nic_t *enp); 212 213 extern void 214 ef10_nic_unprobe( 215 __in efx_nic_t *enp); 216 217 218 /* MAC */ 219 220 extern __checkReturn efx_rc_t 221 ef10_mac_poll( 222 __in efx_nic_t *enp, 223 __out efx_link_mode_t *link_modep); 224 225 extern __checkReturn efx_rc_t 226 ef10_mac_up( 227 __in efx_nic_t *enp, 228 __out boolean_t *mac_upp); 229 230 extern __checkReturn efx_rc_t 231 ef10_mac_addr_set( 232 __in efx_nic_t *enp); 233 234 extern __checkReturn efx_rc_t 235 ef10_mac_pdu_set( 236 __in efx_nic_t *enp); 237 238 extern __checkReturn efx_rc_t 239 ef10_mac_reconfigure( 240 __in efx_nic_t *enp); 241 242 extern __checkReturn efx_rc_t 243 ef10_mac_multicast_list_set( 244 __in efx_nic_t *enp); 245 246 extern __checkReturn efx_rc_t 247 ef10_mac_filter_default_rxq_set( 248 __in efx_nic_t *enp, 249 __in efx_rxq_t *erp, 250 __in boolean_t using_rss); 251 252 extern void 253 ef10_mac_filter_default_rxq_clear( 254 __in efx_nic_t *enp); 255 256 #if EFSYS_OPT_LOOPBACK 257 258 extern __checkReturn efx_rc_t 259 ef10_mac_loopback_set( 260 __in efx_nic_t *enp, 261 __in efx_link_mode_t link_mode, 262 __in efx_loopback_type_t loopback_type); 263 264 #endif /* EFSYS_OPT_LOOPBACK */ 265 266 #if EFSYS_OPT_MAC_STATS 267 268 extern __checkReturn efx_rc_t 269 ef10_mac_stats_update( 270 __in efx_nic_t *enp, 271 __in efsys_mem_t *esmp, 272 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 273 __inout_opt uint32_t *generationp); 274 275 #endif /* EFSYS_OPT_MAC_STATS */ 276 277 278 /* MCDI */ 279 280 #if EFSYS_OPT_MCDI 281 282 extern __checkReturn efx_rc_t 283 ef10_mcdi_init( 284 __in efx_nic_t *enp, 285 __in const efx_mcdi_transport_t *mtp); 286 287 extern void 288 ef10_mcdi_fini( 289 __in efx_nic_t *enp); 290 291 extern void 292 ef10_mcdi_send_request( 293 __in efx_nic_t *enp, 294 __in void *hdrp, 295 __in size_t hdr_len, 296 __in void *sdup, 297 __in size_t sdu_len); 298 299 extern __checkReturn boolean_t 300 ef10_mcdi_poll_response( 301 __in efx_nic_t *enp); 302 303 extern void 304 ef10_mcdi_read_response( 305 __in efx_nic_t *enp, 306 __out_bcount(length) void *bufferp, 307 __in size_t offset, 308 __in size_t length); 309 310 extern efx_rc_t 311 ef10_mcdi_poll_reboot( 312 __in efx_nic_t *enp); 313 314 extern __checkReturn efx_rc_t 315 ef10_mcdi_feature_supported( 316 __in efx_nic_t *enp, 317 __in efx_mcdi_feature_id_t id, 318 __out boolean_t *supportedp); 319 320 #endif /* EFSYS_OPT_MCDI */ 321 322 /* NVRAM */ 323 324 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 325 326 extern __checkReturn efx_rc_t 327 ef10_nvram_buf_read_tlv( 328 __in efx_nic_t *enp, 329 __in_bcount(max_seg_size) caddr_t seg_data, 330 __in size_t max_seg_size, 331 __in uint32_t tag, 332 __deref_out_bcount_opt(*sizep) caddr_t *datap, 333 __out size_t *sizep); 334 335 extern __checkReturn efx_rc_t 336 ef10_nvram_buf_write_tlv( 337 __inout_bcount(partn_size) caddr_t partn_data, 338 __in size_t partn_size, 339 __in uint32_t tag, 340 __in_bcount(tag_size) caddr_t tag_data, 341 __in size_t tag_size, 342 __out size_t *total_lengthp); 343 344 extern __checkReturn efx_rc_t 345 ef10_nvram_partn_read_tlv( 346 __in efx_nic_t *enp, 347 __in uint32_t partn, 348 __in uint32_t tag, 349 __deref_out_bcount_opt(*sizep) caddr_t *datap, 350 __out size_t *sizep); 351 352 extern __checkReturn efx_rc_t 353 ef10_nvram_partn_write_tlv( 354 __in efx_nic_t *enp, 355 __in uint32_t partn, 356 __in uint32_t tag, 357 __in_bcount(size) caddr_t data, 358 __in size_t size); 359 360 extern __checkReturn efx_rc_t 361 ef10_nvram_partn_write_segment_tlv( 362 __in efx_nic_t *enp, 363 __in uint32_t partn, 364 __in uint32_t tag, 365 __in_bcount(size) caddr_t data, 366 __in size_t size, 367 __in boolean_t all_segments); 368 369 extern __checkReturn efx_rc_t 370 ef10_nvram_partn_lock( 371 __in efx_nic_t *enp, 372 __in uint32_t partn); 373 374 extern void 375 ef10_nvram_partn_unlock( 376 __in efx_nic_t *enp, 377 __in uint32_t partn); 378 379 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 380 381 #if EFSYS_OPT_NVRAM 382 383 #if EFSYS_OPT_DIAG 384 385 extern __checkReturn efx_rc_t 386 ef10_nvram_test( 387 __in efx_nic_t *enp); 388 389 #endif /* EFSYS_OPT_DIAG */ 390 391 extern __checkReturn efx_rc_t 392 ef10_nvram_type_to_partn( 393 __in efx_nic_t *enp, 394 __in efx_nvram_type_t type, 395 __out uint32_t *partnp); 396 397 extern __checkReturn efx_rc_t 398 ef10_nvram_partn_size( 399 __in efx_nic_t *enp, 400 __in uint32_t partn, 401 __out size_t *sizep); 402 403 extern __checkReturn efx_rc_t 404 ef10_nvram_partn_rw_start( 405 __in efx_nic_t *enp, 406 __in uint32_t partn, 407 __out size_t *chunk_sizep); 408 409 extern __checkReturn efx_rc_t 410 ef10_nvram_partn_read_mode( 411 __in efx_nic_t *enp, 412 __in uint32_t partn, 413 __in unsigned int offset, 414 __out_bcount(size) caddr_t data, 415 __in size_t size, 416 __in uint32_t mode); 417 418 extern __checkReturn efx_rc_t 419 ef10_nvram_partn_read( 420 __in efx_nic_t *enp, 421 __in uint32_t partn, 422 __in unsigned int offset, 423 __out_bcount(size) caddr_t data, 424 __in size_t size); 425 426 extern __checkReturn efx_rc_t 427 ef10_nvram_partn_erase( 428 __in efx_nic_t *enp, 429 __in uint32_t partn, 430 __in unsigned int offset, 431 __in size_t size); 432 433 extern __checkReturn efx_rc_t 434 ef10_nvram_partn_write( 435 __in efx_nic_t *enp, 436 __in uint32_t partn, 437 __in unsigned int offset, 438 __out_bcount(size) caddr_t data, 439 __in size_t size); 440 441 extern void 442 ef10_nvram_partn_rw_finish( 443 __in efx_nic_t *enp, 444 __in uint32_t partn); 445 446 extern __checkReturn efx_rc_t 447 ef10_nvram_partn_get_version( 448 __in efx_nic_t *enp, 449 __in uint32_t partn, 450 __out uint32_t *subtypep, 451 __out_ecount(4) uint16_t version[4]); 452 453 extern __checkReturn efx_rc_t 454 ef10_nvram_partn_set_version( 455 __in efx_nic_t *enp, 456 __in uint32_t partn, 457 __in_ecount(4) uint16_t version[4]); 458 459 extern __checkReturn efx_rc_t 460 ef10_nvram_buffer_validate( 461 __in efx_nic_t *enp, 462 __in uint32_t partn, 463 __in_bcount(buffer_size) 464 caddr_t bufferp, 465 __in size_t buffer_size); 466 467 extern __checkReturn efx_rc_t 468 ef10_nvram_buffer_create( 469 __in efx_nic_t *enp, 470 __in uint16_t partn_type, 471 __in_bcount(buffer_size) 472 caddr_t bufferp, 473 __in size_t buffer_size); 474 475 extern __checkReturn efx_rc_t 476 ef10_nvram_buffer_find_item_start( 477 __in_bcount(buffer_size) 478 caddr_t bufferp, 479 __in size_t buffer_size, 480 __out uint32_t *startp 481 ); 482 483 extern __checkReturn efx_rc_t 484 ef10_nvram_buffer_find_end( 485 __in_bcount(buffer_size) 486 caddr_t bufferp, 487 __in size_t buffer_size, 488 __in uint32_t offset, 489 __out uint32_t *endp 490 ); 491 492 extern __checkReturn __success(return != B_FALSE) boolean_t 493 ef10_nvram_buffer_find_item( 494 __in_bcount(buffer_size) 495 caddr_t bufferp, 496 __in size_t buffer_size, 497 __in uint32_t offset, 498 __out uint32_t *startp, 499 __out uint32_t *lengthp 500 ); 501 502 extern __checkReturn efx_rc_t 503 ef10_nvram_buffer_get_item( 504 __in_bcount(buffer_size) 505 caddr_t bufferp, 506 __in size_t buffer_size, 507 __in uint32_t offset, 508 __in uint32_t length, 509 __out_bcount_part(item_max_size, *lengthp) 510 caddr_t itemp, 511 __in size_t item_max_size, 512 __out uint32_t *lengthp 513 ); 514 515 extern __checkReturn efx_rc_t 516 ef10_nvram_buffer_insert_item( 517 __in_bcount(buffer_size) 518 caddr_t bufferp, 519 __in size_t buffer_size, 520 __in uint32_t offset, 521 __in_bcount(length) caddr_t keyp, 522 __in uint32_t length, 523 __out uint32_t *lengthp 524 ); 525 526 extern __checkReturn efx_rc_t 527 ef10_nvram_buffer_delete_item( 528 __in_bcount(buffer_size) 529 caddr_t bufferp, 530 __in size_t buffer_size, 531 __in uint32_t offset, 532 __in uint32_t length, 533 __in uint32_t end 534 ); 535 536 extern __checkReturn efx_rc_t 537 ef10_nvram_buffer_finish( 538 __in_bcount(buffer_size) 539 caddr_t bufferp, 540 __in size_t buffer_size 541 ); 542 543 #endif /* EFSYS_OPT_NVRAM */ 544 545 546 /* PHY */ 547 548 typedef struct ef10_link_state_s { 549 uint32_t els_adv_cap_mask; 550 uint32_t els_lp_cap_mask; 551 unsigned int els_fcntl; 552 efx_link_mode_t els_link_mode; 553 #if EFSYS_OPT_LOOPBACK 554 efx_loopback_type_t els_loopback; 555 #endif 556 boolean_t els_mac_up; 557 } ef10_link_state_t; 558 559 extern void 560 ef10_phy_link_ev( 561 __in efx_nic_t *enp, 562 __in efx_qword_t *eqp, 563 __out efx_link_mode_t *link_modep); 564 565 extern __checkReturn efx_rc_t 566 ef10_phy_get_link( 567 __in efx_nic_t *enp, 568 __out ef10_link_state_t *elsp); 569 570 extern __checkReturn efx_rc_t 571 ef10_phy_power( 572 __in efx_nic_t *enp, 573 __in boolean_t on); 574 575 extern __checkReturn efx_rc_t 576 ef10_phy_reconfigure( 577 __in efx_nic_t *enp); 578 579 extern __checkReturn efx_rc_t 580 ef10_phy_verify( 581 __in efx_nic_t *enp); 582 583 extern __checkReturn efx_rc_t 584 ef10_phy_oui_get( 585 __in efx_nic_t *enp, 586 __out uint32_t *ouip); 587 588 #if EFSYS_OPT_PHY_STATS 589 590 extern __checkReturn efx_rc_t 591 ef10_phy_stats_update( 592 __in efx_nic_t *enp, 593 __in efsys_mem_t *esmp, 594 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 595 596 #endif /* EFSYS_OPT_PHY_STATS */ 597 598 599 /* TX */ 600 601 extern __checkReturn efx_rc_t 602 ef10_tx_init( 603 __in efx_nic_t *enp); 604 605 extern void 606 ef10_tx_fini( 607 __in efx_nic_t *enp); 608 609 extern __checkReturn efx_rc_t 610 ef10_tx_qcreate( 611 __in efx_nic_t *enp, 612 __in unsigned int index, 613 __in unsigned int label, 614 __in efsys_mem_t *esmp, 615 __in size_t n, 616 __in uint32_t id, 617 __in uint16_t flags, 618 __in efx_evq_t *eep, 619 __in efx_txq_t *etp, 620 __out unsigned int *addedp); 621 622 extern void 623 ef10_tx_qdestroy( 624 __in efx_txq_t *etp); 625 626 extern __checkReturn efx_rc_t 627 ef10_tx_qpost( 628 __in efx_txq_t *etp, 629 __in_ecount(n) efx_buffer_t *eb, 630 __in unsigned int n, 631 __in unsigned int completed, 632 __inout unsigned int *addedp); 633 634 extern void 635 ef10_tx_qpush( 636 __in efx_txq_t *etp, 637 __in unsigned int added, 638 __in unsigned int pushed); 639 640 extern __checkReturn efx_rc_t 641 ef10_tx_qpace( 642 __in efx_txq_t *etp, 643 __in unsigned int ns); 644 645 extern __checkReturn efx_rc_t 646 ef10_tx_qflush( 647 __in efx_txq_t *etp); 648 649 extern void 650 ef10_tx_qenable( 651 __in efx_txq_t *etp); 652 653 extern __checkReturn efx_rc_t 654 ef10_tx_qpio_enable( 655 __in efx_txq_t *etp); 656 657 extern void 658 ef10_tx_qpio_disable( 659 __in efx_txq_t *etp); 660 661 extern __checkReturn efx_rc_t 662 ef10_tx_qpio_write( 663 __in efx_txq_t *etp, 664 __in_ecount(buf_length) uint8_t *buffer, 665 __in size_t buf_length, 666 __in size_t pio_buf_offset); 667 668 extern __checkReturn efx_rc_t 669 ef10_tx_qpio_post( 670 __in efx_txq_t *etp, 671 __in size_t pkt_length, 672 __in unsigned int completed, 673 __inout unsigned int *addedp); 674 675 extern __checkReturn efx_rc_t 676 ef10_tx_qdesc_post( 677 __in efx_txq_t *etp, 678 __in_ecount(n) efx_desc_t *ed, 679 __in unsigned int n, 680 __in unsigned int completed, 681 __inout unsigned int *addedp); 682 683 extern void 684 ef10_tx_qdesc_dma_create( 685 __in efx_txq_t *etp, 686 __in efsys_dma_addr_t addr, 687 __in size_t size, 688 __in boolean_t eop, 689 __out efx_desc_t *edp); 690 691 extern void 692 ef10_tx_qdesc_tso_create( 693 __in efx_txq_t *etp, 694 __in uint16_t ipv4_id, 695 __in uint32_t tcp_seq, 696 __in uint8_t tcp_flags, 697 __out efx_desc_t *edp); 698 699 extern void 700 ef10_tx_qdesc_tso2_create( 701 __in efx_txq_t *etp, 702 __in uint16_t ipv4_id, 703 __in uint32_t tcp_seq, 704 __in uint16_t tcp_mss, 705 __out_ecount(count) efx_desc_t *edp, 706 __in int count); 707 708 extern void 709 ef10_tx_qdesc_vlantci_create( 710 __in efx_txq_t *etp, 711 __in uint16_t vlan_tci, 712 __out efx_desc_t *edp); 713 714 715 #if EFSYS_OPT_QSTATS 716 717 extern void 718 ef10_tx_qstats_update( 719 __in efx_txq_t *etp, 720 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 721 722 #endif /* EFSYS_OPT_QSTATS */ 723 724 typedef uint32_t efx_piobuf_handle_t; 725 726 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 727 728 extern __checkReturn efx_rc_t 729 ef10_nic_pio_alloc( 730 __inout efx_nic_t *enp, 731 __out uint32_t *bufnump, 732 __out efx_piobuf_handle_t *handlep, 733 __out uint32_t *blknump, 734 __out uint32_t *offsetp, 735 __out size_t *sizep); 736 737 extern __checkReturn efx_rc_t 738 ef10_nic_pio_free( 739 __inout efx_nic_t *enp, 740 __in uint32_t bufnum, 741 __in uint32_t blknum); 742 743 extern __checkReturn efx_rc_t 744 ef10_nic_pio_link( 745 __inout efx_nic_t *enp, 746 __in uint32_t vi_index, 747 __in efx_piobuf_handle_t handle); 748 749 extern __checkReturn efx_rc_t 750 ef10_nic_pio_unlink( 751 __inout efx_nic_t *enp, 752 __in uint32_t vi_index); 753 754 755 /* VPD */ 756 757 #if EFSYS_OPT_VPD 758 759 extern __checkReturn efx_rc_t 760 ef10_vpd_init( 761 __in efx_nic_t *enp); 762 763 extern __checkReturn efx_rc_t 764 ef10_vpd_size( 765 __in efx_nic_t *enp, 766 __out size_t *sizep); 767 768 extern __checkReturn efx_rc_t 769 ef10_vpd_read( 770 __in efx_nic_t *enp, 771 __out_bcount(size) caddr_t data, 772 __in size_t size); 773 774 extern __checkReturn efx_rc_t 775 ef10_vpd_verify( 776 __in efx_nic_t *enp, 777 __in_bcount(size) caddr_t data, 778 __in size_t size); 779 780 extern __checkReturn efx_rc_t 781 ef10_vpd_reinit( 782 __in efx_nic_t *enp, 783 __in_bcount(size) caddr_t data, 784 __in size_t size); 785 786 extern __checkReturn efx_rc_t 787 ef10_vpd_get( 788 __in efx_nic_t *enp, 789 __in_bcount(size) caddr_t data, 790 __in size_t size, 791 __inout efx_vpd_value_t *evvp); 792 793 extern __checkReturn efx_rc_t 794 ef10_vpd_set( 795 __in efx_nic_t *enp, 796 __in_bcount(size) caddr_t data, 797 __in size_t size, 798 __in efx_vpd_value_t *evvp); 799 800 extern __checkReturn efx_rc_t 801 ef10_vpd_next( 802 __in efx_nic_t *enp, 803 __in_bcount(size) caddr_t data, 804 __in size_t size, 805 __out efx_vpd_value_t *evvp, 806 __inout unsigned int *contp); 807 808 extern __checkReturn efx_rc_t 809 ef10_vpd_write( 810 __in efx_nic_t *enp, 811 __in_bcount(size) caddr_t data, 812 __in size_t size); 813 814 extern void 815 ef10_vpd_fini( 816 __in efx_nic_t *enp); 817 818 #endif /* EFSYS_OPT_VPD */ 819 820 821 /* RX */ 822 823 extern __checkReturn efx_rc_t 824 ef10_rx_init( 825 __in efx_nic_t *enp); 826 827 #if EFSYS_OPT_RX_SCATTER 828 extern __checkReturn efx_rc_t 829 ef10_rx_scatter_enable( 830 __in efx_nic_t *enp, 831 __in unsigned int buf_size); 832 #endif /* EFSYS_OPT_RX_SCATTER */ 833 834 835 #if EFSYS_OPT_RX_SCALE 836 837 extern __checkReturn efx_rc_t 838 ef10_rx_scale_mode_set( 839 __in efx_nic_t *enp, 840 __in efx_rx_hash_alg_t alg, 841 __in efx_rx_hash_type_t type, 842 __in boolean_t insert); 843 844 extern __checkReturn efx_rc_t 845 ef10_rx_scale_key_set( 846 __in efx_nic_t *enp, 847 __in_ecount(n) uint8_t *key, 848 __in size_t n); 849 850 extern __checkReturn efx_rc_t 851 ef10_rx_scale_tbl_set( 852 __in efx_nic_t *enp, 853 __in_ecount(n) unsigned int *table, 854 __in size_t n); 855 856 extern __checkReturn uint32_t 857 ef10_rx_prefix_hash( 858 __in efx_nic_t *enp, 859 __in efx_rx_hash_alg_t func, 860 __in uint8_t *buffer); 861 862 #endif /* EFSYS_OPT_RX_SCALE */ 863 864 extern __checkReturn efx_rc_t 865 ef10_rx_prefix_pktlen( 866 __in efx_nic_t *enp, 867 __in uint8_t *buffer, 868 __out uint16_t *lengthp); 869 870 extern void 871 ef10_rx_qpost( 872 __in efx_rxq_t *erp, 873 __in_ecount(n) efsys_dma_addr_t *addrp, 874 __in size_t size, 875 __in unsigned int n, 876 __in unsigned int completed, 877 __in unsigned int added); 878 879 extern void 880 ef10_rx_qpush( 881 __in efx_rxq_t *erp, 882 __in unsigned int added, 883 __inout unsigned int *pushedp); 884 885 extern __checkReturn efx_rc_t 886 ef10_rx_qflush( 887 __in efx_rxq_t *erp); 888 889 extern void 890 ef10_rx_qenable( 891 __in efx_rxq_t *erp); 892 893 extern __checkReturn efx_rc_t 894 ef10_rx_qcreate( 895 __in efx_nic_t *enp, 896 __in unsigned int index, 897 __in unsigned int label, 898 __in efx_rxq_type_t type, 899 __in efsys_mem_t *esmp, 900 __in size_t n, 901 __in uint32_t id, 902 __in efx_evq_t *eep, 903 __in efx_rxq_t *erp); 904 905 extern void 906 ef10_rx_qdestroy( 907 __in efx_rxq_t *erp); 908 909 extern void 910 ef10_rx_fini( 911 __in efx_nic_t *enp); 912 913 #if EFSYS_OPT_FILTER 914 915 typedef struct ef10_filter_handle_s { 916 uint32_t efh_lo; 917 uint32_t efh_hi; 918 } ef10_filter_handle_t; 919 920 typedef struct ef10_filter_entry_s { 921 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 922 ef10_filter_handle_t efe_handle; 923 } ef10_filter_entry_t; 924 925 /* 926 * BUSY flag indicates that an update is in progress. 927 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 928 */ 929 #define EFX_EF10_FILTER_FLAG_BUSY 1U 930 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 931 #define EFX_EF10_FILTER_FLAGS 3U 932 933 /* 934 * Size of the hash table used by the driver. Doesn't need to be the 935 * same size as the hardware's table. 936 */ 937 #define EFX_EF10_FILTER_TBL_ROWS 8192 938 939 /* Only need to allow for one directed and one unknown unicast filter */ 940 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2 941 942 /* Allow for the broadcast address to be added to the multicast list */ 943 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 944 945 typedef struct ef10_filter_table_s { 946 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 947 efx_rxq_t * eft_default_rxq; 948 boolean_t eft_using_rss; 949 uint32_t eft_unicst_filter_indexes[ 950 EFX_EF10_FILTER_UNICAST_FILTERS_MAX]; 951 boolean_t eft_unicst_filter_count; 952 uint32_t eft_mulcst_filter_indexes[ 953 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 954 uint32_t eft_mulcst_filter_count; 955 boolean_t eft_using_all_mulcst; 956 } ef10_filter_table_t; 957 958 __checkReturn efx_rc_t 959 ef10_filter_init( 960 __in efx_nic_t *enp); 961 962 void 963 ef10_filter_fini( 964 __in efx_nic_t *enp); 965 966 __checkReturn efx_rc_t 967 ef10_filter_restore( 968 __in efx_nic_t *enp); 969 970 __checkReturn efx_rc_t 971 ef10_filter_add( 972 __in efx_nic_t *enp, 973 __inout efx_filter_spec_t *spec, 974 __in boolean_t may_replace); 975 976 __checkReturn efx_rc_t 977 ef10_filter_delete( 978 __in efx_nic_t *enp, 979 __inout efx_filter_spec_t *spec); 980 981 extern __checkReturn efx_rc_t 982 ef10_filter_supported_filters( 983 __in efx_nic_t *enp, 984 __out uint32_t *list, 985 __out size_t *length); 986 987 extern __checkReturn efx_rc_t 988 ef10_filter_reconfigure( 989 __in efx_nic_t *enp, 990 __in_ecount(6) uint8_t const *mac_addr, 991 __in boolean_t all_unicst, 992 __in boolean_t mulcst, 993 __in boolean_t all_mulcst, 994 __in boolean_t brdcst, 995 __in_ecount(6*count) uint8_t const *addrs, 996 __in uint32_t count); 997 998 extern void 999 ef10_filter_get_default_rxq( 1000 __in efx_nic_t *enp, 1001 __out efx_rxq_t **erpp, 1002 __out boolean_t *using_rss); 1003 1004 extern void 1005 ef10_filter_default_rxq_set( 1006 __in efx_nic_t *enp, 1007 __in efx_rxq_t *erp, 1008 __in boolean_t using_rss); 1009 1010 extern void 1011 ef10_filter_default_rxq_clear( 1012 __in efx_nic_t *enp); 1013 1014 1015 #endif /* EFSYS_OPT_FILTER */ 1016 1017 extern __checkReturn efx_rc_t 1018 efx_mcdi_get_function_info( 1019 __in efx_nic_t *enp, 1020 __out uint32_t *pfp, 1021 __out_opt uint32_t *vfp); 1022 1023 extern __checkReturn efx_rc_t 1024 efx_mcdi_privilege_mask( 1025 __in efx_nic_t *enp, 1026 __in uint32_t pf, 1027 __in uint32_t vf, 1028 __out uint32_t *maskp); 1029 1030 extern __checkReturn efx_rc_t 1031 efx_mcdi_get_port_assignment( 1032 __in efx_nic_t *enp, 1033 __out uint32_t *portp); 1034 1035 extern __checkReturn efx_rc_t 1036 efx_mcdi_get_port_modes( 1037 __in efx_nic_t *enp, 1038 __out uint32_t *modesp); 1039 1040 extern __checkReturn efx_rc_t 1041 efx_mcdi_get_mac_address_pf( 1042 __in efx_nic_t *enp, 1043 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1044 1045 extern __checkReturn efx_rc_t 1046 efx_mcdi_get_mac_address_vf( 1047 __in efx_nic_t *enp, 1048 __out_ecount_opt(6) uint8_t mac_addrp[6]); 1049 1050 extern __checkReturn efx_rc_t 1051 efx_mcdi_get_clock( 1052 __in efx_nic_t *enp, 1053 __out uint32_t *sys_freqp); 1054 1055 extern __checkReturn efx_rc_t 1056 efx_mcdi_get_vector_cfg( 1057 __in efx_nic_t *enp, 1058 __out_opt uint32_t *vec_basep, 1059 __out_opt uint32_t *pf_nvecp, 1060 __out_opt uint32_t *vf_nvecp); 1061 1062 extern __checkReturn efx_rc_t 1063 ef10_get_datapath_caps( 1064 __in efx_nic_t *enp); 1065 1066 extern __checkReturn efx_rc_t 1067 ef10_get_privilege_mask( 1068 __in efx_nic_t *enp, 1069 __out uint32_t *maskp); 1070 1071 extern __checkReturn efx_rc_t 1072 ef10_external_port_mapping( 1073 __in efx_nic_t *enp, 1074 __in uint32_t port, 1075 __out uint8_t *external_portp); 1076 1077 1078 #ifdef __cplusplus 1079 } 1080 #endif 1081 1082 #endif /* _SYS_EF10_IMPL_H */ 1083