1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Marvell Xenon SDHCI controller driver. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 50 #include <dev/extres/regulator/regulator.h> 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/mmc/bridge.h> 56 #include <dev/mmc/mmc_fdt_helpers.h> 57 #include <dev/mmc/mmcbrvar.h> 58 #include <dev/mmc/mmcreg.h> 59 60 #include <dev/sdhci/sdhci.h> 61 #include <dev/sdhci/sdhci_fdt_gpio.h> 62 #include <dev/sdhci/sdhci_xenon.h> 63 64 #include "mmcbr_if.h" 65 #include "sdhci_if.h" 66 67 #include "opt_mmccam.h" 68 #include "opt_soc.h" 69 70 #define MAX_SLOTS 6 71 72 static struct ofw_compat_data compat_data[] = { 73 { "marvell,armada-3700-sdhci", 1 }, 74 #ifdef SOC_MARVELL_8K 75 { "marvell,armada-cp110-sdhci", 1 }, 76 { "marvell,armada-ap806-sdhci", 1 }, 77 #endif 78 { NULL, 0 } 79 }; 80 81 struct sdhci_xenon_softc { 82 device_t dev; /* Controller device */ 83 int slot_id; /* Controller ID */ 84 phandle_t node; /* FDT node */ 85 uint32_t quirks; /* Chip specific quirks */ 86 uint32_t caps; /* If we override SDHCI_CAPABILITIES */ 87 uint32_t max_clk; /* Max possible freq */ 88 struct resource *irq_res; /* IRQ resource */ 89 void *intrhand; /* Interrupt handle */ 90 struct sdhci_fdt_gpio *gpio; /* GPIO pins for CD detection. */ 91 92 struct sdhci_slot *slot; /* SDHCI internal data */ 93 struct resource *mem_res; /* Memory resource */ 94 95 uint8_t znr; /* PHY ZNR */ 96 uint8_t zpr; /* PHY ZPR */ 97 bool no_18v; /* No 1.8V support */ 98 bool slow_mode; /* PHY slow mode */ 99 100 struct mmc_fdt_helper mmc_helper; /* MMC helper for parsing FDT */ 101 }; 102 103 static uint8_t 104 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused, 105 bus_size_t off) 106 { 107 struct sdhci_xenon_softc *sc = device_get_softc(dev); 108 109 return (bus_read_1(sc->mem_res, off)); 110 } 111 112 static void 113 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused, 114 bus_size_t off, uint8_t val) 115 { 116 struct sdhci_xenon_softc *sc = device_get_softc(dev); 117 118 bus_write_1(sc->mem_res, off, val); 119 } 120 121 static uint16_t 122 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused, 123 bus_size_t off) 124 { 125 struct sdhci_xenon_softc *sc = device_get_softc(dev); 126 127 return (bus_read_2(sc->mem_res, off)); 128 } 129 130 static void 131 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused, 132 bus_size_t off, uint16_t val) 133 { 134 struct sdhci_xenon_softc *sc = device_get_softc(dev); 135 136 bus_write_2(sc->mem_res, off, val); 137 } 138 139 static uint32_t 140 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused, 141 bus_size_t off) 142 { 143 struct sdhci_xenon_softc *sc = device_get_softc(dev); 144 145 return bus_read_4(sc->mem_res, off); 146 } 147 148 static void 149 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused, 150 bus_size_t off, uint32_t val) 151 { 152 struct sdhci_xenon_softc *sc = device_get_softc(dev); 153 154 bus_write_4(sc->mem_res, off, val); 155 } 156 157 static void 158 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 159 bus_size_t off, uint32_t *data, bus_size_t count) 160 { 161 struct sdhci_xenon_softc *sc = device_get_softc(dev); 162 163 bus_read_multi_4(sc->mem_res, off, data, count); 164 } 165 166 static void 167 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 168 bus_size_t off, uint32_t *data, bus_size_t count) 169 { 170 struct sdhci_xenon_softc *sc = device_get_softc(dev); 171 172 bus_write_multi_4(sc->mem_res, off, data, count); 173 } 174 175 static void 176 sdhci_xenon_intr(void *arg) 177 { 178 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg; 179 180 sdhci_generic_intr(sc->slot); 181 } 182 183 static int 184 sdhci_xenon_get_ro(device_t bus, device_t dev) 185 { 186 struct sdhci_xenon_softc *sc = device_get_softc(bus); 187 188 return (sdhci_generic_get_ro(bus, dev) ^ 189 (sc->mmc_helper.props & MMC_PROP_WP_INVERTED)); 190 } 191 192 static bool 193 sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot) 194 { 195 struct sdhci_xenon_softc *sc = device_get_softc(dev); 196 197 return (sdhci_fdt_gpio_get_present(sc->gpio)); 198 } 199 200 static void 201 sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot) 202 { 203 const struct mmc_ios *ios; 204 uint16_t hostctrl2; 205 206 if (slot->version < SDHCI_SPEC_300) 207 return; 208 209 mtx_assert(&slot->mtx, MA_OWNED); 210 ios = &slot->host.ios; 211 212 /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */ 213 hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2); 214 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 215 if (ios->clock > SD_SDR50_MAX) { 216 if (ios->timing == bus_timing_mmc_hs400 || 217 ios->timing == bus_timing_mmc_hs400es) 218 hostctrl2 |= XENON_CTRL2_MMC_HS400; 219 else if (ios->timing == bus_timing_mmc_hs200) 220 hostctrl2 |= XENON_CTRL2_MMC_HS200; 221 else 222 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 223 } 224 else if (ios->clock > SD_SDR25_MAX) 225 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 226 else if (ios->clock > SD_SDR12_MAX) { 227 if (ios->timing == bus_timing_uhs_ddr50 || 228 ios->timing == bus_timing_mmc_ddr52) 229 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 230 else 231 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 232 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 233 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 234 sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2); 235 } 236 237 static int 238 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios) 239 { 240 int i; 241 struct sdhci_xenon_softc *sc; 242 uint32_t reg; 243 244 sc = device_get_softc(brdev); 245 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 246 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT; 247 switch (ios->timing) { 248 case bus_timing_normal: 249 case bus_timing_hs: 250 case bus_timing_uhs_sdr12: 251 case bus_timing_uhs_sdr25: 252 case bus_timing_uhs_sdr50: 253 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 254 break; 255 default: 256 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 257 } 258 if (sc->slow_mode) 259 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 260 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 261 262 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 263 reg |= XENON_PHY_INITIALIZATION; 264 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 265 266 /* Wait for the eMMC PHY init. */ 267 for (i = 100; i > 0; i--) { 268 DELAY(100); 269 270 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 271 if ((reg & XENON_PHY_INITIALIZATION) == 0) 272 break; 273 } 274 275 if (i == 0) { 276 device_printf(brdev, "eMMC PHY failed to initialize\n"); 277 return (ETIMEDOUT); 278 } 279 280 return (0); 281 } 282 283 static int 284 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios) 285 { 286 struct sdhci_xenon_softc *sc; 287 uint32_t reg; 288 289 sc = device_get_softc(brdev); 290 /* Setup pad, set bit[28] and bits[26:24] */ 291 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL); 292 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 293 XENON_FC_QSP_RECEN | XENON_OEN_QSN); 294 /* All FC_XX_RECEIVCE should be set as CMOS Type */ 295 reg |= XENON_FC_ALL_CMOS_RECEIVER; 296 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg); 297 298 /* Set CMD and DQ Pull Up */ 299 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 300 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU); 301 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD); 302 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 303 304 if (ios->timing == bus_timing_normal) 305 return (sdhci_xenon_phy_init(brdev, ios)); 306 307 /* Clear SDIO mode, no SDIO support for now. */ 308 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 309 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 310 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 311 312 /* 313 * Set preferred ZNR and ZPR value. 314 * The ZNR and ZPR value vary between different boards. 315 * Define them both in the DTS for the board! 316 */ 317 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2); 318 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 319 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr); 320 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg); 321 322 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */ 323 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 324 reg &= ~SDHCI_CLOCK_CARD_EN; 325 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 326 327 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL); 328 switch (ios->timing) { 329 case bus_timing_mmc_hs400: 330 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 331 XENON_CMD_DDR_MODE; 332 reg &= ~XENON_DQ_ASYNC_MODE; 333 break; 334 case bus_timing_uhs_ddr50: 335 case bus_timing_mmc_ddr52: 336 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 337 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 338 break; 339 default: 340 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 341 XENON_CMD_DDR_MODE); 342 reg |= XENON_DQ_ASYNC_MODE; 343 } 344 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg); 345 346 /* Enable SD clock. */ 347 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 348 reg |= SDHCI_CLOCK_CARD_EN; 349 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 350 351 if (ios->timing == bus_timing_mmc_hs400) 352 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 353 XENON_LOGIC_TIMING_VALUE); 354 else { 355 /* Disable both SDHC Data Strobe and Enhanced Strobe. */ 356 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL); 357 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); 358 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg); 359 360 /* Clear Strobe line Pull down or Pull up. */ 361 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 362 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU); 363 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 364 } 365 366 return (sdhci_xenon_phy_init(brdev, ios)); 367 } 368 369 static int 370 sdhci_xenon_update_ios(device_t brdev, device_t reqdev) 371 { 372 int err; 373 struct sdhci_xenon_softc *sc; 374 struct mmc_ios *ios; 375 struct sdhci_slot *slot; 376 uint32_t reg; 377 378 err = sdhci_generic_update_ios(brdev, reqdev); 379 if (err != 0) 380 return (err); 381 382 sc = device_get_softc(brdev); 383 slot = device_get_ivars(reqdev); 384 ios = &slot->host.ios; 385 386 switch (ios->power_mode) { 387 case power_on: 388 break; 389 case power_off: 390 if (bootverbose) 391 device_printf(sc->dev, "Powering down sd/mmc\n"); 392 393 if (sc->mmc_helper.vmmc_supply) 394 regulator_disable(sc->mmc_helper.vmmc_supply); 395 if (sc->mmc_helper.vqmmc_supply) 396 regulator_disable(sc->mmc_helper.vqmmc_supply); 397 break; 398 case power_up: 399 if (bootverbose) 400 device_printf(sc->dev, "Powering up sd/mmc\n"); 401 402 if (sc->mmc_helper.vmmc_supply) 403 regulator_enable(sc->mmc_helper.vmmc_supply); 404 if (sc->mmc_helper.vqmmc_supply) 405 regulator_enable(sc->mmc_helper.vqmmc_supply); 406 break; 407 }; 408 409 /* Update the PHY settings. */ 410 if (ios->clock != 0) 411 sdhci_xenon_phy_set(brdev, ios); 412 413 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) { 414 /* Enable SDCLK_IDLEOFF. */ 415 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 416 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id); 417 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 418 } 419 420 return (0); 421 } 422 423 static int 424 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev) 425 { 426 struct sdhci_xenon_softc *sc; 427 struct sdhci_slot *slot; 428 uint16_t hostctrl2; 429 int uvolt, err; 430 431 slot = device_get_ivars(reqdev); 432 433 if (slot->version < SDHCI_SPEC_300) 434 return (0); 435 436 sc = device_get_softc(brdev); 437 438 if (sc->mmc_helper.vqmmc_supply == NULL) 439 return EOPNOTSUPP; 440 441 err = 0; 442 443 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 444 switch (slot->host.ios.vccq) { 445 case vccq_330: 446 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 447 return (0); 448 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 449 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 450 451 uvolt = 3300000; 452 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, 453 uvolt, uvolt); 454 if (err != 0) { 455 device_printf(sc->dev, 456 "Cannot set vqmmc to %d<->%d\n", 457 uvolt, 458 uvolt); 459 return (err); 460 } 461 462 /* 463 * According to the 'SD Host Controller Simplified 464 * Specification 4.20 the host driver should take more 465 * than 5ms for stable time of host voltage regulator 466 * from changing 1.8V Signaling Enable. 467 */ 468 DELAY(5000); 469 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 470 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 471 return (0); 472 return EAGAIN; 473 case vccq_180: 474 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 475 return EINVAL; 476 } 477 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 478 return (0); 479 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 480 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 481 482 uvolt = 1800000; 483 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, 484 uvolt, uvolt); 485 if (err != 0) { 486 device_printf(sc->dev, 487 "Cannot set vqmmc to %d<->%d\n", 488 uvolt, 489 uvolt); 490 return (err); 491 } 492 493 /* 494 * According to the 'SD Host Controller Simplified 495 * Specification 4.20 the host driver should take more 496 * than 5ms for stable time of host voltage regulator 497 * from changing 1.8V Signaling Enable. 498 */ 499 DELAY(5000); 500 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 501 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 502 return (0); 503 return EAGAIN; 504 default: 505 device_printf(brdev, 506 "Attempt to set unsupported signaling voltage\n"); 507 return EINVAL; 508 } 509 } 510 511 static int 512 sdhci_xenon_probe(device_t dev) 513 { 514 struct sdhci_xenon_softc *sc = device_get_softc(dev); 515 pcell_t cid; 516 517 sc->quirks = 0; 518 sc->slot_id = 0; 519 sc->max_clk = XENON_MMC_MAX_CLK; 520 521 if (!ofw_bus_status_okay(dev)) 522 return (ENXIO); 523 524 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 525 return (ENXIO); 526 527 sc->node = ofw_bus_get_node(dev); 528 device_set_desc(dev, "Armada Xenon SDHCI controller"); 529 530 /* Allow dts to patch quirks, slots, and max-frequency. */ 531 if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0) 532 sc->quirks = cid; 533 if ((OF_getencprop(sc->node, "max-frequency", &cid, sizeof(cid))) > 0) 534 sc->max_clk = cid; 535 if (OF_hasprop(sc->node, "no-1-8-v")) 536 sc->no_18v = true; 537 if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode")) 538 sc->slow_mode = true; 539 sc->znr = XENON_ZNR_DEF_VALUE; 540 if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid, 541 sizeof(cid))) > 0) 542 sc->znr = cid & XENON_ZNR_MASK; 543 sc->zpr = XENON_ZPR_DEF_VALUE; 544 if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid, 545 sizeof(cid))) > 0) 546 sc->zpr = cid & XENON_ZPR_MASK; 547 548 return (0); 549 } 550 551 static int 552 sdhci_xenon_attach(device_t dev) 553 { 554 struct sdhci_xenon_softc *sc = device_get_softc(dev); 555 struct sdhci_slot *slot; 556 int err, rid; 557 uint32_t reg; 558 559 sc->dev = dev; 560 561 /* Allocate IRQ. */ 562 rid = 0; 563 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 564 RF_ACTIVE); 565 if (sc->irq_res == NULL) { 566 device_printf(dev, "Can't allocate IRQ\n"); 567 return (ENOMEM); 568 } 569 570 /* Allocate memory. */ 571 rid = 0; 572 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 573 &rid, RF_ACTIVE); 574 if (sc->mem_res == NULL) { 575 bus_release_resource(dev, SYS_RES_IRQ, 576 rman_get_rid(sc->irq_res), sc->irq_res); 577 device_printf(dev, "Can't allocate memory for slot\n"); 578 return (ENOMEM); 579 } 580 581 slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK); 582 583 /* Check if the device is flagged as non-removable. */ 584 if (OF_hasprop(sc->node, "non-removable")) { 585 slot->opt |= SDHCI_NON_REMOVABLE; 586 if (bootverbose) 587 device_printf(dev, "Non-removable media\n"); 588 } 589 590 slot->quirks = sc->quirks; 591 slot->caps = sc->caps; 592 slot->max_clk = sc->max_clk; 593 sc->slot = slot; 594 595 /* 596 * Set up any gpio pin handling described in the FDT data. This cannot 597 * fail; see comments in sdhci_fdt_gpio.h for details. 598 */ 599 sc->gpio = sdhci_fdt_gpio_setup(dev, slot); 600 601 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->slot->host); 602 603 if (sdhci_init_slot(dev, sc->slot, 0)) 604 goto fail; 605 606 /* 1.2V signaling is not supported. */ 607 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_120; 608 609 /* Disable UHS in case of lack of 1.8V VCCQ or the PHY slow mode. */ 610 if (sc->no_18v || sc->slow_mode) 611 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_180; 612 613 /* Activate the interrupt */ 614 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 615 NULL, sdhci_xenon_intr, sc, &sc->intrhand); 616 if (err) { 617 device_printf(dev, "Cannot setup IRQ\n"); 618 goto fail; 619 } 620 621 /* Disable Auto Clock Gating. */ 622 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 623 reg |= XENON_AUTO_CLKGATE_DISABLE; 624 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 625 626 /* Enable this SD controller. */ 627 reg |= (1 << sc->slot_id); 628 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 629 630 /* Enable Parallel Transfer. */ 631 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 632 reg |= (1 << sc->slot_id); 633 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 634 635 /* Enable Auto Clock Gating. */ 636 reg &= ~XENON_AUTO_CLKGATE_DISABLE; 637 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 638 639 /* Disable SDCLK_IDLEOFF before the card initialization. */ 640 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 641 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id)); 642 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 643 644 /* Mask command conflict errors. */ 645 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 646 reg |= XENON_MASK_CMD_CONFLICT_ERR; 647 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 648 649 /* Process cards detection. */ 650 sdhci_start_slot(sc->slot); 651 652 return (0); 653 654 fail: 655 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 656 sc->irq_res); 657 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 658 sc->mem_res); 659 free(sc->slot, M_DEVBUF); 660 sc->slot = NULL; 661 662 return (ENXIO); 663 } 664 665 static int 666 sdhci_xenon_detach(device_t dev) 667 { 668 struct sdhci_xenon_softc *sc = device_get_softc(dev); 669 670 if (sc->gpio != NULL) 671 sdhci_fdt_gpio_teardown(sc->gpio); 672 673 bus_generic_detach(dev); 674 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 675 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 676 sc->irq_res); 677 sdhci_cleanup_slot(sc->slot); 678 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 679 sc->mem_res); 680 free(sc->slot, M_DEVBUF); 681 sc->slot = NULL; 682 683 return (0); 684 } 685 686 static device_method_t sdhci_xenon_methods[] = { 687 /* device_if */ 688 DEVMETHOD(device_probe, sdhci_xenon_probe), 689 DEVMETHOD(device_attach, sdhci_xenon_attach), 690 DEVMETHOD(device_detach, sdhci_xenon_detach), 691 692 /* Bus interface */ 693 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 694 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 695 696 /* mmcbr_if */ 697 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios), 698 DEVMETHOD(mmcbr_request, sdhci_generic_request), 699 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro), 700 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 701 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 702 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq), 703 DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 704 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 705 706 /* SDHCI registers accessors */ 707 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1), 708 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2), 709 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4), 710 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4), 711 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1), 712 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2), 713 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4), 714 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4), 715 DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present), 716 DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing), 717 718 DEVMETHOD_END 719 }; 720 721 static driver_t sdhci_xenon_driver = { 722 "sdhci_xenon", 723 sdhci_xenon_methods, 724 sizeof(struct sdhci_xenon_softc), 725 }; 726 static devclass_t sdhci_xenon_devclass; 727 728 DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass, 729 NULL, NULL); 730 731 SDHCI_DEPEND(sdhci_xenon); 732 #ifndef MMCCAM 733 MMC_DECLARE_BRIDGE(sdhci_xenon); 734 #endif 735