1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Marvell Xenon SDHCI controller driver. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 50 #include <dev/extres/regulator/regulator.h> 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/mmc/bridge.h> 56 #include <dev/mmc/mmc_fdt_helpers.h> 57 #include <dev/mmc/mmcbrvar.h> 58 #include <dev/mmc/mmcreg.h> 59 60 #include <dev/sdhci/sdhci.h> 61 #include <dev/sdhci/sdhci_fdt_gpio.h> 62 #include <dev/sdhci/sdhci_xenon.h> 63 64 #include "mmcbr_if.h" 65 #include "sdhci_if.h" 66 67 #include "opt_mmccam.h" 68 #include "opt_soc.h" 69 70 #define MAX_SLOTS 6 71 72 static struct ofw_compat_data compat_data[] = { 73 { "marvell,armada-3700-sdhci", 1 }, 74 #ifdef SOC_MARVELL_8K 75 { "marvell,armada-cp110-sdhci", 1 }, 76 { "marvell,armada-ap806-sdhci", 1 }, 77 { "marvell,armada-ap807-sdhci", 1 }, 78 #endif 79 { NULL, 0 } 80 }; 81 82 struct sdhci_xenon_softc { 83 device_t dev; /* Controller device */ 84 int slot_id; /* Controller ID */ 85 phandle_t node; /* FDT node */ 86 struct resource *irq_res; /* IRQ resource */ 87 void *intrhand; /* Interrupt handle */ 88 struct sdhci_fdt_gpio *gpio; /* GPIO pins for CD detection. */ 89 90 struct sdhci_slot *slot; /* SDHCI internal data */ 91 struct resource *mem_res; /* Memory resource */ 92 93 uint8_t znr; /* PHY ZNR */ 94 uint8_t zpr; /* PHY ZPR */ 95 bool slow_mode; /* PHY slow mode */ 96 97 struct mmc_fdt_helper mmc_helper; /* MMC helper for parsing FDT */ 98 }; 99 100 static uint8_t 101 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused, 102 bus_size_t off) 103 { 104 struct sdhci_xenon_softc *sc = device_get_softc(dev); 105 106 return (bus_read_1(sc->mem_res, off)); 107 } 108 109 static void 110 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused, 111 bus_size_t off, uint8_t val) 112 { 113 struct sdhci_xenon_softc *sc = device_get_softc(dev); 114 115 bus_write_1(sc->mem_res, off, val); 116 } 117 118 static uint16_t 119 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused, 120 bus_size_t off) 121 { 122 struct sdhci_xenon_softc *sc = device_get_softc(dev); 123 124 return (bus_read_2(sc->mem_res, off)); 125 } 126 127 static void 128 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused, 129 bus_size_t off, uint16_t val) 130 { 131 struct sdhci_xenon_softc *sc = device_get_softc(dev); 132 133 bus_write_2(sc->mem_res, off, val); 134 } 135 136 static uint32_t 137 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused, 138 bus_size_t off) 139 { 140 struct sdhci_xenon_softc *sc = device_get_softc(dev); 141 142 return bus_read_4(sc->mem_res, off); 143 } 144 145 static void 146 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused, 147 bus_size_t off, uint32_t val) 148 { 149 struct sdhci_xenon_softc *sc = device_get_softc(dev); 150 151 bus_write_4(sc->mem_res, off, val); 152 } 153 154 static void 155 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 156 bus_size_t off, uint32_t *data, bus_size_t count) 157 { 158 struct sdhci_xenon_softc *sc = device_get_softc(dev); 159 160 bus_read_multi_4(sc->mem_res, off, data, count); 161 } 162 163 static void 164 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 165 bus_size_t off, uint32_t *data, bus_size_t count) 166 { 167 struct sdhci_xenon_softc *sc = device_get_softc(dev); 168 169 bus_write_multi_4(sc->mem_res, off, data, count); 170 } 171 172 static void 173 sdhci_xenon_intr(void *arg) 174 { 175 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg; 176 177 sdhci_generic_intr(sc->slot); 178 } 179 180 static int 181 sdhci_xenon_get_ro(device_t bus, device_t dev) 182 { 183 struct sdhci_xenon_softc *sc = device_get_softc(bus); 184 185 return (sdhci_generic_get_ro(bus, dev) ^ 186 (sc->mmc_helper.props & MMC_PROP_WP_INVERTED)); 187 } 188 189 static bool 190 sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot) 191 { 192 struct sdhci_xenon_softc *sc = device_get_softc(dev); 193 194 return (sdhci_fdt_gpio_get_present(sc->gpio)); 195 } 196 197 static void 198 sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot) 199 { 200 const struct mmc_ios *ios; 201 uint16_t hostctrl2; 202 203 if (slot->version < SDHCI_SPEC_300) 204 return; 205 206 mtx_assert(&slot->mtx, MA_OWNED); 207 ios = &slot->host.ios; 208 209 /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */ 210 hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2); 211 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 212 if (ios->clock > SD_SDR50_MAX) { 213 if (ios->timing == bus_timing_mmc_hs400 || 214 ios->timing == bus_timing_mmc_hs400es) 215 hostctrl2 |= XENON_CTRL2_MMC_HS400; 216 else if (ios->timing == bus_timing_mmc_hs200) 217 hostctrl2 |= XENON_CTRL2_MMC_HS200; 218 else 219 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 220 } 221 else if (ios->clock > SD_SDR25_MAX) 222 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 223 else if (ios->clock > SD_SDR12_MAX) { 224 if (ios->timing == bus_timing_uhs_ddr50 || 225 ios->timing == bus_timing_mmc_ddr52) 226 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 227 else 228 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 229 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 230 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 231 sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2); 232 } 233 234 static int 235 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios) 236 { 237 int i; 238 struct sdhci_xenon_softc *sc; 239 uint32_t reg; 240 241 sc = device_get_softc(brdev); 242 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 243 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT; 244 switch (ios->timing) { 245 case bus_timing_normal: 246 case bus_timing_hs: 247 case bus_timing_uhs_sdr12: 248 case bus_timing_uhs_sdr25: 249 case bus_timing_uhs_sdr50: 250 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 251 break; 252 default: 253 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 254 } 255 if (sc->slow_mode) 256 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 257 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 258 259 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 260 reg |= XENON_PHY_INITIALIZATION; 261 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 262 263 /* Wait for the eMMC PHY init. */ 264 for (i = 100; i > 0; i--) { 265 DELAY(100); 266 267 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 268 if ((reg & XENON_PHY_INITIALIZATION) == 0) 269 break; 270 } 271 272 if (i == 0) { 273 device_printf(brdev, "eMMC PHY failed to initialize\n"); 274 return (ETIMEDOUT); 275 } 276 277 return (0); 278 } 279 280 static int 281 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios) 282 { 283 struct sdhci_xenon_softc *sc; 284 uint32_t reg; 285 286 sc = device_get_softc(brdev); 287 /* Setup pad, set bit[28] and bits[26:24] */ 288 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL); 289 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 290 XENON_FC_QSP_RECEN | XENON_OEN_QSN); 291 /* All FC_XX_RECEIVCE should be set as CMOS Type */ 292 reg |= XENON_FC_ALL_CMOS_RECEIVER; 293 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg); 294 295 /* Set CMD and DQ Pull Up */ 296 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 297 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU); 298 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD); 299 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 300 301 if (ios->timing == bus_timing_normal) 302 return (sdhci_xenon_phy_init(brdev, ios)); 303 304 /* Clear SDIO mode, no SDIO support for now. */ 305 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 306 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 307 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 308 309 /* 310 * Set preferred ZNR and ZPR value. 311 * The ZNR and ZPR value vary between different boards. 312 * Define them both in the DTS for the board! 313 */ 314 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2); 315 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 316 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr); 317 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg); 318 319 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */ 320 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 321 reg &= ~SDHCI_CLOCK_CARD_EN; 322 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 323 324 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL); 325 switch (ios->timing) { 326 case bus_timing_mmc_hs400: 327 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 328 XENON_CMD_DDR_MODE; 329 reg &= ~XENON_DQ_ASYNC_MODE; 330 break; 331 case bus_timing_uhs_ddr50: 332 case bus_timing_mmc_ddr52: 333 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 334 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 335 break; 336 default: 337 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 338 XENON_CMD_DDR_MODE); 339 reg |= XENON_DQ_ASYNC_MODE; 340 } 341 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg); 342 343 /* Enable SD clock. */ 344 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 345 reg |= SDHCI_CLOCK_CARD_EN; 346 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 347 348 if (ios->timing == bus_timing_mmc_hs400) 349 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 350 XENON_LOGIC_TIMING_VALUE); 351 else { 352 /* Disable both SDHC Data Strobe and Enhanced Strobe. */ 353 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL); 354 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); 355 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg); 356 357 /* Clear Strobe line Pull down or Pull up. */ 358 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 359 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU); 360 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 361 } 362 363 return (sdhci_xenon_phy_init(brdev, ios)); 364 } 365 366 static int 367 sdhci_xenon_update_ios(device_t brdev, device_t reqdev) 368 { 369 int err; 370 struct sdhci_xenon_softc *sc; 371 struct mmc_ios *ios; 372 struct sdhci_slot *slot; 373 uint32_t reg; 374 375 err = sdhci_generic_update_ios(brdev, reqdev); 376 if (err != 0) 377 return (err); 378 379 sc = device_get_softc(brdev); 380 slot = device_get_ivars(reqdev); 381 ios = &slot->host.ios; 382 383 switch (ios->power_mode) { 384 case power_on: 385 break; 386 case power_off: 387 if (bootverbose) 388 device_printf(sc->dev, "Powering down sd/mmc\n"); 389 390 if (sc->mmc_helper.vmmc_supply) 391 regulator_disable(sc->mmc_helper.vmmc_supply); 392 if (sc->mmc_helper.vqmmc_supply) 393 regulator_disable(sc->mmc_helper.vqmmc_supply); 394 break; 395 case power_up: 396 if (bootverbose) 397 device_printf(sc->dev, "Powering up sd/mmc\n"); 398 399 if (sc->mmc_helper.vmmc_supply) 400 regulator_enable(sc->mmc_helper.vmmc_supply); 401 if (sc->mmc_helper.vqmmc_supply) 402 regulator_enable(sc->mmc_helper.vqmmc_supply); 403 break; 404 }; 405 406 /* Update the PHY settings. */ 407 if (ios->clock != 0) 408 sdhci_xenon_phy_set(brdev, ios); 409 410 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) { 411 /* Enable SDCLK_IDLEOFF. */ 412 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 413 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id); 414 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 415 } 416 417 return (0); 418 } 419 420 static int 421 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev) 422 { 423 struct sdhci_xenon_softc *sc; 424 struct sdhci_slot *slot; 425 uint16_t hostctrl2; 426 int uvolt, err; 427 428 slot = device_get_ivars(reqdev); 429 430 if (slot->version < SDHCI_SPEC_300) 431 return (0); 432 433 sc = device_get_softc(brdev); 434 435 if (sc->mmc_helper.vqmmc_supply == NULL) 436 return EOPNOTSUPP; 437 438 err = 0; 439 440 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 441 switch (slot->host.ios.vccq) { 442 case vccq_330: 443 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 444 return (0); 445 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 446 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 447 448 uvolt = 3300000; 449 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, 450 uvolt, uvolt); 451 if (err != 0) { 452 device_printf(sc->dev, 453 "Cannot set vqmmc to %d<->%d\n", 454 uvolt, 455 uvolt); 456 return (err); 457 } 458 459 /* 460 * According to the 'SD Host Controller Simplified 461 * Specification 4.20 the host driver should take more 462 * than 5ms for stable time of host voltage regulator 463 * from changing 1.8V Signaling Enable. 464 */ 465 DELAY(5000); 466 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 467 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 468 return (0); 469 return EAGAIN; 470 case vccq_180: 471 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 472 return EINVAL; 473 } 474 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 475 return (0); 476 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 477 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 478 479 uvolt = 1800000; 480 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, 481 uvolt, uvolt); 482 if (err != 0) { 483 device_printf(sc->dev, 484 "Cannot set vqmmc to %d<->%d\n", 485 uvolt, 486 uvolt); 487 return (err); 488 } 489 490 /* 491 * According to the 'SD Host Controller Simplified 492 * Specification 4.20 the host driver should take more 493 * than 5ms for stable time of host voltage regulator 494 * from changing 1.8V Signaling Enable. 495 */ 496 DELAY(5000); 497 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 498 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 499 return (0); 500 return EAGAIN; 501 default: 502 device_printf(brdev, 503 "Attempt to set unsupported signaling voltage\n"); 504 return EINVAL; 505 } 506 } 507 508 static void 509 sdhci_xenon_fdt_parse(device_t dev, struct sdhci_slot *slot) 510 { 511 struct sdhci_xenon_softc *sc = device_get_softc(dev); 512 pcell_t cid; 513 514 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &slot->host); 515 516 /* Allow dts to patch quirks, slots, and max-frequency. */ 517 if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0) 518 slot->quirks = cid; 519 if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode")) 520 sc->slow_mode = true; 521 sc->znr = XENON_ZNR_DEF_VALUE; 522 if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid, 523 sizeof(cid))) > 0) 524 sc->znr = cid & XENON_ZNR_MASK; 525 sc->zpr = XENON_ZPR_DEF_VALUE; 526 if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid, 527 sizeof(cid))) > 0) 528 sc->zpr = cid & XENON_ZPR_MASK; 529 } 530 531 static int 532 sdhci_xenon_probe(device_t dev) 533 { 534 if (!ofw_bus_status_okay(dev)) 535 return (ENXIO); 536 537 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 538 return (ENXIO); 539 540 device_set_desc(dev, "Armada Xenon SDHCI controller"); 541 542 return (0); 543 } 544 545 static int 546 sdhci_xenon_attach(device_t dev) 547 { 548 struct sdhci_xenon_softc *sc = device_get_softc(dev); 549 struct sdhci_slot *slot; 550 int err, rid; 551 uint32_t reg; 552 553 sc->dev = dev; 554 sc->slot_id = 0; 555 sc->node = ofw_bus_get_node(dev); 556 557 /* Allocate IRQ. */ 558 rid = 0; 559 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 560 RF_ACTIVE); 561 if (sc->irq_res == NULL) { 562 device_printf(dev, "Can't allocate IRQ\n"); 563 return (ENOMEM); 564 } 565 566 /* Allocate memory. */ 567 rid = 0; 568 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 569 &rid, RF_ACTIVE); 570 if (sc->mem_res == NULL) { 571 bus_release_resource(dev, SYS_RES_IRQ, 572 rman_get_rid(sc->irq_res), sc->irq_res); 573 device_printf(dev, "Can't allocate memory for slot\n"); 574 return (ENOMEM); 575 } 576 577 slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK); 578 579 /* 580 * Set up any gpio pin handling described in the FDT data. This cannot 581 * fail; see comments in sdhci_fdt_gpio.h for details. 582 */ 583 sc->gpio = sdhci_fdt_gpio_setup(dev, slot); 584 585 sdhci_xenon_fdt_parse(dev, slot); 586 587 slot->max_clk = XENON_MMC_MAX_CLK; 588 if (slot->host.f_max > 0) 589 slot->max_clk = slot->host.f_max; 590 /* Check if the device is flagged as non-removable. */ 591 if (sc->mmc_helper.props & MMC_PROP_NON_REMOVABLE) { 592 slot->opt |= SDHCI_NON_REMOVABLE; 593 if (bootverbose) 594 device_printf(dev, "Non-removable media\n"); 595 } 596 597 sc->slot = slot; 598 599 if (sdhci_init_slot(dev, sc->slot, 0)) 600 goto fail; 601 602 /* 1.2V signaling is not supported. */ 603 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_120; 604 605 /* Disable UHS in case of the PHY slow mode. */ 606 if (sc->slow_mode) 607 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_180; 608 609 /* Activate the interrupt */ 610 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 611 NULL, sdhci_xenon_intr, sc, &sc->intrhand); 612 if (err) { 613 device_printf(dev, "Cannot setup IRQ\n"); 614 goto fail; 615 } 616 617 /* Disable Auto Clock Gating. */ 618 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 619 reg |= XENON_AUTO_CLKGATE_DISABLE; 620 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 621 622 /* Enable this SD controller. */ 623 reg |= (1 << sc->slot_id); 624 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 625 626 /* Enable Parallel Transfer. */ 627 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 628 reg |= (1 << sc->slot_id); 629 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 630 631 /* Enable Auto Clock Gating. */ 632 reg &= ~XENON_AUTO_CLKGATE_DISABLE; 633 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 634 635 /* Disable SDCLK_IDLEOFF before the card initialization. */ 636 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 637 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id)); 638 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 639 640 /* Mask command conflict errors. */ 641 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 642 reg |= XENON_MASK_CMD_CONFLICT_ERR; 643 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 644 645 /* Process cards detection. */ 646 sdhci_start_slot(sc->slot); 647 648 return (0); 649 650 fail: 651 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 652 sc->irq_res); 653 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 654 sc->mem_res); 655 free(sc->slot, M_DEVBUF); 656 sc->slot = NULL; 657 658 return (ENXIO); 659 } 660 661 static int 662 sdhci_xenon_detach(device_t dev) 663 { 664 struct sdhci_xenon_softc *sc = device_get_softc(dev); 665 666 if (sc->gpio != NULL) 667 sdhci_fdt_gpio_teardown(sc->gpio); 668 669 bus_generic_detach(dev); 670 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 671 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 672 sc->irq_res); 673 sdhci_cleanup_slot(sc->slot); 674 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 675 sc->mem_res); 676 free(sc->slot, M_DEVBUF); 677 sc->slot = NULL; 678 679 return (0); 680 } 681 682 static device_method_t sdhci_xenon_methods[] = { 683 /* device_if */ 684 DEVMETHOD(device_probe, sdhci_xenon_probe), 685 DEVMETHOD(device_attach, sdhci_xenon_attach), 686 DEVMETHOD(device_detach, sdhci_xenon_detach), 687 688 /* Bus interface */ 689 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 690 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 691 692 /* mmcbr_if */ 693 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios), 694 DEVMETHOD(mmcbr_request, sdhci_generic_request), 695 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro), 696 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 697 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 698 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq), 699 DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 700 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 701 702 /* SDHCI registers accessors */ 703 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1), 704 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2), 705 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4), 706 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4), 707 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1), 708 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2), 709 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4), 710 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4), 711 DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present), 712 DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing), 713 714 DEVMETHOD_END 715 }; 716 717 static driver_t sdhci_xenon_driver = { 718 "sdhci_xenon", 719 sdhci_xenon_methods, 720 sizeof(struct sdhci_xenon_softc), 721 }; 722 static devclass_t sdhci_xenon_devclass; 723 724 DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass, 725 NULL, NULL); 726 727 SDHCI_DEPEND(sdhci_xenon); 728 #ifndef MMCCAM 729 MMC_DECLARE_BRIDGE(sdhci_xenon); 730 #endif 731