1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Marvell Xenon SDHCI controller driver. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <dev/extres/regulator/regulator.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcbrvar.h> 53 #include <dev/mmc/mmcreg.h> 54 55 #include <dev/sdhci/sdhci.h> 56 #include <dev/sdhci/sdhci_xenon.h> 57 58 #include "mmcbr_if.h" 59 #include "sdhci_if.h" 60 61 #include "opt_mmccam.h" 62 #include "opt_soc.h" 63 64 #define MAX_SLOTS 6 65 66 static uint8_t 67 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused, 68 bus_size_t off) 69 { 70 struct sdhci_xenon_softc *sc = device_get_softc(dev); 71 72 return (bus_read_1(sc->mem_res, off)); 73 } 74 75 static void 76 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused, 77 bus_size_t off, uint8_t val) 78 { 79 struct sdhci_xenon_softc *sc = device_get_softc(dev); 80 81 bus_write_1(sc->mem_res, off, val); 82 } 83 84 static uint16_t 85 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused, 86 bus_size_t off) 87 { 88 struct sdhci_xenon_softc *sc = device_get_softc(dev); 89 90 return (bus_read_2(sc->mem_res, off)); 91 } 92 93 static void 94 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused, 95 bus_size_t off, uint16_t val) 96 { 97 struct sdhci_xenon_softc *sc = device_get_softc(dev); 98 99 bus_write_2(sc->mem_res, off, val); 100 } 101 102 static uint32_t 103 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused, 104 bus_size_t off) 105 { 106 struct sdhci_xenon_softc *sc = device_get_softc(dev); 107 108 return bus_read_4(sc->mem_res, off); 109 } 110 111 static void 112 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused, 113 bus_size_t off, uint32_t val) 114 { 115 struct sdhci_xenon_softc *sc = device_get_softc(dev); 116 117 bus_write_4(sc->mem_res, off, val); 118 } 119 120 static void 121 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 122 bus_size_t off, uint32_t *data, bus_size_t count) 123 { 124 struct sdhci_xenon_softc *sc = device_get_softc(dev); 125 126 bus_read_multi_4(sc->mem_res, off, data, count); 127 } 128 129 static void 130 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 131 bus_size_t off, uint32_t *data, bus_size_t count) 132 { 133 struct sdhci_xenon_softc *sc = device_get_softc(dev); 134 135 bus_write_multi_4(sc->mem_res, off, data, count); 136 } 137 138 static void 139 sdhci_xenon_intr(void *arg) 140 { 141 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg; 142 143 sdhci_generic_intr(sc->slot); 144 } 145 146 static int 147 sdhci_xenon_get_ro(device_t bus, device_t dev) 148 { 149 struct sdhci_xenon_softc *sc = device_get_softc(bus); 150 151 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 152 } 153 154 static void 155 sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot) 156 { 157 const struct mmc_ios *ios; 158 uint16_t hostctrl2; 159 160 if (slot->version < SDHCI_SPEC_300) 161 return; 162 163 mtx_assert(&slot->mtx, MA_OWNED); 164 ios = &slot->host.ios; 165 166 /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */ 167 hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2); 168 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 169 if (ios->clock > SD_SDR50_MAX) { 170 if (ios->timing == bus_timing_mmc_hs400 || 171 ios->timing == bus_timing_mmc_hs400es) 172 hostctrl2 |= XENON_CTRL2_MMC_HS400; 173 else if (ios->timing == bus_timing_mmc_hs200) 174 hostctrl2 |= XENON_CTRL2_MMC_HS200; 175 else 176 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 177 } 178 else if (ios->clock > SD_SDR25_MAX) 179 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 180 else if (ios->clock > SD_SDR12_MAX) { 181 if (ios->timing == bus_timing_uhs_ddr50 || 182 ios->timing == bus_timing_mmc_ddr52) 183 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 184 else 185 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 186 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 187 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 188 sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2); 189 } 190 191 static int 192 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios) 193 { 194 int i; 195 struct sdhci_xenon_softc *sc; 196 uint32_t reg; 197 198 sc = device_get_softc(brdev); 199 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 200 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT; 201 switch (ios->timing) { 202 case bus_timing_normal: 203 case bus_timing_hs: 204 case bus_timing_uhs_sdr12: 205 case bus_timing_uhs_sdr25: 206 case bus_timing_uhs_sdr50: 207 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 208 break; 209 default: 210 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 211 } 212 if (sc->slow_mode) 213 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 214 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 215 216 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 217 reg |= XENON_PHY_INITIALIZATION; 218 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 219 220 /* Wait for the eMMC PHY init. */ 221 for (i = 100; i > 0; i--) { 222 DELAY(100); 223 224 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 225 if ((reg & XENON_PHY_INITIALIZATION) == 0) 226 break; 227 } 228 229 if (i == 0) { 230 device_printf(brdev, "eMMC PHY failed to initialize\n"); 231 return (ETIMEDOUT); 232 } 233 234 return (0); 235 } 236 237 static int 238 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios) 239 { 240 struct sdhci_xenon_softc *sc; 241 uint32_t reg; 242 243 sc = device_get_softc(brdev); 244 /* Setup pad, set bit[28] and bits[26:24] */ 245 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL); 246 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 247 XENON_FC_QSP_RECEN | XENON_OEN_QSN); 248 /* All FC_XX_RECEIVCE should be set as CMOS Type */ 249 reg |= XENON_FC_ALL_CMOS_RECEIVER; 250 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg); 251 252 /* Set CMD and DQ Pull Up */ 253 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 254 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU); 255 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD); 256 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 257 258 if (ios->timing == bus_timing_normal) 259 return (sdhci_xenon_phy_init(brdev, ios)); 260 261 /* Clear SDIO mode, no SDIO support for now. */ 262 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 263 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 264 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 265 266 /* 267 * Set preferred ZNR and ZPR value. 268 * The ZNR and ZPR value vary between different boards. 269 * Define them both in the DTS for the board! 270 */ 271 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2); 272 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 273 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr); 274 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg); 275 276 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */ 277 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 278 reg &= ~SDHCI_CLOCK_CARD_EN; 279 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 280 281 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL); 282 switch (ios->timing) { 283 case bus_timing_mmc_hs400: 284 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 285 XENON_CMD_DDR_MODE; 286 reg &= ~XENON_DQ_ASYNC_MODE; 287 break; 288 case bus_timing_uhs_ddr50: 289 case bus_timing_mmc_ddr52: 290 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 291 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 292 break; 293 default: 294 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 295 XENON_CMD_DDR_MODE); 296 reg |= XENON_DQ_ASYNC_MODE; 297 } 298 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg); 299 300 /* Enable SD clock. */ 301 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 302 reg |= SDHCI_CLOCK_CARD_EN; 303 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 304 305 if (ios->timing == bus_timing_mmc_hs400) 306 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 307 XENON_LOGIC_TIMING_VALUE); 308 else { 309 /* Disable both SDHC Data Strobe and Enhanced Strobe. */ 310 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL); 311 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); 312 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg); 313 314 /* Clear Strobe line Pull down or Pull up. */ 315 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 316 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU); 317 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 318 } 319 320 return (sdhci_xenon_phy_init(brdev, ios)); 321 } 322 323 static int 324 sdhci_xenon_update_ios(device_t brdev, device_t reqdev) 325 { 326 int err; 327 struct sdhci_xenon_softc *sc; 328 struct mmc_ios *ios; 329 struct sdhci_slot *slot; 330 uint32_t reg; 331 332 err = sdhci_generic_update_ios(brdev, reqdev); 333 if (err != 0) 334 return (err); 335 336 sc = device_get_softc(brdev); 337 slot = device_get_ivars(reqdev); 338 ios = &slot->host.ios; 339 340 switch (ios->power_mode) { 341 case power_on: 342 break; 343 case power_off: 344 if (bootverbose) 345 device_printf(sc->dev, "Powering down sd/mmc\n"); 346 347 if (sc->vmmc_supply) 348 regulator_disable(sc->vmmc_supply); 349 if (sc->vqmmc_supply) 350 regulator_disable(sc->vqmmc_supply); 351 break; 352 case power_up: 353 if (bootverbose) 354 device_printf(sc->dev, "Powering up sd/mmc\n"); 355 356 if (sc->vmmc_supply) 357 regulator_enable(sc->vmmc_supply); 358 if (sc->vqmmc_supply) 359 regulator_enable(sc->vqmmc_supply); 360 break; 361 }; 362 363 /* Update the PHY settings. */ 364 if (ios->clock != 0) 365 sdhci_xenon_phy_set(brdev, ios); 366 367 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) { 368 /* Enable SDCLK_IDLEOFF. */ 369 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 370 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id); 371 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 372 } 373 374 return (0); 375 } 376 377 static int 378 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev) 379 { 380 struct sdhci_xenon_softc *sc; 381 struct sdhci_slot *slot; 382 uint16_t hostctrl2; 383 int uvolt, err; 384 385 slot = device_get_ivars(reqdev); 386 387 if (slot->version < SDHCI_SPEC_300) 388 return (0); 389 390 sc = device_get_softc(brdev); 391 392 if (sc->vqmmc_supply == NULL && !sc->skip_regulators) 393 return (EOPNOTSUPP); 394 395 err = 0; 396 397 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 398 switch (slot->host.ios.vccq) { 399 case vccq_330: 400 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 401 return (0); 402 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 403 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 404 405 if (!sc->skip_regulators) { 406 uvolt = 3300000; 407 err = regulator_set_voltage(sc->vqmmc_supply, 408 uvolt, uvolt); 409 if (err != 0) { 410 device_printf(sc->dev, 411 "Cannot set vqmmc to %d<->%d\n", 412 uvolt, 413 uvolt); 414 return (err); 415 } 416 } 417 418 /* 419 * According to the 'SD Host Controller Simplified 420 * Specification 4.20 the host driver should take more 421 * than 5ms for stable time of host voltage regulator 422 * from changing 1.8V Signaling Enable. 423 */ 424 DELAY(5000); 425 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 426 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 427 return (0); 428 return (EAGAIN); 429 case vccq_180: 430 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 431 return (EINVAL); 432 } 433 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 434 return (0); 435 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 436 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 437 438 if (!sc->skip_regulators) { 439 uvolt = 1800000; 440 err = regulator_set_voltage(sc->vqmmc_supply, 441 uvolt, uvolt); 442 if (err != 0) { 443 device_printf(sc->dev, 444 "Cannot set vqmmc to %d<->%d\n", 445 uvolt, 446 uvolt); 447 return (err); 448 } 449 } 450 451 /* 452 * According to the 'SD Host Controller Simplified 453 * Specification 4.20 the host driver should take more 454 * than 5ms for stable time of host voltage regulator 455 * from changing 1.8V Signaling Enable. 456 */ 457 DELAY(5000); 458 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 459 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 460 return (0); 461 return (EAGAIN); 462 default: 463 device_printf(brdev, 464 "Attempt to set unsupported signaling voltage\n"); 465 return (EINVAL); 466 } 467 } 468 469 static void 470 sdhci_xenon_parse_prop(device_t dev) 471 { 472 struct sdhci_xenon_softc *sc; 473 uint32_t val; 474 475 sc = device_get_softc(dev); 476 val = 0; 477 478 if (device_get_property(dev, "quirks", 479 &val, sizeof(val), DEVICE_PROP_UINT32) > 0) 480 sc->slot->quirks = val; 481 sc->znr = XENON_ZNR_DEF_VALUE; 482 if (device_get_property(dev, "marvell,xenon-phy-znr", 483 &val, sizeof(val), DEVICE_PROP_UINT32) > 0) 484 sc->znr = val & XENON_ZNR_MASK; 485 sc->zpr = XENON_ZPR_DEF_VALUE; 486 if (device_get_property(dev, "marvell,xenon-phy-zpr", 487 &val, sizeof(val), DEVICE_PROP_UINT32) > 0) 488 sc->zpr = val & XENON_ZPR_MASK; 489 if (device_has_property(dev, "marvell,xenon-phy-slow-mode")) 490 sc->slow_mode = true; 491 } 492 493 int 494 sdhci_xenon_attach(device_t dev) 495 { 496 struct sdhci_xenon_softc *sc = device_get_softc(dev); 497 int err, rid; 498 uint32_t reg; 499 500 sc->dev = dev; 501 sc->slot_id = 0; 502 503 /* Allocate IRQ. */ 504 rid = 0; 505 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 506 RF_ACTIVE); 507 if (sc->irq_res == NULL) { 508 device_printf(dev, "Can't allocate IRQ\n"); 509 return (ENOMEM); 510 } 511 512 /* Allocate memory. */ 513 rid = 0; 514 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 515 &rid, RF_ACTIVE); 516 if (sc->mem_res == NULL) { 517 bus_release_resource(dev, SYS_RES_IRQ, 518 rman_get_rid(sc->irq_res), sc->irq_res); 519 device_printf(dev, "Can't allocate memory for slot\n"); 520 return (ENOMEM); 521 } 522 523 sdhci_xenon_parse_prop(dev); 524 525 sc->slot->max_clk = XENON_MMC_MAX_CLK; 526 if (sc->slot->host.f_max > 0) 527 sc->slot->max_clk = sc->slot->host.f_max; 528 529 if (sdhci_init_slot(dev, sc->slot, 0)) 530 goto fail; 531 532 /* 1.2V signaling is not supported. */ 533 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_120; 534 535 /* Disable UHS in case of the PHY slow mode. */ 536 if (sc->slow_mode) 537 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_180; 538 539 /* Activate the interrupt */ 540 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 541 NULL, sdhci_xenon_intr, sc, &sc->intrhand); 542 if (err) { 543 device_printf(dev, "Cannot setup IRQ\n"); 544 goto fail; 545 } 546 547 /* Disable Auto Clock Gating. */ 548 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 549 reg |= XENON_AUTO_CLKGATE_DISABLE; 550 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 551 552 /* Enable this SD controller. */ 553 reg |= (1 << sc->slot_id); 554 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 555 556 /* Enable Parallel Transfer. */ 557 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 558 reg |= (1 << sc->slot_id); 559 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 560 561 /* Enable Auto Clock Gating. */ 562 reg &= ~XENON_AUTO_CLKGATE_DISABLE; 563 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 564 565 /* Disable SDCLK_IDLEOFF before the card initialization. */ 566 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 567 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id)); 568 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 569 570 /* Mask command conflict errors. */ 571 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 572 reg |= XENON_MASK_CMD_CONFLICT_ERR; 573 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 574 575 /* Process cards detection. */ 576 sdhci_start_slot(sc->slot); 577 578 return (0); 579 580 fail: 581 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 582 sc->irq_res); 583 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 584 sc->mem_res); 585 free(sc->slot, M_DEVBUF); 586 sc->slot = NULL; 587 588 return (ENXIO); 589 } 590 591 int 592 sdhci_xenon_detach(device_t dev) 593 { 594 struct sdhci_xenon_softc *sc = device_get_softc(dev); 595 596 bus_generic_detach(dev); 597 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 598 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 599 sc->irq_res); 600 sdhci_cleanup_slot(sc->slot); 601 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 602 sc->mem_res); 603 free(sc->slot, M_DEVBUF); 604 sc->slot = NULL; 605 606 return (0); 607 } 608 609 static device_method_t sdhci_xenon_methods[] = { 610 /* Bus interface */ 611 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 612 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 613 614 /* mmcbr_if */ 615 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios), 616 DEVMETHOD(mmcbr_request, sdhci_generic_request), 617 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro), 618 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 619 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 620 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq), 621 DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 622 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 623 624 /* SDHCI registers accessors */ 625 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1), 626 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2), 627 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4), 628 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4), 629 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1), 630 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2), 631 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4), 632 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4), 633 DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing), 634 635 DEVMETHOD_END 636 }; 637 638 DEFINE_CLASS_0(sdhci_xenon, sdhci_xenon_driver, sdhci_xenon_methods, 639 sizeof(struct sdhci_xenon_softc)); 640 641 SDHCI_DEPEND(sdhci_xenon); 642 #ifndef MMCCAM 643 MMC_DECLARE_BRIDGE(sdhci_xenon); 644 #endif 645