xref: /freebsd/sys/dev/sdhci/sdhci_pci.c (revision dc318a4ffabcbfa23bb56a33403aad36e6de30af)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include "opt_mmccam.h"
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/lock.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/resource.h>
41 #include <sys/rman.h>
42 #include <sys/sysctl.h>
43 #include <sys/taskqueue.h>
44 
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
47 
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 
51 #include <dev/mmc/bridge.h>
52 
53 #include <dev/sdhci/sdhci.h>
54 
55 #include "mmcbr_if.h"
56 #include "sdhci_if.h"
57 
58 /*
59  * PCI registers
60  */
61 #define	PCI_SDHCI_IFPIO			0x00
62 #define	PCI_SDHCI_IFDMA			0x01
63 #define	PCI_SDHCI_IFVENDOR		0x02
64 
65 #define	PCI_SLOT_INFO			0x40	/* 8 bits */
66 #define	PCI_SLOT_INFO_SLOTS(x)		(((x >> 4) & 7) + 1)
67 #define	PCI_SLOT_INFO_FIRST_BAR(x)	((x) & 7)
68 
69 /*
70  * RICOH specific PCI registers
71  */
72 #define	SDHC_PCI_MODE_KEY		0xf9
73 #define	SDHC_PCI_MODE			0x150
74 #define	SDHC_PCI_MODE_SD20		0x10
75 #define	SDHC_PCI_BASE_FREQ_KEY		0xfc
76 #define	SDHC_PCI_BASE_FREQ		0xe1
77 
78 static const struct sdhci_device {
79 	uint32_t	model;
80 	uint16_t	subvendor;
81 	const char	*desc;
82 	u_int		quirks;
83 } sdhci_devices[] = {
84 	{ 0x08221180,	0xffff,	"RICOH R5C822 SD",
85 	    SDHCI_QUIRK_FORCE_DMA },
86 	{ 0xe8221180,	0xffff,	"RICOH R5CE822 SD",
87 	    SDHCI_QUIRK_FORCE_DMA |
88 	    SDHCI_QUIRK_LOWER_FREQUENCY },
89 	{ 0xe8231180,	0xffff,	"RICOH R5CE823 SD",
90 	    SDHCI_QUIRK_LOWER_FREQUENCY },
91 	{ 0x8034104c,	0xffff, "TI XX21/XX11 SD",
92 	    SDHCI_QUIRK_FORCE_DMA },
93 	{ 0x803c104c,	0xffff, "TI XX12 SD",
94 	    SDHCI_QUIRK_FORCE_DMA |
95 	    SDHCI_QUIRK_WAITFOR_RESET_ASSERTED },
96 	{ 0x05501524,	0xffff, "ENE CB712 SD",
97 	    SDHCI_QUIRK_BROKEN_TIMINGS },
98 	{ 0x05511524,	0xffff, "ENE CB712 SD 2",
99 	    SDHCI_QUIRK_BROKEN_TIMINGS },
100 	{ 0x07501524,	0xffff, "ENE CB714 SD",
101 	    SDHCI_QUIRK_RESET_ON_IOS |
102 	    SDHCI_QUIRK_BROKEN_TIMINGS },
103 	{ 0x07511524,	0xffff, "ENE CB714 SD 2",
104 	    SDHCI_QUIRK_RESET_ON_IOS |
105 	    SDHCI_QUIRK_BROKEN_TIMINGS },
106 	{ 0x410111ab,	0xffff, "Marvell CaFe SD",
107 	    SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
108 	{ 0x2381197B,	0xffff,	"JMicron JMB38X SD",
109 	    SDHCI_QUIRK_32BIT_DMA_SIZE |
110 	    SDHCI_QUIRK_RESET_AFTER_REQUEST },
111 	{ 0x16bc14e4,	0xffff,	"Broadcom BCM577xx SDXC/MMC Card Reader",
112 	    SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
113 	{ 0x0f148086,	0xffff,	"Intel Bay Trail eMMC 4.5 Controller",
114 	    /* DDR52 is supported but affected by the VLI54 erratum */
115 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
116 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
117 	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
118 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN},
119 	{ 0x0f158086,	0xffff,	"Intel Bay Trail SDXC Controller",
120 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
121 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
122 	{ 0x0f508086,	0xffff,	"Intel Bay Trail eMMC 4.5 Controller",
123 	    /* DDR52 is supported but affected by the VLI54 erratum */
124 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
125 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
126 	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
127 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
128 	{ 0x19db8086,	0xffff,	"Intel Denverton eMMC 5.0 Controller",
129 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
130 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
131 	    SDHCI_QUIRK_MMC_DDR52 |
132 	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
133 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
134 	{ 0x22948086,	0xffff,	"Intel Braswell eMMC 4.5.1 Controller",
135 	    SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
136 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
137 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
138 	    SDHCI_QUIRK_MMC_DDR52 |
139 	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
140 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
141 	{ 0x22968086,	0xffff,	"Intel Braswell SDXC Controller",
142 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
143 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
144 	{ 0x5aca8086,	0xffff,	"Intel Apollo Lake SDXC Controller",
145 	    SDHCI_QUIRK_BROKEN_DMA |	/* APL18 erratum */
146 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
147 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
148 	{ 0x5acc8086,	0xffff,	"Intel Apollo Lake eMMC 5.0 Controller",
149 	    SDHCI_QUIRK_BROKEN_DMA |	/* APL18 erratum */
150 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET |
151 	    SDHCI_QUIRK_WAIT_WHILE_BUSY |
152 	    SDHCI_QUIRK_MMC_DDR52 |
153 	    SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
154 	    SDHCI_QUIRK_PRESET_VALUE_BROKEN },
155 	{ 0,		0xffff,	NULL,
156 	    0 }
157 };
158 
159 struct sdhci_pci_softc {
160 	u_int		quirks;		/* Chip specific quirks */
161 	struct resource *irq_res;	/* IRQ resource */
162 	void		*intrhand;	/* Interrupt handle */
163 
164 	int		num_slots;	/* Number of slots on this controller */
165 	struct sdhci_slot slots[6];
166 	struct resource	*mem_res[6];	/* Memory resource */
167 	uint8_t		cfg_freq;	/* Saved frequency */
168 	uint8_t		cfg_mode;	/* Saved mode */
169 };
170 
171 static int sdhci_enable_msi = 1;
172 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
173     0, "Enable MSI interrupts");
174 
175 static uint8_t
176 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
177 {
178 	struct sdhci_pci_softc *sc = device_get_softc(dev);
179 
180 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
181 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
182 	return bus_read_1(sc->mem_res[slot->num], off);
183 }
184 
185 static void
186 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
187     bus_size_t off, uint8_t val)
188 {
189 	struct sdhci_pci_softc *sc = device_get_softc(dev);
190 
191 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
192 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
193 	bus_write_1(sc->mem_res[slot->num], off, val);
194 }
195 
196 static uint16_t
197 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
198 {
199 	struct sdhci_pci_softc *sc = device_get_softc(dev);
200 
201 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
202 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
203 	return bus_read_2(sc->mem_res[slot->num], off);
204 }
205 
206 static void
207 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
208     bus_size_t off, uint16_t val)
209 {
210 	struct sdhci_pci_softc *sc = device_get_softc(dev);
211 
212 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
213 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
214 	bus_write_2(sc->mem_res[slot->num], off, val);
215 }
216 
217 static uint32_t
218 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
219 {
220 	struct sdhci_pci_softc *sc = device_get_softc(dev);
221 
222 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
223 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
224 	return bus_read_4(sc->mem_res[slot->num], off);
225 }
226 
227 static void
228 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
229     bus_size_t off, uint32_t val)
230 {
231 	struct sdhci_pci_softc *sc = device_get_softc(dev);
232 
233 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
234 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
235 	bus_write_4(sc->mem_res[slot->num], off, val);
236 }
237 
238 static void
239 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
240     bus_size_t off, uint32_t *data, bus_size_t count)
241 {
242 	struct sdhci_pci_softc *sc = device_get_softc(dev);
243 
244 	bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
245 }
246 
247 static void
248 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
249     bus_size_t off, uint32_t *data, bus_size_t count)
250 {
251 	struct sdhci_pci_softc *sc = device_get_softc(dev);
252 
253 	bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
254 }
255 
256 static void sdhci_pci_intr(void *arg);
257 
258 static void
259 sdhci_lower_frequency(device_t dev)
260 {
261 	struct sdhci_pci_softc *sc = device_get_softc(dev);
262 
263 	/*
264 	 * Enable SD2.0 mode.
265 	 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
266 	 */
267 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
268 	sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
269 	pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
270 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
271 
272 	/*
273 	 * Some SD/MMC cards don't work with the default base
274 	 * clock frequency of 200 MHz.  Lower it to 50 MHz.
275 	 */
276 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
277 	sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
278 	pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
279 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
280 }
281 
282 static void
283 sdhci_restore_frequency(device_t dev)
284 {
285 	struct sdhci_pci_softc *sc = device_get_softc(dev);
286 
287 	/* Restore mode. */
288 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
289 	pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
290 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
291 
292 	/* Restore frequency. */
293 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
294 	pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
295 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
296 }
297 
298 static int
299 sdhci_pci_probe(device_t dev)
300 {
301 	uint32_t model;
302 	uint16_t subvendor;
303 	uint8_t class, subclass;
304 	int i, result;
305 
306 	model = (uint32_t)pci_get_device(dev) << 16;
307 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
308 	subvendor = pci_get_subvendor(dev);
309 	class = pci_get_class(dev);
310 	subclass = pci_get_subclass(dev);
311 
312 	result = ENXIO;
313 	for (i = 0; sdhci_devices[i].model != 0; i++) {
314 		if (sdhci_devices[i].model == model &&
315 		    (sdhci_devices[i].subvendor == 0xffff ||
316 		    sdhci_devices[i].subvendor == subvendor)) {
317 			device_set_desc(dev, sdhci_devices[i].desc);
318 			result = BUS_PROBE_DEFAULT;
319 			break;
320 		}
321 	}
322 	if (result == ENXIO && class == PCIC_BASEPERIPH &&
323 	    subclass == PCIS_BASEPERIPH_SDHC) {
324 		device_set_desc(dev, "Generic SD HCI");
325 		result = BUS_PROBE_GENERIC;
326 	}
327 
328 	return (result);
329 }
330 
331 static int
332 sdhci_pci_attach(device_t dev)
333 {
334 	struct sdhci_pci_softc *sc = device_get_softc(dev);
335 	struct sdhci_slot *slot;
336 	uint32_t model;
337 	uint16_t subvendor;
338 	int bar, err, rid, slots, i;
339 
340 	model = (uint32_t)pci_get_device(dev) << 16;
341 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
342 	subvendor = pci_get_subvendor(dev);
343 	/* Apply chip specific quirks. */
344 	for (i = 0; sdhci_devices[i].model != 0; i++) {
345 		if (sdhci_devices[i].model == model &&
346 		    (sdhci_devices[i].subvendor == 0xffff ||
347 		    sdhci_devices[i].subvendor == subvendor)) {
348 			sc->quirks = sdhci_devices[i].quirks;
349 			break;
350 		}
351 	}
352 	sc->quirks &= ~sdhci_quirk_clear;
353 	sc->quirks |= sdhci_quirk_set;
354 
355 	/* Some controllers need to be bumped into the right mode. */
356 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
357 		sdhci_lower_frequency(dev);
358 	/* Read slots info from PCI registers. */
359 	slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
360 	bar = PCI_SLOT_INFO_FIRST_BAR(slots);
361 	slots = PCI_SLOT_INFO_SLOTS(slots);
362 	if (slots > 6 || bar > 5) {
363 		device_printf(dev, "Incorrect slots information (%d, %d).\n",
364 		    slots, bar);
365 		return (EINVAL);
366 	}
367 	/* Allocate IRQ. */
368 	i = 1;
369 	rid = 0;
370 	if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
371 		rid = 1;
372 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
373 		RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
374 	if (sc->irq_res == NULL) {
375 		device_printf(dev, "Can't allocate IRQ\n");
376 		pci_release_msi(dev);
377 		return (ENOMEM);
378 	}
379 	/* Scan all slots. */
380 	for (i = 0; i < slots; i++) {
381 		slot = &sc->slots[sc->num_slots];
382 
383 		/* Allocate memory. */
384 		rid = PCIR_BAR(bar + i);
385 		sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
386 		    &rid, RF_ACTIVE);
387 		if (sc->mem_res[i] == NULL) {
388 			device_printf(dev,
389 			    "Can't allocate memory for slot %d\n", i);
390 			continue;
391 		}
392 
393 		slot->quirks = sc->quirks;
394 
395 		if (sdhci_init_slot(dev, slot, i) != 0)
396 			continue;
397 
398 		sc->num_slots++;
399 	}
400 	device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
401 	/* Activate the interrupt */
402 	err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
403 	    NULL, sdhci_pci_intr, sc, &sc->intrhand);
404 	if (err)
405 		device_printf(dev, "Can't setup IRQ\n");
406 	pci_enable_busmaster(dev);
407 	/* Process cards detection. */
408 	for (i = 0; i < sc->num_slots; i++) {
409 		sdhci_start_slot(&sc->slots[i]);
410 	}
411 
412 	return (0);
413 }
414 
415 static int
416 sdhci_pci_detach(device_t dev)
417 {
418 	struct sdhci_pci_softc *sc = device_get_softc(dev);
419 	int i;
420 
421 	bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
422 	bus_release_resource(dev, SYS_RES_IRQ,
423 	    rman_get_rid(sc->irq_res), sc->irq_res);
424 	pci_release_msi(dev);
425 
426 	for (i = 0; i < sc->num_slots; i++) {
427 		sdhci_cleanup_slot(&sc->slots[i]);
428 		bus_release_resource(dev, SYS_RES_MEMORY,
429 		    rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
430 	}
431 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
432 		sdhci_restore_frequency(dev);
433 	return (0);
434 }
435 
436 static int
437 sdhci_pci_shutdown(device_t dev)
438 {
439 	struct sdhci_pci_softc *sc = device_get_softc(dev);
440 
441 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
442 		sdhci_restore_frequency(dev);
443 	return (0);
444 }
445 
446 static int
447 sdhci_pci_suspend(device_t dev)
448 {
449 	struct sdhci_pci_softc *sc = device_get_softc(dev);
450 	int i, err;
451 
452 	err = bus_generic_suspend(dev);
453 	if (err)
454 		return (err);
455 	for (i = 0; i < sc->num_slots; i++)
456 		sdhci_generic_suspend(&sc->slots[i]);
457 	return (0);
458 }
459 
460 static int
461 sdhci_pci_resume(device_t dev)
462 {
463 	struct sdhci_pci_softc *sc = device_get_softc(dev);
464 	int i, err;
465 
466 	for (i = 0; i < sc->num_slots; i++)
467 		sdhci_generic_resume(&sc->slots[i]);
468 	err = bus_generic_resume(dev);
469 	if (err)
470 		return (err);
471 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
472 		sdhci_lower_frequency(dev);
473 	return (0);
474 }
475 
476 static void
477 sdhci_pci_intr(void *arg)
478 {
479 	struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
480 	int i;
481 
482 	for (i = 0; i < sc->num_slots; i++)
483 		sdhci_generic_intr(&sc->slots[i]);
484 }
485 
486 static device_method_t sdhci_methods[] = {
487 	/* device_if */
488 	DEVMETHOD(device_probe,		sdhci_pci_probe),
489 	DEVMETHOD(device_attach,	sdhci_pci_attach),
490 	DEVMETHOD(device_detach,	sdhci_pci_detach),
491 	DEVMETHOD(device_shutdown,	sdhci_pci_shutdown),
492 	DEVMETHOD(device_suspend,	sdhci_pci_suspend),
493 	DEVMETHOD(device_resume,	sdhci_pci_resume),
494 
495 	/* Bus interface */
496 	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
497 	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
498 
499 	/* mmcbr_if */
500 	DEVMETHOD(mmcbr_update_ios,	sdhci_generic_update_ios),
501 	DEVMETHOD(mmcbr_switch_vccq,	sdhci_generic_switch_vccq),
502 	DEVMETHOD(mmcbr_tune,		sdhci_generic_tune),
503 	DEVMETHOD(mmcbr_retune,		sdhci_generic_retune),
504 	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
505 	DEVMETHOD(mmcbr_get_ro,		sdhci_generic_get_ro),
506 	DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
507 	DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
508 
509 	/* SDHCI accessors */
510 	DEVMETHOD(sdhci_read_1,		sdhci_pci_read_1),
511 	DEVMETHOD(sdhci_read_2,		sdhci_pci_read_2),
512 	DEVMETHOD(sdhci_read_4,		sdhci_pci_read_4),
513 	DEVMETHOD(sdhci_read_multi_4,	sdhci_pci_read_multi_4),
514 	DEVMETHOD(sdhci_write_1,	sdhci_pci_write_1),
515 	DEVMETHOD(sdhci_write_2,	sdhci_pci_write_2),
516 	DEVMETHOD(sdhci_write_4,	sdhci_pci_write_4),
517 	DEVMETHOD(sdhci_write_multi_4,	sdhci_pci_write_multi_4),
518 	DEVMETHOD(sdhci_set_uhs_timing,	sdhci_generic_set_uhs_timing),
519 
520 	DEVMETHOD_END
521 };
522 
523 static driver_t sdhci_pci_driver = {
524 	"sdhci_pci",
525 	sdhci_methods,
526 	sizeof(struct sdhci_pci_softc),
527 };
528 static devclass_t sdhci_pci_devclass;
529 
530 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
531     NULL);
532 SDHCI_DEPEND(sdhci_pci);
533 
534 #ifndef MMCCAM
535 MMC_DECLARE_BRIDGE(sdhci_pci);
536 #endif
537