1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/module.h> 35 #include <sys/mutex.h> 36 #include <sys/resource.h> 37 #include <sys/rman.h> 38 #include <sys/sysctl.h> 39 #include <sys/taskqueue.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 47 #include <dev/mmc/bridge.h> 48 49 #include <dev/sdhci/sdhci.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci_if.h" 53 54 /* 55 * PCI registers 56 */ 57 #define PCI_SDHCI_IFPIO 0x00 58 #define PCI_SDHCI_IFDMA 0x01 59 #define PCI_SDHCI_IFVENDOR 0x02 60 61 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 62 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 63 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 64 65 /* 66 * RICOH specific PCI registers 67 */ 68 #define SDHC_PCI_MODE_KEY 0xf9 69 #define SDHC_PCI_MODE 0x150 70 #define SDHC_PCI_MODE_SD20 0x10 71 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 72 #define SDHC_PCI_BASE_FREQ 0xe1 73 74 static const struct sdhci_device { 75 uint32_t model; 76 uint16_t subvendor; 77 const char *desc; 78 u_int quirks; 79 } sdhci_devices[] = { 80 { 0x08221180, 0xffff, "RICOH R5C822 SD", 81 SDHCI_QUIRK_FORCE_DMA }, 82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 83 SDHCI_QUIRK_FORCE_DMA | 84 SDHCI_QUIRK_LOWER_FREQUENCY }, 85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 86 SDHCI_QUIRK_LOWER_FREQUENCY }, 87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 88 SDHCI_QUIRK_FORCE_DMA }, 89 { 0x05501524, 0xffff, "ENE CB712 SD", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x05511524, 0xffff, "ENE CB712 SD 2", 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07501524, 0xffff, "ENE CB714 SD", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x07511524, 0xffff, "ENE CB714 SD 2", 97 SDHCI_QUIRK_RESET_ON_IOS | 98 SDHCI_QUIRK_BROKEN_TIMINGS }, 99 { 0x410111ab, 0xffff, "Marvell CaFe SD", 100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 101 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 102 SDHCI_QUIRK_32BIT_DMA_SIZE | 103 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 107 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 108 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 109 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 110 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 111 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 112 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 113 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 114 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 115 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 116 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 117 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 118 SDHCI_QUIRK_INTEL_POWER_UP_RESET }, 119 { 0, 0xffff, NULL, 120 0 } 121 }; 122 123 struct sdhci_pci_softc { 124 u_int quirks; /* Chip specific quirks */ 125 struct resource *irq_res; /* IRQ resource */ 126 void *intrhand; /* Interrupt handle */ 127 128 int num_slots; /* Number of slots on this controller */ 129 struct sdhci_slot slots[6]; 130 struct resource *mem_res[6]; /* Memory resource */ 131 uint8_t cfg_freq; /* Saved frequency */ 132 uint8_t cfg_mode; /* Saved mode */ 133 }; 134 135 static int sdhci_enable_msi = 1; 136 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 137 0, "Enable MSI interrupts"); 138 139 static uint8_t 140 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 141 { 142 struct sdhci_pci_softc *sc = device_get_softc(dev); 143 144 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 145 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 146 return bus_read_1(sc->mem_res[slot->num], off); 147 } 148 149 static void 150 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 151 uint8_t val) 152 { 153 struct sdhci_pci_softc *sc = device_get_softc(dev); 154 155 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 157 bus_write_1(sc->mem_res[slot->num], off, val); 158 } 159 160 static uint16_t 161 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 162 { 163 struct sdhci_pci_softc *sc = device_get_softc(dev); 164 165 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167 return bus_read_2(sc->mem_res[slot->num], off); 168 } 169 170 static void 171 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 172 uint16_t val) 173 { 174 struct sdhci_pci_softc *sc = device_get_softc(dev); 175 176 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 177 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 178 bus_write_2(sc->mem_res[slot->num], off, val); 179 } 180 181 static uint32_t 182 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 183 { 184 struct sdhci_pci_softc *sc = device_get_softc(dev); 185 186 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 187 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 188 return bus_read_4(sc->mem_res[slot->num], off); 189 } 190 191 static void 192 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 193 uint32_t val) 194 { 195 struct sdhci_pci_softc *sc = device_get_softc(dev); 196 197 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 198 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 199 bus_write_4(sc->mem_res[slot->num], off, val); 200 } 201 202 static void 203 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 204 bus_size_t off, uint32_t *data, bus_size_t count) 205 { 206 struct sdhci_pci_softc *sc = device_get_softc(dev); 207 208 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 209 } 210 211 static void 212 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 213 bus_size_t off, uint32_t *data, bus_size_t count) 214 { 215 struct sdhci_pci_softc *sc = device_get_softc(dev); 216 217 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 218 } 219 220 static void sdhci_pci_intr(void *arg); 221 222 static void 223 sdhci_lower_frequency(device_t dev) 224 { 225 struct sdhci_pci_softc *sc = device_get_softc(dev); 226 227 /* 228 * Enable SD2.0 mode. 229 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 230 */ 231 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 232 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 233 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 234 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 235 236 /* 237 * Some SD/MMC cards don't work with the default base 238 * clock frequency of 200 MHz. Lower it to 50 MHz. 239 */ 240 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 241 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 242 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 243 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 244 } 245 246 static void 247 sdhci_restore_frequency(device_t dev) 248 { 249 struct sdhci_pci_softc *sc = device_get_softc(dev); 250 251 /* Restore mode. */ 252 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 253 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 254 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 255 256 /* Restore frequency. */ 257 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 258 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 259 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 260 } 261 262 static int 263 sdhci_pci_probe(device_t dev) 264 { 265 uint32_t model; 266 uint16_t subvendor; 267 uint8_t class, subclass; 268 int i, result; 269 270 model = (uint32_t)pci_get_device(dev) << 16; 271 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 272 subvendor = pci_get_subvendor(dev); 273 class = pci_get_class(dev); 274 subclass = pci_get_subclass(dev); 275 276 result = ENXIO; 277 for (i = 0; sdhci_devices[i].model != 0; i++) { 278 if (sdhci_devices[i].model == model && 279 (sdhci_devices[i].subvendor == 0xffff || 280 sdhci_devices[i].subvendor == subvendor)) { 281 device_set_desc(dev, sdhci_devices[i].desc); 282 result = BUS_PROBE_DEFAULT; 283 break; 284 } 285 } 286 if (result == ENXIO && class == PCIC_BASEPERIPH && 287 subclass == PCIS_BASEPERIPH_SDHC) { 288 device_set_desc(dev, "Generic SD HCI"); 289 result = BUS_PROBE_GENERIC; 290 } 291 292 return (result); 293 } 294 295 static int 296 sdhci_pci_attach(device_t dev) 297 { 298 struct sdhci_pci_softc *sc = device_get_softc(dev); 299 struct sdhci_slot *slot; 300 uint32_t model; 301 uint16_t subvendor; 302 int bar, err, rid, slots, i; 303 304 model = (uint32_t)pci_get_device(dev) << 16; 305 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 306 subvendor = pci_get_subvendor(dev); 307 /* Apply chip specific quirks. */ 308 for (i = 0; sdhci_devices[i].model != 0; i++) { 309 if (sdhci_devices[i].model == model && 310 (sdhci_devices[i].subvendor == 0xffff || 311 sdhci_devices[i].subvendor == subvendor)) { 312 sc->quirks = sdhci_devices[i].quirks; 313 break; 314 } 315 } 316 /* Some controllers need to be bumped into the right mode. */ 317 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 318 sdhci_lower_frequency(dev); 319 /* Read slots info from PCI registers. */ 320 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 321 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 322 slots = PCI_SLOT_INFO_SLOTS(slots); 323 if (slots > 6 || bar > 5) { 324 device_printf(dev, "Incorrect slots information (%d, %d).\n", 325 slots, bar); 326 return (EINVAL); 327 } 328 /* Allocate IRQ. */ 329 i = 1; 330 rid = 0; 331 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 332 rid = 1; 333 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 334 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 335 if (sc->irq_res == NULL) { 336 device_printf(dev, "Can't allocate IRQ\n"); 337 pci_release_msi(dev); 338 return (ENOMEM); 339 } 340 /* Scan all slots. */ 341 for (i = 0; i < slots; i++) { 342 slot = &sc->slots[sc->num_slots]; 343 344 /* Allocate memory. */ 345 rid = PCIR_BAR(bar + i); 346 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 347 &rid, RF_ACTIVE); 348 if (sc->mem_res[i] == NULL) { 349 device_printf(dev, 350 "Can't allocate memory for slot %d\n", i); 351 continue; 352 } 353 354 slot->quirks = sc->quirks; 355 356 if (sdhci_init_slot(dev, slot, i) != 0) 357 continue; 358 359 sc->num_slots++; 360 } 361 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 362 /* Activate the interrupt */ 363 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 364 NULL, sdhci_pci_intr, sc, &sc->intrhand); 365 if (err) 366 device_printf(dev, "Can't setup IRQ\n"); 367 pci_enable_busmaster(dev); 368 /* Process cards detection. */ 369 for (i = 0; i < sc->num_slots; i++) 370 sdhci_start_slot(&sc->slots[i]); 371 372 return (0); 373 } 374 375 static int 376 sdhci_pci_detach(device_t dev) 377 { 378 struct sdhci_pci_softc *sc = device_get_softc(dev); 379 int i; 380 381 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 382 bus_release_resource(dev, SYS_RES_IRQ, 383 rman_get_rid(sc->irq_res), sc->irq_res); 384 pci_release_msi(dev); 385 386 for (i = 0; i < sc->num_slots; i++) { 387 sdhci_cleanup_slot(&sc->slots[i]); 388 bus_release_resource(dev, SYS_RES_MEMORY, 389 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 390 } 391 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 392 sdhci_restore_frequency(dev); 393 return (0); 394 } 395 396 static int 397 sdhci_pci_shutdown(device_t dev) 398 { 399 struct sdhci_pci_softc *sc = device_get_softc(dev); 400 401 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 402 sdhci_restore_frequency(dev); 403 return (0); 404 } 405 406 static int 407 sdhci_pci_suspend(device_t dev) 408 { 409 struct sdhci_pci_softc *sc = device_get_softc(dev); 410 int i, err; 411 412 err = bus_generic_suspend(dev); 413 if (err) 414 return (err); 415 for (i = 0; i < sc->num_slots; i++) 416 sdhci_generic_suspend(&sc->slots[i]); 417 return (0); 418 } 419 420 static int 421 sdhci_pci_resume(device_t dev) 422 { 423 struct sdhci_pci_softc *sc = device_get_softc(dev); 424 int i, err; 425 426 for (i = 0; i < sc->num_slots; i++) 427 sdhci_generic_resume(&sc->slots[i]); 428 err = bus_generic_resume(dev); 429 if (err) 430 return (err); 431 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 432 sdhci_lower_frequency(dev); 433 return (0); 434 } 435 436 static void 437 sdhci_pci_intr(void *arg) 438 { 439 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 440 int i; 441 442 for (i = 0; i < sc->num_slots; i++) 443 sdhci_generic_intr(&sc->slots[i]); 444 } 445 446 static device_method_t sdhci_methods[] = { 447 /* device_if */ 448 DEVMETHOD(device_probe, sdhci_pci_probe), 449 DEVMETHOD(device_attach, sdhci_pci_attach), 450 DEVMETHOD(device_detach, sdhci_pci_detach), 451 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 452 DEVMETHOD(device_suspend, sdhci_pci_suspend), 453 DEVMETHOD(device_resume, sdhci_pci_resume), 454 455 /* Bus interface */ 456 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 457 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 458 459 /* mmcbr_if */ 460 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 461 DEVMETHOD(mmcbr_request, sdhci_generic_request), 462 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 463 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 464 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 465 466 /* SDHCI registers accessors */ 467 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 468 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 469 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 470 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 471 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 472 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 473 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 474 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 475 476 DEVMETHOD_END 477 }; 478 479 static driver_t sdhci_pci_driver = { 480 "sdhci_pci", 481 sdhci_methods, 482 sizeof(struct sdhci_pci_softc), 483 }; 484 static devclass_t sdhci_pci_devclass; 485 486 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 487 NULL); 488 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 489 MMC_DECLARE_BRIDGE(sdhci_pci); 490