1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/stdarg.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include "sdhci.h" 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 /* 58 * PCI registers 59 */ 60 61 #define PCI_SDHCI_IFPIO 0x00 62 #define PCI_SDHCI_IFDMA 0x01 63 #define PCI_SDHCI_IFVENDOR 0x02 64 65 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 66 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69 /* 70 * RICOH specific PCI registers 71 */ 72 #define SDHC_PCI_MODE_KEY 0xf9 73 #define SDHC_PCI_MODE 0x150 74 #define SDHC_PCI_MODE_SD20 0x10 75 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 76 #define SDHC_PCI_BASE_FREQ 0xe1 77 78 static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 const char *desc; 82 u_int quirks; 83 } sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87 SDHCI_QUIRK_FORCE_DMA | 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90 SDHCI_QUIRK_LOWER_FREQUENCY }, 91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92 SDHCI_QUIRK_FORCE_DMA }, 93 { 0x05501524, 0xffff, "ENE CB712 SD", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x05511524, 0xffff, "ENE CB712 SD 2", 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07501524, 0xffff, "ENE CB714 SD", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x07511524, 0xffff, "ENE CB714 SD 2", 101 SDHCI_QUIRK_RESET_ON_IOS | 102 SDHCI_QUIRK_BROKEN_TIMINGS }, 103 { 0x410111ab, 0xffff, "Marvell CaFe SD", 104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106 SDHCI_QUIRK_32BIT_DMA_SIZE | 107 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 109 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 110 { 0x22948086, 0xffff, "Intel Braswell Storage Cluster Control MMC Port", 111 0 }, 112 { 0, 0xffff, NULL, 113 0 } 114 }; 115 116 struct sdhci_pci_softc { 117 u_int quirks; /* Chip specific quirks */ 118 struct resource *irq_res; /* IRQ resource */ 119 void *intrhand; /* Interrupt handle */ 120 121 int num_slots; /* Number of slots on this controller */ 122 struct sdhci_slot slots[6]; 123 struct resource *mem_res[6]; /* Memory resource */ 124 uint8_t cfg_freq; /* Saved mode */ 125 uint8_t cfg_mode; /* Saved frequency */ 126 }; 127 128 static int sdhci_enable_msi = 1; 129 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 130 0, "Enable MSI interrupts"); 131 132 static uint8_t 133 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 134 { 135 struct sdhci_pci_softc *sc = device_get_softc(dev); 136 137 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 138 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 139 return bus_read_1(sc->mem_res[slot->num], off); 140 } 141 142 static void 143 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 144 { 145 struct sdhci_pci_softc *sc = device_get_softc(dev); 146 147 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 148 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 149 bus_write_1(sc->mem_res[slot->num], off, val); 150 } 151 152 static uint16_t 153 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 154 { 155 struct sdhci_pci_softc *sc = device_get_softc(dev); 156 157 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 158 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 159 return bus_read_2(sc->mem_res[slot->num], off); 160 } 161 162 static void 163 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 164 { 165 struct sdhci_pci_softc *sc = device_get_softc(dev); 166 167 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 168 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 169 bus_write_2(sc->mem_res[slot->num], off, val); 170 } 171 172 static uint32_t 173 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 174 { 175 struct sdhci_pci_softc *sc = device_get_softc(dev); 176 177 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 178 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 179 return bus_read_4(sc->mem_res[slot->num], off); 180 } 181 182 static void 183 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 184 { 185 struct sdhci_pci_softc *sc = device_get_softc(dev); 186 187 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 188 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 189 bus_write_4(sc->mem_res[slot->num], off, val); 190 } 191 192 static void 193 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 194 bus_size_t off, uint32_t *data, bus_size_t count) 195 { 196 struct sdhci_pci_softc *sc = device_get_softc(dev); 197 198 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 199 } 200 201 static void 202 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 203 bus_size_t off, uint32_t *data, bus_size_t count) 204 { 205 struct sdhci_pci_softc *sc = device_get_softc(dev); 206 207 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 208 } 209 210 static void sdhci_pci_intr(void *arg); 211 212 static void 213 sdhci_lower_frequency(device_t dev) 214 { 215 struct sdhci_pci_softc *sc = device_get_softc(dev); 216 217 /* 218 * Enable SD2.0 mode. 219 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 220 */ 221 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 222 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 223 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 224 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 225 226 /* 227 * Some SD/MMC cards don't work with the default base 228 * clock frequency of 200 MHz. Lower it to 50 MHz. 229 */ 230 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 231 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 232 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 233 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 234 } 235 236 static void 237 sdhci_restore_frequency(device_t dev) 238 { 239 struct sdhci_pci_softc *sc = device_get_softc(dev); 240 241 /* Restore mode. */ 242 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 243 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 244 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 245 246 /* Restore frequency. */ 247 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 248 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 249 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 250 } 251 252 static int 253 sdhci_pci_probe(device_t dev) 254 { 255 uint32_t model; 256 uint16_t subvendor; 257 uint8_t class, subclass; 258 int i, result; 259 260 model = (uint32_t)pci_get_device(dev) << 16; 261 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 262 subvendor = pci_get_subvendor(dev); 263 class = pci_get_class(dev); 264 subclass = pci_get_subclass(dev); 265 266 result = ENXIO; 267 for (i = 0; sdhci_devices[i].model != 0; i++) { 268 if (sdhci_devices[i].model == model && 269 (sdhci_devices[i].subvendor == 0xffff || 270 sdhci_devices[i].subvendor == subvendor)) { 271 device_set_desc(dev, sdhci_devices[i].desc); 272 result = BUS_PROBE_DEFAULT; 273 break; 274 } 275 } 276 if (result == ENXIO && class == PCIC_BASEPERIPH && 277 subclass == PCIS_BASEPERIPH_SDHC) { 278 device_set_desc(dev, "Generic SD HCI"); 279 result = BUS_PROBE_GENERIC; 280 } 281 282 return (result); 283 } 284 285 static int 286 sdhci_pci_attach(device_t dev) 287 { 288 struct sdhci_pci_softc *sc = device_get_softc(dev); 289 uint32_t model; 290 uint16_t subvendor; 291 int bar, err, rid, slots, i; 292 293 model = (uint32_t)pci_get_device(dev) << 16; 294 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 295 subvendor = pci_get_subvendor(dev); 296 /* Apply chip specific quirks. */ 297 for (i = 0; sdhci_devices[i].model != 0; i++) { 298 if (sdhci_devices[i].model == model && 299 (sdhci_devices[i].subvendor == 0xffff || 300 sdhci_devices[i].subvendor == subvendor)) { 301 sc->quirks = sdhci_devices[i].quirks; 302 break; 303 } 304 } 305 /* Some controllers need to be bumped into the right mode. */ 306 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 307 sdhci_lower_frequency(dev); 308 /* Read slots info from PCI registers. */ 309 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 310 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 311 slots = PCI_SLOT_INFO_SLOTS(slots); 312 if (slots > 6 || bar > 5) { 313 device_printf(dev, "Incorrect slots information (%d, %d).\n", 314 slots, bar); 315 return (EINVAL); 316 } 317 /* Allocate IRQ. */ 318 i = 1; 319 rid = 0; 320 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 321 rid = 1; 322 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 323 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 324 if (sc->irq_res == NULL) { 325 device_printf(dev, "Can't allocate IRQ\n"); 326 pci_release_msi(dev); 327 return (ENOMEM); 328 } 329 /* Scan all slots. */ 330 for (i = 0; i < slots; i++) { 331 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 332 333 /* Allocate memory. */ 334 rid = PCIR_BAR(bar + i); 335 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 336 &rid, RF_ACTIVE); 337 if (sc->mem_res[i] == NULL) { 338 device_printf(dev, "Can't allocate memory for slot %d\n", i); 339 continue; 340 } 341 342 slot->quirks = sc->quirks; 343 344 if (sdhci_init_slot(dev, slot, i) != 0) 345 continue; 346 347 sc->num_slots++; 348 } 349 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 350 /* Activate the interrupt */ 351 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 352 NULL, sdhci_pci_intr, sc, &sc->intrhand); 353 if (err) 354 device_printf(dev, "Can't setup IRQ\n"); 355 pci_enable_busmaster(dev); 356 /* Process cards detection. */ 357 for (i = 0; i < sc->num_slots; i++) { 358 struct sdhci_slot *slot = &sc->slots[i]; 359 360 sdhci_start_slot(slot); 361 } 362 363 return (0); 364 } 365 366 static int 367 sdhci_pci_detach(device_t dev) 368 { 369 struct sdhci_pci_softc *sc = device_get_softc(dev); 370 int i; 371 372 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 373 bus_release_resource(dev, SYS_RES_IRQ, 374 rman_get_rid(sc->irq_res), sc->irq_res); 375 pci_release_msi(dev); 376 377 for (i = 0; i < sc->num_slots; i++) { 378 struct sdhci_slot *slot = &sc->slots[i]; 379 380 sdhci_cleanup_slot(slot); 381 bus_release_resource(dev, SYS_RES_MEMORY, 382 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 383 } 384 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 385 sdhci_restore_frequency(dev); 386 return (0); 387 } 388 389 static int 390 sdhci_pci_shutdown(device_t dev) 391 { 392 struct sdhci_pci_softc *sc = device_get_softc(dev); 393 394 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 395 sdhci_restore_frequency(dev); 396 return (0); 397 } 398 399 static int 400 sdhci_pci_suspend(device_t dev) 401 { 402 struct sdhci_pci_softc *sc = device_get_softc(dev); 403 int i, err; 404 405 err = bus_generic_suspend(dev); 406 if (err) 407 return (err); 408 for (i = 0; i < sc->num_slots; i++) 409 sdhci_generic_suspend(&sc->slots[i]); 410 return (0); 411 } 412 413 static int 414 sdhci_pci_resume(device_t dev) 415 { 416 struct sdhci_pci_softc *sc = device_get_softc(dev); 417 int i, err; 418 419 for (i = 0; i < sc->num_slots; i++) 420 sdhci_generic_resume(&sc->slots[i]); 421 err = bus_generic_resume(dev); 422 if (err) 423 return (err); 424 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 425 sdhci_lower_frequency(dev); 426 return (0); 427 } 428 429 static void 430 sdhci_pci_intr(void *arg) 431 { 432 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 433 int i; 434 435 for (i = 0; i < sc->num_slots; i++) { 436 struct sdhci_slot *slot = &sc->slots[i]; 437 sdhci_generic_intr(slot); 438 } 439 } 440 441 static device_method_t sdhci_methods[] = { 442 /* device_if */ 443 DEVMETHOD(device_probe, sdhci_pci_probe), 444 DEVMETHOD(device_attach, sdhci_pci_attach), 445 DEVMETHOD(device_detach, sdhci_pci_detach), 446 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 447 DEVMETHOD(device_suspend, sdhci_pci_suspend), 448 DEVMETHOD(device_resume, sdhci_pci_resume), 449 450 /* Bus interface */ 451 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 452 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 453 454 /* mmcbr_if */ 455 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 456 DEVMETHOD(mmcbr_request, sdhci_generic_request), 457 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 458 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 459 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 460 461 /* SDHCI registers accessors */ 462 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 463 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 464 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 465 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 466 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 467 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 468 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 469 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 470 471 DEVMETHOD_END 472 }; 473 474 static driver_t sdhci_pci_driver = { 475 "sdhci_pci", 476 sdhci_methods, 477 sizeof(struct sdhci_pci_softc), 478 }; 479 static devclass_t sdhci_pci_devclass; 480 481 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 482 NULL); 483 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 484 DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); 485 MODULE_DEPEND(sdhci_pci, mmc, 1, 1, 1); 486