1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/module.h> 35 #include <sys/mutex.h> 36 #include <sys/resource.h> 37 #include <sys/rman.h> 38 #include <sys/sysctl.h> 39 #include <sys/taskqueue.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 47 #include <dev/mmc/bridge.h> 48 49 #include <dev/sdhci/sdhci.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci_if.h" 53 54 /* 55 * PCI registers 56 */ 57 #define PCI_SDHCI_IFPIO 0x00 58 #define PCI_SDHCI_IFDMA 0x01 59 #define PCI_SDHCI_IFVENDOR 0x02 60 61 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 62 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 63 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 64 65 /* 66 * RICOH specific PCI registers 67 */ 68 #define SDHC_PCI_MODE_KEY 0xf9 69 #define SDHC_PCI_MODE 0x150 70 #define SDHC_PCI_MODE_SD20 0x10 71 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 72 #define SDHC_PCI_BASE_FREQ 0xe1 73 74 static const struct sdhci_device { 75 uint32_t model; 76 uint16_t subvendor; 77 const char *desc; 78 u_int quirks; 79 } sdhci_devices[] = { 80 { 0x08221180, 0xffff, "RICOH R5C822 SD", 81 SDHCI_QUIRK_FORCE_DMA }, 82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 83 SDHCI_QUIRK_FORCE_DMA | 84 SDHCI_QUIRK_LOWER_FREQUENCY }, 85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 86 SDHCI_QUIRK_LOWER_FREQUENCY }, 87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 88 SDHCI_QUIRK_FORCE_DMA }, 89 { 0x05501524, 0xffff, "ENE CB712 SD", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x05511524, 0xffff, "ENE CB712 SD 2", 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07501524, 0xffff, "ENE CB714 SD", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x07511524, 0xffff, "ENE CB714 SD 2", 97 SDHCI_QUIRK_RESET_ON_IOS | 98 SDHCI_QUIRK_BROKEN_TIMINGS }, 99 { 0x410111ab, 0xffff, "Marvell CaFe SD", 100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 101 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 102 SDHCI_QUIRK_32BIT_DMA_SIZE | 103 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 107 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 108 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 109 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 110 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 111 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 112 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 113 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 114 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 115 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 116 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 117 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 118 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 119 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 120 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 121 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 122 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 123 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 124 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 125 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 126 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 127 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 128 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 129 { 0, 0xffff, NULL, 130 0 } 131 }; 132 133 struct sdhci_pci_softc { 134 u_int quirks; /* Chip specific quirks */ 135 struct resource *irq_res; /* IRQ resource */ 136 void *intrhand; /* Interrupt handle */ 137 138 int num_slots; /* Number of slots on this controller */ 139 struct sdhci_slot slots[6]; 140 struct resource *mem_res[6]; /* Memory resource */ 141 uint8_t cfg_freq; /* Saved frequency */ 142 uint8_t cfg_mode; /* Saved mode */ 143 }; 144 145 static int sdhci_enable_msi = 1; 146 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 147 0, "Enable MSI interrupts"); 148 149 static uint8_t 150 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 151 { 152 struct sdhci_pci_softc *sc = device_get_softc(dev); 153 154 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 155 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 156 return bus_read_1(sc->mem_res[slot->num], off); 157 } 158 159 static void 160 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 161 uint8_t val) 162 { 163 struct sdhci_pci_softc *sc = device_get_softc(dev); 164 165 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167 bus_write_1(sc->mem_res[slot->num], off, val); 168 } 169 170 static uint16_t 171 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 172 { 173 struct sdhci_pci_softc *sc = device_get_softc(dev); 174 175 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 176 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 177 return bus_read_2(sc->mem_res[slot->num], off); 178 } 179 180 static void 181 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 182 uint16_t val) 183 { 184 struct sdhci_pci_softc *sc = device_get_softc(dev); 185 186 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 187 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 188 bus_write_2(sc->mem_res[slot->num], off, val); 189 } 190 191 static uint32_t 192 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 193 { 194 struct sdhci_pci_softc *sc = device_get_softc(dev); 195 196 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 197 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 198 return bus_read_4(sc->mem_res[slot->num], off); 199 } 200 201 static void 202 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 203 uint32_t val) 204 { 205 struct sdhci_pci_softc *sc = device_get_softc(dev); 206 207 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 208 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 209 bus_write_4(sc->mem_res[slot->num], off, val); 210 } 211 212 static void 213 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 214 bus_size_t off, uint32_t *data, bus_size_t count) 215 { 216 struct sdhci_pci_softc *sc = device_get_softc(dev); 217 218 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 219 } 220 221 static void 222 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 223 bus_size_t off, uint32_t *data, bus_size_t count) 224 { 225 struct sdhci_pci_softc *sc = device_get_softc(dev); 226 227 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 228 } 229 230 static void sdhci_pci_intr(void *arg); 231 232 static void 233 sdhci_lower_frequency(device_t dev) 234 { 235 struct sdhci_pci_softc *sc = device_get_softc(dev); 236 237 /* 238 * Enable SD2.0 mode. 239 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 240 */ 241 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 242 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 243 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 244 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 245 246 /* 247 * Some SD/MMC cards don't work with the default base 248 * clock frequency of 200 MHz. Lower it to 50 MHz. 249 */ 250 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 251 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 252 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 253 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 254 } 255 256 static void 257 sdhci_restore_frequency(device_t dev) 258 { 259 struct sdhci_pci_softc *sc = device_get_softc(dev); 260 261 /* Restore mode. */ 262 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 263 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 264 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 265 266 /* Restore frequency. */ 267 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 268 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 269 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 270 } 271 272 static int 273 sdhci_pci_probe(device_t dev) 274 { 275 uint32_t model; 276 uint16_t subvendor; 277 uint8_t class, subclass; 278 int i, result; 279 280 model = (uint32_t)pci_get_device(dev) << 16; 281 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 282 subvendor = pci_get_subvendor(dev); 283 class = pci_get_class(dev); 284 subclass = pci_get_subclass(dev); 285 286 result = ENXIO; 287 for (i = 0; sdhci_devices[i].model != 0; i++) { 288 if (sdhci_devices[i].model == model && 289 (sdhci_devices[i].subvendor == 0xffff || 290 sdhci_devices[i].subvendor == subvendor)) { 291 device_set_desc(dev, sdhci_devices[i].desc); 292 result = BUS_PROBE_DEFAULT; 293 break; 294 } 295 } 296 if (result == ENXIO && class == PCIC_BASEPERIPH && 297 subclass == PCIS_BASEPERIPH_SDHC) { 298 device_set_desc(dev, "Generic SD HCI"); 299 result = BUS_PROBE_GENERIC; 300 } 301 302 return (result); 303 } 304 305 static int 306 sdhci_pci_attach(device_t dev) 307 { 308 struct sdhci_pci_softc *sc = device_get_softc(dev); 309 struct sdhci_slot *slot; 310 uint32_t model; 311 uint16_t subvendor; 312 int bar, err, rid, slots, i; 313 314 model = (uint32_t)pci_get_device(dev) << 16; 315 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 316 subvendor = pci_get_subvendor(dev); 317 /* Apply chip specific quirks. */ 318 for (i = 0; sdhci_devices[i].model != 0; i++) { 319 if (sdhci_devices[i].model == model && 320 (sdhci_devices[i].subvendor == 0xffff || 321 sdhci_devices[i].subvendor == subvendor)) { 322 sc->quirks = sdhci_devices[i].quirks; 323 break; 324 } 325 } 326 /* Some controllers need to be bumped into the right mode. */ 327 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 328 sdhci_lower_frequency(dev); 329 /* Read slots info from PCI registers. */ 330 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 331 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 332 slots = PCI_SLOT_INFO_SLOTS(slots); 333 if (slots > 6 || bar > 5) { 334 device_printf(dev, "Incorrect slots information (%d, %d).\n", 335 slots, bar); 336 return (EINVAL); 337 } 338 /* Allocate IRQ. */ 339 i = 1; 340 rid = 0; 341 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 342 rid = 1; 343 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 344 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 345 if (sc->irq_res == NULL) { 346 device_printf(dev, "Can't allocate IRQ\n"); 347 pci_release_msi(dev); 348 return (ENOMEM); 349 } 350 /* Scan all slots. */ 351 for (i = 0; i < slots; i++) { 352 slot = &sc->slots[sc->num_slots]; 353 354 /* Allocate memory. */ 355 rid = PCIR_BAR(bar + i); 356 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 357 &rid, RF_ACTIVE); 358 if (sc->mem_res[i] == NULL) { 359 device_printf(dev, 360 "Can't allocate memory for slot %d\n", i); 361 continue; 362 } 363 364 slot->quirks = sc->quirks; 365 366 if (sdhci_init_slot(dev, slot, i) != 0) 367 continue; 368 369 sc->num_slots++; 370 } 371 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 372 /* Activate the interrupt */ 373 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 374 NULL, sdhci_pci_intr, sc, &sc->intrhand); 375 if (err) 376 device_printf(dev, "Can't setup IRQ\n"); 377 pci_enable_busmaster(dev); 378 /* Process cards detection. */ 379 for (i = 0; i < sc->num_slots; i++) 380 sdhci_start_slot(&sc->slots[i]); 381 382 return (0); 383 } 384 385 static int 386 sdhci_pci_detach(device_t dev) 387 { 388 struct sdhci_pci_softc *sc = device_get_softc(dev); 389 int i; 390 391 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 392 bus_release_resource(dev, SYS_RES_IRQ, 393 rman_get_rid(sc->irq_res), sc->irq_res); 394 pci_release_msi(dev); 395 396 for (i = 0; i < sc->num_slots; i++) { 397 sdhci_cleanup_slot(&sc->slots[i]); 398 bus_release_resource(dev, SYS_RES_MEMORY, 399 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 400 } 401 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 402 sdhci_restore_frequency(dev); 403 return (0); 404 } 405 406 static int 407 sdhci_pci_shutdown(device_t dev) 408 { 409 struct sdhci_pci_softc *sc = device_get_softc(dev); 410 411 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 412 sdhci_restore_frequency(dev); 413 return (0); 414 } 415 416 static int 417 sdhci_pci_suspend(device_t dev) 418 { 419 struct sdhci_pci_softc *sc = device_get_softc(dev); 420 int i, err; 421 422 err = bus_generic_suspend(dev); 423 if (err) 424 return (err); 425 for (i = 0; i < sc->num_slots; i++) 426 sdhci_generic_suspend(&sc->slots[i]); 427 return (0); 428 } 429 430 static int 431 sdhci_pci_resume(device_t dev) 432 { 433 struct sdhci_pci_softc *sc = device_get_softc(dev); 434 int i, err; 435 436 for (i = 0; i < sc->num_slots; i++) 437 sdhci_generic_resume(&sc->slots[i]); 438 err = bus_generic_resume(dev); 439 if (err) 440 return (err); 441 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 442 sdhci_lower_frequency(dev); 443 return (0); 444 } 445 446 static void 447 sdhci_pci_intr(void *arg) 448 { 449 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 450 int i; 451 452 for (i = 0; i < sc->num_slots; i++) 453 sdhci_generic_intr(&sc->slots[i]); 454 } 455 456 static device_method_t sdhci_methods[] = { 457 /* device_if */ 458 DEVMETHOD(device_probe, sdhci_pci_probe), 459 DEVMETHOD(device_attach, sdhci_pci_attach), 460 DEVMETHOD(device_detach, sdhci_pci_detach), 461 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 462 DEVMETHOD(device_suspend, sdhci_pci_suspend), 463 DEVMETHOD(device_resume, sdhci_pci_resume), 464 465 /* Bus interface */ 466 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 467 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 468 469 /* mmcbr_if */ 470 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 471 DEVMETHOD(mmcbr_request, sdhci_generic_request), 472 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 473 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 474 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 475 476 /* SDHCI registers accessors */ 477 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 478 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 479 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 480 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 481 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 482 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 483 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 484 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 485 486 DEVMETHOD_END 487 }; 488 489 static driver_t sdhci_pci_driver = { 490 "sdhci_pci", 491 sdhci_methods, 492 sizeof(struct sdhci_pci_softc), 493 }; 494 static devclass_t sdhci_pci_devclass; 495 496 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 497 NULL); 498 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 499 MMC_DECLARE_BRIDGE(sdhci_pci); 500