xref: /freebsd/sys/dev/sdhci/sdhci_pci.c (revision 642870485c089b57000fe538d3485e272b038d59)
1 /*-
2  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/resource.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41 
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/stdarg.h>
48 
49 #include <dev/mmc/bridge.h>
50 #include <dev/mmc/mmcreg.h>
51 #include <dev/mmc/mmcbrvar.h>
52 
53 #include "sdhci.h"
54 #include "mmcbr_if.h"
55 #include "sdhci_if.h"
56 
57 /*
58  * PCI registers
59  */
60 
61 #define	PCI_SDHCI_IFPIO			0x00
62 #define	PCI_SDHCI_IFDMA			0x01
63 #define	PCI_SDHCI_IFVENDOR		0x02
64 
65 #define	PCI_SLOT_INFO			0x40	/* 8 bits */
66 #define	PCI_SLOT_INFO_SLOTS(x)		(((x >> 4) & 7) + 1)
67 #define	PCI_SLOT_INFO_FIRST_BAR(x)	((x) & 7)
68 
69 /*
70  * RICOH specific PCI registers
71  */
72 #define	SDHC_PCI_MODE_KEY		0xf9
73 #define	SDHC_PCI_MODE			0x150
74 #define	SDHC_PCI_MODE_SD20		0x10
75 #define	SDHC_PCI_BASE_FREQ_KEY		0xfc
76 #define	SDHC_PCI_BASE_FREQ		0xe1
77 
78 static const struct sdhci_device {
79 	uint32_t	model;
80 	uint16_t	subvendor;
81 	const char	*desc;
82 	u_int		quirks;
83 } sdhci_devices[] = {
84 	{ 0x08221180,	0xffff,	"RICOH R5C822 SD",
85 	    SDHCI_QUIRK_FORCE_DMA },
86 	{ 0xe8221180,	0xffff,	"RICOH R5CE822 SD",
87 	    SDHCI_QUIRK_FORCE_DMA |
88 	    SDHCI_QUIRK_LOWER_FREQUENCY },
89 	{ 0xe8231180,	0xffff,	"RICOH R5CE823 SD",
90 	    SDHCI_QUIRK_LOWER_FREQUENCY },
91 	{ 0x8034104c,	0xffff, "TI XX21/XX11 SD",
92 	    SDHCI_QUIRK_FORCE_DMA },
93 	{ 0x05501524,	0xffff, "ENE CB712 SD",
94 	    SDHCI_QUIRK_BROKEN_TIMINGS },
95 	{ 0x05511524,	0xffff, "ENE CB712 SD 2",
96 	    SDHCI_QUIRK_BROKEN_TIMINGS },
97 	{ 0x07501524,	0xffff, "ENE CB714 SD",
98 	    SDHCI_QUIRK_RESET_ON_IOS |
99 	    SDHCI_QUIRK_BROKEN_TIMINGS },
100 	{ 0x07511524,	0xffff, "ENE CB714 SD 2",
101 	    SDHCI_QUIRK_RESET_ON_IOS |
102 	    SDHCI_QUIRK_BROKEN_TIMINGS },
103 	{ 0x410111ab,	0xffff, "Marvell CaFe SD",
104 	    SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
105 	{ 0x2381197B,	0xffff,	"JMicron JMB38X SD",
106 	    SDHCI_QUIRK_32BIT_DMA_SIZE |
107 	    SDHCI_QUIRK_RESET_AFTER_REQUEST },
108 	{ 0x16bc14e4,	0xffff,	"Broadcom BCM577xx SDXC/MMC Card Reader",
109 	    SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
110 	{ 0x0f148086,	0xffff,	"Intel Bay Trail eMMC 4.5 Controller",
111 	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
112 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET },
113 	{ 0x0f508086,	0xffff,	"Intel Bay Trail eMMC 4.5 Controller",
114 	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
115 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET },
116 	{ 0x22948086,	0xffff,	"Intel Braswell eMMC 4.5.1 Controller",
117 	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
118 	    SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
119 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET },
120 	{ 0x5acc8086,	0xffff,	"Intel Apollo Lake eMMC 5.0 Controller",
121 	    SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
122 	    SDHCI_QUIRK_INTEL_POWER_UP_RESET },
123 	{ 0,		0xffff,	NULL,
124 	    0 }
125 };
126 
127 struct sdhci_pci_softc {
128 	u_int		quirks;		/* Chip specific quirks */
129 	struct resource *irq_res;	/* IRQ resource */
130 	void		*intrhand;	/* Interrupt handle */
131 
132 	int		num_slots;	/* Number of slots on this controller */
133 	struct sdhci_slot slots[6];
134 	struct resource	*mem_res[6];	/* Memory resource */
135 	uint8_t		cfg_freq;	/* Saved frequency */
136 	uint8_t		cfg_mode;	/* Saved mode */
137 };
138 
139 static int sdhci_enable_msi = 1;
140 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
141     0, "Enable MSI interrupts");
142 
143 static uint8_t
144 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
145 {
146 	struct sdhci_pci_softc *sc = device_get_softc(dev);
147 
148 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
149 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
150 	return bus_read_1(sc->mem_res[slot->num], off);
151 }
152 
153 static void
154 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
155     uint8_t val)
156 {
157 	struct sdhci_pci_softc *sc = device_get_softc(dev);
158 
159 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
160 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
161 	bus_write_1(sc->mem_res[slot->num], off, val);
162 }
163 
164 static uint16_t
165 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
166 {
167 	struct sdhci_pci_softc *sc = device_get_softc(dev);
168 
169 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
170 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
171 	return bus_read_2(sc->mem_res[slot->num], off);
172 }
173 
174 static void
175 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
176     uint16_t val)
177 {
178 	struct sdhci_pci_softc *sc = device_get_softc(dev);
179 
180 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
181 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
182 	bus_write_2(sc->mem_res[slot->num], off, val);
183 }
184 
185 static uint32_t
186 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
187 {
188 	struct sdhci_pci_softc *sc = device_get_softc(dev);
189 
190 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
191 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
192 	return bus_read_4(sc->mem_res[slot->num], off);
193 }
194 
195 static void
196 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
197     uint32_t val)
198 {
199 	struct sdhci_pci_softc *sc = device_get_softc(dev);
200 
201 	bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
202 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
203 	bus_write_4(sc->mem_res[slot->num], off, val);
204 }
205 
206 static void
207 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot,
208     bus_size_t off, uint32_t *data, bus_size_t count)
209 {
210 	struct sdhci_pci_softc *sc = device_get_softc(dev);
211 
212 	bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
213 }
214 
215 static void
216 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot,
217     bus_size_t off, uint32_t *data, bus_size_t count)
218 {
219 	struct sdhci_pci_softc *sc = device_get_softc(dev);
220 
221 	bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
222 }
223 
224 static void sdhci_pci_intr(void *arg);
225 
226 static void
227 sdhci_lower_frequency(device_t dev)
228 {
229 	struct sdhci_pci_softc *sc = device_get_softc(dev);
230 
231 	/*
232 	 * Enable SD2.0 mode.
233 	 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
234 	 */
235 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
236 	sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
237 	pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
238 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
239 
240 	/*
241 	 * Some SD/MMC cards don't work with the default base
242 	 * clock frequency of 200 MHz.  Lower it to 50 MHz.
243 	 */
244 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
245 	sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
246 	pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
247 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
248 }
249 
250 static void
251 sdhci_restore_frequency(device_t dev)
252 {
253 	struct sdhci_pci_softc *sc = device_get_softc(dev);
254 
255 	/* Restore mode. */
256 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
257 	pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
258 	pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
259 
260 	/* Restore frequency. */
261 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
262 	pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
263 	pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
264 }
265 
266 static int
267 sdhci_pci_probe(device_t dev)
268 {
269 	uint32_t model;
270 	uint16_t subvendor;
271 	uint8_t class, subclass;
272 	int i, result;
273 
274 	model = (uint32_t)pci_get_device(dev) << 16;
275 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
276 	subvendor = pci_get_subvendor(dev);
277 	class = pci_get_class(dev);
278 	subclass = pci_get_subclass(dev);
279 
280 	result = ENXIO;
281 	for (i = 0; sdhci_devices[i].model != 0; i++) {
282 		if (sdhci_devices[i].model == model &&
283 		    (sdhci_devices[i].subvendor == 0xffff ||
284 		    sdhci_devices[i].subvendor == subvendor)) {
285 			device_set_desc(dev, sdhci_devices[i].desc);
286 			result = BUS_PROBE_DEFAULT;
287 			break;
288 		}
289 	}
290 	if (result == ENXIO && class == PCIC_BASEPERIPH &&
291 	    subclass == PCIS_BASEPERIPH_SDHC) {
292 		device_set_desc(dev, "Generic SD HCI");
293 		result = BUS_PROBE_GENERIC;
294 	}
295 
296 	return (result);
297 }
298 
299 static int
300 sdhci_pci_attach(device_t dev)
301 {
302 	struct sdhci_pci_softc *sc = device_get_softc(dev);
303 	struct sdhci_slot *slot;
304 	uint32_t model;
305 	uint16_t subvendor;
306 	int bar, err, rid, slots, i;
307 
308 	model = (uint32_t)pci_get_device(dev) << 16;
309 	model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
310 	subvendor = pci_get_subvendor(dev);
311 	/* Apply chip specific quirks. */
312 	for (i = 0; sdhci_devices[i].model != 0; i++) {
313 		if (sdhci_devices[i].model == model &&
314 		    (sdhci_devices[i].subvendor == 0xffff ||
315 		    sdhci_devices[i].subvendor == subvendor)) {
316 			sc->quirks = sdhci_devices[i].quirks;
317 			break;
318 		}
319 	}
320 	/* Some controllers need to be bumped into the right mode. */
321 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
322 		sdhci_lower_frequency(dev);
323 	/* Read slots info from PCI registers. */
324 	slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
325 	bar = PCI_SLOT_INFO_FIRST_BAR(slots);
326 	slots = PCI_SLOT_INFO_SLOTS(slots);
327 	if (slots > 6 || bar > 5) {
328 		device_printf(dev, "Incorrect slots information (%d, %d).\n",
329 		    slots, bar);
330 		return (EINVAL);
331 	}
332 	/* Allocate IRQ. */
333 	i = 1;
334 	rid = 0;
335 	if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
336 		rid = 1;
337 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
338 		RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
339 	if (sc->irq_res == NULL) {
340 		device_printf(dev, "Can't allocate IRQ\n");
341 		pci_release_msi(dev);
342 		return (ENOMEM);
343 	}
344 	/* Scan all slots. */
345 	for (i = 0; i < slots; i++) {
346 		slot = &sc->slots[sc->num_slots];
347 
348 		/* Allocate memory. */
349 		rid = PCIR_BAR(bar + i);
350 		sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
351 		    &rid, RF_ACTIVE);
352 		if (sc->mem_res[i] == NULL) {
353 			device_printf(dev,
354 			    "Can't allocate memory for slot %d\n", i);
355 			continue;
356 		}
357 
358 		slot->quirks = sc->quirks;
359 
360 		if (sdhci_init_slot(dev, slot, i) != 0)
361 			continue;
362 
363 		sc->num_slots++;
364 	}
365 	device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
366 	/* Activate the interrupt */
367 	err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
368 	    NULL, sdhci_pci_intr, sc, &sc->intrhand);
369 	if (err)
370 		device_printf(dev, "Can't setup IRQ\n");
371 	pci_enable_busmaster(dev);
372 	/* Process cards detection. */
373 	for (i = 0; i < sc->num_slots; i++)
374 		sdhci_start_slot(&sc->slots[i]);
375 
376 	return (0);
377 }
378 
379 static int
380 sdhci_pci_detach(device_t dev)
381 {
382 	struct sdhci_pci_softc *sc = device_get_softc(dev);
383 	int i;
384 
385 	bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
386 	bus_release_resource(dev, SYS_RES_IRQ,
387 	    rman_get_rid(sc->irq_res), sc->irq_res);
388 	pci_release_msi(dev);
389 
390 	for (i = 0; i < sc->num_slots; i++) {
391 		sdhci_cleanup_slot(&sc->slots[i]);
392 		bus_release_resource(dev, SYS_RES_MEMORY,
393 		    rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
394 	}
395 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
396 		sdhci_restore_frequency(dev);
397 	return (0);
398 }
399 
400 static int
401 sdhci_pci_shutdown(device_t dev)
402 {
403 	struct sdhci_pci_softc *sc = device_get_softc(dev);
404 
405 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
406 		sdhci_restore_frequency(dev);
407 	return (0);
408 }
409 
410 static int
411 sdhci_pci_suspend(device_t dev)
412 {
413 	struct sdhci_pci_softc *sc = device_get_softc(dev);
414 	int i, err;
415 
416 	err = bus_generic_suspend(dev);
417 	if (err)
418 		return (err);
419 	for (i = 0; i < sc->num_slots; i++)
420 		sdhci_generic_suspend(&sc->slots[i]);
421 	return (0);
422 }
423 
424 static int
425 sdhci_pci_resume(device_t dev)
426 {
427 	struct sdhci_pci_softc *sc = device_get_softc(dev);
428 	int i, err;
429 
430 	for (i = 0; i < sc->num_slots; i++)
431 		sdhci_generic_resume(&sc->slots[i]);
432 	err = bus_generic_resume(dev);
433 	if (err)
434 		return (err);
435 	if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
436 		sdhci_lower_frequency(dev);
437 	return (0);
438 }
439 
440 static void
441 sdhci_pci_intr(void *arg)
442 {
443 	struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
444 	int i;
445 
446 	for (i = 0; i < sc->num_slots; i++)
447 		sdhci_generic_intr(&sc->slots[i]);
448 }
449 
450 static device_method_t sdhci_methods[] = {
451 	/* device_if */
452 	DEVMETHOD(device_probe,		sdhci_pci_probe),
453 	DEVMETHOD(device_attach,	sdhci_pci_attach),
454 	DEVMETHOD(device_detach,	sdhci_pci_detach),
455 	DEVMETHOD(device_shutdown,	sdhci_pci_shutdown),
456 	DEVMETHOD(device_suspend,	sdhci_pci_suspend),
457 	DEVMETHOD(device_resume,	sdhci_pci_resume),
458 
459 	/* Bus interface */
460 	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
461 	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
462 
463 	/* mmcbr_if */
464 	DEVMETHOD(mmcbr_update_ios,	sdhci_generic_update_ios),
465 	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
466 	DEVMETHOD(mmcbr_get_ro,		sdhci_generic_get_ro),
467 	DEVMETHOD(mmcbr_acquire_host,   sdhci_generic_acquire_host),
468 	DEVMETHOD(mmcbr_release_host,   sdhci_generic_release_host),
469 
470 	/* SDHCI registers accessors */
471 	DEVMETHOD(sdhci_read_1,		sdhci_pci_read_1),
472 	DEVMETHOD(sdhci_read_2,		sdhci_pci_read_2),
473 	DEVMETHOD(sdhci_read_4,		sdhci_pci_read_4),
474 	DEVMETHOD(sdhci_read_multi_4,	sdhci_pci_read_multi_4),
475 	DEVMETHOD(sdhci_write_1,	sdhci_pci_write_1),
476 	DEVMETHOD(sdhci_write_2,	sdhci_pci_write_2),
477 	DEVMETHOD(sdhci_write_4,	sdhci_pci_write_4),
478 	DEVMETHOD(sdhci_write_multi_4,	sdhci_pci_write_multi_4),
479 
480 	DEVMETHOD_END
481 };
482 
483 static driver_t sdhci_pci_driver = {
484 	"sdhci_pci",
485 	sdhci_methods,
486 	sizeof(struct sdhci_pci_softc),
487 };
488 static devclass_t sdhci_pci_devclass;
489 
490 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
491     NULL);
492 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
493 DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL);
494 MODULE_DEPEND(sdhci_pci, mmc, 1, 1, 1);
495