1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/stdarg.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include "sdhci.h" 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 /* 58 * PCI registers 59 */ 60 61 #define PCI_SDHCI_IFPIO 0x00 62 #define PCI_SDHCI_IFDMA 0x01 63 #define PCI_SDHCI_IFVENDOR 0x02 64 65 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 66 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69 /* 70 * RICOH specific PCI registers 71 */ 72 #define SDHC_PCI_MODE_KEY 0xf9 73 #define SDHC_PCI_MODE 0x150 74 #define SDHC_PCI_MODE_SD20 0x10 75 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 76 #define SDHC_PCI_BASE_FREQ 0xe1 77 78 static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 char *desc; 82 u_int quirks; 83 } sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH SD", 87 SDHCI_QUIRK_FORCE_DMA }, 88 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 89 SDHCI_QUIRK_LOWER_FREQUENCY }, 90 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 91 SDHCI_QUIRK_FORCE_DMA }, 92 { 0x05501524, 0xffff, "ENE CB712 SD", 93 SDHCI_QUIRK_BROKEN_TIMINGS }, 94 { 0x05511524, 0xffff, "ENE CB712 SD 2", 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x07501524, 0xffff, "ENE CB714 SD", 97 SDHCI_QUIRK_RESET_ON_IOS | 98 SDHCI_QUIRK_BROKEN_TIMINGS }, 99 { 0x07511524, 0xffff, "ENE CB714 SD 2", 100 SDHCI_QUIRK_RESET_ON_IOS | 101 SDHCI_QUIRK_BROKEN_TIMINGS }, 102 { 0x410111ab, 0xffff, "Marvell CaFe SD", 103 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 104 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 105 SDHCI_QUIRK_32BIT_DMA_SIZE | 106 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 107 { 0, 0xffff, NULL, 108 0 } 109 }; 110 111 struct sdhci_pci_softc { 112 device_t dev; /* Controller device */ 113 u_int quirks; /* Chip specific quirks */ 114 struct resource *irq_res; /* IRQ resource */ 115 int irq_rid; 116 void *intrhand; /* Interrupt handle */ 117 118 int num_slots; /* Number of slots on this controller */ 119 struct sdhci_slot slots[6]; 120 struct resource *mem_res[6]; /* Memory resource */ 121 int mem_rid[6]; 122 }; 123 124 static SYSCTL_NODE(_hw, OID_AUTO, sdhci_pci, CTLFLAG_RD, 0, "sdhci PCI driver"); 125 126 int sdhci_pci_debug; 127 SYSCTL_INT(_hw_sdhci_pci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_pci_debug, 0, "Debug level"); 128 129 static uint8_t 130 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 131 { 132 struct sdhci_pci_softc *sc = device_get_softc(dev); 133 134 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 135 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 136 return bus_read_1(sc->mem_res[slot->num], off); 137 } 138 139 static void 140 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 141 { 142 struct sdhci_pci_softc *sc = device_get_softc(dev); 143 144 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 145 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 146 bus_write_1(sc->mem_res[slot->num], off, val); 147 } 148 149 static uint16_t 150 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 151 { 152 struct sdhci_pci_softc *sc = device_get_softc(dev); 153 154 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 155 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 156 return bus_read_2(sc->mem_res[slot->num], off); 157 } 158 159 static void 160 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 161 { 162 struct sdhci_pci_softc *sc = device_get_softc(dev); 163 164 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 165 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 166 bus_write_2(sc->mem_res[slot->num], off, val); 167 } 168 169 static uint32_t 170 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 171 { 172 struct sdhci_pci_softc *sc = device_get_softc(dev); 173 174 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 175 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 176 return bus_read_4(sc->mem_res[slot->num], off); 177 } 178 179 static void 180 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 181 { 182 struct sdhci_pci_softc *sc = device_get_softc(dev); 183 184 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 185 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 186 bus_write_4(sc->mem_res[slot->num], off, val); 187 } 188 189 static void 190 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 191 bus_size_t off, uint32_t *data, bus_size_t count) 192 { 193 struct sdhci_pci_softc *sc = device_get_softc(dev); 194 195 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 196 } 197 198 static void 199 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 200 bus_size_t off, uint32_t *data, bus_size_t count) 201 { 202 struct sdhci_pci_softc *sc = device_get_softc(dev); 203 204 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 205 } 206 207 static void sdhci_pci_intr(void *arg); 208 209 static void 210 sdhci_lower_frequency(device_t dev) 211 { 212 213 /* Enable SD2.0 mode. */ 214 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 215 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 216 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 217 218 /* 219 * Some SD/MMC cards don't work with the default base 220 * clock frequency of 200MHz. Lower it to 50Hz. 221 */ 222 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 223 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 224 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 225 } 226 227 static int 228 sdhci_pci_probe(device_t dev) 229 { 230 uint32_t model; 231 uint16_t subvendor; 232 uint8_t class, subclass; 233 int i, result; 234 235 model = (uint32_t)pci_get_device(dev) << 16; 236 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 237 subvendor = pci_get_subvendor(dev); 238 class = pci_get_class(dev); 239 subclass = pci_get_subclass(dev); 240 241 result = ENXIO; 242 for (i = 0; sdhci_devices[i].model != 0; i++) { 243 if (sdhci_devices[i].model == model && 244 (sdhci_devices[i].subvendor == 0xffff || 245 sdhci_devices[i].subvendor == subvendor)) { 246 device_set_desc(dev, sdhci_devices[i].desc); 247 result = BUS_PROBE_DEFAULT; 248 break; 249 } 250 } 251 if (result == ENXIO && class == PCIC_BASEPERIPH && 252 subclass == PCIS_BASEPERIPH_SDHC) { 253 device_set_desc(dev, "Generic SD HCI"); 254 result = BUS_PROBE_GENERIC; 255 } 256 257 return (result); 258 } 259 260 static int 261 sdhci_pci_attach(device_t dev) 262 { 263 struct sdhci_pci_softc *sc = device_get_softc(dev); 264 uint32_t model; 265 uint16_t subvendor; 266 uint8_t class, subclass, progif; 267 int err, slots, bar, i; 268 269 sc->dev = dev; 270 model = (uint32_t)pci_get_device(dev) << 16; 271 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 272 subvendor = pci_get_subvendor(dev); 273 class = pci_get_class(dev); 274 subclass = pci_get_subclass(dev); 275 progif = pci_get_progif(dev); 276 /* Apply chip specific quirks. */ 277 for (i = 0; sdhci_devices[i].model != 0; i++) { 278 if (sdhci_devices[i].model == model && 279 (sdhci_devices[i].subvendor == 0xffff || 280 sdhci_devices[i].subvendor == subvendor)) { 281 sc->quirks = sdhci_devices[i].quirks; 282 break; 283 } 284 } 285 /* Some controllers need to be bumped into the right mode. */ 286 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 287 sdhci_lower_frequency(dev); 288 /* Read slots info from PCI registers. */ 289 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 290 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 291 slots = PCI_SLOT_INFO_SLOTS(slots); 292 if (slots > 6 || bar > 5) { 293 device_printf(dev, "Incorrect slots information (%d, %d).\n", 294 slots, bar); 295 return (EINVAL); 296 } 297 /* Allocate IRQ. */ 298 sc->irq_rid = 0; 299 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 300 RF_SHAREABLE | RF_ACTIVE); 301 if (sc->irq_res == NULL) { 302 device_printf(dev, "Can't allocate IRQ\n"); 303 return (ENOMEM); 304 } 305 /* Scan all slots. */ 306 for (i = 0; i < slots; i++) { 307 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 308 309 /* Allocate memory. */ 310 sc->mem_rid[i] = PCIR_BAR(bar + i); 311 sc->mem_res[i] = bus_alloc_resource(dev, 312 SYS_RES_MEMORY, &(sc->mem_rid[i]), 0ul, ~0ul, 0x100, RF_ACTIVE); 313 if (sc->mem_res[i] == NULL) { 314 device_printf(dev, "Can't allocate memory for slot %d\n", i); 315 continue; 316 } 317 318 if (sdhci_init_slot(dev, slot, i) != 0) 319 continue; 320 321 322 sc->num_slots++; 323 } 324 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 325 /* Activate the interrupt */ 326 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 327 NULL, sdhci_pci_intr, sc, &sc->intrhand); 328 if (err) 329 device_printf(dev, "Can't setup IRQ\n"); 330 pci_enable_busmaster(dev); 331 /* Process cards detection. */ 332 for (i = 0; i < sc->num_slots; i++) { 333 struct sdhci_slot *slot = &sc->slots[i]; 334 335 sdhci_start_slot(slot); 336 } 337 338 return (0); 339 } 340 341 static int 342 sdhci_pci_detach(device_t dev) 343 { 344 struct sdhci_pci_softc *sc = device_get_softc(dev); 345 int i; 346 347 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 348 bus_release_resource(dev, SYS_RES_IRQ, 349 sc->irq_rid, sc->irq_res); 350 351 for (i = 0; i < sc->num_slots; i++) { 352 struct sdhci_slot *slot = &sc->slots[i]; 353 354 sdhci_cleanup_slot(slot); 355 bus_release_resource(dev, SYS_RES_MEMORY, 356 sc->mem_rid[i], sc->mem_res[i]); 357 } 358 return (0); 359 } 360 361 static int 362 sdhci_pci_suspend(device_t dev) 363 { 364 struct sdhci_pci_softc *sc = device_get_softc(dev); 365 int i, err; 366 367 err = bus_generic_suspend(dev); 368 if (err) 369 return (err); 370 for (i = 0; i < sc->num_slots; i++) 371 sdhci_generic_suspend(&sc->slots[i]); 372 return (0); 373 } 374 375 static int 376 sdhci_pci_resume(device_t dev) 377 { 378 struct sdhci_pci_softc *sc = device_get_softc(dev); 379 int i; 380 381 for (i = 0; i < sc->num_slots; i++) 382 sdhci_generic_resume(&sc->slots[i]); 383 return (bus_generic_resume(dev)); 384 } 385 386 387 static void 388 sdhci_pci_intr(void *arg) 389 { 390 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 391 int i; 392 393 for (i = 0; i < sc->num_slots; i++) { 394 struct sdhci_slot *slot = &sc->slots[i]; 395 sdhci_generic_intr(slot); 396 } 397 } 398 399 static device_method_t sdhci_methods[] = { 400 /* device_if */ 401 DEVMETHOD(device_probe, sdhci_pci_probe), 402 DEVMETHOD(device_attach, sdhci_pci_attach), 403 DEVMETHOD(device_detach, sdhci_pci_detach), 404 DEVMETHOD(device_suspend, sdhci_pci_suspend), 405 DEVMETHOD(device_resume, sdhci_pci_resume), 406 407 /* Bus interface */ 408 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 409 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 410 411 /* mmcbr_if */ 412 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 413 DEVMETHOD(mmcbr_request, sdhci_generic_request), 414 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 415 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 416 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 417 418 /* SDHCI registers accessors */ 419 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 420 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 421 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 422 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 423 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 424 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 425 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 426 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 427 428 DEVMETHOD_END 429 }; 430 431 static driver_t sdhci_pci_driver = { 432 "sdhci_pci", 433 sdhci_methods, 434 sizeof(struct sdhci_pci_softc), 435 }; 436 static devclass_t sdhci_pci_devclass; 437 438 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, 0, 0); 439 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 440