1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/stdarg.h> 48 49 #include <dev/mmc/bridge.h> 50 #include <dev/mmc/mmcreg.h> 51 #include <dev/mmc/mmcbrvar.h> 52 53 #include "sdhci.h" 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 /* 58 * PCI registers 59 */ 60 61 #define PCI_SDHCI_IFPIO 0x00 62 #define PCI_SDHCI_IFDMA 0x01 63 #define PCI_SDHCI_IFVENDOR 0x02 64 65 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 66 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69 /* 70 * RICOH specific PCI registers 71 */ 72 #define SDHC_PCI_MODE_KEY 0xf9 73 #define SDHC_PCI_MODE 0x150 74 #define SDHC_PCI_MODE_SD20 0x10 75 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 76 #define SDHC_PCI_BASE_FREQ 0xe1 77 78 static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 const char *desc; 82 u_int quirks; 83 } sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87 SDHCI_QUIRK_FORCE_DMA | 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90 SDHCI_QUIRK_LOWER_FREQUENCY }, 91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92 SDHCI_QUIRK_FORCE_DMA }, 93 { 0x05501524, 0xffff, "ENE CB712 SD", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x05511524, 0xffff, "ENE CB712 SD 2", 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07501524, 0xffff, "ENE CB714 SD", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x07511524, 0xffff, "ENE CB714 SD 2", 101 SDHCI_QUIRK_RESET_ON_IOS | 102 SDHCI_QUIRK_BROKEN_TIMINGS }, 103 { 0x410111ab, 0xffff, "Marvell CaFe SD", 104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106 SDHCI_QUIRK_32BIT_DMA_SIZE | 107 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108 { 0, 0xffff, NULL, 109 0 } 110 }; 111 112 struct sdhci_pci_softc { 113 u_int quirks; /* Chip specific quirks */ 114 struct resource *irq_res; /* IRQ resource */ 115 void *intrhand; /* Interrupt handle */ 116 117 int num_slots; /* Number of slots on this controller */ 118 struct sdhci_slot slots[6]; 119 struct resource *mem_res[6]; /* Memory resource */ 120 uint8_t cfg_freq; /* Saved mode */ 121 uint8_t cfg_mode; /* Saved frequency */ 122 }; 123 124 static int sdhci_enable_msi = 1; 125 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 126 0, "Enable MSI interrupts"); 127 128 static uint8_t 129 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 130 { 131 struct sdhci_pci_softc *sc = device_get_softc(dev); 132 133 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 134 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 135 return bus_read_1(sc->mem_res[slot->num], off); 136 } 137 138 static void 139 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 140 { 141 struct sdhci_pci_softc *sc = device_get_softc(dev); 142 143 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 144 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 145 bus_write_1(sc->mem_res[slot->num], off, val); 146 } 147 148 static uint16_t 149 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 150 { 151 struct sdhci_pci_softc *sc = device_get_softc(dev); 152 153 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 154 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 155 return bus_read_2(sc->mem_res[slot->num], off); 156 } 157 158 static void 159 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 160 { 161 struct sdhci_pci_softc *sc = device_get_softc(dev); 162 163 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 164 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 165 bus_write_2(sc->mem_res[slot->num], off, val); 166 } 167 168 static uint32_t 169 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 170 { 171 struct sdhci_pci_softc *sc = device_get_softc(dev); 172 173 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 174 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 175 return bus_read_4(sc->mem_res[slot->num], off); 176 } 177 178 static void 179 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 180 { 181 struct sdhci_pci_softc *sc = device_get_softc(dev); 182 183 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 184 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 185 bus_write_4(sc->mem_res[slot->num], off, val); 186 } 187 188 static void 189 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 190 bus_size_t off, uint32_t *data, bus_size_t count) 191 { 192 struct sdhci_pci_softc *sc = device_get_softc(dev); 193 194 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 195 } 196 197 static void 198 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 199 bus_size_t off, uint32_t *data, bus_size_t count) 200 { 201 struct sdhci_pci_softc *sc = device_get_softc(dev); 202 203 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 204 } 205 206 static void sdhci_pci_intr(void *arg); 207 208 static void 209 sdhci_lower_frequency(device_t dev) 210 { 211 struct sdhci_pci_softc *sc = device_get_softc(dev); 212 213 /* 214 * Enable SD2.0 mode. 215 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 216 */ 217 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 218 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 219 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 220 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 221 222 /* 223 * Some SD/MMC cards don't work with the default base 224 * clock frequency of 200 MHz. Lower it to 50 MHz. 225 */ 226 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 227 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 228 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 229 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 230 } 231 232 static void 233 sdhci_restore_frequency(device_t dev) 234 { 235 struct sdhci_pci_softc *sc = device_get_softc(dev); 236 237 /* Restore mode. */ 238 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 239 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 240 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 241 242 /* Restore frequency. */ 243 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 244 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 245 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 246 } 247 248 static int 249 sdhci_pci_probe(device_t dev) 250 { 251 uint32_t model; 252 uint16_t subvendor; 253 uint8_t class, subclass; 254 int i, result; 255 256 model = (uint32_t)pci_get_device(dev) << 16; 257 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 258 subvendor = pci_get_subvendor(dev); 259 class = pci_get_class(dev); 260 subclass = pci_get_subclass(dev); 261 262 result = ENXIO; 263 for (i = 0; sdhci_devices[i].model != 0; i++) { 264 if (sdhci_devices[i].model == model && 265 (sdhci_devices[i].subvendor == 0xffff || 266 sdhci_devices[i].subvendor == subvendor)) { 267 device_set_desc(dev, sdhci_devices[i].desc); 268 result = BUS_PROBE_DEFAULT; 269 break; 270 } 271 } 272 if (result == ENXIO && class == PCIC_BASEPERIPH && 273 subclass == PCIS_BASEPERIPH_SDHC) { 274 device_set_desc(dev, "Generic SD HCI"); 275 result = BUS_PROBE_GENERIC; 276 } 277 278 return (result); 279 } 280 281 static int 282 sdhci_pci_attach(device_t dev) 283 { 284 struct sdhci_pci_softc *sc = device_get_softc(dev); 285 uint32_t model; 286 uint16_t subvendor; 287 int bar, err, rid, slots, i; 288 289 model = (uint32_t)pci_get_device(dev) << 16; 290 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 291 subvendor = pci_get_subvendor(dev); 292 /* Apply chip specific quirks. */ 293 for (i = 0; sdhci_devices[i].model != 0; i++) { 294 if (sdhci_devices[i].model == model && 295 (sdhci_devices[i].subvendor == 0xffff || 296 sdhci_devices[i].subvendor == subvendor)) { 297 sc->quirks = sdhci_devices[i].quirks; 298 break; 299 } 300 } 301 /* Some controllers need to be bumped into the right mode. */ 302 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 303 sdhci_lower_frequency(dev); 304 /* Read slots info from PCI registers. */ 305 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 306 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 307 slots = PCI_SLOT_INFO_SLOTS(slots); 308 if (slots > 6 || bar > 5) { 309 device_printf(dev, "Incorrect slots information (%d, %d).\n", 310 slots, bar); 311 return (EINVAL); 312 } 313 /* Allocate IRQ. */ 314 i = 1; 315 rid = 0; 316 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 317 rid = 1; 318 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 319 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 320 if (sc->irq_res == NULL) { 321 device_printf(dev, "Can't allocate IRQ\n"); 322 pci_release_msi(dev); 323 return (ENOMEM); 324 } 325 /* Scan all slots. */ 326 for (i = 0; i < slots; i++) { 327 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 328 329 /* Allocate memory. */ 330 rid = PCIR_BAR(bar + i); 331 sc->mem_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, 332 &rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 333 if (sc->mem_res[i] == NULL) { 334 device_printf(dev, "Can't allocate memory for slot %d\n", i); 335 continue; 336 } 337 338 if (sdhci_init_slot(dev, slot, i) != 0) 339 continue; 340 341 sc->num_slots++; 342 } 343 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 344 /* Activate the interrupt */ 345 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 346 NULL, sdhci_pci_intr, sc, &sc->intrhand); 347 if (err) 348 device_printf(dev, "Can't setup IRQ\n"); 349 pci_enable_busmaster(dev); 350 /* Process cards detection. */ 351 for (i = 0; i < sc->num_slots; i++) { 352 struct sdhci_slot *slot = &sc->slots[i]; 353 354 sdhci_start_slot(slot); 355 } 356 357 return (0); 358 } 359 360 static int 361 sdhci_pci_detach(device_t dev) 362 { 363 struct sdhci_pci_softc *sc = device_get_softc(dev); 364 int i; 365 366 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 367 bus_release_resource(dev, SYS_RES_IRQ, 368 rman_get_rid(sc->irq_res), sc->irq_res); 369 pci_release_msi(dev); 370 371 for (i = 0; i < sc->num_slots; i++) { 372 struct sdhci_slot *slot = &sc->slots[i]; 373 374 sdhci_cleanup_slot(slot); 375 bus_release_resource(dev, SYS_RES_MEMORY, 376 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 377 } 378 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 379 sdhci_restore_frequency(dev); 380 return (0); 381 } 382 383 static int 384 sdhci_pci_shutdown(device_t dev) 385 { 386 struct sdhci_pci_softc *sc = device_get_softc(dev); 387 388 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 389 sdhci_restore_frequency(dev); 390 return (0); 391 } 392 393 static int 394 sdhci_pci_suspend(device_t dev) 395 { 396 struct sdhci_pci_softc *sc = device_get_softc(dev); 397 int i, err; 398 399 err = bus_generic_suspend(dev); 400 if (err) 401 return (err); 402 for (i = 0; i < sc->num_slots; i++) 403 sdhci_generic_suspend(&sc->slots[i]); 404 return (0); 405 } 406 407 static int 408 sdhci_pci_resume(device_t dev) 409 { 410 struct sdhci_pci_softc *sc = device_get_softc(dev); 411 int i; 412 413 for (i = 0; i < sc->num_slots; i++) 414 sdhci_generic_resume(&sc->slots[i]); 415 return (bus_generic_resume(dev)); 416 } 417 418 static void 419 sdhci_pci_intr(void *arg) 420 { 421 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 422 int i; 423 424 for (i = 0; i < sc->num_slots; i++) { 425 struct sdhci_slot *slot = &sc->slots[i]; 426 sdhci_generic_intr(slot); 427 } 428 } 429 430 static device_method_t sdhci_methods[] = { 431 /* device_if */ 432 DEVMETHOD(device_probe, sdhci_pci_probe), 433 DEVMETHOD(device_attach, sdhci_pci_attach), 434 DEVMETHOD(device_detach, sdhci_pci_detach), 435 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 436 DEVMETHOD(device_suspend, sdhci_pci_suspend), 437 DEVMETHOD(device_resume, sdhci_pci_resume), 438 439 /* Bus interface */ 440 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 441 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 442 443 /* mmcbr_if */ 444 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 445 DEVMETHOD(mmcbr_request, sdhci_generic_request), 446 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 447 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 448 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 449 450 /* SDHCI registers accessors */ 451 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 452 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 453 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 454 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 455 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 456 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 457 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 458 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 459 460 DEVMETHOD_END 461 }; 462 463 static driver_t sdhci_pci_driver = { 464 "sdhci_pci", 465 sdhci_methods, 466 sizeof(struct sdhci_pci_softc), 467 }; 468 static devclass_t sdhci_pci_devclass; 469 470 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 471 NULL); 472 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 473