1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 - 2021 Alstom Group. 5 * Copyright (c) 2020 - 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */ 30 31 #include <sys/param.h> 32 #include <sys/endian.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/rman.h> 36 #include <sys/sysctl.h> 37 #include <sys/taskqueue.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 42 #include <dev/clk/clk.h> 43 #include <dev/syscon/syscon.h> 44 #include <dev/mmc/bridge.h> 45 #include <dev/mmc/mmcbrvar.h> 46 #include <dev/mmc/mmc_fdt_helpers.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 #include <dev/sdhci/sdhci.h> 50 #include <dev/sdhci/sdhci_fdt_gpio.h> 51 52 #include "mmcbr_if.h" 53 #include "sdhci_if.h" 54 #include "syscon_if.h" 55 56 #define RD4 (sc->read) 57 #define WR4 (sc->write) 58 59 #define SDHCI_FSL_PRES_STATE 0x24 60 #define SDHCI_FSL_PRES_SDSTB (1 << 3) 61 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07 62 63 #define SDHCI_FSL_PROT_CTRL 0x28 64 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1) 65 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1) 66 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1) 67 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1) 68 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4) 69 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4) 70 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4) 71 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8) 72 #define SDHCI_FSL_PROT_CTRL_VOLT_SEL (1 << 10) 73 74 #define SDHCI_FSL_IRQSTAT 0x30 75 #define SDHCI_FSL_IRQSTAT_BRR (1 << 5) 76 #define SDHCI_FSL_IRQSTAT_CINTSEN (1 << 8) 77 #define SDHCI_FSL_IRQSTAT_RTE (1 << 12) 78 #define SDHCI_FSL_IRQSTAT_TNE (1 << 26) 79 80 #define SDHCI_FSL_SYS_CTRL 0x2c 81 #define SDHCI_FSL_CLK_IPGEN (1 << 0) 82 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3) 83 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0 84 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4 85 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00 86 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8 87 88 #define SDHCI_FSL_WTMK_LVL 0x44 89 #define SDHCI_FSL_WTMK_RD_512B (0 << 0) 90 #define SDHCI_FSL_WTMK_WR_512B (0 << 15) 91 92 #define SDHCI_FSL_AUTOCERR 0x3C 93 #define SDHCI_FSL_AUTOCERR_UHMS_HS200 (3 << 16) 94 #define SDHCI_FSL_AUTOCERR_UHMS (7 << 16) 95 #define SDHCI_FSL_AUTOCERR_EXTN (1 << 22) 96 #define SDHCI_FSL_AUTOCERR_SMPCLKSEL (1 << 23) 97 #define SDHCI_FSL_AUTOCERR_UHMS_SHIFT 16 98 99 #define SDHCI_FSL_HOST_VERSION 0xfc 100 #define SDHCI_FSL_VENDOR_V23 0x13 101 102 #define SDHCI_FSL_CAPABILITIES2 0x114 103 104 #define SDHCI_FSL_TBCTL 0x120 105 106 #define SDHCI_FSL_TBSTAT 0x124 107 #define SDHCI_FSL_TBCTL_TBEN (1 << 2) 108 #define SDHCI_FSL_TBCTL_HS400_EN (1 << 4) 109 #define SDHCI_FSL_TBCTL_SAMP_CMD_DQS (1 << 5) 110 #define SDHCI_FSL_TBCTL_HS400_WND_ADJ (1 << 6) 111 #define SDHCI_FSL_TBCTL_TB_MODE_MASK 0x3 112 #define SDHCI_FSL_TBCTL_MODE_1 0 113 #define SDHCI_FSL_TBCTL_MODE_2 1 114 #define SDHCI_FSL_TBCTL_MODE_3 2 115 #define SDHCI_FSL_TBCTL_MODE_SW 3 116 117 #define SDHCI_FSL_TBPTR 0x128 118 #define SDHCI_FSL_TBPTR_WND_START_SHIFT 8 119 #define SDHCI_FSL_TBPTR_WND_MASK 0x7F 120 121 #define SDHCI_FSL_SDCLKCTL 0x144 122 #define SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL (1 << 15) 123 #define SDHCI_FSL_SDCLKCTL_LPBK_CLK_SEL (1 << 31) 124 125 #define SDHCI_FSL_SDTIMINGCTL 0x148 126 #define SDHCI_FSL_SDTIMINGCTL_FLW_CTL (1 << 15) 127 128 #define SDHCI_FSL_DLLCFG0 0x160 129 #define SDHCI_FSL_DLLCFG0_FREQ_SEL (1 << 27) 130 #define SDHCI_FSL_DLLCFG0_RESET (1 << 30) 131 #define SDHCI_FSL_DLLCFG0_EN (1 << 31) 132 133 #define SDHCI_FSL_DLLCFG1 0x164 134 #define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31) 135 136 #define SDHCI_FSL_DLLSTAT0 0x170 137 #define SDHCI_FSL_DLLSTAT0_SLV_STS (1 << 27) 138 139 #define SDHCI_FSL_ESDHC_CTRL 0x40c 140 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) 141 #define SDHCI_FSL_ESDHC_CTRL_FAF (1 << 18) 142 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) 143 144 #define SCFG_SDHCIOVSELCR 0x408 145 #define SCFG_SDHCIOVSELCR_TGLEN (1 << 0) 146 #define SCFG_SDHCIOVSELCR_VS (1 << 31) 147 #define SCFG_SDHCIOVSELCR_VSELVAL_MASK (3 << 1) 148 #define SCFG_SDHCIOVSELCR_VSELVAL_1_8 0x0 149 #define SCFG_SDHCIOVSELCR_VSELVAL_3_3 0x2 150 151 #define SDHCI_FSL_CAN_VDD_MASK \ 152 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330) 153 154 /* Some platforms do not detect pulse width correctly. */ 155 #define SDHCI_FSL_UNRELIABLE_PULSE_DET (1 << 0) 156 /* On some platforms switching voltage to 1.8V is not supported */ 157 #define SDHCI_FSL_UNSUPP_1_8V (1 << 1) 158 /* Hardware tuning can fail, fallback to SW tuning in that case. */ 159 #define SDHCI_FSL_TUNING_ERRATUM_TYPE1 (1 << 2) 160 /* 161 * Pointer window might not be set properly on some platforms. 162 * Check window and perform SW tuning. 163 */ 164 #define SDHCI_FSL_TUNING_ERRATUM_TYPE2 (1 << 3) 165 /* 166 * In HS400 mode only 4, 8, 12 clock dividers can be used. 167 * Use the smallest value, bigger than requested in that case. 168 */ 169 #define SDHCI_FSL_HS400_LIMITED_CLK_DIV (1 << 4) 170 171 /* 172 * Some SoCs don't have a fixed regulator. Switching voltage 173 * requires special routine including syscon registers. 174 */ 175 #define SDHCI_FSL_MISSING_VCCQ_REG (1 << 5) 176 177 /* 178 * HS400 tuning is done in HS200 mode, but it has to be done using 179 * the target frequency. In order to apply the errata above we need to 180 * know the target mode during tuning procedure. Use this flag for just that. 181 */ 182 #define SDHCI_FSL_HS400_FLAG (1 << 0) 183 184 #define SDHCI_FSL_MAX_RETRIES 20000 /* DELAY(10) * this = 200ms */ 185 186 struct sdhci_fsl_fdt_softc { 187 device_t dev; 188 const struct sdhci_fsl_fdt_soc_data *soc_data; 189 struct resource *mem_res; 190 struct resource *irq_res; 191 void *irq_cookie; 192 uint32_t baseclk_hz; 193 uint32_t maxclk_hz; 194 struct sdhci_fdt_gpio *gpio; 195 struct sdhci_slot slot; 196 bool slot_init_done; 197 uint32_t cmd_and_mode; 198 uint16_t sdclk_bits; 199 struct mmc_helper fdt_helper; 200 uint32_t div_ratio; 201 uint8_t vendor_ver; 202 uint32_t flags; 203 204 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t); 205 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t); 206 }; 207 208 struct sdhci_fsl_fdt_soc_data { 209 int quirks; 210 int baseclk_div; 211 uint8_t errata; 212 char *syscon_compat; 213 }; 214 215 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1012a_soc_data = { 216 .quirks = 0, 217 .baseclk_div = 1, 218 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2, 219 .syscon_compat = "fsl,ls1012a-scfg", 220 }; 221 222 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = { 223 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | 224 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 225 .baseclk_div = 2, 226 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 227 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 228 }; 229 230 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { 231 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP, 232 .baseclk_div = 2, 233 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2, 234 .syscon_compat = "fsl,ls1046a-scfg", 235 }; 236 237 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_lx2160a_soc_data = { 238 .quirks = 0, 239 .baseclk_div = 2, 240 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 241 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 242 }; 243 244 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = { 245 .quirks = 0, 246 .baseclk_div = 1, 247 }; 248 249 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = { 250 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data}, 251 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data}, 252 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data}, 253 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data}, 254 {NULL, 0} 255 }; 256 257 static uint32_t 258 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 259 { 260 261 return (be32toh(bus_read_4(sc->mem_res, off))); 262 } 263 264 static void 265 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 266 { 267 268 bus_write_4(sc->mem_res, off, htobe32(val)); 269 } 270 271 static uint32_t 272 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 273 { 274 275 return (bus_read_4(sc->mem_res, off)); 276 } 277 278 static void 279 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 280 { 281 282 bus_write_4(sc->mem_res, off, val); 283 } 284 285 286 static uint16_t 287 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc) 288 { 289 uint16_t val; 290 291 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN; 292 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) 293 val |= SDHCI_CLOCK_INT_STABLE; 294 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) 295 val |= SDHCI_CLOCK_CARD_EN; 296 297 return (val); 298 } 299 300 /* 301 * Calculate clock prescaler and divisor values based on the following formula: 302 * `frequency = base clock / (prescaler * divisor)`. 303 */ 304 #define SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div) \ 305 do { \ 306 (pre) = (sc)->vendor_ver < SDHCI_FSL_VENDOR_V23 ? 2 : 1;\ 307 while ((freq) < (base) / ((pre) * 16) && (pre) < 256) \ 308 (pre) <<= 1; \ 309 /* div/pre can't both be set to 1, according to PM. */ \ 310 (div) = ((pre) == 1 ? 2 : 1); \ 311 while ((freq) < (base) / ((pre) * (div)) && (div) < 16) \ 312 ++(div); \ 313 } while (0) 314 315 static void 316 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, struct sdhci_slot *slot, 317 uint16_t val) 318 { 319 uint32_t prescale, div, val32, div_ratio; 320 321 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK; 322 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 323 324 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 325 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 326 return; 327 } 328 329 /* 330 * Ignore dividers provided by core in `sdhci_set_clock` and calculate 331 * them anew with higher accuracy. 332 */ 333 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div); 334 335 div_ratio = prescale * div; 336 337 /* 338 * According to limited clock division erratum, clock dividers in hs400 339 * can be only 4, 8 or 12 340 */ 341 if ((sc->soc_data->errata & SDHCI_FSL_HS400_LIMITED_CLK_DIV) && 342 (sc->slot.host.ios.timing == bus_timing_mmc_hs400 || 343 (sc->flags & SDHCI_FSL_HS400_FLAG))) { 344 if (div_ratio <= 4) { 345 prescale = 4; 346 div = 1; 347 } else if (div_ratio <= 8) { 348 prescale = 4; 349 div = 2; 350 } else if (div_ratio <= 12) { 351 prescale = 4; 352 div = 3; 353 } else { 354 device_printf(sc->dev, "Unsupported clock divider.\n"); 355 } 356 } 357 358 sc->div_ratio = prescale * div; 359 if (bootverbose) 360 device_printf(sc->dev, 361 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", 362 slot->clock, sc->baseclk_hz / (prescale * div), 363 sc->baseclk_hz, prescale, div); 364 365 prescale >>= 1; 366 div -= 1; 367 368 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK); 369 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT; 370 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT; 371 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN; 372 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 373 } 374 375 static uint8_t 376 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 377 { 378 struct sdhci_fsl_fdt_softc *sc; 379 uint32_t wrk32, val32; 380 381 sc = device_get_softc(dev); 382 383 switch (off) { 384 case SDHCI_HOST_CONTROL: 385 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 386 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 387 SDHCI_CTRL_FORCE_CARD); 388 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT) 389 val32 |= SDHCI_CTRL_4BITBUS; 390 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT) 391 val32 |= SDHCI_CTRL_8BITBUS; 392 return (val32); 393 case SDHCI_POWER_CONTROL: 394 return (SDHCI_POWER_ON | SDHCI_POWER_300); 395 default: 396 break; 397 } 398 399 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); 400 } 401 402 static uint16_t 403 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 404 { 405 struct sdhci_fsl_fdt_softc *sc; 406 uint32_t val32; 407 408 sc = device_get_softc(dev); 409 410 switch (off) { 411 case SDHCI_CLOCK_CONTROL: 412 return (sdhci_fsl_fdt_get_clock(sc)); 413 case SDHCI_HOST_VERSION: 414 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); 415 case SDHCI_TRANSFER_MODE: 416 return (sc->cmd_and_mode & UINT16_MAX); 417 case SDHCI_COMMAND_FLAGS: 418 return (sc->cmd_and_mode >> 16); 419 case SDHCI_SLOT_INT_STATUS: 420 /* 421 * eSDHC hardware manages only a single slot. 422 * Synthesize a slot interrupt status register for slot 1 below. 423 */ 424 val32 = RD4(sc, SDHCI_INT_STATUS); 425 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 426 return (!!val32); 427 default: 428 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); 429 } 430 } 431 432 static uint32_t 433 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 434 { 435 struct sdhci_fsl_fdt_softc *sc; 436 uint32_t wrk32, val32; 437 438 sc = device_get_softc(dev); 439 440 if (off == SDHCI_BUFFER) 441 return (bus_read_4(sc->mem_res, off)); 442 if (off == SDHCI_CAPABILITIES2) 443 off = SDHCI_FSL_CAPABILITIES2; 444 445 val32 = RD4(sc, off); 446 447 if (off == SDHCI_PRESENT_STATE) { 448 wrk32 = val32; 449 val32 &= SDHCI_FSL_PRES_COMPAT_MASK; 450 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 451 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD; 452 } 453 454 return (val32); 455 } 456 457 static void 458 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 459 uint32_t *data, bus_size_t count) 460 { 461 struct sdhci_fsl_fdt_softc *sc; 462 463 sc = device_get_softc(dev); 464 bus_read_multi_4(sc->mem_res, off, data, count); 465 } 466 467 static void 468 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 469 uint8_t val) 470 { 471 struct sdhci_fsl_fdt_softc *sc; 472 uint32_t val32; 473 474 sc = device_get_softc(dev); 475 476 switch (off) { 477 case SDHCI_HOST_CONTROL: 478 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 479 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK; 480 val32 |= (val & SDHCI_CTRL_LED); 481 482 if (val & SDHCI_CTRL_8BITBUS) 483 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT; 484 else 485 /* Bus width is 1-bit when this flag is not set. */ 486 val32 |= (val & SDHCI_CTRL_4BITBUS); 487 /* Enable SDMA by masking out this field. */ 488 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK; 489 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); 490 val32 |= (val & (SDHCI_CTRL_CARD_DET | 491 SDHCI_CTRL_FORCE_CARD)); 492 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 493 return; 494 case SDHCI_POWER_CONTROL: 495 return; 496 default: 497 val32 = RD4(sc, off & ~3); 498 val32 &= ~(UINT8_MAX << (off & 3) * 8); 499 val32 |= (val << (off & 3) * 8); 500 WR4(sc, off & ~3, val32); 501 return; 502 } 503 } 504 505 static void 506 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 507 uint16_t val) 508 { 509 struct sdhci_fsl_fdt_softc *sc; 510 uint32_t val32; 511 512 sc = device_get_softc(dev); 513 514 switch (off) { 515 case SDHCI_CLOCK_CONTROL: 516 fsl_sdhc_fdt_set_clock(sc, slot, val); 517 return; 518 /* 519 * eSDHC hardware combines command and mode into a single 520 * register. Cache it here, so that command isn't written 521 * until after mode. 522 */ 523 case SDHCI_TRANSFER_MODE: 524 sc->cmd_and_mode = val; 525 return; 526 case SDHCI_COMMAND_FLAGS: 527 sc->cmd_and_mode = 528 (sc->cmd_and_mode & UINT16_MAX) | (val << 16); 529 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 530 sc->cmd_and_mode = 0; 531 return; 532 case SDHCI_HOST_CONTROL2: 533 /* 534 * Switching to HS400 requires a special procedure, 535 * which is done in sdhci_fsl_fdt_set_uhs_timing. 536 */ 537 if ((val & SDHCI_CTRL2_UHS_MASK) == SDHCI_CTRL2_MMC_HS400) 538 val &= ~SDHCI_CTRL2_MMC_HS400; 539 default: 540 val32 = RD4(sc, off & ~3); 541 val32 &= ~(UINT16_MAX << (off & 3) * 8); 542 val32 |= ((val & UINT16_MAX) << (off & 3) * 8); 543 WR4(sc, off & ~3, val32); 544 return; 545 } 546 } 547 548 static void 549 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 550 uint32_t val) 551 { 552 struct sdhci_fsl_fdt_softc *sc; 553 554 sc = device_get_softc(dev); 555 556 switch (off) { 557 case SDHCI_BUFFER: 558 bus_write_4(sc->mem_res, off, val); 559 return; 560 /* 561 * eSDHC hardware lacks support for the SDMA buffer boundary 562 * feature and instead generates SDHCI_INT_DMA_END interrupts 563 * after each completed DMA data transfer. 564 * Since this duplicates the SDHCI_INT_DATA_END functionality, 565 * mask out the unneeded SDHCI_INT_DMA_END interrupt. 566 */ 567 case SDHCI_INT_ENABLE: 568 case SDHCI_SIGNAL_ENABLE: 569 val &= ~SDHCI_INT_DMA_END; 570 /* FALLTHROUGH. */ 571 default: 572 WR4(sc, off, val); 573 return; 574 } 575 } 576 577 static void 578 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 579 bus_size_t off, uint32_t *data, bus_size_t count) 580 { 581 struct sdhci_fsl_fdt_softc *sc; 582 583 sc = device_get_softc(dev); 584 bus_write_multi_4(sc->mem_res, off, data, count); 585 } 586 587 static void 588 sdhci_fsl_fdt_irq(void *arg) 589 { 590 struct sdhci_fsl_fdt_softc *sc; 591 592 sc = arg; 593 sdhci_generic_intr(&sc->slot); 594 return; 595 } 596 597 static int 598 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev) 599 { 600 int err; 601 struct sdhci_fsl_fdt_softc *sc; 602 struct mmc_ios *ios; 603 struct sdhci_slot *slot; 604 605 err = sdhci_generic_update_ios(brdev, reqdev); 606 if (err != 0) 607 return (err); 608 609 sc = device_get_softc(brdev); 610 slot = device_get_ivars(reqdev); 611 ios = &slot->host.ios; 612 613 switch (ios->power_mode) { 614 case power_on: 615 break; 616 case power_off: 617 if (bootverbose) 618 device_printf(sc->dev, "Powering down sd/mmc\n"); 619 620 if (sc->fdt_helper.vmmc_supply) 621 regulator_disable(sc->fdt_helper.vmmc_supply); 622 if (sc->fdt_helper.vqmmc_supply) 623 regulator_disable(sc->fdt_helper.vqmmc_supply); 624 break; 625 case power_up: 626 if (bootverbose) 627 device_printf(sc->dev, "Powering up sd/mmc\n"); 628 629 if (sc->fdt_helper.vmmc_supply) 630 regulator_enable(sc->fdt_helper.vmmc_supply); 631 if (sc->fdt_helper.vqmmc_supply) 632 regulator_enable(sc->fdt_helper.vqmmc_supply); 633 break; 634 }; 635 636 return (0); 637 } 638 639 static int 640 sdhci_fsl_fdt_switch_syscon_voltage(device_t dev, 641 struct sdhci_fsl_fdt_softc *sc, enum mmc_vccq vccq) 642 { 643 struct syscon *syscon; 644 phandle_t syscon_node; 645 uint32_t reg; 646 647 if (sc->soc_data->syscon_compat == NULL) { 648 device_printf(dev, "Empty syscon compat string.\n"); 649 return (ENXIO); 650 } 651 652 syscon_node = ofw_bus_find_compatible(OF_finddevice("/"), 653 sc->soc_data->syscon_compat); 654 655 if (syscon_get_by_ofw_node(dev, syscon_node, &syscon) != 0) { 656 device_printf(dev, "Could not find syscon node.\n"); 657 return (ENXIO); 658 } 659 660 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 661 reg &= ~SCFG_SDHCIOVSELCR_VSELVAL_MASK; 662 reg |= SCFG_SDHCIOVSELCR_TGLEN; 663 664 switch (vccq) { 665 case vccq_180: 666 reg |= SCFG_SDHCIOVSELCR_VSELVAL_1_8; 667 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 668 669 DELAY(5000); 670 671 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 672 reg |= SCFG_SDHCIOVSELCR_VS; 673 break; 674 case vccq_330: 675 reg |= SCFG_SDHCIOVSELCR_VSELVAL_3_3; 676 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 677 678 DELAY(5000); 679 680 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 681 reg &= ~SCFG_SDHCIOVSELCR_VS; 682 break; 683 default: 684 device_printf(dev, "Unsupported voltage requested.\n"); 685 return (ENXIO); 686 } 687 688 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 689 690 return (0); 691 } 692 693 static int 694 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev) 695 { 696 struct sdhci_fsl_fdt_softc *sc; 697 struct sdhci_slot *slot; 698 regulator_t vqmmc_supply; 699 uint32_t val_old, val; 700 int uvolt, err = 0; 701 702 sc = device_get_softc(brdev); 703 slot = device_get_ivars(reqdev); 704 705 val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL); 706 707 switch (slot->host.ios.vccq) { 708 case vccq_180: 709 if (sc->soc_data->errata & SDHCI_FSL_UNSUPP_1_8V) 710 return (EOPNOTSUPP); 711 712 val |= SDHCI_FSL_PROT_CTRL_VOLT_SEL; 713 uvolt = 1800000; 714 break; 715 case vccq_330: 716 val &= ~SDHCI_FSL_PROT_CTRL_VOLT_SEL; 717 uvolt = 3300000; 718 break; 719 default: 720 return (EOPNOTSUPP); 721 } 722 723 WR4(sc, SDHCI_FSL_PROT_CTRL, val); 724 725 if (sc->soc_data->errata & SDHCI_FSL_MISSING_VCCQ_REG) { 726 err = sdhci_fsl_fdt_switch_syscon_voltage(brdev, sc, 727 slot->host.ios.vccq); 728 if (err != 0) 729 goto vccq_fail; 730 } 731 732 vqmmc_supply = sc->fdt_helper.vqmmc_supply; 733 /* 734 * Even though we expect to find a fixed regulator in this controller 735 * family, let's play safe. 736 */ 737 if (vqmmc_supply != NULL) { 738 err = regulator_set_voltage(vqmmc_supply, uvolt, uvolt); 739 if (err != 0) 740 goto vccq_fail; 741 } 742 743 return (0); 744 745 vccq_fail: 746 device_printf(sc->dev, "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt); 747 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old); 748 749 return (err); 750 } 751 752 static int 753 sdhci_fsl_fdt_get_ro(device_t bus, device_t child) 754 { 755 struct sdhci_fsl_fdt_softc *sc; 756 757 sc = device_get_softc(bus); 758 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 759 } 760 761 static bool 762 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot) 763 { 764 struct sdhci_fsl_fdt_softc *sc; 765 766 sc = device_get_softc(dev); 767 return (sdhci_fdt_gpio_get_present(sc->gpio)); 768 } 769 770 static uint32_t 771 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len) 772 { 773 uint32_t vdd_min, vdd_max; 774 uint32_t vdd_mask = 0; 775 int i; 776 777 /* Ranges are organized as pairs of values. */ 778 if ((len % 2) != 0) { 779 device_printf(dev, "Invalid voltage range\n"); 780 return (0); 781 } 782 len = len / 2; 783 784 for (i = 0; i < len; i++) { 785 vdd_min = vdd_ranges[2 * i]; 786 vdd_max = vdd_ranges[2 * i + 1]; 787 788 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 || 789 vdd_max < 1650 || vdd_max > 3600) { 790 device_printf(dev, "Voltage range %d - %d is out of bounds\n", 791 vdd_min, vdd_max); 792 return (0); 793 } 794 795 if (vdd_min <= 1800 && vdd_max >= 1800) 796 vdd_mask |= SDHCI_CAN_VDD_180; 797 if (vdd_min <= 3000 && vdd_max >= 3000) 798 vdd_mask |= SDHCI_CAN_VDD_300; 799 if (vdd_min <= 3300 && vdd_max >= 3300) 800 vdd_mask |= SDHCI_CAN_VDD_330; 801 } 802 803 return (vdd_mask); 804 } 805 806 static void 807 sdhci_fsl_fdt_of_parse(device_t dev) 808 { 809 struct sdhci_fsl_fdt_softc *sc; 810 phandle_t node; 811 pcell_t *voltage_ranges; 812 uint32_t vdd_mask = 0; 813 ssize_t num_ranges; 814 815 sc = device_get_softc(dev); 816 node = ofw_bus_get_node(dev); 817 818 /* Call mmc_fdt_parse in order to get mmc related properties. */ 819 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host); 820 821 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot, 822 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND); 823 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot, 824 SDHCI_CAPABILITIES2); 825 826 /* Parse the "voltage-ranges" dts property. */ 827 num_ranges = OF_getencprop_alloc(node, "voltage-ranges", 828 (void **) &voltage_ranges); 829 if (num_ranges <= 0) 830 return; 831 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges, 832 num_ranges / sizeof(uint32_t)); 833 OF_prop_free(voltage_ranges); 834 835 /* Overwrite voltage caps only if we got something from dts. */ 836 if (vdd_mask != 0 && 837 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) { 838 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK); 839 sc->slot.caps |= vdd_mask; 840 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS; 841 } 842 } 843 844 static int 845 sdhci_fsl_poll_register(struct sdhci_fsl_fdt_softc *sc, 846 uint32_t reg, uint32_t mask, int value) 847 { 848 int retries; 849 850 retries = SDHCI_FSL_MAX_RETRIES; 851 852 while ((RD4(sc, reg) & mask) != value) { 853 if (!retries--) 854 return (ENXIO); 855 856 DELAY(10); 857 } 858 859 return (0); 860 } 861 862 static int 863 sdhci_fsl_fdt_attach(device_t dev) 864 { 865 struct sdhci_fsl_fdt_softc *sc; 866 struct mmc_host *host; 867 uint32_t val, buf_order; 868 uintptr_t ocd_data; 869 uint64_t clk_hz; 870 phandle_t node; 871 int rid, ret; 872 clk_t clk; 873 874 node = ofw_bus_get_node(dev); 875 sc = device_get_softc(dev); 876 ocd_data = ofw_bus_search_compatible(dev, 877 sdhci_fsl_fdt_compat_data)->ocd_data; 878 sc->dev = dev; 879 sc->flags = 0; 880 host = &sc->slot.host; 881 rid = 0; 882 883 /* 884 * LX2160A needs its own soc_data in order to apply SoC 885 * specific quriks. Since the controller is identified 886 * only with a generic compatible string we need to do this dance here. 887 */ 888 if (ofw_bus_node_is_compatible(OF_finddevice("/"), "fsl,lx2160a")) 889 sc->soc_data = &sdhci_fsl_fdt_lx2160a_soc_data; 890 else 891 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data; 892 893 sc->slot.quirks = sc->soc_data->quirks; 894 895 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 896 RF_ACTIVE); 897 if (sc->mem_res == NULL) { 898 device_printf(dev, 899 "Could not allocate resources for controller\n"); 900 return (ENOMEM); 901 } 902 903 rid = 0; 904 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 905 RF_ACTIVE); 906 if (sc->irq_res == NULL) { 907 device_printf(dev, 908 "Could not allocate irq resources for controller\n"); 909 ret = ENOMEM; 910 goto err_free_mem; 911 } 912 913 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 914 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie); 915 if (ret != 0) { 916 device_printf(dev, "Could not setup IRQ handler\n"); 917 goto err_free_irq_res; 918 } 919 920 ret = clk_get_by_ofw_index(dev, node, 0, &clk); 921 if (ret != 0) { 922 device_printf(dev, "Parent clock not found\n"); 923 goto err_free_irq; 924 } 925 926 ret = clk_get_freq(clk, &clk_hz); 927 if (ret != 0) { 928 device_printf(dev, 929 "Could not get parent clock frequency\n"); 930 goto err_free_irq; 931 } 932 933 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div; 934 935 /* Figure out eSDHC block endianness before we touch any HW regs. */ 936 if (OF_hasprop(node, "little-endian")) { 937 sc->read = read_le; 938 sc->write = write_le; 939 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE; 940 } else { 941 sc->read = read_be; 942 sc->write = write_be; 943 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP; 944 } 945 946 sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) & 947 SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; 948 949 sdhci_fsl_fdt_of_parse(dev); 950 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz; 951 952 /* 953 * Setting this register affects byte order in SDHCI_BUFFER only. 954 * If the eSDHC block is connected over a big-endian bus, the data 955 * read from/written to the buffer will be already byte swapped. 956 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert 957 * the byte order again, resulting in a native byte order. 958 * The read/write callbacks accommodate for this behavior. 959 */ 960 val = RD4(sc, SDHCI_FSL_PROT_CTRL); 961 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK; 962 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 963 964 /* 965 * Gate the SD clock and set its source to 966 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set 967 * to match this. 968 */ 969 val = RD4(sc, SDHCI_CLOCK_CONTROL); 970 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); 971 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 972 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); 973 sc->slot.max_clk = sc->maxclk_hz; 974 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 975 976 /* 977 * Set the buffer watermark level to 128 words (512 bytes) for both 978 * read and write. The hardware has a restriction that when the read or 979 * write ready status is asserted, that means you can read exactly the 980 * number of words set in the watermark register before you have to 981 * re-check the status and potentially wait for more data. The main 982 * sdhci driver provides no hook for doing status checking on less than 983 * a full block boundary, so we set the watermark level to be a full 984 * block. Reads and writes where the block size is less than the 985 * watermark size will work correctly too, no need to change the 986 * watermark for different size blocks. However, 128 is the maximum 987 * allowed for the watermark, so PIO is limitted to 512 byte blocks. 988 */ 989 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | 990 SDHCI_FSL_WTMK_RD_512B); 991 992 ret = sdhci_init_slot(dev, &sc->slot, 0); 993 if (ret != 0) 994 goto err_free_gpio; 995 sc->slot_init_done = true; 996 sdhci_start_slot(&sc->slot); 997 998 return (bus_generic_attach(dev)); 999 1000 err_free_gpio: 1001 sdhci_fdt_gpio_teardown(sc->gpio); 1002 err_free_irq: 1003 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 1004 err_free_irq_res: 1005 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 1006 err_free_mem: 1007 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 1008 return (ret); 1009 } 1010 1011 static int 1012 sdhci_fsl_fdt_detach(device_t dev) 1013 { 1014 struct sdhci_fsl_fdt_softc *sc; 1015 1016 sc = device_get_softc(dev); 1017 if (sc->slot_init_done) 1018 sdhci_cleanup_slot(&sc->slot); 1019 if (sc->gpio != NULL) 1020 sdhci_fdt_gpio_teardown(sc->gpio); 1021 if (sc->irq_cookie != NULL) 1022 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 1023 if (sc->irq_res != NULL) 1024 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 1025 if (sc->mem_res != NULL) 1026 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 1027 return (0); 1028 } 1029 1030 static int 1031 sdhci_fsl_fdt_probe(device_t dev) 1032 { 1033 1034 if (!ofw_bus_status_okay(dev)) 1035 return (ENXIO); 1036 1037 if (!ofw_bus_search_compatible(dev, 1038 sdhci_fsl_fdt_compat_data)->ocd_data) 1039 return (ENXIO); 1040 1041 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller"); 1042 return (BUS_PROBE_DEFAULT); 1043 } 1044 1045 static int 1046 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which, 1047 uintptr_t *result) 1048 { 1049 struct sdhci_slot *slot = device_get_ivars(child); 1050 1051 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) { 1052 /* 1053 * In the absence of SDMA buffer boundary functionality, 1054 * limit the maximum data length per read/write command 1055 * to bounce buffer size. 1056 */ 1057 *result = howmany(slot->sdma_bbufsz, 512); 1058 return (0); 1059 } 1060 return (sdhci_generic_read_ivar(bus, child, which, result)); 1061 } 1062 1063 static int 1064 sdhci_fsl_fdt_write_ivar(device_t bus, device_t child, int which, 1065 uintptr_t value) 1066 { 1067 struct sdhci_fsl_fdt_softc *sc; 1068 struct sdhci_slot *slot = device_get_ivars(child); 1069 uint32_t prescale, div; 1070 1071 /* Don't depend on clock resolution limits from sdhci core. */ 1072 if (which == MMCBR_IVAR_CLOCK) { 1073 if (value == 0) { 1074 slot->host.ios.clock = 0; 1075 return (0); 1076 } 1077 1078 sc = device_get_softc(bus); 1079 1080 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div); 1081 slot->host.ios.clock = sc->baseclk_hz / (prescale * div); 1082 1083 return (0); 1084 } 1085 1086 return (sdhci_generic_write_ivar(bus, child, which, value)); 1087 } 1088 1089 static void 1090 sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask) 1091 { 1092 struct sdhci_fsl_fdt_softc *sc; 1093 uint32_t val; 1094 1095 sdhci_generic_reset(dev, slot, mask); 1096 1097 if (!(mask & SDHCI_RESET_ALL)) 1098 return; 1099 1100 sc = device_get_softc(dev); 1101 1102 /* Some registers have to be cleared by hand. */ 1103 if (slot->version >= SDHCI_SPEC_300) { 1104 val = RD4(sc, SDHCI_FSL_TBCTL); 1105 val &= ~SDHCI_FSL_TBCTL_TBEN; 1106 WR4(sc, SDHCI_FSL_TBCTL, val); 1107 } 1108 1109 /* 1110 * Pulse width detection is not reliable on some boards. Perform 1111 * workaround by clearing register's bit according to errata. 1112 */ 1113 if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) { 1114 val = RD4(sc, SDHCI_FSL_DLLCFG1); 1115 val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH; 1116 WR4(sc, SDHCI_FSL_DLLCFG1, val); 1117 } 1118 1119 sc->flags = 0; 1120 } 1121 1122 static void 1123 sdhci_fsl_switch_tuning_block(device_t dev, bool enable) 1124 { 1125 struct sdhci_fsl_fdt_softc *sc; 1126 uint32_t reg; 1127 1128 sc = device_get_softc(dev); 1129 1130 reg = RD4(sc, SDHCI_FSL_TBCTL); 1131 1132 if (enable) 1133 reg |= SDHCI_FSL_TBCTL_TBEN; 1134 else 1135 reg &= ~SDHCI_FSL_TBCTL_TBEN; 1136 1137 WR4(sc, SDHCI_FSL_TBCTL, reg); 1138 } 1139 1140 static int 1141 sdhci_fsl_sw_tuning(struct sdhci_fsl_fdt_softc *sc, device_t bus, 1142 device_t child, bool hs400, uint32_t wnd_start, uint32_t wnd_end) 1143 { 1144 uint32_t reg; 1145 int error; 1146 1147 if (sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE1 || 1148 abs(wnd_start - wnd_end) <= (4 * sc->div_ratio + 2)) { 1149 wnd_start = 5 * sc->div_ratio; 1150 wnd_end = 3 * sc->div_ratio; 1151 } else { 1152 wnd_start = 8 * sc->div_ratio; 1153 wnd_end = 4 * sc->div_ratio; 1154 } 1155 1156 reg = RD4(sc, SDHCI_FSL_TBPTR); 1157 reg &= ~SDHCI_FSL_TBPTR_WND_MASK; 1158 reg &= ~(SDHCI_FSL_TBPTR_WND_MASK << SDHCI_FSL_TBPTR_WND_START_SHIFT); 1159 reg |= wnd_start << SDHCI_FSL_TBPTR_WND_START_SHIFT; 1160 reg |= wnd_end; 1161 WR4(sc, SDHCI_FSL_TBPTR, reg); 1162 1163 /* 1164 * Normally those are supposed to be set in sdhci_execute_tuning. 1165 * However in our case we need a small delay between setting the two. 1166 */ 1167 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1168 reg |= SDHCI_FSL_AUTOCERR_EXTN; 1169 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1170 DELAY(10); 1171 reg |= SDHCI_FSL_AUTOCERR_SMPCLKSEL; 1172 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1173 1174 reg = RD4(sc, SDHCI_FSL_TBCTL); 1175 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1176 reg |= SDHCI_FSL_TBCTL_MODE_SW; 1177 WR4(sc, SDHCI_FSL_TBCTL, reg); 1178 1179 error = sdhci_generic_tune(bus, child, hs400); 1180 if (error != 0) { 1181 device_printf(bus, 1182 "Failed to execute generic tune while performing software tuning.\n"); 1183 } 1184 1185 return (error); 1186 } 1187 1188 static int 1189 sdhci_fsl_fdt_tune(device_t bus, device_t child, bool hs400) 1190 { 1191 struct sdhci_fsl_fdt_softc *sc; 1192 uint32_t wnd_start, wnd_end; 1193 uint32_t clk_divider, reg; 1194 struct sdhci_slot *slot; 1195 int error; 1196 1197 sc = device_get_softc(bus); 1198 slot = device_get_ivars(child); 1199 1200 if (sc->slot.host.ios.timing == bus_timing_uhs_sdr50 && 1201 !(slot->opt & SDHCI_SDR50_NEEDS_TUNING)) 1202 return (0); 1203 1204 /* 1205 * For tuning mode SD clock divider must be within 3 to 16. 1206 * We also need to match the frequency to whatever mode is used. 1207 * For that reason we're just bailing if the dividers don't match 1208 * that requirement. 1209 */ 1210 clk_divider = sc->baseclk_hz / slot->clock; 1211 if (clk_divider < 3 || clk_divider > 16) 1212 return (ENXIO); 1213 1214 if (hs400) 1215 sc->flags |= SDHCI_FSL_HS400_FLAG; 1216 1217 /* Disable clock. */ 1218 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1219 1220 /* Wait for PRSSTAT[SDSTB] to be set by hardware. */ 1221 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1222 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1223 if (error != 0) 1224 device_printf(bus, 1225 "Timeout while waiting for clock to stabilize.\n"); 1226 1227 /* Flush async IO. */ 1228 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1229 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1230 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1231 1232 /* Wait for ESDHC[FAF] to be cleared by hardware. */ 1233 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1234 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1235 if (error) 1236 device_printf(bus, 1237 "Timeout while waiting for hardware.\n"); 1238 1239 /* 1240 * Set TBCTL[TB_EN] register and program valid tuning mode. 1241 * According to RM MODE_3 means that: 1242 * "eSDHC takes care of the re-tuning during data transfer 1243 * (auto re-tuning).". 1244 * Tuning mode can only be changed while the clock is disabled. 1245 */ 1246 reg = RD4(sc, SDHCI_FSL_TBCTL); 1247 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1248 reg |= SDHCI_FSL_TBCTL_TBEN | SDHCI_FSL_TBCTL_MODE_3; 1249 WR4(sc, SDHCI_FSL_TBCTL, reg); 1250 1251 /* Enable clock. */ 1252 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | sc->sdclk_bits); 1253 1254 /* Wait for clock to stabilize. */ 1255 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1256 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1257 if (error) 1258 device_printf(bus, 1259 "Timeout while waiting for clock to stabilize.\n"); 1260 1261 /* Perform hardware tuning. */ 1262 error = sdhci_generic_tune(bus, child, hs400); 1263 1264 reg = RD4(sc, SDHCI_FSL_TBPTR); 1265 wnd_start = reg >> SDHCI_FSL_TBPTR_WND_START_SHIFT; 1266 wnd_start &= SDHCI_FSL_TBPTR_WND_MASK; 1267 wnd_end = reg & SDHCI_FSL_TBPTR_WND_MASK; 1268 1269 /* 1270 * For erratum type2 affected platforms, the controller can erroneously 1271 * declare that the tuning was successful. Verify the tuning window to 1272 * make sure that we're fine. 1273 */ 1274 if (error == 0 && 1275 sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE2 && 1276 abs(wnd_start - wnd_end) > (4 * sc->div_ratio + 2)) { 1277 error = EIO; 1278 } 1279 1280 /* If hardware tuning failed, try software tuning. */ 1281 if (error != 0 && 1282 (sc->soc_data->errata & 1283 (SDHCI_FSL_TUNING_ERRATUM_TYPE1 | 1284 SDHCI_FSL_TUNING_ERRATUM_TYPE2))) { 1285 error = sdhci_fsl_sw_tuning(sc, bus, child, hs400, wnd_start, 1286 wnd_end); 1287 if (error != 0) 1288 device_printf(bus, "Software tuning failed.\n"); 1289 } 1290 1291 if (error != 0) { 1292 sdhci_fsl_switch_tuning_block(bus, false); 1293 return (error); 1294 } 1295 if (hs400) { 1296 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1297 reg |= SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1298 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1299 } 1300 1301 return (0); 1302 } 1303 1304 static int 1305 sdhci_fsl_fdt_retune(device_t bus, device_t child, bool reset) 1306 { 1307 struct sdhci_slot *slot; 1308 struct sdhci_fsl_fdt_softc *sc; 1309 1310 slot = device_get_ivars(child); 1311 sc = device_get_softc(bus); 1312 1313 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1314 return (0); 1315 1316 /* HS400 must be tuned in HS200 mode. */ 1317 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1318 return (EINVAL); 1319 1320 /* 1321 * Only re-tuning with full reset is supported. 1322 * The controller is normally put in "mode 3", which means that 1323 * periodic re-tuning is done automatically. See comment in 1324 * sdhci_fsl_fdt_tune for details. 1325 * Because of that re-tuning should only be triggered as a result 1326 * of a CRC error. 1327 */ 1328 if (!reset) 1329 return (ENOTSUP); 1330 1331 return (sdhci_fsl_fdt_tune(bus, child, 1332 sc->flags & SDHCI_FSL_HS400_FLAG)); 1333 } 1334 static void 1335 sdhci_fsl_disable_hs400_mode(device_t dev, struct sdhci_fsl_fdt_softc *sc) 1336 { 1337 uint32_t reg; 1338 int error; 1339 1340 /* Check if HS400 is enabled right now. */ 1341 reg = RD4(sc, SDHCI_FSL_TBCTL); 1342 if ((reg & SDHCI_FSL_TBCTL_HS400_EN) == 0) 1343 return; 1344 1345 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1346 reg &= ~SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1347 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1348 1349 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1350 reg &= ~SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1351 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1352 1353 fsl_sdhc_fdt_set_clock(sc, &sc->slot, sc->sdclk_bits); 1354 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1355 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1356 if (error != 0) 1357 device_printf(dev, 1358 "Internal clock never stabilized.\n"); 1359 1360 reg = RD4(sc, SDHCI_FSL_TBCTL); 1361 reg &= ~SDHCI_FSL_TBCTL_HS400_EN; 1362 WR4(sc, SDHCI_FSL_TBCTL, reg); 1363 1364 fsl_sdhc_fdt_set_clock(sc, &sc->slot, SDHCI_CLOCK_CARD_EN | 1365 sc->sdclk_bits); 1366 1367 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1368 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1369 if (error != 0) 1370 device_printf(dev, 1371 "Internal clock never stabilized.\n"); 1372 1373 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1374 reg &= ~(SDHCI_FSL_DLLCFG0_EN | 1375 SDHCI_FSL_DLLCFG0_FREQ_SEL); 1376 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1377 1378 reg = RD4(sc, SDHCI_FSL_TBCTL); 1379 reg &= ~SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1380 WR4(sc, SDHCI_FSL_TBCTL, reg); 1381 1382 sdhci_fsl_switch_tuning_block(dev, false); 1383 } 1384 1385 static void 1386 sdhci_fsl_enable_hs400_mode(device_t dev, struct sdhci_slot *slot, 1387 struct sdhci_fsl_fdt_softc *sc) 1388 { 1389 uint32_t reg; 1390 int error; 1391 1392 sdhci_fsl_switch_tuning_block(dev, true); 1393 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1394 1395 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1396 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1397 if (error != 0) 1398 device_printf(dev, 1399 "Timeout while waiting for clock to stabilize.\n"); 1400 1401 reg = RD4(sc, SDHCI_FSL_TBCTL); 1402 reg |= SDHCI_FSL_TBCTL_HS400_EN; 1403 WR4(sc, SDHCI_FSL_TBCTL, reg); 1404 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1405 reg |= SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1406 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1407 1408 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1409 sc->sdclk_bits); 1410 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1411 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1412 if (error != 0) 1413 device_printf(dev, 1414 "Timeout while waiting for clock to stabilize.\n"); 1415 1416 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1417 reg |= SDHCI_FSL_DLLCFG0_EN | SDHCI_FSL_DLLCFG0_RESET | 1418 SDHCI_FSL_DLLCFG0_FREQ_SEL; 1419 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1420 1421 /* 1422 * The reset bit is not a self clearing one. 1423 * Give it some time and clear it manually. 1424 */ 1425 DELAY(100); 1426 reg &= ~SDHCI_FSL_DLLCFG0_RESET; 1427 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1428 1429 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_DLLSTAT0, 1430 SDHCI_FSL_DLLSTAT0_SLV_STS, SDHCI_FSL_DLLSTAT0_SLV_STS); 1431 if (error != 0) 1432 device_printf(dev, 1433 "Timeout while waiting for DLL0.\n"); 1434 1435 reg = RD4(sc, SDHCI_FSL_TBCTL); 1436 reg |= SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1437 WR4(sc, SDHCI_FSL_TBCTL, reg); 1438 1439 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1440 1441 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1442 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1443 if (error != 0) 1444 device_printf(dev, 1445 "timeout while waiting for clock to stabilize.\n"); 1446 1447 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1448 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1449 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1450 1451 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1452 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1453 if (error != 0) 1454 device_printf(dev, 1455 "Timeout while waiting for hardware.\n"); 1456 1457 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1458 sc->sdclk_bits); 1459 1460 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1461 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1462 if (error != 0) 1463 device_printf(dev, 1464 "Timeout while waiting for clock to stabilize.\n"); 1465 } 1466 1467 static void 1468 sdhci_fsl_fdt_set_uhs_timing(device_t dev, struct sdhci_slot *slot) 1469 { 1470 struct sdhci_fsl_fdt_softc *sc; 1471 const struct mmc_ios *ios; 1472 uint32_t mode, reg; 1473 1474 sc = device_get_softc(dev); 1475 ios = &slot->host.ios; 1476 mode = 0; 1477 1478 /* 1479 * When we switch to HS400 this function is called twice. 1480 * First after the timing is set, and then after the clock 1481 * is changed to the target frequency. 1482 * The controller can be switched to HS400 only after the latter 1483 * is done. 1484 */ 1485 if (slot->host.ios.timing == bus_timing_mmc_hs400 && 1486 ios->clock > SD_SDR50_MAX) 1487 sdhci_fsl_enable_hs400_mode(dev, slot, sc); 1488 else if (slot->host.ios.timing < bus_timing_mmc_hs400) { 1489 sdhci_fsl_disable_hs400_mode(dev, sc); 1490 1491 /* 1492 * Switching to HS400 requires a custom procedure executed in 1493 * sdhci_fsl_enable_hs400_mode in case above. 1494 * For all other modes we just need to set the corresponding flag. 1495 */ 1496 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1497 reg &= ~SDHCI_FSL_AUTOCERR_UHMS; 1498 if (ios->clock > SD_SDR50_MAX) 1499 mode = SDHCI_CTRL2_UHS_SDR104; 1500 else if (ios->clock > SD_SDR25_MAX) 1501 mode = SDHCI_CTRL2_UHS_SDR50; 1502 else if (ios->clock > SD_SDR12_MAX) { 1503 if (ios->timing == bus_timing_uhs_ddr50 || 1504 ios->timing == bus_timing_mmc_ddr52) 1505 mode = SDHCI_CTRL2_UHS_DDR50; 1506 else 1507 mode = SDHCI_CTRL2_UHS_SDR25; 1508 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1509 mode = SDHCI_CTRL2_UHS_SDR12; 1510 1511 reg |= mode << SDHCI_FSL_AUTOCERR_UHMS_SHIFT; 1512 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1513 } 1514 } 1515 1516 static const device_method_t sdhci_fsl_fdt_methods[] = { 1517 /* Device interface. */ 1518 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe), 1519 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach), 1520 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach), 1521 1522 /* Bus interface. */ 1523 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar), 1524 DEVMETHOD(bus_write_ivar, sdhci_fsl_fdt_write_ivar), 1525 1526 /* MMC bridge interface. */ 1527 DEVMETHOD(mmcbr_request, sdhci_generic_request), 1528 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro), 1529 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 1530 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 1531 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq), 1532 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios), 1533 DEVMETHOD(mmcbr_tune, sdhci_fsl_fdt_tune), 1534 DEVMETHOD(mmcbr_retune, sdhci_fsl_fdt_retune), 1535 1536 /* SDHCI accessors. */ 1537 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1), 1538 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2), 1539 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4), 1540 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4), 1541 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1), 1542 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2), 1543 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4), 1544 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4), 1545 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present), 1546 DEVMETHOD(sdhci_reset, sdhci_fsl_fdt_reset), 1547 DEVMETHOD(sdhci_set_uhs_timing, sdhci_fsl_fdt_set_uhs_timing), 1548 DEVMETHOD_END 1549 }; 1550 1551 static driver_t sdhci_fsl_fdt_driver = { 1552 "sdhci_fsl_fdt", 1553 sdhci_fsl_fdt_methods, 1554 sizeof(struct sdhci_fsl_fdt_softc), 1555 }; 1556 1557 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, NULL, NULL); 1558 SDHCI_DEPEND(sdhci_fsl_fdt); 1559 1560 #ifndef MMCCAM 1561 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt); 1562 #endif 1563