1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 - 2021 Alstom Group. 5 * Copyright (c) 2020 - 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include <dev/extres/clk/clk.h> 46 #include <dev/mmc/bridge.h> 47 #include <dev/mmc/mmcbrvar.h> 48 #include <dev/mmc/mmc_fdt_helpers.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 #include <dev/sdhci/sdhci.h> 52 #include <dev/sdhci/sdhci_fdt_gpio.h> 53 54 #include "mmcbr_if.h" 55 #include "sdhci_if.h" 56 57 #define RD4 (sc->read) 58 #define WR4 (sc->write) 59 60 #define SDHCI_FSL_PRES_STATE 0x24 61 #define SDHCI_FSL_PRES_SDSTB (1 << 3) 62 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07 63 64 #define SDHCI_FSL_PROT_CTRL 0x28 65 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1) 66 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1) 67 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1) 68 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1) 69 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4) 70 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4) 71 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4) 72 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8) 73 #define SDHCI_FSL_PROT_CTRL_VOLT_SEL (1 << 10) 74 75 #define SDHCI_FSL_IRQSTAT 0x30 76 #define SDHCI_FSL_IRQSTAT_BRR (1 << 5) 77 #define SDHCI_FSL_IRQSTAT_CINTSEN (1 << 8) 78 #define SDHCI_FSL_IRQSTAT_RTE (1 << 12) 79 #define SDHCI_FSL_IRQSTAT_TNE (1 << 26) 80 81 #define SDHCI_FSL_SYS_CTRL 0x2c 82 #define SDHCI_FSL_CLK_IPGEN (1 << 0) 83 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3) 84 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0 85 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4 86 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00 87 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8 88 89 #define SDHCI_FSL_WTMK_LVL 0x44 90 #define SDHCI_FSL_WTMK_RD_512B (0 << 0) 91 #define SDHCI_FSL_WTMK_WR_512B (0 << 15) 92 93 #define SDHCI_FSL_AUTOCERR 0x3C 94 #define SDHCI_FSL_AUTOCERR_UHMS_HS200 (3 << 17) 95 #define SDHCI_FSL_AUTOCERR_UHMS (7 << 18) 96 #define SDHCI_FSL_AUTOCERR_EXTN (1 << 22) 97 #define SDHCI_FSL_AUTOCERR_SMPCLKSEL (1 << 23) 98 99 #define SDHCI_FSL_HOST_VERSION 0xfc 100 #define SDHCI_FSL_VENDOR_V23 0x13 101 102 #define SDHCI_FSL_CAPABILITIES2 0x114 103 104 #define SDHCI_FSL_TBCTL 0x120 105 106 #define SDHCI_FSL_TBSTAT 0x124 107 #define SDHCI_FSL_TBCTL_TBEN (1 << 2) 108 #define SDHCI_FSL_TBCTL_HS400_EN (1 << 4) 109 #define SDHCI_FSL_TBCTL_SAMP_CMD_DQS (1 << 5) 110 #define SDHCI_FSL_TBCTL_HS400_WND_ADJ (1 << 6) 111 #define SDHCI_FSL_TBCTL_TB_MODE_MASK 0x3 112 #define SDHCI_FSL_TBCTL_MODE_1 0 113 #define SDHCI_FSL_TBCTL_MODE_2 1 114 #define SDHCI_FSL_TBCTL_MODE_3 2 115 #define SDHCI_FSL_TBCTL_MODE_SW 3 116 117 #define SDHCI_FSL_TBPTR 0x128 118 #define SDHCI_FSL_TBPTR_WND_START 0x7F00 119 #define SDHCI_FSL_TBPTR_WND_END 0x7F 120 121 #define SDHCI_FSL_SDCLKCTL 0x144 122 #define SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL (1 << 15) 123 #define SDHCI_FSL_SDCLKCTL_LPBK_CLK_SEL (1 << 31) 124 125 #define SDHCI_FSL_SDTIMINGCTL 0x148 126 #define SDHCI_FSL_SDTIMINGCTL_FLW_CTL (1 << 15) 127 128 #define SDHCI_FSL_DLLCFG0 0x160 129 #define SDHCI_FSL_DLLCFG0_FREQ_SEL (1 << 27) 130 #define SDHCI_FSL_DLLCFG0_EN (1 << 31) 131 132 #define SDHCI_FSL_DLLCFG1 0x164 133 #define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31) 134 135 #define SDHCI_FSL_DLLCFG1 0x164 136 #define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31) 137 138 #define SDHCI_FSL_ESDHC_CTRL 0x40c 139 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) 140 #define SDHCI_FSL_ESDHC_CTRL_FAF (1 << 18) 141 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) 142 143 #define SDHCI_FSL_CAN_VDD_MASK \ 144 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330) 145 146 /* Some platforms do not detect pulse width correctly. */ 147 #define SDHCI_FSL_UNRELIABLE_PULSE_DET (1 << 0) 148 /* On some platforms switching voltage to 1.8V is not supported */ 149 #define SDHCI_FSL_UNSUPP_1_8V (1 << 1) 150 /* Hardware tuning can fail, fallback to SW tuning in that case. */ 151 #define SDHCI_FSL_TUNING_ERRATUM_TYPE1 (1 << 2) 152 /* 153 * Pointer window might not be set properly on some platforms. 154 * Check window and perform SW tuning. 155 */ 156 #define SDHCI_FSL_TUNING_ERRATUM_TYPE2 (1 << 3) 157 /* 158 * In HS400 mode only 4, 8, 12 clock dividers can be used. 159 * Use the smallest value, bigger than requested in that case. 160 */ 161 #define SDHCI_FSL_HS400_LIMITED_CLK_DIV (1 << 4) 162 163 #define SDHCI_FSL_HS400_FLAG (1 << 0) 164 #define SDHCI_FSL_SWITCH_TO_HS400_FLAG (1 << 1) 165 #define SDHCI_FSL_HS400_DONE (1 << 2) 166 167 #define SDHCI_FSL_MAX_RETRIES 10 168 169 struct sdhci_fsl_fdt_softc { 170 device_t dev; 171 const struct sdhci_fsl_fdt_soc_data *soc_data; 172 struct resource *mem_res; 173 struct resource *irq_res; 174 void *irq_cookie; 175 uint32_t baseclk_hz; 176 uint32_t maxclk_hz; 177 struct sdhci_fdt_gpio *gpio; 178 struct sdhci_slot slot; 179 bool slot_init_done; 180 uint32_t cmd_and_mode; 181 uint16_t sdclk_bits; 182 struct mmc_helper fdt_helper; 183 uint8_t vendor_ver; 184 uint32_t flags; 185 enum mmc_bus_timing last_mode; 186 187 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t); 188 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t); 189 }; 190 191 struct sdhci_fsl_fdt_soc_data { 192 int quirks; 193 int baseclk_div; 194 uint8_t errata; 195 }; 196 197 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1012a_soc_data = { 198 .quirks = 0, 199 .baseclk_div = 1, 200 .errata = SDHCI_FSL_UNSUPP_1_8V, 201 }; 202 203 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = { 204 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | 205 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 206 .baseclk_div = 2, 207 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 208 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 209 }; 210 211 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { 212 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP, 213 .baseclk_div = 2, 214 .errata = SDHCI_FSL_UNSUPP_1_8V, 215 }; 216 217 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = { 218 .quirks = 0, 219 .baseclk_div = 1, 220 }; 221 222 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = { 223 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data}, 224 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data}, 225 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data}, 226 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data}, 227 {NULL, 0} 228 }; 229 230 static uint32_t 231 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 232 { 233 234 return (be32toh(bus_read_4(sc->mem_res, off))); 235 } 236 237 static void 238 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 239 { 240 241 bus_write_4(sc->mem_res, off, htobe32(val)); 242 } 243 244 static uint32_t 245 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 246 { 247 248 return (bus_read_4(sc->mem_res, off)); 249 } 250 251 static void 252 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 253 { 254 255 bus_write_4(sc->mem_res, off, val); 256 } 257 258 259 static uint16_t 260 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc) 261 { 262 uint16_t val; 263 264 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN; 265 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) 266 val |= SDHCI_CLOCK_INT_STABLE; 267 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) 268 val |= SDHCI_CLOCK_CARD_EN; 269 270 return (val); 271 } 272 273 /* 274 * Calculate clock prescaler and divisor values based on the following formula: 275 * `frequency = base clock / (prescaler * divisor)`. 276 */ 277 #define SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div) \ 278 do { \ 279 (pre) = (sc)->vendor_ver < SDHCI_FSL_VENDOR_V23 ? 2 : 1;\ 280 while ((freq) < (base) / ((pre) * 16) && (pre) < 256) \ 281 (pre) <<= 1; \ 282 /* div/pre can't both be set to 1, according to PM. */ \ 283 (div) = ((pre) == 1 ? 2 : 1); \ 284 while ((freq) < (base) / ((pre) * (div)) && (div) < 16) \ 285 ++(div); \ 286 } while (0) 287 288 static void 289 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, struct sdhci_slot *slot, 290 uint16_t val) 291 { 292 uint32_t prescale, div, val32, div_ratio; 293 294 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK; 295 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 296 297 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 298 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 299 return; 300 } 301 302 /* 303 * Ignore dividers provided by core in `sdhci_set_clock` and calculate 304 * them anew with higher accuracy. 305 */ 306 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div); 307 308 #ifdef DEBUG 309 device_printf(sc->dev, 310 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", 311 slot->clock, sc->baseclk_hz / (prescale * div), 312 sc->baseclk_hz, prescale, div); 313 #endif 314 315 div_ratio = prescale * div; 316 317 /* 318 * According to limited clock division erratum, clock dividers in hs400 319 * can be only 4, 8 or 12 320 */ 321 if ((sc->soc_data->errata & SDHCI_FSL_HS400_LIMITED_CLK_DIV) && 322 (sc->slot.host.ios.timing == bus_timing_mmc_hs400 || 323 (sc->flags & SDHCI_FSL_HS400_FLAG))) { 324 if (div_ratio <= 4) { 325 prescale = 4; 326 div = 1; 327 } else if (div_ratio <= 8) { 328 prescale = 4; 329 div = 2; 330 } else if (div_ratio <= 12) { 331 prescale = 4; 332 div = 3; 333 } else { 334 device_printf(sc->dev, "Unsupported clock divider.\n"); 335 } 336 } 337 338 prescale >>= 1; 339 div -= 1; 340 341 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK); 342 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT; 343 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT; 344 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN; 345 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 346 } 347 348 static uint8_t 349 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 350 { 351 struct sdhci_fsl_fdt_softc *sc; 352 uint32_t wrk32, val32; 353 354 sc = device_get_softc(dev); 355 356 switch (off) { 357 case SDHCI_HOST_CONTROL: 358 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 359 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 360 SDHCI_CTRL_FORCE_CARD); 361 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT) 362 val32 |= SDHCI_CTRL_4BITBUS; 363 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT) 364 val32 |= SDHCI_CTRL_8BITBUS; 365 return (val32); 366 case SDHCI_POWER_CONTROL: 367 return (SDHCI_POWER_ON | SDHCI_POWER_300); 368 default: 369 break; 370 } 371 372 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); 373 } 374 375 static uint16_t 376 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 377 { 378 struct sdhci_fsl_fdt_softc *sc; 379 uint32_t val32; 380 381 sc = device_get_softc(dev); 382 383 switch (off) { 384 case SDHCI_CLOCK_CONTROL: 385 return (sdhci_fsl_fdt_get_clock(sc)); 386 case SDHCI_HOST_VERSION: 387 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); 388 case SDHCI_TRANSFER_MODE: 389 return (sc->cmd_and_mode & UINT16_MAX); 390 case SDHCI_COMMAND_FLAGS: 391 return (sc->cmd_and_mode >> 16); 392 case SDHCI_SLOT_INT_STATUS: 393 /* 394 * eSDHC hardware manages only a single slot. 395 * Synthesize a slot interrupt status register for slot 1 below. 396 */ 397 val32 = RD4(sc, SDHCI_INT_STATUS); 398 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 399 return (!!val32); 400 default: 401 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); 402 } 403 } 404 405 static uint32_t 406 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 407 { 408 struct sdhci_fsl_fdt_softc *sc; 409 uint32_t wrk32, val32; 410 411 sc = device_get_softc(dev); 412 413 if (off == SDHCI_BUFFER) 414 return (bus_read_4(sc->mem_res, off)); 415 if (off == SDHCI_CAPABILITIES2) 416 off = SDHCI_FSL_CAPABILITIES2; 417 418 val32 = RD4(sc, off); 419 420 if (off == SDHCI_PRESENT_STATE) { 421 wrk32 = val32; 422 val32 &= SDHCI_FSL_PRES_COMPAT_MASK; 423 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 424 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD; 425 } 426 427 return (val32); 428 } 429 430 static void 431 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 432 uint32_t *data, bus_size_t count) 433 { 434 struct sdhci_fsl_fdt_softc *sc; 435 436 sc = device_get_softc(dev); 437 bus_read_multi_4(sc->mem_res, off, data, count); 438 } 439 440 static void 441 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 442 uint8_t val) 443 { 444 struct sdhci_fsl_fdt_softc *sc; 445 uint32_t val32; 446 447 sc = device_get_softc(dev); 448 449 switch (off) { 450 case SDHCI_HOST_CONTROL: 451 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 452 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK; 453 val32 |= (val & SDHCI_CTRL_LED); 454 455 if (val & SDHCI_CTRL_8BITBUS) 456 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT; 457 else 458 /* Bus width is 1-bit when this flag is not set. */ 459 val32 |= (val & SDHCI_CTRL_4BITBUS); 460 /* Enable SDMA by masking out this field. */ 461 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK; 462 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); 463 val32 |= (val & (SDHCI_CTRL_CARD_DET | 464 SDHCI_CTRL_FORCE_CARD)); 465 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 466 return; 467 case SDHCI_POWER_CONTROL: 468 return; 469 default: 470 val32 = RD4(sc, off & ~3); 471 val32 &= ~(UINT8_MAX << (off & 3) * 8); 472 val32 |= (val << (off & 3) * 8); 473 WR4(sc, off & ~3, val32); 474 return; 475 } 476 } 477 478 static void 479 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 480 uint16_t val) 481 { 482 struct sdhci_fsl_fdt_softc *sc; 483 uint32_t val32; 484 485 sc = device_get_softc(dev); 486 487 switch (off) { 488 case SDHCI_CLOCK_CONTROL: 489 fsl_sdhc_fdt_set_clock(sc, slot, val); 490 return; 491 /* 492 * eSDHC hardware combines command and mode into a single 493 * register. Cache it here, so that command isn't written 494 * until after mode. 495 */ 496 case SDHCI_TRANSFER_MODE: 497 sc->cmd_and_mode = val; 498 return; 499 case SDHCI_COMMAND_FLAGS: 500 sc->cmd_and_mode = 501 (sc->cmd_and_mode & UINT16_MAX) | (val << 16); 502 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 503 sc->cmd_and_mode = 0; 504 return; 505 /* 506 * When switching to HS400 mode, setting these registers 507 * is required for successful tuning. 508 */ 509 case SDHCI_HOST_CONTROL2: 510 if ((val & SDHCI_CTRL2_MMC_HS400) && 511 (sc->flags & SDHCI_FSL_SWITCH_TO_HS400_FLAG)) { 512 val32 = RD4(sc, SDHCI_FSL_TBCTL); 513 val32 |= SDHCI_FSL_TBCTL_HS400_EN; 514 WR4(sc, SDHCI_FSL_TBCTL, val32); 515 516 val32 = RD4(sc, SDHCI_FSL_SDCLKCTL); 517 val32 |= SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 518 WR4(sc, SDHCI_FSL_SDCLKCTL, val32); 519 520 } 521 522 val &= ~SDHCI_CTRL2_MMC_HS400; 523 default: 524 val32 = RD4(sc, off & ~3); 525 val32 &= ~(UINT16_MAX << (off & 3) * 8); 526 val32 |= ((val & UINT16_MAX) << (off & 3) * 8); 527 WR4(sc, off & ~3, val32); 528 return; 529 } 530 } 531 532 static void 533 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 534 uint32_t val) 535 { 536 struct sdhci_fsl_fdt_softc *sc; 537 538 sc = device_get_softc(dev); 539 540 switch (off) { 541 case SDHCI_BUFFER: 542 bus_write_4(sc->mem_res, off, val); 543 return; 544 /* 545 * eSDHC hardware lacks support for the SDMA buffer boundary 546 * feature and instead generates SDHCI_INT_DMA_END interrupts 547 * after each completed DMA data transfer. 548 * Since this duplicates the SDHCI_INT_DATA_END functionality, 549 * mask out the unneeded SDHCI_INT_DMA_END interrupt. 550 */ 551 case SDHCI_INT_ENABLE: 552 case SDHCI_SIGNAL_ENABLE: 553 val &= ~SDHCI_INT_DMA_END; 554 /* FALLTHROUGH. */ 555 default: 556 WR4(sc, off, val); 557 return; 558 } 559 } 560 561 static void 562 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 563 bus_size_t off, uint32_t *data, bus_size_t count) 564 { 565 struct sdhci_fsl_fdt_softc *sc; 566 567 sc = device_get_softc(dev); 568 bus_write_multi_4(sc->mem_res, off, data, count); 569 } 570 571 static void 572 sdhci_fsl_fdt_irq(void *arg) 573 { 574 struct sdhci_fsl_fdt_softc *sc; 575 576 sc = arg; 577 sdhci_generic_intr(&sc->slot); 578 return; 579 } 580 581 static int 582 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev) 583 { 584 int err; 585 struct sdhci_fsl_fdt_softc *sc; 586 struct mmc_ios *ios; 587 struct sdhci_slot *slot; 588 589 err = sdhci_generic_update_ios(brdev, reqdev); 590 if (err != 0) 591 return (err); 592 593 sc = device_get_softc(brdev); 594 slot = device_get_ivars(reqdev); 595 ios = &slot->host.ios; 596 597 switch (ios->power_mode) { 598 case power_on: 599 break; 600 case power_off: 601 if (bootverbose) 602 device_printf(sc->dev, "Powering down sd/mmc\n"); 603 604 if (sc->fdt_helper.vmmc_supply) 605 regulator_disable(sc->fdt_helper.vmmc_supply); 606 if (sc->fdt_helper.vqmmc_supply) 607 regulator_disable(sc->fdt_helper.vqmmc_supply); 608 break; 609 case power_up: 610 if (bootverbose) 611 device_printf(sc->dev, "Powering up sd/mmc\n"); 612 613 if (sc->fdt_helper.vmmc_supply) 614 regulator_enable(sc->fdt_helper.vmmc_supply); 615 if (sc->fdt_helper.vqmmc_supply) 616 regulator_enable(sc->fdt_helper.vqmmc_supply); 617 break; 618 }; 619 620 return (0); 621 } 622 623 static int 624 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev) 625 { 626 struct sdhci_fsl_fdt_softc *sc; 627 struct sdhci_slot *slot; 628 regulator_t vqmmc_supply; 629 uint32_t val_old, val; 630 int uvolt, err; 631 632 sc = device_get_softc(brdev); 633 slot = device_get_ivars(reqdev); 634 635 val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL); 636 637 switch (slot->host.ios.vccq) { 638 case vccq_180: 639 if (sc->soc_data->errata & SDHCI_FSL_UNSUPP_1_8V) 640 return (EOPNOTSUPP); 641 642 val |= SDHCI_FSL_PROT_CTRL_VOLT_SEL; 643 uvolt = 1800000; 644 break; 645 case vccq_330: 646 val &= ~SDHCI_FSL_PROT_CTRL_VOLT_SEL; 647 uvolt = 3300000; 648 break; 649 default: 650 return (EOPNOTSUPP); 651 } 652 653 WR4(sc, SDHCI_FSL_PROT_CTRL, val); 654 655 vqmmc_supply = sc->fdt_helper.vqmmc_supply; 656 /* 657 * Even though we expect to find a fixed regulator in this controller 658 * family, let's play safe. 659 */ 660 if (vqmmc_supply != NULL) { 661 err = regulator_set_voltage(vqmmc_supply, uvolt, uvolt); 662 if (err != 0) { 663 device_printf(sc->dev, 664 "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt); 665 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old); 666 return (err); 667 } 668 } 669 670 return (0); 671 } 672 673 static int 674 sdhci_fsl_fdt_get_ro(device_t bus, device_t child) 675 { 676 struct sdhci_fsl_fdt_softc *sc; 677 678 sc = device_get_softc(bus); 679 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 680 } 681 682 static bool 683 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot) 684 { 685 struct sdhci_fsl_fdt_softc *sc; 686 687 sc = device_get_softc(dev); 688 return (sdhci_fdt_gpio_get_present(sc->gpio)); 689 } 690 691 static uint32_t 692 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len) 693 { 694 uint32_t vdd_min, vdd_max; 695 uint32_t vdd_mask = 0; 696 int i; 697 698 /* Ranges are organized as pairs of values. */ 699 if ((len % 2) != 0) { 700 device_printf(dev, "Invalid voltage range\n"); 701 return (0); 702 } 703 len = len / 2; 704 705 for (i = 0; i < len; i++) { 706 vdd_min = vdd_ranges[2 * i]; 707 vdd_max = vdd_ranges[2 * i + 1]; 708 709 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 || 710 vdd_max < 1650 || vdd_max > 3600) { 711 device_printf(dev, "Voltage range %d - %d is out of bounds\n", 712 vdd_min, vdd_max); 713 return (0); 714 } 715 716 if (vdd_min <= 1800 && vdd_max >= 1800) 717 vdd_mask |= SDHCI_CAN_VDD_180; 718 if (vdd_min <= 3000 && vdd_max >= 3000) 719 vdd_mask |= SDHCI_CAN_VDD_300; 720 if (vdd_min <= 3300 && vdd_max >= 3300) 721 vdd_mask |= SDHCI_CAN_VDD_330; 722 } 723 724 return (vdd_mask); 725 } 726 727 static void 728 sdhci_fsl_fdt_of_parse(device_t dev) 729 { 730 struct sdhci_fsl_fdt_softc *sc; 731 phandle_t node; 732 pcell_t *voltage_ranges; 733 uint32_t vdd_mask = 0; 734 ssize_t num_ranges; 735 736 sc = device_get_softc(dev); 737 node = ofw_bus_get_node(dev); 738 739 /* Call mmc_fdt_parse in order to get mmc related properties. */ 740 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host); 741 742 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot, 743 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND); 744 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot, 745 SDHCI_CAPABILITIES2); 746 747 /* Parse the "voltage-ranges" dts property. */ 748 num_ranges = OF_getencprop_alloc(node, "voltage-ranges", 749 (void **) &voltage_ranges); 750 if (num_ranges <= 0) 751 return; 752 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges, 753 num_ranges / sizeof(uint32_t)); 754 OF_prop_free(voltage_ranges); 755 756 /* Overwrite voltage caps only if we got something from dts. */ 757 if (vdd_mask != 0 && 758 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) { 759 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK); 760 sc->slot.caps |= vdd_mask; 761 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS; 762 } 763 } 764 765 static int 766 sdhci_fsl_poll_register(struct sdhci_fsl_fdt_softc *sc, 767 uint32_t reg, uint32_t mask, int value) 768 { 769 int retries; 770 771 retries = SDHCI_FSL_MAX_RETRIES; 772 773 while ((RD4(sc, reg) & mask) != value) { 774 if (!retries--) 775 return (ENXIO); 776 777 DELAY(10); 778 } 779 780 return (0); 781 } 782 783 static int 784 sdhci_fsl_fdt_attach(device_t dev) 785 { 786 struct sdhci_fsl_fdt_softc *sc; 787 struct mmc_host *host; 788 uint32_t val, buf_order; 789 uintptr_t ocd_data; 790 uint64_t clk_hz; 791 phandle_t node; 792 int rid, ret; 793 clk_t clk; 794 795 node = ofw_bus_get_node(dev); 796 sc = device_get_softc(dev); 797 ocd_data = ofw_bus_search_compatible(dev, 798 sdhci_fsl_fdt_compat_data)->ocd_data; 799 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data; 800 sc->dev = dev; 801 sc->slot.quirks = sc->soc_data->quirks; 802 sc->flags = 0; 803 sc->last_mode = bus_timing_normal; 804 host = &sc->slot.host; 805 806 rid = 0; 807 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 808 RF_ACTIVE); 809 if (sc->mem_res == NULL) { 810 device_printf(dev, 811 "Could not allocate resources for controller\n"); 812 return (ENOMEM); 813 } 814 815 rid = 0; 816 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 817 RF_ACTIVE); 818 if (sc->irq_res == NULL) { 819 device_printf(dev, 820 "Could not allocate irq resources for controller\n"); 821 ret = ENOMEM; 822 goto err_free_mem; 823 } 824 825 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 826 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie); 827 if (ret != 0) { 828 device_printf(dev, "Could not setup IRQ handler\n"); 829 goto err_free_irq_res; 830 } 831 832 ret = clk_get_by_ofw_index(dev, node, 0, &clk); 833 if (ret != 0) { 834 device_printf(dev, "Parent clock not found\n"); 835 goto err_free_irq; 836 } 837 838 ret = clk_get_freq(clk, &clk_hz); 839 if (ret != 0) { 840 device_printf(dev, 841 "Could not get parent clock frequency\n"); 842 goto err_free_irq; 843 } 844 845 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div; 846 847 /* Figure out eSDHC block endianness before we touch any HW regs. */ 848 if (OF_hasprop(node, "little-endian")) { 849 sc->read = read_le; 850 sc->write = write_le; 851 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE; 852 } else { 853 sc->read = read_be; 854 sc->write = write_be; 855 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP; 856 } 857 858 sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) & 859 SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; 860 861 sdhci_fsl_fdt_of_parse(dev); 862 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz; 863 864 /* 865 * Setting this register affects byte order in SDHCI_BUFFER only. 866 * If the eSDHC block is connected over a big-endian bus, the data 867 * read from/written to the buffer will be already byte swapped. 868 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert 869 * the byte order again, resulting in a native byte order. 870 * The read/write callbacks accommodate for this behavior. 871 */ 872 val = RD4(sc, SDHCI_FSL_PROT_CTRL); 873 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK; 874 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 875 876 /* 877 * Gate the SD clock and set its source to 878 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set 879 * to match this. 880 */ 881 val = RD4(sc, SDHCI_CLOCK_CONTROL); 882 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); 883 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 884 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); 885 sc->slot.max_clk = sc->maxclk_hz; 886 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 887 888 /* 889 * Pulse width detection is not reliable on some boards. Perform 890 * workaround by clearing register's bit according to errata. 891 */ 892 if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) { 893 val = RD4(sc, SDHCI_FSL_DLLCFG1); 894 val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH; 895 WR4(sc, SDHCI_FSL_DLLCFG1, val); 896 } 897 898 /* 899 * Set the buffer watermark level to 128 words (512 bytes) for both 900 * read and write. The hardware has a restriction that when the read or 901 * write ready status is asserted, that means you can read exactly the 902 * number of words set in the watermark register before you have to 903 * re-check the status and potentially wait for more data. The main 904 * sdhci driver provides no hook for doing status checking on less than 905 * a full block boundary, so we set the watermark level to be a full 906 * block. Reads and writes where the block size is less than the 907 * watermark size will work correctly too, no need to change the 908 * watermark for different size blocks. However, 128 is the maximum 909 * allowed for the watermark, so PIO is limitted to 512 byte blocks. 910 */ 911 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | 912 SDHCI_FSL_WTMK_RD_512B); 913 914 ret = sdhci_init_slot(dev, &sc->slot, 0); 915 if (ret != 0) 916 goto err_free_gpio; 917 sc->slot_init_done = true; 918 sdhci_start_slot(&sc->slot); 919 920 return (bus_generic_attach(dev)); 921 922 err_free_gpio: 923 sdhci_fdt_gpio_teardown(sc->gpio); 924 err_free_irq: 925 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 926 err_free_irq_res: 927 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 928 err_free_mem: 929 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 930 return (ret); 931 } 932 933 static int 934 sdhci_fsl_fdt_detach(device_t dev) 935 { 936 struct sdhci_fsl_fdt_softc *sc; 937 938 sc = device_get_softc(dev); 939 if (sc->slot_init_done) 940 sdhci_cleanup_slot(&sc->slot); 941 if (sc->gpio != NULL) 942 sdhci_fdt_gpio_teardown(sc->gpio); 943 if (sc->irq_cookie != NULL) 944 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 945 if (sc->irq_res != NULL) 946 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 947 if (sc->mem_res != NULL) 948 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 949 return (0); 950 } 951 952 static int 953 sdhci_fsl_fdt_probe(device_t dev) 954 { 955 956 if (!ofw_bus_status_okay(dev)) 957 return (ENXIO); 958 959 if (!ofw_bus_search_compatible(dev, 960 sdhci_fsl_fdt_compat_data)->ocd_data) 961 return (ENXIO); 962 963 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller"); 964 return (BUS_PROBE_DEFAULT); 965 } 966 967 static int 968 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which, 969 uintptr_t *result) 970 { 971 struct sdhci_slot *slot = device_get_ivars(child); 972 973 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) { 974 /* 975 * In the absence of SDMA buffer boundary functionality, 976 * limit the maximum data length per read/write command 977 * to bounce buffer size. 978 */ 979 *result = howmany(slot->sdma_bbufsz, 512); 980 return (0); 981 } 982 return (sdhci_generic_read_ivar(bus, child, which, result)); 983 } 984 985 static int 986 sdhci_fsl_fdt_write_ivar(device_t bus, device_t child, int which, 987 uintptr_t value) 988 { 989 struct sdhci_fsl_fdt_softc *sc; 990 struct sdhci_slot *slot = device_get_ivars(child); 991 uint32_t prescale, div; 992 993 /* Don't depend on clock resolution limits from sdhci core. */ 994 if (which == MMCBR_IVAR_CLOCK) { 995 if (value == 0) { 996 slot->host.ios.clock = 0; 997 return (0); 998 } 999 1000 sc = device_get_softc(bus); 1001 1002 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div); 1003 slot->host.ios.clock = sc->baseclk_hz / (prescale * div); 1004 1005 return (0); 1006 } 1007 1008 return (sdhci_generic_write_ivar(bus, child, which, value)); 1009 } 1010 1011 static void 1012 sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask) 1013 { 1014 struct sdhci_fsl_fdt_softc *sc; 1015 uint32_t val; 1016 1017 sdhci_generic_reset(dev, slot, mask); 1018 1019 if (!(mask & SDHCI_RESET_ALL)) 1020 return; 1021 1022 sc = device_get_softc(dev); 1023 1024 /* Some registers have to be cleared by hand. */ 1025 if (slot->version >= SDHCI_SPEC_300) { 1026 val = RD4(sc, SDHCI_FSL_TBCTL); 1027 val &= ~SDHCI_FSL_TBCTL_TBEN; 1028 WR4(sc, SDHCI_FSL_TBCTL, val); 1029 } 1030 1031 sc->flags &= ~SDHCI_FSL_HS400_DONE; 1032 } 1033 1034 static void 1035 sdhci_fsl_switch_tuning_block(device_t dev, bool enable) 1036 { 1037 struct sdhci_fsl_fdt_softc *sc; 1038 uint32_t reg; 1039 1040 sc = device_get_softc(dev); 1041 1042 reg = RD4(sc, SDHCI_FSL_TBCTL); 1043 1044 if (enable) 1045 reg |= SDHCI_FSL_TBCTL_TBEN; 1046 else 1047 reg &= ~SDHCI_FSL_TBCTL_TBEN; 1048 1049 WR4(sc, SDHCI_FSL_TBCTL, reg); 1050 } 1051 1052 static int 1053 sdhci_hw_tuning(struct sdhci_fsl_fdt_softc *sc, device_t bus, device_t child, 1054 bool hs400) 1055 { 1056 int error, retries; 1057 uint32_t reg; 1058 1059 retries = SDHCI_FSL_MAX_RETRIES; 1060 1061 /* Set SYSCTL2[EXTN] to start the tuning procedure. */ 1062 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1063 reg |= SDHCI_FSL_AUTOCERR_EXTN; 1064 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1065 1066 while (true) { 1067 /* Execute generic tuning to issue CMD19 and CMD21. */ 1068 error = sdhci_generic_tune(bus, child, hs400); 1069 if (error != 0) { 1070 device_printf(bus, "Generic tuning failed.\n"); 1071 return (error); 1072 } 1073 1074 /* 1075 * Tuning is done after a corresponding interrupt 1076 * is set. 1077 */ 1078 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_IRQSTAT, 1079 SDHCI_FSL_IRQSTAT_BRR, SDHCI_FSL_IRQSTAT_BRR); 1080 if (error) 1081 device_printf(sc->dev, 1082 "Timeout while waiting for hardware to finish tuning.\n"); 1083 1084 /* Clear IRQSTAT[BRR] register. */ 1085 reg = RD4(sc, SDHCI_FSL_IRQSTAT); 1086 reg &= ~SDHCI_FSL_IRQSTAT_BRR; 1087 WR4(sc, SDHCI_FSL_IRQSTAT, reg); 1088 1089 /* Check SYSCTL2[EXTN] register. */ 1090 if ((RD4(sc, SDHCI_FSL_AUTOCERR) & 1091 SDHCI_FSL_AUTOCERR_EXTN) == 0) 1092 break; 1093 1094 if (!retries--) { 1095 error = ENXIO; 1096 device_printf(bus, 1097 "Failed to execute HW tuning.\n"); 1098 break; 1099 } 1100 1101 DELAY(10); 1102 } 1103 1104 /* Check SYSCTL2[SMPCLKSEL]. */ 1105 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1106 if (!(reg & SDHCI_FSL_AUTOCERR_SMPCLKSEL)) { 1107 error = ENXIO; 1108 device_printf(bus, 1109 "Hardware tuning failed. Turning off tuning block\n"); 1110 sdhci_fsl_switch_tuning_block(bus, false); 1111 } else 1112 error = 0; 1113 1114 return (error); 1115 } 1116 1117 static int 1118 sdhci_fsl_sw_tuning(struct sdhci_fsl_fdt_softc *sc, device_t bus, 1119 device_t child, bool hs400, uint32_t wnd_start, uint32_t wnd_end) 1120 { 1121 uint32_t start_p, end_p, reg; 1122 int error; 1123 1124 wnd_start = 5 * sc->soc_data->baseclk_div; 1125 wnd_end = 3 * sc->soc_data->baseclk_div; 1126 1127 reg = RD4(sc, SDHCI_FSL_TBCTL); 1128 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1129 reg |= SDHCI_FSL_TBCTL_MODE_SW; 1130 WR4(sc, SDHCI_FSL_TBCTL, reg); 1131 1132 reg = RD4(sc, SDHCI_FSL_TBPTR); 1133 start_p = reg | SDHCI_FSL_TBPTR_WND_START; 1134 end_p = reg | SDHCI_FSL_TBPTR_WND_END; 1135 1136 if (abs(start_p - end_p) > (4 * sc->soc_data->baseclk_div + 2)) { 1137 wnd_start = 8 * sc->soc_data->baseclk_div; 1138 wnd_end = 4 * sc->soc_data->baseclk_div; 1139 } else { 1140 wnd_start = 5 * sc->soc_data->baseclk_div; 1141 wnd_end = 3 * sc->soc_data->baseclk_div; 1142 } 1143 1144 reg |= (wnd_start << 14); 1145 reg |= (wnd_end << 6); 1146 WR4(sc, SDHCI_FSL_TBPTR, reg); 1147 1148 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1149 reg |= SDHCI_FSL_AUTOCERR_EXTN | SDHCI_FSL_AUTOCERR_SMPCLKSEL; 1150 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1151 1152 error = sdhci_generic_tune(bus, child, hs400); 1153 if (error != 0) { 1154 device_printf(bus, 1155 "Failed to execute generic tune while performing software tuning.\n"); 1156 return (error); 1157 } 1158 1159 reg = RD4(sc, SDHCI_FSL_IRQSTAT); 1160 reg &= ~SDHCI_FSL_IRQSTAT_BRR; 1161 WR4(sc, SDHCI_FSL_IRQSTAT, reg); 1162 1163 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1164 if (!(reg & SDHCI_FSL_AUTOCERR_SMPCLKSEL)) { 1165 /* Error occured, need to disable tuning block. */ 1166 reg = RD4(sc, SDHCI_FSL_TBCTL); 1167 reg &= ~SDHCI_FSL_TBCTL_TBEN; 1168 WR4(sc, SDHCI_FSL_TBCTL, reg); 1169 error = ENXIO; 1170 } 1171 1172 return (error); 1173 } 1174 1175 static int 1176 sdhci_fsl_fdt_tune(device_t bus, device_t child, bool hs400) 1177 { 1178 uint32_t wnd_start, wnd_end, clk_divider, reg; 1179 struct sdhci_fsl_fdt_softc *sc; 1180 struct sdhci_slot *slot; 1181 int error; 1182 1183 sc = device_get_softc(bus); 1184 slot = device_get_ivars(child); 1185 error = 0; 1186 clk_divider = slot->max_clk / slot->clock; 1187 1188 /* For tuning mode SD clock divider must be within 3 to 16. */ 1189 if (clk_divider < 3 || clk_divider > 16) 1190 return (ENXIO); 1191 1192 if (hs400) 1193 sc->flags |= SDHCI_FSL_HS400_FLAG; 1194 1195 /* Disable clock. */ 1196 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1197 1198 /* Wait for PRSSTAT[SDSTB] to be set by hardware. */ 1199 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1200 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1201 if (error != 0) 1202 device_printf(bus, 1203 "Timeout while waiting for hardware.\n"); 1204 1205 /* Set ESDHCCTL[FAF] register. */ 1206 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1207 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1208 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1209 1210 /* Wait for ESDHC[FAF] to be cleared by hardware. */ 1211 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1212 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1213 if (error) 1214 device_printf(bus, 1215 "Timeout while waiting for hardware.\n"); 1216 1217 /* Set AUTOCERR[UHSM] register. */ 1218 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1219 reg &= ~SDHCI_FSL_AUTOCERR_UHMS; 1220 reg |= SDHCI_FSL_AUTOCERR_UHMS_HS200; 1221 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1222 1223 /* Set TBCTL[TB_EN] register and program valid tuning mode. */ 1224 reg = RD4(sc, SDHCI_FSL_TBCTL); 1225 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1226 reg |= SDHCI_FSL_TBCTL_TBEN | SDHCI_FSL_TBCTL_MODE_3; 1227 WR4(sc, SDHCI_FSL_TBCTL, reg); 1228 1229 /* Enable clock. */ 1230 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | sc->sdclk_bits); 1231 1232 /* Wait for clock to stabilize. */ 1233 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1234 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1235 if (error) 1236 device_printf(bus, 1237 "Timeout while waiting for clock to stabilize.\n"); 1238 1239 /* Perform hardware tuning. */ 1240 error = sdhci_hw_tuning(sc, bus, child, hs400); 1241 1242 reg = RD4(sc, SDHCI_FSL_TBPTR); 1243 wnd_start = reg & SDHCI_FSL_TBPTR_WND_START; 1244 wnd_end = reg & SDHCI_FSL_TBPTR_WND_END; 1245 1246 /* For erratum type2 affected platforms, check tuning pointer window. */ 1247 if (sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE2) { 1248 if (abs(wnd_start - wnd_end) > 1249 (4 * sc->soc_data->baseclk_div + 2)) 1250 error = ENXIO; 1251 } 1252 1253 if (error != 0 && 1254 (sc->soc_data->errata & 1255 (SDHCI_FSL_TUNING_ERRATUM_TYPE1 | 1256 SDHCI_FSL_TUNING_ERRATUM_TYPE2))) { 1257 /* If hardware tuning failed, try software tuning. */ 1258 error = sdhci_fsl_sw_tuning(sc, bus, child, hs400, wnd_start, 1259 wnd_end); 1260 if (error != 0) 1261 device_printf(bus, "Software tuning failed.\n"); 1262 } 1263 1264 if (error != 0) { 1265 sdhci_fsl_switch_tuning_block(bus, false); 1266 1267 return (error); 1268 } 1269 1270 if (hs400) { 1271 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1272 reg |= SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1273 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1274 1275 /* 1276 * Tuning block needs to be disabled now. 1277 * It will be enabled by set_uhs_signalling 1278 */ 1279 reg = RD4(sc, SDHCI_FSL_TBCTL); 1280 reg &= ~SDHCI_FSL_TBCTL_TBEN; 1281 WR4(sc, SDHCI_FSL_TBCTL, reg); 1282 } 1283 1284 return (0); 1285 } 1286 1287 static void 1288 sdhci_fsl_disable_hs400_mode(device_t dev, struct sdhci_fsl_fdt_softc *sc) 1289 { 1290 uint32_t reg; 1291 int error; 1292 1293 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1294 reg &= ~SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1295 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1296 1297 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1298 reg &= ~SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1299 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1300 1301 fsl_sdhc_fdt_set_clock(sc, &sc->slot, sc->sdclk_bits); 1302 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1303 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1304 if (error != 0) 1305 device_printf(dev, 1306 "Internal clock never stabilized.\n"); 1307 1308 reg = RD4(sc, SDHCI_FSL_TBCTL); 1309 reg &= ~SDHCI_FSL_TBCTL_HS400_EN; 1310 WR4(sc, SDHCI_FSL_TBCTL, reg); 1311 1312 fsl_sdhc_fdt_set_clock(sc, &sc->slot, SDHCI_CLOCK_CARD_EN | 1313 sc->sdclk_bits); 1314 1315 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1316 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1317 if (error != 0) 1318 device_printf(dev, 1319 "Internal clock never stabilized.\n"); 1320 1321 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1322 reg &= ~(SDHCI_FSL_DLLCFG0_EN | 1323 SDHCI_FSL_DLLCFG0_FREQ_SEL); 1324 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1325 1326 reg = RD4(sc, SDHCI_FSL_TBCTL); 1327 reg &= ~SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1328 WR4(sc, SDHCI_FSL_TBCTL, reg); 1329 1330 sdhci_fsl_switch_tuning_block(dev, false); 1331 } 1332 1333 static void 1334 sdhci_fsl_enable_hs400_mode(device_t dev, struct sdhci_slot *slot, 1335 struct sdhci_fsl_fdt_softc *sc) 1336 { 1337 uint32_t reg; 1338 int error; 1339 1340 sdhci_fsl_switch_tuning_block(dev, true); 1341 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1342 1343 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1344 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1345 if (error != 0) 1346 device_printf(dev, "Internal clock never stabilized.\n"); 1347 1348 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1349 sc->sdclk_bits); 1350 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1351 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1352 if (error != 0) 1353 device_printf(dev, "Internal clock never stabilized.\n"); 1354 1355 reg = sc->read(sc, SDHCI_FSL_DLLCFG0); 1356 reg |= SDHCI_FSL_DLLCFG0_EN | SDHCI_FSL_DLLCFG0_FREQ_SEL; 1357 sc->write(sc, SDHCI_FSL_DLLCFG0, reg); 1358 1359 DELAY(20); 1360 1361 reg = sc->read(sc, SDHCI_FSL_TBCTL); 1362 reg |= SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1363 sc->write(sc, SDHCI_FSL_TBCTL, reg); 1364 1365 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1366 1367 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1368 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1369 if (error != 0) 1370 device_printf(dev, 1371 "Timeout while waiting for clock to stabilize.\n"); 1372 1373 reg = sc->read(sc, SDHCI_FSL_ESDHC_CTRL); 1374 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1375 sc->write(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1376 1377 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1378 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1379 if (error != 0) 1380 device_printf(dev, 1381 "Timeout while waiting for hardware.\n"); 1382 1383 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1384 sc->sdclk_bits); 1385 1386 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1387 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1388 if (error != 0) 1389 device_printf(dev, 1390 "Timeout while waiting for clock to stabilize.\n"); 1391 1392 sdhci_generic_set_uhs_timing(dev, slot); 1393 sc->flags = SDHCI_FSL_HS400_DONE; 1394 } 1395 1396 static void 1397 sdhci_fsl_fdt_set_uhs_timing(device_t dev, struct sdhci_slot *slot) 1398 { 1399 struct sdhci_fsl_fdt_softc *sc; 1400 uint32_t reg; 1401 1402 sc = device_get_softc(dev); 1403 1404 if (sc->flags & SDHCI_FSL_HS400_DONE) 1405 return; 1406 1407 reg = RD4(sc, SDHCI_FSL_TBCTL); 1408 1409 if (slot->host.ios.timing == bus_timing_hs && 1410 (!(sc->flags & SDHCI_FSL_SWITCH_TO_HS400_FLAG)) && 1411 sc->last_mode >= bus_timing_mmc_hs200) { 1412 sdhci_fsl_switch_tuning_block(dev, false); 1413 1414 if (reg & SDHCI_FSL_TBCTL_HS400_EN) 1415 sdhci_fsl_disable_hs400_mode(dev, sc); 1416 1417 sc->flags |= SDHCI_FSL_SWITCH_TO_HS400_FLAG; 1418 1419 return; 1420 } 1421 1422 if ((slot->host.ios.timing == bus_timing_mmc_hs400) && 1423 sc->flags & SDHCI_FSL_SWITCH_TO_HS400_FLAG) { 1424 if (sc->last_mode < bus_timing_uhs_sdr50) { 1425 sc->last_mode = sc->slot.host.ios.timing; 1426 return; 1427 } 1428 1429 sdhci_fsl_enable_hs400_mode(dev, slot, sc); 1430 1431 } else 1432 sdhci_generic_set_uhs_timing(dev, slot); 1433 1434 sc->last_mode = sc->slot.host.ios.timing; 1435 } 1436 1437 static const device_method_t sdhci_fsl_fdt_methods[] = { 1438 /* Device interface. */ 1439 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe), 1440 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach), 1441 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach), 1442 1443 /* Bus interface. */ 1444 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar), 1445 DEVMETHOD(bus_write_ivar, sdhci_fsl_fdt_write_ivar), 1446 1447 /* MMC bridge interface. */ 1448 DEVMETHOD(mmcbr_request, sdhci_generic_request), 1449 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro), 1450 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 1451 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 1452 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq), 1453 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios), 1454 DEVMETHOD(mmcbr_tune, sdhci_fsl_fdt_tune), 1455 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 1456 1457 /* SDHCI accessors. */ 1458 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1), 1459 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2), 1460 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4), 1461 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4), 1462 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1), 1463 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2), 1464 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4), 1465 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4), 1466 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present), 1467 DEVMETHOD(sdhci_reset, sdhci_fsl_fdt_reset), 1468 DEVMETHOD(sdhci_set_uhs_timing, sdhci_fsl_fdt_set_uhs_timing), 1469 DEVMETHOD_END 1470 }; 1471 1472 static devclass_t sdhci_fsl_fdt_devclass; 1473 static driver_t sdhci_fsl_fdt_driver = { 1474 "sdhci_fsl_fdt", 1475 sdhci_fsl_fdt_methods, 1476 sizeof(struct sdhci_fsl_fdt_softc), 1477 }; 1478 1479 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, 1480 sdhci_fsl_fdt_devclass, NULL, NULL); 1481 SDHCI_DEPEND(sdhci_fsl_fdt); 1482 1483 #ifndef MMCCAM 1484 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt); 1485 #endif 1486