xref: /freebsd/sys/dev/sdhci/sdhci_fsl_fdt.c (revision 3332f1b444d4a73238e9f59cca27bfc95fe936bd)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2020 Alstom Group.
5  * Copyright (c) 2020 Semihalf.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include <sys/param.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41 
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 
45 #include <dev/extres/clk/clk.h>
46 #include <dev/mmc/bridge.h>
47 #include <dev/mmc/mmcbrvar.h>
48 #include <dev/mmc/mmc_fdt_helpers.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/sdhci/sdhci.h>
52 #include <dev/sdhci/sdhci_fdt_gpio.h>
53 
54 #include "mmcbr_if.h"
55 #include "sdhci_if.h"
56 
57 #define	RD4	(sc->read)
58 #define	WR4	(sc->write)
59 
60 #define	SDHCI_FSL_PRES_STATE		0x24
61 #define	SDHCI_FSL_PRES_SDSTB		(1 << 3)
62 #define	SDHCI_FSL_PRES_COMPAT_MASK	0x000f0f07
63 
64 #define	SDHCI_FSL_PROT_CTRL		0x28
65 #define	SDHCI_FSL_PROT_CTRL_WIDTH_1BIT	(0 << 1)
66 #define	SDHCI_FSL_PROT_CTRL_WIDTH_4BIT	(1 << 1)
67 #define	SDHCI_FSL_PROT_CTRL_WIDTH_8BIT	(2 << 1)
68 #define	SDHCI_FSL_PROT_CTRL_WIDTH_MASK	(3 << 1)
69 #define	SDHCI_FSL_PROT_CTRL_BYTE_SWAP	(0 << 4)
70 #define	SDHCI_FSL_PROT_CTRL_BYTE_NATIVE	(2 << 4)
71 #define	SDHCI_FSL_PROT_CTRL_BYTE_MASK	(3 << 4)
72 #define	SDHCI_FSL_PROT_CTRL_DMA_MASK	(3 << 8)
73 
74 #define	SDHCI_FSL_SYS_CTRL		0x2c
75 #define	SDHCI_FSL_CLK_IPGEN		(1 << 0)
76 #define	SDHCI_FSL_CLK_SDCLKEN		(1 << 3)
77 #define	SDHCI_FSL_CLK_DIVIDER_MASK	0x000000f0
78 #define	SDHCI_FSL_CLK_DIVIDER_SHIFT	4
79 #define	SDHCI_FSL_CLK_PRESCALE_MASK	0x0000ff00
80 #define	SDHCI_FSL_CLK_PRESCALE_SHIFT	8
81 
82 #define	SDHCI_FSL_WTMK_LVL		0x44
83 #define	SDHCI_FSL_WTMK_RD_512B		(0 << 0)
84 #define	SDHCI_FSL_WTMK_WR_512B		(0 << 15)
85 
86 #define	SDHCI_FSL_HOST_VERSION		0xfc
87 #define	SDHCI_FSL_VENDOR_V23		0x13
88 #define	SDHCI_FSL_CAPABILITIES2		0x114
89 
90 #define	SDHCI_FSL_TBCTL			0x120
91 #define	SDHCI_FSL_TBCTL_TBEN		(1 << 2)
92 
93 #define	SDHCI_FSL_ESDHC_CTRL		0x40c
94 #define	SDHCI_FSL_ESDHC_CTRL_SNOOP	(1 << 6)
95 #define	SDHCI_FSL_ESDHC_CTRL_CLK_DIV2	(1 << 19)
96 
97 #define SDHCI_FSL_CAN_VDD_MASK		\
98     (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330)
99 
100 struct sdhci_fsl_fdt_softc {
101 	device_t				dev;
102 	const struct sdhci_fsl_fdt_soc_data	*soc_data;
103 	struct resource				*mem_res;
104 	struct resource				*irq_res;
105 	void					*irq_cookie;
106 	uint32_t				baseclk_hz;
107 	uint32_t				maxclk_hz;
108 	struct sdhci_fdt_gpio			*gpio;
109 	struct sdhci_slot			slot;
110 	bool					slot_init_done;
111 	uint32_t				cmd_and_mode;
112 	uint16_t				sdclk_bits;
113 	struct mmc_helper			fdt_helper;
114 	uint8_t					vendor_ver;
115 
116 	uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t);
117 	void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t);
118 };
119 
120 struct sdhci_fsl_fdt_soc_data {
121 	int quirks;
122 	int baseclk_div;
123 };
124 
125 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = {
126 	.quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT |
127 	    SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
128 	.baseclk_div = 2,
129 };
130 
131 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = {
132 	.quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP,
133 	.baseclk_div = 2,
134 };
135 
136 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = {
137 	.quirks = 0,
138 	.baseclk_div = 1,
139 };
140 
141 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = {
142 	{"fsl,ls1028a-esdhc",	(uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data},
143 	{"fsl,ls1046a-esdhc",	(uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data},
144 	{"fsl,esdhc",		(uintptr_t)&sdhci_fsl_fdt_gen_data},
145 	{NULL,			0}
146 };
147 
148 static uint32_t
149 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
150 {
151 
152 	return (be32toh(bus_read_4(sc->mem_res, off)));
153 }
154 
155 static void
156 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
157 {
158 
159 	bus_write_4(sc->mem_res, off, htobe32(val));
160 }
161 
162 static uint32_t
163 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
164 {
165 
166 	return (bus_read_4(sc->mem_res, off));
167 }
168 
169 static void
170 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
171 {
172 
173 	bus_write_4(sc->mem_res, off, val);
174 }
175 
176 
177 static uint16_t
178 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc)
179 {
180 	uint16_t val;
181 
182 	val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN;
183 	if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)
184 		val |= SDHCI_CLOCK_INT_STABLE;
185 	if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)
186 		val |= SDHCI_CLOCK_CARD_EN;
187 
188 	return (val);
189 }
190 
191 /*
192  * Calculate clock prescaler and divisor values based on the following formula:
193  * `frequency = base clock / (prescaler * divisor)`.
194  */
195 #define	SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div)			\
196 	do {								\
197 		(pre) = (sc)->vendor_ver < SDHCI_FSL_VENDOR_V23 ? 2 : 1;\
198 		while ((freq) < (base) / ((pre) * 16) && (pre) < 256)	\
199 			(pre) <<= 1;					\
200 		/* div/pre can't both be set to 1, according to PM. */	\
201 		(div) = ((pre) == 1 ? 2 : 1);				\
202 		while ((freq) < (base) / ((pre) * (div)) && (div) < 16)	\
203 			++(div);					\
204 	} while (0)
205 
206 static void
207 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, struct sdhci_slot *slot,
208     uint16_t val)
209 {
210 	uint32_t prescale, div, val32;
211 
212 	sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK;
213 	val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
214 
215 	if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
216 		WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN);
217 		return;
218 	}
219 
220 	/*
221 	 * Ignore dividers provided by core in `sdhci_set_clock` and calculate
222 	 * them anew with higher accuracy.
223 	 */
224 	SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div);
225 
226 #ifdef DEBUG
227 	device_printf(sc->dev,
228 	    "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n",
229 	    slot->clock, sc->baseclk_hz / (prescale * div),
230 	    sc->baseclk_hz, prescale, div);
231 #endif
232 
233 	prescale >>= 1;
234 	div -= 1;
235 
236 	val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK);
237 	val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT;
238 	val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT;
239 	val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN;
240 	WR4(sc, SDHCI_CLOCK_CONTROL, val32);
241 }
242 
243 static uint8_t
244 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
245 {
246 	struct sdhci_fsl_fdt_softc *sc;
247 	uint32_t wrk32, val32;
248 
249 	sc = device_get_softc(dev);
250 
251 	switch (off) {
252 	case SDHCI_HOST_CONTROL:
253 		wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
254 		val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
255 		    SDHCI_CTRL_FORCE_CARD);
256 		if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT)
257 			val32 |= SDHCI_CTRL_4BITBUS;
258 		else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT)
259 			val32 |= SDHCI_CTRL_8BITBUS;
260 		return (val32);
261 	case SDHCI_POWER_CONTROL:
262 		return (SDHCI_POWER_ON | SDHCI_POWER_300);
263 	default:
264 		break;
265 	}
266 
267 	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);
268 }
269 
270 static uint16_t
271 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
272 {
273 	struct sdhci_fsl_fdt_softc *sc;
274 	uint32_t val32;
275 
276 	sc = device_get_softc(dev);
277 
278 	switch (off) {
279 	case SDHCI_CLOCK_CONTROL:
280 		return (sdhci_fsl_fdt_get_clock(sc));
281 	case SDHCI_HOST_VERSION:
282 		return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);
283 	case SDHCI_TRANSFER_MODE:
284 		return (sc->cmd_and_mode & UINT16_MAX);
285 	case SDHCI_COMMAND_FLAGS:
286 		return (sc->cmd_and_mode >> 16);
287 	case SDHCI_SLOT_INT_STATUS:
288 	/*
289 	 * eSDHC hardware manages only a single slot.
290 	 * Synthesize a slot interrupt status register for slot 1 below.
291 	 */
292 		val32 = RD4(sc, SDHCI_INT_STATUS);
293 		val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
294 		return (!!val32);
295 	default:
296 		return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX);
297 	}
298 }
299 
300 static uint32_t
301 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
302 {
303 	struct sdhci_fsl_fdt_softc *sc;
304 	uint32_t wrk32, val32;
305 
306 	sc = device_get_softc(dev);
307 
308 	if (off == SDHCI_BUFFER)
309 		return (bus_read_4(sc->mem_res, off));
310 	if (off == SDHCI_CAPABILITIES2)
311 		off = SDHCI_FSL_CAPABILITIES2;
312 
313 	val32 = RD4(sc, off);
314 
315 	if (off == SDHCI_PRESENT_STATE) {
316 		wrk32 = val32;
317 		val32 &= SDHCI_FSL_PRES_COMPAT_MASK;
318 		val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
319 		val32 |= (wrk32 << 1) & SDHCI_STATE_CMD;
320 	}
321 
322 	return (val32);
323 }
324 
325 static void
326 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
327     uint32_t *data, bus_size_t count)
328 {
329 	struct sdhci_fsl_fdt_softc *sc;
330 
331 	sc = device_get_softc(dev);
332 	bus_read_multi_4(sc->mem_res, off, data, count);
333 }
334 
335 static void
336 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
337     uint8_t val)
338 {
339 	struct sdhci_fsl_fdt_softc *sc;
340 	uint32_t val32;
341 
342 	sc = device_get_softc(dev);
343 
344 	switch (off) {
345 	case SDHCI_HOST_CONTROL:
346 		val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
347 		val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK;
348 		val32 |= (val & SDHCI_CTRL_LED);
349 
350 		if (val & SDHCI_CTRL_8BITBUS)
351 			val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT;
352 		else
353 			/* Bus width is 1-bit when this flag is not set. */
354 			val32 |= (val & SDHCI_CTRL_4BITBUS);
355 		/* Enable SDMA by masking out this field. */
356 		val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK;
357 		val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD);
358 		val32 |= (val & (SDHCI_CTRL_CARD_DET |
359 		    SDHCI_CTRL_FORCE_CARD));
360 		WR4(sc, SDHCI_FSL_PROT_CTRL, val32);
361 		return;
362 	case SDHCI_POWER_CONTROL:
363 		return;
364 	default:
365 		val32 = RD4(sc, off & ~3);
366 		val32 &= ~(UINT8_MAX << (off & 3) * 8);
367 		val32 |= (val << (off & 3) * 8);
368 		WR4(sc, off & ~3, val32);
369 		return;
370 	}
371 }
372 
373 static void
374 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
375     uint16_t val)
376 {
377 	struct sdhci_fsl_fdt_softc *sc;
378 	uint32_t val32;
379 
380 	sc = device_get_softc(dev);
381 
382 	switch (off) {
383 	case SDHCI_CLOCK_CONTROL:
384 		fsl_sdhc_fdt_set_clock(sc, slot, val);
385 		return;
386 	/*
387 	 * eSDHC hardware combines command and mode into a single
388 	 * register. Cache it here, so that command isn't written
389 	 * until after mode.
390 	 */
391 	case SDHCI_TRANSFER_MODE:
392 		sc->cmd_and_mode = val;
393 		return;
394 	case SDHCI_COMMAND_FLAGS:
395 		sc->cmd_and_mode =
396 		    (sc->cmd_and_mode & UINT16_MAX) | (val << 16);
397 		WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
398 		sc->cmd_and_mode = 0;
399 		return;
400 	default:
401 		val32 = RD4(sc, off & ~3);
402 		val32 &= ~(UINT16_MAX << (off & 3) * 8);
403 		val32 |= ((val & UINT16_MAX) << (off & 3) * 8);
404 		WR4(sc, off & ~3, val32);
405 		return;
406 	}
407 }
408 
409 static void
410 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
411     uint32_t val)
412 {
413 	struct sdhci_fsl_fdt_softc *sc;
414 
415 	sc = device_get_softc(dev);
416 
417 	switch (off) {
418 	case SDHCI_BUFFER:
419 		bus_write_4(sc->mem_res, off, val);
420 		return;
421 	/*
422 	 * eSDHC hardware lacks support for the SDMA buffer boundary
423 	 * feature and instead generates SDHCI_INT_DMA_END interrupts
424 	 * after each completed DMA data transfer.
425 	 * Since this duplicates the SDHCI_INT_DATA_END functionality,
426 	 * mask out the unneeded SDHCI_INT_DMA_END interrupt.
427 	 */
428 	case SDHCI_INT_ENABLE:
429 	case SDHCI_SIGNAL_ENABLE:
430 		val &= ~SDHCI_INT_DMA_END;
431 	/* FALLTHROUGH. */
432 	default:
433 		WR4(sc, off, val);
434 		return;
435 	}
436 }
437 
438 static void
439 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
440     bus_size_t off, uint32_t *data, bus_size_t count)
441 {
442 	struct sdhci_fsl_fdt_softc *sc;
443 
444 	sc = device_get_softc(dev);
445 	bus_write_multi_4(sc->mem_res, off, data, count);
446 }
447 
448 static void
449 sdhci_fsl_fdt_irq(void *arg)
450 {
451 	struct sdhci_fsl_fdt_softc *sc;
452 
453 	sc = arg;
454 	sdhci_generic_intr(&sc->slot);
455 	return;
456 }
457 
458 static int
459 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev)
460 {
461 	int err;
462 	struct sdhci_fsl_fdt_softc *sc;
463 	struct mmc_ios *ios;
464 	struct sdhci_slot *slot;
465 
466 	err = sdhci_generic_update_ios(brdev, reqdev);
467 	if (err != 0)
468 		return (err);
469 
470 	sc = device_get_softc(brdev);
471 	slot = device_get_ivars(reqdev);
472 	ios = &slot->host.ios;
473 
474 	switch (ios->power_mode) {
475 	case power_on:
476 		break;
477 	case power_off:
478 		if (bootverbose)
479 			device_printf(sc->dev, "Powering down sd/mmc\n");
480 
481 		if (sc->fdt_helper.vmmc_supply)
482 			regulator_disable(sc->fdt_helper.vmmc_supply);
483 		if (sc->fdt_helper.vqmmc_supply)
484 			regulator_disable(sc->fdt_helper.vqmmc_supply);
485 		break;
486 	case power_up:
487 		if (bootverbose)
488 			device_printf(sc->dev, "Powering up sd/mmc\n");
489 
490 		if (sc->fdt_helper.vmmc_supply)
491 			regulator_enable(sc->fdt_helper.vmmc_supply);
492 		if (sc->fdt_helper.vqmmc_supply)
493 			regulator_enable(sc->fdt_helper.vqmmc_supply);
494 		break;
495 	};
496 
497 	return (0);
498 }
499 
500 static int
501 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev)
502 {
503 	struct sdhci_fsl_fdt_softc *sc;
504 	struct sdhci_slot *slot;
505 	int uvolt, err;
506 
507 	sc = device_get_softc(brdev);
508 
509 	if (sc->fdt_helper.vqmmc_supply == NULL)
510 		return EOPNOTSUPP;
511 
512 	err = sdhci_generic_switch_vccq(brdev, reqdev);
513 	if (err != 0)
514 		return (err);
515 
516 	slot = device_get_ivars(reqdev);
517 	switch (slot->host.ios.vccq) {
518 	case vccq_180:
519 		uvolt = 1800000;
520 		break;
521 	case vccq_330:
522 		uvolt = 3300000;
523 		break;
524 	default:
525 		return EINVAL;
526 	}
527 
528 	err = regulator_set_voltage(sc->fdt_helper.vqmmc_supply, uvolt, uvolt);
529 	if (err != 0) {
530 		device_printf(sc->dev,
531 		    "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt);
532 		return (err);
533 	}
534 
535 	return (0);
536 }
537 
538 static int
539 sdhci_fsl_fdt_get_ro(device_t bus, device_t child)
540 {
541 	struct sdhci_fsl_fdt_softc *sc;
542 
543 	sc = device_get_softc(bus);
544 	return (sdhci_fdt_gpio_get_readonly(sc->gpio));
545 }
546 
547 static bool
548 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot)
549 {
550 	struct sdhci_fsl_fdt_softc *sc;
551 
552 	sc = device_get_softc(dev);
553 	return (sdhci_fdt_gpio_get_present(sc->gpio));
554 }
555 
556 static uint32_t
557 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len)
558 {
559 	uint32_t vdd_min, vdd_max;
560 	uint32_t vdd_mask = 0;
561 	int i;
562 
563 	/* Ranges are organized as pairs of values. */
564 	if ((len % 2) != 0) {
565 		device_printf(dev, "Invalid voltage range\n");
566 		return (0);
567 	}
568 	len = len / 2;
569 
570 	for (i = 0; i < len; i++) {
571 		vdd_min = vdd_ranges[2 * i];
572 		vdd_max = vdd_ranges[2 * i + 1];
573 
574 		if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 ||
575 		    vdd_max < 1650 || vdd_max > 3600) {
576 			device_printf(dev, "Voltage range %d - %d is out of bounds\n",
577 			    vdd_min, vdd_max);
578 			return (0);
579 		}
580 
581 		if (vdd_min <= 1800 && vdd_max >= 1800)
582 			vdd_mask |= SDHCI_CAN_VDD_180;
583 		if (vdd_min <= 3000 && vdd_max >= 3000)
584 			vdd_mask |= SDHCI_CAN_VDD_300;
585 		if (vdd_min <= 3300 && vdd_max >= 3300)
586 			vdd_mask |= SDHCI_CAN_VDD_330;
587 	}
588 
589 	return (vdd_mask);
590 }
591 
592 static void
593 sdhci_fsl_fdt_of_parse(device_t dev)
594 {
595 	struct sdhci_fsl_fdt_softc *sc;
596 	phandle_t node;
597 	pcell_t *voltage_ranges;
598 	uint32_t vdd_mask = 0;
599 	ssize_t num_ranges;
600 
601 	sc = device_get_softc(dev);
602 	node = ofw_bus_get_node(dev);
603 
604 	/* Call mmc_fdt_parse in order to get mmc related properties. */
605 	mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host);
606 
607 	sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot,
608 	    SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND);
609 	sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot,
610 	    SDHCI_CAPABILITIES2);
611 
612 	/* Parse the "voltage-ranges" dts property. */
613 	num_ranges = OF_getencprop_alloc(node, "voltage-ranges",
614 	    (void **) &voltage_ranges);
615 	if (num_ranges <= 0)
616 		return;
617 	vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges,
618 	    num_ranges / sizeof(uint32_t));
619 	OF_prop_free(voltage_ranges);
620 
621 	/* Overwrite voltage caps only if we got something from dts. */
622 	if (vdd_mask != 0 &&
623 	    (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) {
624 		sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK);
625 		sc->slot.caps |= vdd_mask;
626 		sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS;
627 	}
628 }
629 
630 static int
631 sdhci_fsl_fdt_attach(device_t dev)
632 {
633 	struct sdhci_fsl_fdt_softc *sc;
634 	struct mmc_host *host;
635 	uint32_t val, buf_order;
636 	uintptr_t ocd_data;
637 	uint64_t clk_hz;
638 	phandle_t node;
639 	int rid, ret;
640 	clk_t clk;
641 
642 	node = ofw_bus_get_node(dev);
643 	sc = device_get_softc(dev);
644 	ocd_data = ofw_bus_search_compatible(dev,
645 	    sdhci_fsl_fdt_compat_data)->ocd_data;
646 	sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data;
647 	sc->dev = dev;
648 	sc->slot.quirks = sc->soc_data->quirks;
649 	host = &sc->slot.host;
650 
651 	rid = 0;
652 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
653 	    RF_ACTIVE);
654 	if (sc->mem_res == NULL) {
655 		device_printf(dev,
656 		    "Could not allocate resources for controller\n");
657 		return (ENOMEM);
658 	}
659 
660 	rid = 0;
661 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
662 	    RF_ACTIVE);
663 	if (sc->irq_res == NULL) {
664 		device_printf(dev,
665 		    "Could not allocate irq resources for controller\n");
666 		ret = ENOMEM;
667 		goto err_free_mem;
668 	}
669 
670 	ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
671 	    NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie);
672 	if (ret != 0) {
673 		device_printf(dev, "Could not setup IRQ handler\n");
674 		goto err_free_irq_res;
675 	}
676 
677 	ret = clk_get_by_ofw_index(dev, node, 0, &clk);
678 	if (ret != 0) {
679 		device_printf(dev, "Parent clock not found\n");
680 		goto err_free_irq;
681 	}
682 
683 	ret = clk_get_freq(clk, &clk_hz);
684 	if (ret != 0) {
685 		device_printf(dev,
686 		    "Could not get parent clock frequency\n");
687 		goto err_free_irq;
688 	}
689 
690 	sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div;
691 
692 	/* Figure out eSDHC block endianness before we touch any HW regs. */
693 	if (OF_hasprop(node, "little-endian")) {
694 		sc->read = read_le;
695 		sc->write = write_le;
696 		buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE;
697 	} else {
698 		sc->read = read_be;
699 		sc->write = write_be;
700 		buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP;
701 	}
702 
703 	sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) &
704 	    SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
705 
706 	sdhci_fsl_fdt_of_parse(dev);
707 	sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz;
708 
709 	/*
710 	 * Setting this register affects byte order in SDHCI_BUFFER only.
711 	 * If the eSDHC block is connected over a big-endian bus, the data
712 	 * read from/written to the buffer will be already byte swapped.
713 	 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert
714 	 * the byte order again, resulting in a native byte order.
715 	 * The read/write callbacks accommodate for this behavior.
716 	 */
717 	val = RD4(sc, SDHCI_FSL_PROT_CTRL);
718 	val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK;
719 	WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order);
720 
721 	/*
722 	 * Gate the SD clock and set its source to
723 	 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set
724 	 * to match this.
725 	 */
726 	val = RD4(sc, SDHCI_CLOCK_CONTROL);
727 	WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN);
728 	val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
729 	WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2);
730 	sc->slot.max_clk = sc->maxclk_hz;
731 	sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
732 
733 	/*
734 	 * Set the buffer watermark level to 128 words (512 bytes) for both
735 	 * read and write. The hardware has a restriction that when the read or
736 	 * write ready status is asserted, that means you can read exactly the
737 	 * number of words set in the watermark register before you have to
738 	 * re-check the status and potentially wait for more data. The main
739 	 * sdhci driver provides no hook for doing status checking on less than
740 	 * a full block boundary, so we set the watermark level to be a full
741 	 * block. Reads and writes where the block size is less than the
742 	 * watermark size will work correctly too, no need to change the
743 	 * watermark for different size blocks. However, 128 is the maximum
744 	 * allowed for the watermark, so PIO is limitted to 512 byte blocks.
745 	 */
746 	WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B |
747 	    SDHCI_FSL_WTMK_RD_512B);
748 
749 	ret = sdhci_init_slot(dev, &sc->slot, 0);
750 	if (ret != 0)
751 		goto err_free_gpio;
752 	sc->slot_init_done = true;
753 	sdhci_start_slot(&sc->slot);
754 
755 	return (bus_generic_attach(dev));
756 
757 err_free_gpio:
758 	sdhci_fdt_gpio_teardown(sc->gpio);
759 err_free_irq:
760 	bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
761 err_free_irq_res:
762 	bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
763 err_free_mem:
764 	bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
765 	return (ret);
766 }
767 
768 static int
769 sdhci_fsl_fdt_detach(device_t dev)
770 {
771 	struct sdhci_fsl_fdt_softc *sc;
772 
773 	sc = device_get_softc(dev);
774 	if (sc->slot_init_done)
775 		sdhci_cleanup_slot(&sc->slot);
776 	if (sc->gpio != NULL)
777 		sdhci_fdt_gpio_teardown(sc->gpio);
778 	if (sc->irq_cookie != NULL)
779 		bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
780 	if (sc->irq_res != NULL)
781 		bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
782 	if (sc->mem_res != NULL)
783 		bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
784 	return (0);
785 }
786 
787 static int
788 sdhci_fsl_fdt_probe(device_t dev)
789 {
790 
791 	if (!ofw_bus_status_okay(dev))
792 		return (ENXIO);
793 
794 	if (!ofw_bus_search_compatible(dev,
795 	   sdhci_fsl_fdt_compat_data)->ocd_data)
796 		return (ENXIO);
797 
798 	device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller");
799 	return (BUS_PROBE_DEFAULT);
800 }
801 
802 static int
803 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which,
804     uintptr_t *result)
805 {
806 	struct sdhci_slot *slot = device_get_ivars(child);
807 
808 	if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) {
809 		/*
810 		 * In the absence of SDMA buffer boundary functionality,
811 		 * limit the maximum data length per read/write command
812 		 * to bounce buffer size.
813 		 */
814 		*result = howmany(slot->sdma_bbufsz, 512);
815 		return (0);
816 	}
817 	return (sdhci_generic_read_ivar(bus, child, which, result));
818 }
819 
820 static int
821 sdhci_fsl_fdt_write_ivar(device_t bus, device_t child, int which,
822     uintptr_t value)
823 {
824 	struct sdhci_fsl_fdt_softc *sc;
825 	struct sdhci_slot *slot = device_get_ivars(child);
826 	uint32_t prescale, div;
827 
828 	/* Don't depend on clock resolution limits from sdhci core. */
829 	if (which == MMCBR_IVAR_CLOCK) {
830 		if (value == 0) {
831 			slot->host.ios.clock = 0;
832 			return (0);
833 		}
834 
835 		sc = device_get_softc(bus);
836 
837 		SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div);
838 		slot->host.ios.clock = sc->baseclk_hz / (prescale * div);
839 
840 		return (0);
841 	}
842 
843 	return (sdhci_generic_write_ivar(bus, child, which, value));
844 }
845 
846 static void
847 sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask)
848 {
849 	struct sdhci_fsl_fdt_softc *sc;
850 	uint32_t val;
851 
852 	sdhci_generic_reset(dev, slot, mask);
853 
854 	if (!(mask & SDHCI_RESET_ALL))
855 		return;
856 
857 	sc = device_get_softc(dev);
858 
859 	/* Some registers have to be cleared by hand. */
860 	if (slot->version >= SDHCI_SPEC_300) {
861 		val = RD4(sc, SDHCI_FSL_TBCTL);
862 		val &= ~SDHCI_FSL_TBCTL_TBEN;
863 		WR4(sc, SDHCI_FSL_TBCTL, val);
864 	}
865 }
866 
867 static const device_method_t sdhci_fsl_fdt_methods[] = {
868 	/* Device interface. */
869 	DEVMETHOD(device_probe,			sdhci_fsl_fdt_probe),
870 	DEVMETHOD(device_attach,		sdhci_fsl_fdt_attach),
871 	DEVMETHOD(device_detach,		sdhci_fsl_fdt_detach),
872 
873 	/* Bus interface. */
874 	DEVMETHOD(bus_read_ivar,		sdhci_fsl_fdt_read_ivar),
875 	DEVMETHOD(bus_write_ivar,		sdhci_fsl_fdt_write_ivar),
876 
877 	/* MMC bridge interface. */
878 	DEVMETHOD(mmcbr_request,		sdhci_generic_request),
879 	DEVMETHOD(mmcbr_get_ro,			sdhci_fsl_fdt_get_ro),
880 	DEVMETHOD(mmcbr_acquire_host,		sdhci_generic_acquire_host),
881 	DEVMETHOD(mmcbr_release_host,		sdhci_generic_release_host),
882 	DEVMETHOD(mmcbr_switch_vccq,		sdhci_fsl_fdt_switch_vccq),
883 	DEVMETHOD(mmcbr_update_ios,		sdhci_fsl_fdt_update_ios),
884 
885 	/* SDHCI accessors. */
886 	DEVMETHOD(sdhci_read_1,			sdhci_fsl_fdt_read_1),
887 	DEVMETHOD(sdhci_read_2,			sdhci_fsl_fdt_read_2),
888 	DEVMETHOD(sdhci_read_4,			sdhci_fsl_fdt_read_4),
889 	DEVMETHOD(sdhci_read_multi_4,		sdhci_fsl_fdt_read_multi_4),
890 	DEVMETHOD(sdhci_write_1,		sdhci_fsl_fdt_write_1),
891 	DEVMETHOD(sdhci_write_2,		sdhci_fsl_fdt_write_2),
892 	DEVMETHOD(sdhci_write_4,		sdhci_fsl_fdt_write_4),
893 	DEVMETHOD(sdhci_write_multi_4,		sdhci_fsl_fdt_write_multi_4),
894 	DEVMETHOD(sdhci_get_card_present,	sdhci_fsl_fdt_get_card_present),
895 	DEVMETHOD(sdhci_reset,			sdhci_fsl_fdt_reset),
896 	DEVMETHOD_END
897 };
898 
899 static devclass_t sdhci_fsl_fdt_devclass;
900 static driver_t sdhci_fsl_fdt_driver = {
901 	"sdhci_fsl_fdt",
902 	sdhci_fsl_fdt_methods,
903 	sizeof(struct sdhci_fsl_fdt_softc),
904 };
905 
906 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver,
907     sdhci_fsl_fdt_devclass, NULL, NULL);
908 SDHCI_DEPEND(sdhci_fsl_fdt);
909 
910 #ifndef MMCCAM
911 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt);
912 #endif
913