1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 - 2021 Alstom Group. 5 * Copyright (c) 2020 - 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/sysctl.h> 38 #include <sys/taskqueue.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include <dev/extres/clk/clk.h> 44 #include <dev/extres/syscon/syscon.h> 45 #include <dev/mmc/bridge.h> 46 #include <dev/mmc/mmcbrvar.h> 47 #include <dev/mmc/mmc_fdt_helpers.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/sdhci/sdhci.h> 51 #include <dev/sdhci/sdhci_fdt_gpio.h> 52 53 #include "mmcbr_if.h" 54 #include "sdhci_if.h" 55 #include "syscon_if.h" 56 57 #define RD4 (sc->read) 58 #define WR4 (sc->write) 59 60 #define SDHCI_FSL_PRES_STATE 0x24 61 #define SDHCI_FSL_PRES_SDSTB (1 << 3) 62 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07 63 64 #define SDHCI_FSL_PROT_CTRL 0x28 65 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1) 66 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1) 67 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1) 68 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1) 69 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4) 70 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4) 71 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4) 72 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8) 73 #define SDHCI_FSL_PROT_CTRL_VOLT_SEL (1 << 10) 74 75 #define SDHCI_FSL_IRQSTAT 0x30 76 #define SDHCI_FSL_IRQSTAT_BRR (1 << 5) 77 #define SDHCI_FSL_IRQSTAT_CINTSEN (1 << 8) 78 #define SDHCI_FSL_IRQSTAT_RTE (1 << 12) 79 #define SDHCI_FSL_IRQSTAT_TNE (1 << 26) 80 81 #define SDHCI_FSL_SYS_CTRL 0x2c 82 #define SDHCI_FSL_CLK_IPGEN (1 << 0) 83 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3) 84 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0 85 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4 86 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00 87 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8 88 89 #define SDHCI_FSL_WTMK_LVL 0x44 90 #define SDHCI_FSL_WTMK_RD_512B (0 << 0) 91 #define SDHCI_FSL_WTMK_WR_512B (0 << 15) 92 93 #define SDHCI_FSL_AUTOCERR 0x3C 94 #define SDHCI_FSL_AUTOCERR_UHMS_HS200 (3 << 16) 95 #define SDHCI_FSL_AUTOCERR_UHMS (7 << 16) 96 #define SDHCI_FSL_AUTOCERR_EXTN (1 << 22) 97 #define SDHCI_FSL_AUTOCERR_SMPCLKSEL (1 << 23) 98 #define SDHCI_FSL_AUTOCERR_UHMS_SHIFT 16 99 100 #define SDHCI_FSL_HOST_VERSION 0xfc 101 #define SDHCI_FSL_VENDOR_V23 0x13 102 103 #define SDHCI_FSL_CAPABILITIES2 0x114 104 105 #define SDHCI_FSL_TBCTL 0x120 106 107 #define SDHCI_FSL_TBSTAT 0x124 108 #define SDHCI_FSL_TBCTL_TBEN (1 << 2) 109 #define SDHCI_FSL_TBCTL_HS400_EN (1 << 4) 110 #define SDHCI_FSL_TBCTL_SAMP_CMD_DQS (1 << 5) 111 #define SDHCI_FSL_TBCTL_HS400_WND_ADJ (1 << 6) 112 #define SDHCI_FSL_TBCTL_TB_MODE_MASK 0x3 113 #define SDHCI_FSL_TBCTL_MODE_1 0 114 #define SDHCI_FSL_TBCTL_MODE_2 1 115 #define SDHCI_FSL_TBCTL_MODE_3 2 116 #define SDHCI_FSL_TBCTL_MODE_SW 3 117 118 #define SDHCI_FSL_TBPTR 0x128 119 #define SDHCI_FSL_TBPTR_WND_START_SHIFT 8 120 #define SDHCI_FSL_TBPTR_WND_MASK 0x7F 121 122 #define SDHCI_FSL_SDCLKCTL 0x144 123 #define SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL (1 << 15) 124 #define SDHCI_FSL_SDCLKCTL_LPBK_CLK_SEL (1 << 31) 125 126 #define SDHCI_FSL_SDTIMINGCTL 0x148 127 #define SDHCI_FSL_SDTIMINGCTL_FLW_CTL (1 << 15) 128 129 #define SDHCI_FSL_DLLCFG0 0x160 130 #define SDHCI_FSL_DLLCFG0_FREQ_SEL (1 << 27) 131 #define SDHCI_FSL_DLLCFG0_RESET (1 << 30) 132 #define SDHCI_FSL_DLLCFG0_EN (1 << 31) 133 134 #define SDHCI_FSL_DLLCFG1 0x164 135 #define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31) 136 137 #define SDHCI_FSL_DLLSTAT0 0x170 138 #define SDHCI_FSL_DLLSTAT0_SLV_STS (1 << 27) 139 140 #define SDHCI_FSL_ESDHC_CTRL 0x40c 141 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) 142 #define SDHCI_FSL_ESDHC_CTRL_FAF (1 << 18) 143 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) 144 145 #define SCFG_SDHCIOVSELCR 0x408 146 #define SCFG_SDHCIOVSELCR_TGLEN (1 << 0) 147 #define SCFG_SDHCIOVSELCR_VS (1 << 31) 148 #define SCFG_SDHCIOVSELCR_VSELVAL_MASK (3 << 1) 149 #define SCFG_SDHCIOVSELCR_VSELVAL_1_8 0x0 150 #define SCFG_SDHCIOVSELCR_VSELVAL_3_3 0x2 151 152 #define SDHCI_FSL_CAN_VDD_MASK \ 153 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330) 154 155 /* Some platforms do not detect pulse width correctly. */ 156 #define SDHCI_FSL_UNRELIABLE_PULSE_DET (1 << 0) 157 /* On some platforms switching voltage to 1.8V is not supported */ 158 #define SDHCI_FSL_UNSUPP_1_8V (1 << 1) 159 /* Hardware tuning can fail, fallback to SW tuning in that case. */ 160 #define SDHCI_FSL_TUNING_ERRATUM_TYPE1 (1 << 2) 161 /* 162 * Pointer window might not be set properly on some platforms. 163 * Check window and perform SW tuning. 164 */ 165 #define SDHCI_FSL_TUNING_ERRATUM_TYPE2 (1 << 3) 166 /* 167 * In HS400 mode only 4, 8, 12 clock dividers can be used. 168 * Use the smallest value, bigger than requested in that case. 169 */ 170 #define SDHCI_FSL_HS400_LIMITED_CLK_DIV (1 << 4) 171 172 /* 173 * Some SoCs don't have a fixed regulator. Switching voltage 174 * requires special routine including syscon registers. 175 */ 176 #define SDHCI_FSL_MISSING_VCCQ_REG (1 << 5) 177 178 /* 179 * HS400 tuning is done in HS200 mode, but it has to be done using 180 * the target frequency. In order to apply the errata above we need to 181 * know the target mode during tuning procedure. Use this flag for just that. 182 */ 183 #define SDHCI_FSL_HS400_FLAG (1 << 0) 184 185 #define SDHCI_FSL_MAX_RETRIES 20000 /* DELAY(10) * this = 200ms */ 186 187 struct sdhci_fsl_fdt_softc { 188 device_t dev; 189 const struct sdhci_fsl_fdt_soc_data *soc_data; 190 struct resource *mem_res; 191 struct resource *irq_res; 192 void *irq_cookie; 193 uint32_t baseclk_hz; 194 uint32_t maxclk_hz; 195 struct sdhci_fdt_gpio *gpio; 196 struct sdhci_slot slot; 197 bool slot_init_done; 198 uint32_t cmd_and_mode; 199 uint16_t sdclk_bits; 200 struct mmc_helper fdt_helper; 201 uint32_t div_ratio; 202 uint8_t vendor_ver; 203 uint32_t flags; 204 205 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t); 206 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t); 207 }; 208 209 struct sdhci_fsl_fdt_soc_data { 210 int quirks; 211 int baseclk_div; 212 uint8_t errata; 213 char *syscon_compat; 214 }; 215 216 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1012a_soc_data = { 217 .quirks = 0, 218 .baseclk_div = 1, 219 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2, 220 .syscon_compat = "fsl,ls1012a-scfg", 221 }; 222 223 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = { 224 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | 225 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 226 .baseclk_div = 2, 227 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 228 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 229 }; 230 231 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { 232 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP, 233 .baseclk_div = 2, 234 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2, 235 .syscon_compat = "fsl,ls1046a-scfg", 236 }; 237 238 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_lx2160a_soc_data = { 239 .quirks = 0, 240 .baseclk_div = 2, 241 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET | 242 SDHCI_FSL_HS400_LIMITED_CLK_DIV, 243 }; 244 245 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = { 246 .quirks = 0, 247 .baseclk_div = 1, 248 }; 249 250 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = { 251 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data}, 252 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data}, 253 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data}, 254 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data}, 255 {NULL, 0} 256 }; 257 258 static uint32_t 259 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 260 { 261 262 return (be32toh(bus_read_4(sc->mem_res, off))); 263 } 264 265 static void 266 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 267 { 268 269 bus_write_4(sc->mem_res, off, htobe32(val)); 270 } 271 272 static uint32_t 273 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 274 { 275 276 return (bus_read_4(sc->mem_res, off)); 277 } 278 279 static void 280 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 281 { 282 283 bus_write_4(sc->mem_res, off, val); 284 } 285 286 287 static uint16_t 288 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc) 289 { 290 uint16_t val; 291 292 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN; 293 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) 294 val |= SDHCI_CLOCK_INT_STABLE; 295 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) 296 val |= SDHCI_CLOCK_CARD_EN; 297 298 return (val); 299 } 300 301 /* 302 * Calculate clock prescaler and divisor values based on the following formula: 303 * `frequency = base clock / (prescaler * divisor)`. 304 */ 305 #define SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div) \ 306 do { \ 307 (pre) = (sc)->vendor_ver < SDHCI_FSL_VENDOR_V23 ? 2 : 1;\ 308 while ((freq) < (base) / ((pre) * 16) && (pre) < 256) \ 309 (pre) <<= 1; \ 310 /* div/pre can't both be set to 1, according to PM. */ \ 311 (div) = ((pre) == 1 ? 2 : 1); \ 312 while ((freq) < (base) / ((pre) * (div)) && (div) < 16) \ 313 ++(div); \ 314 } while (0) 315 316 static void 317 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, struct sdhci_slot *slot, 318 uint16_t val) 319 { 320 uint32_t prescale, div, val32, div_ratio; 321 322 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK; 323 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 324 325 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 326 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 327 return; 328 } 329 330 /* 331 * Ignore dividers provided by core in `sdhci_set_clock` and calculate 332 * them anew with higher accuracy. 333 */ 334 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div); 335 336 div_ratio = prescale * div; 337 338 /* 339 * According to limited clock division erratum, clock dividers in hs400 340 * can be only 4, 8 or 12 341 */ 342 if ((sc->soc_data->errata & SDHCI_FSL_HS400_LIMITED_CLK_DIV) && 343 (sc->slot.host.ios.timing == bus_timing_mmc_hs400 || 344 (sc->flags & SDHCI_FSL_HS400_FLAG))) { 345 if (div_ratio <= 4) { 346 prescale = 4; 347 div = 1; 348 } else if (div_ratio <= 8) { 349 prescale = 4; 350 div = 2; 351 } else if (div_ratio <= 12) { 352 prescale = 4; 353 div = 3; 354 } else { 355 device_printf(sc->dev, "Unsupported clock divider.\n"); 356 } 357 } 358 359 sc->div_ratio = prescale * div; 360 if (bootverbose) 361 device_printf(sc->dev, 362 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", 363 slot->clock, sc->baseclk_hz / (prescale * div), 364 sc->baseclk_hz, prescale, div); 365 366 prescale >>= 1; 367 div -= 1; 368 369 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK); 370 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT; 371 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT; 372 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN; 373 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 374 } 375 376 static uint8_t 377 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 378 { 379 struct sdhci_fsl_fdt_softc *sc; 380 uint32_t wrk32, val32; 381 382 sc = device_get_softc(dev); 383 384 switch (off) { 385 case SDHCI_HOST_CONTROL: 386 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 387 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 388 SDHCI_CTRL_FORCE_CARD); 389 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT) 390 val32 |= SDHCI_CTRL_4BITBUS; 391 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT) 392 val32 |= SDHCI_CTRL_8BITBUS; 393 return (val32); 394 case SDHCI_POWER_CONTROL: 395 return (SDHCI_POWER_ON | SDHCI_POWER_300); 396 default: 397 break; 398 } 399 400 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); 401 } 402 403 static uint16_t 404 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 405 { 406 struct sdhci_fsl_fdt_softc *sc; 407 uint32_t val32; 408 409 sc = device_get_softc(dev); 410 411 switch (off) { 412 case SDHCI_CLOCK_CONTROL: 413 return (sdhci_fsl_fdt_get_clock(sc)); 414 case SDHCI_HOST_VERSION: 415 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); 416 case SDHCI_TRANSFER_MODE: 417 return (sc->cmd_and_mode & UINT16_MAX); 418 case SDHCI_COMMAND_FLAGS: 419 return (sc->cmd_and_mode >> 16); 420 case SDHCI_SLOT_INT_STATUS: 421 /* 422 * eSDHC hardware manages only a single slot. 423 * Synthesize a slot interrupt status register for slot 1 below. 424 */ 425 val32 = RD4(sc, SDHCI_INT_STATUS); 426 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 427 return (!!val32); 428 default: 429 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); 430 } 431 } 432 433 static uint32_t 434 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 435 { 436 struct sdhci_fsl_fdt_softc *sc; 437 uint32_t wrk32, val32; 438 439 sc = device_get_softc(dev); 440 441 if (off == SDHCI_BUFFER) 442 return (bus_read_4(sc->mem_res, off)); 443 if (off == SDHCI_CAPABILITIES2) 444 off = SDHCI_FSL_CAPABILITIES2; 445 446 val32 = RD4(sc, off); 447 448 if (off == SDHCI_PRESENT_STATE) { 449 wrk32 = val32; 450 val32 &= SDHCI_FSL_PRES_COMPAT_MASK; 451 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 452 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD; 453 } 454 455 return (val32); 456 } 457 458 static void 459 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 460 uint32_t *data, bus_size_t count) 461 { 462 struct sdhci_fsl_fdt_softc *sc; 463 464 sc = device_get_softc(dev); 465 bus_read_multi_4(sc->mem_res, off, data, count); 466 } 467 468 static void 469 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 470 uint8_t val) 471 { 472 struct sdhci_fsl_fdt_softc *sc; 473 uint32_t val32; 474 475 sc = device_get_softc(dev); 476 477 switch (off) { 478 case SDHCI_HOST_CONTROL: 479 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 480 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK; 481 val32 |= (val & SDHCI_CTRL_LED); 482 483 if (val & SDHCI_CTRL_8BITBUS) 484 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT; 485 else 486 /* Bus width is 1-bit when this flag is not set. */ 487 val32 |= (val & SDHCI_CTRL_4BITBUS); 488 /* Enable SDMA by masking out this field. */ 489 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK; 490 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); 491 val32 |= (val & (SDHCI_CTRL_CARD_DET | 492 SDHCI_CTRL_FORCE_CARD)); 493 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 494 return; 495 case SDHCI_POWER_CONTROL: 496 return; 497 default: 498 val32 = RD4(sc, off & ~3); 499 val32 &= ~(UINT8_MAX << (off & 3) * 8); 500 val32 |= (val << (off & 3) * 8); 501 WR4(sc, off & ~3, val32); 502 return; 503 } 504 } 505 506 static void 507 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 508 uint16_t val) 509 { 510 struct sdhci_fsl_fdt_softc *sc; 511 uint32_t val32; 512 513 sc = device_get_softc(dev); 514 515 switch (off) { 516 case SDHCI_CLOCK_CONTROL: 517 fsl_sdhc_fdt_set_clock(sc, slot, val); 518 return; 519 /* 520 * eSDHC hardware combines command and mode into a single 521 * register. Cache it here, so that command isn't written 522 * until after mode. 523 */ 524 case SDHCI_TRANSFER_MODE: 525 sc->cmd_and_mode = val; 526 return; 527 case SDHCI_COMMAND_FLAGS: 528 sc->cmd_and_mode = 529 (sc->cmd_and_mode & UINT16_MAX) | (val << 16); 530 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 531 sc->cmd_and_mode = 0; 532 return; 533 case SDHCI_HOST_CONTROL2: 534 /* 535 * Switching to HS400 requires a special procedure, 536 * which is done in sdhci_fsl_fdt_set_uhs_timing. 537 */ 538 if ((val & SDHCI_CTRL2_UHS_MASK) == SDHCI_CTRL2_MMC_HS400) 539 val &= ~SDHCI_CTRL2_MMC_HS400; 540 default: 541 val32 = RD4(sc, off & ~3); 542 val32 &= ~(UINT16_MAX << (off & 3) * 8); 543 val32 |= ((val & UINT16_MAX) << (off & 3) * 8); 544 WR4(sc, off & ~3, val32); 545 return; 546 } 547 } 548 549 static void 550 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 551 uint32_t val) 552 { 553 struct sdhci_fsl_fdt_softc *sc; 554 555 sc = device_get_softc(dev); 556 557 switch (off) { 558 case SDHCI_BUFFER: 559 bus_write_4(sc->mem_res, off, val); 560 return; 561 /* 562 * eSDHC hardware lacks support for the SDMA buffer boundary 563 * feature and instead generates SDHCI_INT_DMA_END interrupts 564 * after each completed DMA data transfer. 565 * Since this duplicates the SDHCI_INT_DATA_END functionality, 566 * mask out the unneeded SDHCI_INT_DMA_END interrupt. 567 */ 568 case SDHCI_INT_ENABLE: 569 case SDHCI_SIGNAL_ENABLE: 570 val &= ~SDHCI_INT_DMA_END; 571 /* FALLTHROUGH. */ 572 default: 573 WR4(sc, off, val); 574 return; 575 } 576 } 577 578 static void 579 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 580 bus_size_t off, uint32_t *data, bus_size_t count) 581 { 582 struct sdhci_fsl_fdt_softc *sc; 583 584 sc = device_get_softc(dev); 585 bus_write_multi_4(sc->mem_res, off, data, count); 586 } 587 588 static void 589 sdhci_fsl_fdt_irq(void *arg) 590 { 591 struct sdhci_fsl_fdt_softc *sc; 592 593 sc = arg; 594 sdhci_generic_intr(&sc->slot); 595 return; 596 } 597 598 static int 599 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev) 600 { 601 int err; 602 struct sdhci_fsl_fdt_softc *sc; 603 struct mmc_ios *ios; 604 struct sdhci_slot *slot; 605 606 err = sdhci_generic_update_ios(brdev, reqdev); 607 if (err != 0) 608 return (err); 609 610 sc = device_get_softc(brdev); 611 slot = device_get_ivars(reqdev); 612 ios = &slot->host.ios; 613 614 switch (ios->power_mode) { 615 case power_on: 616 break; 617 case power_off: 618 if (bootverbose) 619 device_printf(sc->dev, "Powering down sd/mmc\n"); 620 621 if (sc->fdt_helper.vmmc_supply) 622 regulator_disable(sc->fdt_helper.vmmc_supply); 623 if (sc->fdt_helper.vqmmc_supply) 624 regulator_disable(sc->fdt_helper.vqmmc_supply); 625 break; 626 case power_up: 627 if (bootverbose) 628 device_printf(sc->dev, "Powering up sd/mmc\n"); 629 630 if (sc->fdt_helper.vmmc_supply) 631 regulator_enable(sc->fdt_helper.vmmc_supply); 632 if (sc->fdt_helper.vqmmc_supply) 633 regulator_enable(sc->fdt_helper.vqmmc_supply); 634 break; 635 }; 636 637 return (0); 638 } 639 640 static int 641 sdhci_fsl_fdt_switch_syscon_voltage(device_t dev, 642 struct sdhci_fsl_fdt_softc *sc, enum mmc_vccq vccq) 643 { 644 struct syscon *syscon; 645 phandle_t syscon_node; 646 uint32_t reg; 647 648 if (sc->soc_data->syscon_compat == NULL) { 649 device_printf(dev, "Empty syscon compat string.\n"); 650 return (ENXIO); 651 } 652 653 syscon_node = ofw_bus_find_compatible(OF_finddevice("/"), 654 sc->soc_data->syscon_compat); 655 656 if (syscon_get_by_ofw_node(dev, syscon_node, &syscon) != 0) { 657 device_printf(dev, "Could not find syscon node.\n"); 658 return (ENXIO); 659 } 660 661 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 662 reg &= ~SCFG_SDHCIOVSELCR_VSELVAL_MASK; 663 reg |= SCFG_SDHCIOVSELCR_TGLEN; 664 665 switch (vccq) { 666 case vccq_180: 667 reg |= SCFG_SDHCIOVSELCR_VSELVAL_1_8; 668 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 669 670 DELAY(5000); 671 672 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 673 reg |= SCFG_SDHCIOVSELCR_VS; 674 break; 675 case vccq_330: 676 reg |= SCFG_SDHCIOVSELCR_VSELVAL_3_3; 677 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 678 679 DELAY(5000); 680 681 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR); 682 reg &= ~SCFG_SDHCIOVSELCR_VS; 683 break; 684 default: 685 device_printf(dev, "Unsupported voltage requested.\n"); 686 return (ENXIO); 687 } 688 689 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg); 690 691 return (0); 692 } 693 694 static int 695 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev) 696 { 697 struct sdhci_fsl_fdt_softc *sc; 698 struct sdhci_slot *slot; 699 regulator_t vqmmc_supply; 700 uint32_t val_old, val; 701 int uvolt, err = 0; 702 703 sc = device_get_softc(brdev); 704 slot = device_get_ivars(reqdev); 705 706 val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL); 707 708 switch (slot->host.ios.vccq) { 709 case vccq_180: 710 if (sc->soc_data->errata & SDHCI_FSL_UNSUPP_1_8V) 711 return (EOPNOTSUPP); 712 713 val |= SDHCI_FSL_PROT_CTRL_VOLT_SEL; 714 uvolt = 1800000; 715 break; 716 case vccq_330: 717 val &= ~SDHCI_FSL_PROT_CTRL_VOLT_SEL; 718 uvolt = 3300000; 719 break; 720 default: 721 return (EOPNOTSUPP); 722 } 723 724 WR4(sc, SDHCI_FSL_PROT_CTRL, val); 725 726 if (sc->soc_data->errata & SDHCI_FSL_MISSING_VCCQ_REG) { 727 err = sdhci_fsl_fdt_switch_syscon_voltage(brdev, sc, 728 slot->host.ios.vccq); 729 if (err != 0) 730 goto vccq_fail; 731 } 732 733 vqmmc_supply = sc->fdt_helper.vqmmc_supply; 734 /* 735 * Even though we expect to find a fixed regulator in this controller 736 * family, let's play safe. 737 */ 738 if (vqmmc_supply != NULL) { 739 err = regulator_set_voltage(vqmmc_supply, uvolt, uvolt); 740 if (err != 0) 741 goto vccq_fail; 742 } 743 744 return (0); 745 746 vccq_fail: 747 device_printf(sc->dev, "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt); 748 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old); 749 750 return (err); 751 } 752 753 static int 754 sdhci_fsl_fdt_get_ro(device_t bus, device_t child) 755 { 756 struct sdhci_fsl_fdt_softc *sc; 757 758 sc = device_get_softc(bus); 759 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 760 } 761 762 static bool 763 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot) 764 { 765 struct sdhci_fsl_fdt_softc *sc; 766 767 sc = device_get_softc(dev); 768 return (sdhci_fdt_gpio_get_present(sc->gpio)); 769 } 770 771 static uint32_t 772 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len) 773 { 774 uint32_t vdd_min, vdd_max; 775 uint32_t vdd_mask = 0; 776 int i; 777 778 /* Ranges are organized as pairs of values. */ 779 if ((len % 2) != 0) { 780 device_printf(dev, "Invalid voltage range\n"); 781 return (0); 782 } 783 len = len / 2; 784 785 for (i = 0; i < len; i++) { 786 vdd_min = vdd_ranges[2 * i]; 787 vdd_max = vdd_ranges[2 * i + 1]; 788 789 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 || 790 vdd_max < 1650 || vdd_max > 3600) { 791 device_printf(dev, "Voltage range %d - %d is out of bounds\n", 792 vdd_min, vdd_max); 793 return (0); 794 } 795 796 if (vdd_min <= 1800 && vdd_max >= 1800) 797 vdd_mask |= SDHCI_CAN_VDD_180; 798 if (vdd_min <= 3000 && vdd_max >= 3000) 799 vdd_mask |= SDHCI_CAN_VDD_300; 800 if (vdd_min <= 3300 && vdd_max >= 3300) 801 vdd_mask |= SDHCI_CAN_VDD_330; 802 } 803 804 return (vdd_mask); 805 } 806 807 static void 808 sdhci_fsl_fdt_of_parse(device_t dev) 809 { 810 struct sdhci_fsl_fdt_softc *sc; 811 phandle_t node; 812 pcell_t *voltage_ranges; 813 uint32_t vdd_mask = 0; 814 ssize_t num_ranges; 815 816 sc = device_get_softc(dev); 817 node = ofw_bus_get_node(dev); 818 819 /* Call mmc_fdt_parse in order to get mmc related properties. */ 820 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host); 821 822 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot, 823 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND); 824 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot, 825 SDHCI_CAPABILITIES2); 826 827 /* Parse the "voltage-ranges" dts property. */ 828 num_ranges = OF_getencprop_alloc(node, "voltage-ranges", 829 (void **) &voltage_ranges); 830 if (num_ranges <= 0) 831 return; 832 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges, 833 num_ranges / sizeof(uint32_t)); 834 OF_prop_free(voltage_ranges); 835 836 /* Overwrite voltage caps only if we got something from dts. */ 837 if (vdd_mask != 0 && 838 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) { 839 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK); 840 sc->slot.caps |= vdd_mask; 841 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS; 842 } 843 } 844 845 static int 846 sdhci_fsl_poll_register(struct sdhci_fsl_fdt_softc *sc, 847 uint32_t reg, uint32_t mask, int value) 848 { 849 int retries; 850 851 retries = SDHCI_FSL_MAX_RETRIES; 852 853 while ((RD4(sc, reg) & mask) != value) { 854 if (!retries--) 855 return (ENXIO); 856 857 DELAY(10); 858 } 859 860 return (0); 861 } 862 863 static int 864 sdhci_fsl_fdt_attach(device_t dev) 865 { 866 struct sdhci_fsl_fdt_softc *sc; 867 struct mmc_host *host; 868 uint32_t val, buf_order; 869 uintptr_t ocd_data; 870 uint64_t clk_hz; 871 phandle_t node; 872 int rid, ret; 873 clk_t clk; 874 875 node = ofw_bus_get_node(dev); 876 sc = device_get_softc(dev); 877 ocd_data = ofw_bus_search_compatible(dev, 878 sdhci_fsl_fdt_compat_data)->ocd_data; 879 sc->dev = dev; 880 sc->flags = 0; 881 host = &sc->slot.host; 882 rid = 0; 883 884 /* 885 * LX2160A needs its own soc_data in order to apply SoC 886 * specific quriks. Since the controller is identified 887 * only with a generic compatible string we need to do this dance here. 888 */ 889 if (ofw_bus_node_is_compatible(OF_finddevice("/"), "fsl,lx2160a")) 890 sc->soc_data = &sdhci_fsl_fdt_lx2160a_soc_data; 891 else 892 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data; 893 894 sc->slot.quirks = sc->soc_data->quirks; 895 896 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 897 RF_ACTIVE); 898 if (sc->mem_res == NULL) { 899 device_printf(dev, 900 "Could not allocate resources for controller\n"); 901 return (ENOMEM); 902 } 903 904 rid = 0; 905 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 906 RF_ACTIVE); 907 if (sc->irq_res == NULL) { 908 device_printf(dev, 909 "Could not allocate irq resources for controller\n"); 910 ret = ENOMEM; 911 goto err_free_mem; 912 } 913 914 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 915 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie); 916 if (ret != 0) { 917 device_printf(dev, "Could not setup IRQ handler\n"); 918 goto err_free_irq_res; 919 } 920 921 ret = clk_get_by_ofw_index(dev, node, 0, &clk); 922 if (ret != 0) { 923 device_printf(dev, "Parent clock not found\n"); 924 goto err_free_irq; 925 } 926 927 ret = clk_get_freq(clk, &clk_hz); 928 if (ret != 0) { 929 device_printf(dev, 930 "Could not get parent clock frequency\n"); 931 goto err_free_irq; 932 } 933 934 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div; 935 936 /* Figure out eSDHC block endianness before we touch any HW regs. */ 937 if (OF_hasprop(node, "little-endian")) { 938 sc->read = read_le; 939 sc->write = write_le; 940 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE; 941 } else { 942 sc->read = read_be; 943 sc->write = write_be; 944 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP; 945 } 946 947 sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) & 948 SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; 949 950 sdhci_fsl_fdt_of_parse(dev); 951 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz; 952 953 /* 954 * Setting this register affects byte order in SDHCI_BUFFER only. 955 * If the eSDHC block is connected over a big-endian bus, the data 956 * read from/written to the buffer will be already byte swapped. 957 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert 958 * the byte order again, resulting in a native byte order. 959 * The read/write callbacks accommodate for this behavior. 960 */ 961 val = RD4(sc, SDHCI_FSL_PROT_CTRL); 962 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK; 963 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 964 965 /* 966 * Gate the SD clock and set its source to 967 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set 968 * to match this. 969 */ 970 val = RD4(sc, SDHCI_CLOCK_CONTROL); 971 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); 972 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 973 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); 974 sc->slot.max_clk = sc->maxclk_hz; 975 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 976 977 /* 978 * Set the buffer watermark level to 128 words (512 bytes) for both 979 * read and write. The hardware has a restriction that when the read or 980 * write ready status is asserted, that means you can read exactly the 981 * number of words set in the watermark register before you have to 982 * re-check the status and potentially wait for more data. The main 983 * sdhci driver provides no hook for doing status checking on less than 984 * a full block boundary, so we set the watermark level to be a full 985 * block. Reads and writes where the block size is less than the 986 * watermark size will work correctly too, no need to change the 987 * watermark for different size blocks. However, 128 is the maximum 988 * allowed for the watermark, so PIO is limitted to 512 byte blocks. 989 */ 990 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | 991 SDHCI_FSL_WTMK_RD_512B); 992 993 ret = sdhci_init_slot(dev, &sc->slot, 0); 994 if (ret != 0) 995 goto err_free_gpio; 996 sc->slot_init_done = true; 997 sdhci_start_slot(&sc->slot); 998 999 return (bus_generic_attach(dev)); 1000 1001 err_free_gpio: 1002 sdhci_fdt_gpio_teardown(sc->gpio); 1003 err_free_irq: 1004 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 1005 err_free_irq_res: 1006 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 1007 err_free_mem: 1008 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 1009 return (ret); 1010 } 1011 1012 static int 1013 sdhci_fsl_fdt_detach(device_t dev) 1014 { 1015 struct sdhci_fsl_fdt_softc *sc; 1016 1017 sc = device_get_softc(dev); 1018 if (sc->slot_init_done) 1019 sdhci_cleanup_slot(&sc->slot); 1020 if (sc->gpio != NULL) 1021 sdhci_fdt_gpio_teardown(sc->gpio); 1022 if (sc->irq_cookie != NULL) 1023 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 1024 if (sc->irq_res != NULL) 1025 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 1026 if (sc->mem_res != NULL) 1027 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 1028 return (0); 1029 } 1030 1031 static int 1032 sdhci_fsl_fdt_probe(device_t dev) 1033 { 1034 1035 if (!ofw_bus_status_okay(dev)) 1036 return (ENXIO); 1037 1038 if (!ofw_bus_search_compatible(dev, 1039 sdhci_fsl_fdt_compat_data)->ocd_data) 1040 return (ENXIO); 1041 1042 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller"); 1043 return (BUS_PROBE_DEFAULT); 1044 } 1045 1046 static int 1047 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which, 1048 uintptr_t *result) 1049 { 1050 struct sdhci_slot *slot = device_get_ivars(child); 1051 1052 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) { 1053 /* 1054 * In the absence of SDMA buffer boundary functionality, 1055 * limit the maximum data length per read/write command 1056 * to bounce buffer size. 1057 */ 1058 *result = howmany(slot->sdma_bbufsz, 512); 1059 return (0); 1060 } 1061 return (sdhci_generic_read_ivar(bus, child, which, result)); 1062 } 1063 1064 static int 1065 sdhci_fsl_fdt_write_ivar(device_t bus, device_t child, int which, 1066 uintptr_t value) 1067 { 1068 struct sdhci_fsl_fdt_softc *sc; 1069 struct sdhci_slot *slot = device_get_ivars(child); 1070 uint32_t prescale, div; 1071 1072 /* Don't depend on clock resolution limits from sdhci core. */ 1073 if (which == MMCBR_IVAR_CLOCK) { 1074 if (value == 0) { 1075 slot->host.ios.clock = 0; 1076 return (0); 1077 } 1078 1079 sc = device_get_softc(bus); 1080 1081 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div); 1082 slot->host.ios.clock = sc->baseclk_hz / (prescale * div); 1083 1084 return (0); 1085 } 1086 1087 return (sdhci_generic_write_ivar(bus, child, which, value)); 1088 } 1089 1090 static void 1091 sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask) 1092 { 1093 struct sdhci_fsl_fdt_softc *sc; 1094 uint32_t val; 1095 1096 sdhci_generic_reset(dev, slot, mask); 1097 1098 if (!(mask & SDHCI_RESET_ALL)) 1099 return; 1100 1101 sc = device_get_softc(dev); 1102 1103 /* Some registers have to be cleared by hand. */ 1104 if (slot->version >= SDHCI_SPEC_300) { 1105 val = RD4(sc, SDHCI_FSL_TBCTL); 1106 val &= ~SDHCI_FSL_TBCTL_TBEN; 1107 WR4(sc, SDHCI_FSL_TBCTL, val); 1108 } 1109 1110 /* 1111 * Pulse width detection is not reliable on some boards. Perform 1112 * workaround by clearing register's bit according to errata. 1113 */ 1114 if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) { 1115 val = RD4(sc, SDHCI_FSL_DLLCFG1); 1116 val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH; 1117 WR4(sc, SDHCI_FSL_DLLCFG1, val); 1118 } 1119 1120 sc->flags = 0; 1121 } 1122 1123 static void 1124 sdhci_fsl_switch_tuning_block(device_t dev, bool enable) 1125 { 1126 struct sdhci_fsl_fdt_softc *sc; 1127 uint32_t reg; 1128 1129 sc = device_get_softc(dev); 1130 1131 reg = RD4(sc, SDHCI_FSL_TBCTL); 1132 1133 if (enable) 1134 reg |= SDHCI_FSL_TBCTL_TBEN; 1135 else 1136 reg &= ~SDHCI_FSL_TBCTL_TBEN; 1137 1138 WR4(sc, SDHCI_FSL_TBCTL, reg); 1139 } 1140 1141 static int 1142 sdhci_fsl_sw_tuning(struct sdhci_fsl_fdt_softc *sc, device_t bus, 1143 device_t child, bool hs400, uint32_t wnd_start, uint32_t wnd_end) 1144 { 1145 uint32_t reg; 1146 int error; 1147 1148 if (sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE1 || 1149 abs(wnd_start - wnd_end) <= (4 * sc->div_ratio + 2)) { 1150 wnd_start = 5 * sc->div_ratio; 1151 wnd_end = 3 * sc->div_ratio; 1152 } else { 1153 wnd_start = 8 * sc->div_ratio; 1154 wnd_end = 4 * sc->div_ratio; 1155 } 1156 1157 reg = RD4(sc, SDHCI_FSL_TBPTR); 1158 reg &= ~SDHCI_FSL_TBPTR_WND_MASK; 1159 reg &= ~(SDHCI_FSL_TBPTR_WND_MASK << SDHCI_FSL_TBPTR_WND_START_SHIFT); 1160 reg |= wnd_start << SDHCI_FSL_TBPTR_WND_START_SHIFT; 1161 reg |= wnd_end; 1162 WR4(sc, SDHCI_FSL_TBPTR, reg); 1163 1164 /* 1165 * Normally those are supposed to be set in sdhci_execute_tuning. 1166 * However in our case we need a small delay between setting the two. 1167 */ 1168 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1169 reg |= SDHCI_FSL_AUTOCERR_EXTN; 1170 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1171 DELAY(10); 1172 reg |= SDHCI_FSL_AUTOCERR_SMPCLKSEL; 1173 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1174 1175 reg = RD4(sc, SDHCI_FSL_TBCTL); 1176 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1177 reg |= SDHCI_FSL_TBCTL_MODE_SW; 1178 WR4(sc, SDHCI_FSL_TBCTL, reg); 1179 1180 error = sdhci_generic_tune(bus, child, hs400); 1181 if (error != 0) { 1182 device_printf(bus, 1183 "Failed to execute generic tune while performing software tuning.\n"); 1184 } 1185 1186 return (error); 1187 } 1188 1189 static int 1190 sdhci_fsl_fdt_tune(device_t bus, device_t child, bool hs400) 1191 { 1192 struct sdhci_fsl_fdt_softc *sc; 1193 uint32_t wnd_start, wnd_end; 1194 uint32_t clk_divider, reg; 1195 struct sdhci_slot *slot; 1196 int error; 1197 1198 sc = device_get_softc(bus); 1199 slot = device_get_ivars(child); 1200 1201 if (sc->slot.host.ios.timing == bus_timing_uhs_sdr50 && 1202 !(slot->opt & SDHCI_SDR50_NEEDS_TUNING)) 1203 return (0); 1204 1205 /* 1206 * For tuning mode SD clock divider must be within 3 to 16. 1207 * We also need to match the frequency to whatever mode is used. 1208 * For that reason we're just bailing if the dividers don't match 1209 * that requirement. 1210 */ 1211 clk_divider = sc->baseclk_hz / slot->clock; 1212 if (clk_divider < 3 || clk_divider > 16) 1213 return (ENXIO); 1214 1215 if (hs400) 1216 sc->flags |= SDHCI_FSL_HS400_FLAG; 1217 1218 /* Disable clock. */ 1219 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1220 1221 /* Wait for PRSSTAT[SDSTB] to be set by hardware. */ 1222 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1223 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1224 if (error != 0) 1225 device_printf(bus, 1226 "Timeout while waiting for clock to stabilize.\n"); 1227 1228 /* Flush async IO. */ 1229 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1230 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1231 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1232 1233 /* Wait for ESDHC[FAF] to be cleared by hardware. */ 1234 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1235 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1236 if (error) 1237 device_printf(bus, 1238 "Timeout while waiting for hardware.\n"); 1239 1240 /* 1241 * Set TBCTL[TB_EN] register and program valid tuning mode. 1242 * According to RM MODE_3 means that: 1243 * "eSDHC takes care of the re-tuning during data transfer 1244 * (auto re-tuning).". 1245 * Tuning mode can only be changed while the clock is disabled. 1246 */ 1247 reg = RD4(sc, SDHCI_FSL_TBCTL); 1248 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK; 1249 reg |= SDHCI_FSL_TBCTL_TBEN | SDHCI_FSL_TBCTL_MODE_3; 1250 WR4(sc, SDHCI_FSL_TBCTL, reg); 1251 1252 /* Enable clock. */ 1253 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | sc->sdclk_bits); 1254 1255 /* Wait for clock to stabilize. */ 1256 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1257 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1258 if (error) 1259 device_printf(bus, 1260 "Timeout while waiting for clock to stabilize.\n"); 1261 1262 /* Perform hardware tuning. */ 1263 error = sdhci_generic_tune(bus, child, hs400); 1264 1265 reg = RD4(sc, SDHCI_FSL_TBPTR); 1266 wnd_start = reg >> SDHCI_FSL_TBPTR_WND_START_SHIFT; 1267 wnd_start &= SDHCI_FSL_TBPTR_WND_MASK; 1268 wnd_end = reg & SDHCI_FSL_TBPTR_WND_MASK; 1269 1270 /* 1271 * For erratum type2 affected platforms, the controller can erroneously 1272 * declare that the tuning was successful. Verify the tuning window to 1273 * make sure that we're fine. 1274 */ 1275 if (error == 0 && 1276 sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE2 && 1277 abs(wnd_start - wnd_end) > (4 * sc->div_ratio + 2)) { 1278 error = EIO; 1279 } 1280 1281 /* If hardware tuning failed, try software tuning. */ 1282 if (error != 0 && 1283 (sc->soc_data->errata & 1284 (SDHCI_FSL_TUNING_ERRATUM_TYPE1 | 1285 SDHCI_FSL_TUNING_ERRATUM_TYPE2))) { 1286 error = sdhci_fsl_sw_tuning(sc, bus, child, hs400, wnd_start, 1287 wnd_end); 1288 if (error != 0) 1289 device_printf(bus, "Software tuning failed.\n"); 1290 } 1291 1292 if (error != 0) { 1293 sdhci_fsl_switch_tuning_block(bus, false); 1294 return (error); 1295 } 1296 if (hs400) { 1297 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1298 reg |= SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1299 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1300 } 1301 1302 return (0); 1303 } 1304 1305 static int 1306 sdhci_fsl_fdt_retune(device_t bus, device_t child, bool reset) 1307 { 1308 struct sdhci_slot *slot; 1309 struct sdhci_fsl_fdt_softc *sc; 1310 1311 slot = device_get_ivars(child); 1312 sc = device_get_softc(bus); 1313 1314 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1315 return (0); 1316 1317 /* HS400 must be tuned in HS200 mode. */ 1318 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1319 return (EINVAL); 1320 1321 /* 1322 * Only re-tuning with full reset is supported. 1323 * The controller is normally put in "mode 3", which means that 1324 * periodic re-tuning is done automatically. See comment in 1325 * sdhci_fsl_fdt_tune for details. 1326 * Because of that re-tuning should only be triggered as a result 1327 * of a CRC error. 1328 */ 1329 if (!reset) 1330 return (ENOTSUP); 1331 1332 return (sdhci_fsl_fdt_tune(bus, child, 1333 sc->flags & SDHCI_FSL_HS400_FLAG)); 1334 } 1335 static void 1336 sdhci_fsl_disable_hs400_mode(device_t dev, struct sdhci_fsl_fdt_softc *sc) 1337 { 1338 uint32_t reg; 1339 int error; 1340 1341 /* Check if HS400 is enabled right now. */ 1342 reg = RD4(sc, SDHCI_FSL_TBCTL); 1343 if ((reg & SDHCI_FSL_TBCTL_HS400_EN) == 0) 1344 return; 1345 1346 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL); 1347 reg &= ~SDHCI_FSL_SDTIMINGCTL_FLW_CTL; 1348 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); 1349 1350 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1351 reg &= ~SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1352 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1353 1354 fsl_sdhc_fdt_set_clock(sc, &sc->slot, sc->sdclk_bits); 1355 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1356 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1357 if (error != 0) 1358 device_printf(dev, 1359 "Internal clock never stabilized.\n"); 1360 1361 reg = RD4(sc, SDHCI_FSL_TBCTL); 1362 reg &= ~SDHCI_FSL_TBCTL_HS400_EN; 1363 WR4(sc, SDHCI_FSL_TBCTL, reg); 1364 1365 fsl_sdhc_fdt_set_clock(sc, &sc->slot, SDHCI_CLOCK_CARD_EN | 1366 sc->sdclk_bits); 1367 1368 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1369 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1370 if (error != 0) 1371 device_printf(dev, 1372 "Internal clock never stabilized.\n"); 1373 1374 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1375 reg &= ~(SDHCI_FSL_DLLCFG0_EN | 1376 SDHCI_FSL_DLLCFG0_FREQ_SEL); 1377 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1378 1379 reg = RD4(sc, SDHCI_FSL_TBCTL); 1380 reg &= ~SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1381 WR4(sc, SDHCI_FSL_TBCTL, reg); 1382 1383 sdhci_fsl_switch_tuning_block(dev, false); 1384 } 1385 1386 static void 1387 sdhci_fsl_enable_hs400_mode(device_t dev, struct sdhci_slot *slot, 1388 struct sdhci_fsl_fdt_softc *sc) 1389 { 1390 uint32_t reg; 1391 int error; 1392 1393 sdhci_fsl_switch_tuning_block(dev, true); 1394 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1395 1396 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1397 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1398 if (error != 0) 1399 device_printf(dev, 1400 "Timeout while waiting for clock to stabilize.\n"); 1401 1402 reg = RD4(sc, SDHCI_FSL_TBCTL); 1403 reg |= SDHCI_FSL_TBCTL_HS400_EN; 1404 WR4(sc, SDHCI_FSL_TBCTL, reg); 1405 reg = RD4(sc, SDHCI_FSL_SDCLKCTL); 1406 reg |= SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL; 1407 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); 1408 1409 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1410 sc->sdclk_bits); 1411 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1412 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1413 if (error != 0) 1414 device_printf(dev, 1415 "Timeout while waiting for clock to stabilize.\n"); 1416 1417 reg = RD4(sc, SDHCI_FSL_DLLCFG0); 1418 reg |= SDHCI_FSL_DLLCFG0_EN | SDHCI_FSL_DLLCFG0_RESET | 1419 SDHCI_FSL_DLLCFG0_FREQ_SEL; 1420 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1421 1422 /* 1423 * The reset bit is not a self clearing one. 1424 * Give it some time and clear it manually. 1425 */ 1426 DELAY(100); 1427 reg &= ~SDHCI_FSL_DLLCFG0_RESET; 1428 WR4(sc, SDHCI_FSL_DLLCFG0, reg); 1429 1430 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_DLLSTAT0, 1431 SDHCI_FSL_DLLSTAT0_SLV_STS, SDHCI_FSL_DLLSTAT0_SLV_STS); 1432 if (error != 0) 1433 device_printf(dev, 1434 "Timeout while waiting for DLL0.\n"); 1435 1436 reg = RD4(sc, SDHCI_FSL_TBCTL); 1437 reg |= SDHCI_FSL_TBCTL_HS400_WND_ADJ; 1438 WR4(sc, SDHCI_FSL_TBCTL, reg); 1439 1440 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits); 1441 1442 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1443 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1444 if (error != 0) 1445 device_printf(dev, 1446 "timeout while waiting for clock to stabilize.\n"); 1447 1448 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 1449 reg |= SDHCI_FSL_ESDHC_CTRL_FAF; 1450 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); 1451 1452 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL, 1453 SDHCI_FSL_ESDHC_CTRL_FAF, 0); 1454 if (error != 0) 1455 device_printf(dev, 1456 "Timeout while waiting for hardware.\n"); 1457 1458 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | 1459 sc->sdclk_bits); 1460 1461 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE, 1462 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB); 1463 if (error != 0) 1464 device_printf(dev, 1465 "Timeout while waiting for clock to stabilize.\n"); 1466 } 1467 1468 static void 1469 sdhci_fsl_fdt_set_uhs_timing(device_t dev, struct sdhci_slot *slot) 1470 { 1471 struct sdhci_fsl_fdt_softc *sc; 1472 const struct mmc_ios *ios; 1473 uint32_t mode, reg; 1474 1475 sc = device_get_softc(dev); 1476 ios = &slot->host.ios; 1477 mode = 0; 1478 1479 /* 1480 * When we switch to HS400 this function is called twice. 1481 * First after the timing is set, and then after the clock 1482 * is changed to the target frequency. 1483 * The controller can be switched to HS400 only after the latter 1484 * is done. 1485 */ 1486 if (slot->host.ios.timing == bus_timing_mmc_hs400 && 1487 ios->clock > SD_SDR50_MAX) 1488 sdhci_fsl_enable_hs400_mode(dev, slot, sc); 1489 else if (slot->host.ios.timing < bus_timing_mmc_hs400) { 1490 sdhci_fsl_disable_hs400_mode(dev, sc); 1491 1492 /* 1493 * Switching to HS400 requires a custom procedure executed in 1494 * sdhci_fsl_enable_hs400_mode in case above. 1495 * For all other modes we just need to set the corresponding flag. 1496 */ 1497 reg = RD4(sc, SDHCI_FSL_AUTOCERR); 1498 reg &= ~SDHCI_FSL_AUTOCERR_UHMS; 1499 if (ios->clock > SD_SDR50_MAX) 1500 mode = SDHCI_CTRL2_UHS_SDR104; 1501 else if (ios->clock > SD_SDR25_MAX) 1502 mode = SDHCI_CTRL2_UHS_SDR50; 1503 else if (ios->clock > SD_SDR12_MAX) { 1504 if (ios->timing == bus_timing_uhs_ddr50 || 1505 ios->timing == bus_timing_mmc_ddr52) 1506 mode = SDHCI_CTRL2_UHS_DDR50; 1507 else 1508 mode = SDHCI_CTRL2_UHS_SDR25; 1509 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1510 mode = SDHCI_CTRL2_UHS_SDR12; 1511 1512 reg |= mode << SDHCI_FSL_AUTOCERR_UHMS_SHIFT; 1513 WR4(sc, SDHCI_FSL_AUTOCERR, reg); 1514 } 1515 } 1516 1517 static const device_method_t sdhci_fsl_fdt_methods[] = { 1518 /* Device interface. */ 1519 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe), 1520 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach), 1521 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach), 1522 1523 /* Bus interface. */ 1524 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar), 1525 DEVMETHOD(bus_write_ivar, sdhci_fsl_fdt_write_ivar), 1526 1527 /* MMC bridge interface. */ 1528 DEVMETHOD(mmcbr_request, sdhci_generic_request), 1529 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro), 1530 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 1531 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 1532 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq), 1533 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios), 1534 DEVMETHOD(mmcbr_tune, sdhci_fsl_fdt_tune), 1535 DEVMETHOD(mmcbr_retune, sdhci_fsl_fdt_retune), 1536 1537 /* SDHCI accessors. */ 1538 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1), 1539 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2), 1540 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4), 1541 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4), 1542 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1), 1543 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2), 1544 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4), 1545 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4), 1546 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present), 1547 DEVMETHOD(sdhci_reset, sdhci_fsl_fdt_reset), 1548 DEVMETHOD(sdhci_set_uhs_timing, sdhci_fsl_fdt_set_uhs_timing), 1549 DEVMETHOD_END 1550 }; 1551 1552 static driver_t sdhci_fsl_fdt_driver = { 1553 "sdhci_fsl_fdt", 1554 sdhci_fsl_fdt_methods, 1555 sizeof(struct sdhci_fsl_fdt_softc), 1556 }; 1557 1558 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, NULL, NULL); 1559 SDHCI_DEPEND(sdhci_fsl_fdt); 1560 1561 #ifndef MMCCAM 1562 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt); 1563 #endif 1564