xref: /freebsd/sys/dev/sdhci/sdhci_fdt.c (revision e0656a491411fe65ed8b9135add026358b24951f)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2012 Thomas Skibo
5  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /* Generic driver to attach sdhci controllers on simplebus.
30  * Derived mainly from sdhci_pci.c
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/resource.h>
44 #include <sys/rman.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
47 
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54 
55 #include <dev/mmc/bridge.h>
56 
57 #include <dev/sdhci/sdhci.h>
58 
59 #include "mmcbr_if.h"
60 #include "sdhci_if.h"
61 
62 #define	MAX_SLOTS		6
63 #define	SDHCI_FDT_ARMADA38X	1
64 #define	SDHCI_FDT_GENERIC	2
65 #define	SDHCI_FDT_XLNX_ZY7	3
66 #define	SDHCI_FDT_QUALCOMM	4
67 
68 static struct ofw_compat_data compat_data[] = {
69 	{ "marvell,armada-380-sdhci",	SDHCI_FDT_ARMADA38X },
70 	{ "sdhci_generic",		SDHCI_FDT_GENERIC },
71 	{ "qcom,sdhci-msm-v4",		SDHCI_FDT_QUALCOMM },
72 	{ "xlnx,zy7_sdhci",		SDHCI_FDT_XLNX_ZY7 },
73 	{ NULL, 0 }
74 };
75 
76 struct sdhci_fdt_softc {
77 	device_t	dev;		/* Controller device */
78 	u_int		quirks;		/* Chip specific quirks */
79 	u_int		caps;		/* If we override SDHCI_CAPABILITIES */
80 	uint32_t	max_clk;	/* Max possible freq */
81 	struct resource *irq_res;	/* IRQ resource */
82 	void		*intrhand;	/* Interrupt handle */
83 
84 	int		num_slots;	/* Number of slots on this controller*/
85 	struct sdhci_slot slots[MAX_SLOTS];
86 	struct resource	*mem_res[MAX_SLOTS];	/* Memory resource */
87 
88 	bool		wp_inverted;	/* WP pin is inverted */
89 	bool		no_18v;		/* No 1.8V support */
90 };
91 
92 static uint8_t
93 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
94 {
95 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
96 
97 	return (bus_read_1(sc->mem_res[slot->num], off));
98 }
99 
100 static void
101 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
102     uint8_t val)
103 {
104 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
105 
106 	bus_write_1(sc->mem_res[slot->num], off, val);
107 }
108 
109 static uint16_t
110 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
111 {
112 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
113 
114 	return (bus_read_2(sc->mem_res[slot->num], off));
115 }
116 
117 static void
118 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
119     uint16_t val)
120 {
121 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
122 
123 	bus_write_2(sc->mem_res[slot->num], off, val);
124 }
125 
126 static uint32_t
127 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
128 {
129 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
130 	uint32_t val32;
131 
132 	val32 = bus_read_4(sc->mem_res[slot->num], off);
133 	if (off == SDHCI_CAPABILITIES && sc->no_18v)
134 		val32 &= ~SDHCI_CAN_VDD_180;
135 
136 	return (val32);
137 }
138 
139 static void
140 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
141     uint32_t val)
142 {
143 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
144 
145 	bus_write_4(sc->mem_res[slot->num], off, val);
146 }
147 
148 static void
149 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot,
150     bus_size_t off, uint32_t *data, bus_size_t count)
151 {
152 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
153 
154 	bus_read_multi_4(sc->mem_res[slot->num], off, data, count);
155 }
156 
157 static void
158 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
159     bus_size_t off, uint32_t *data, bus_size_t count)
160 {
161 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
162 
163 	bus_write_multi_4(sc->mem_res[slot->num], off, data, count);
164 }
165 
166 static void
167 sdhci_fdt_intr(void *arg)
168 {
169 	struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg;
170 	int i;
171 
172 	for (i = 0; i < sc->num_slots; i++)
173 		sdhci_generic_intr(&sc->slots[i]);
174 }
175 
176 static int
177 sdhci_fdt_get_ro(device_t bus, device_t dev)
178 {
179 	struct sdhci_fdt_softc *sc = device_get_softc(bus);
180 
181 	return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
182 }
183 
184 static int
185 sdhci_fdt_probe(device_t dev)
186 {
187 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
188 	phandle_t node;
189 	pcell_t cid;
190 
191 	sc->quirks = 0;
192 	sc->num_slots = 1;
193 	sc->max_clk = 0;
194 
195 	if (!ofw_bus_status_okay(dev))
196 		return (ENXIO);
197 
198 	switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
199 	case SDHCI_FDT_ARMADA38X:
200 		sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP;
201 		device_set_desc(dev, "ARMADA38X SDHCI controller");
202 		break;
203 	case SDHCI_FDT_GENERIC:
204 		device_set_desc(dev, "generic fdt SDHCI controller");
205 		break;
206 	case SDHCI_FDT_QUALCOMM:
207 		sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE;
208 		device_set_desc(dev, "Qualcomm FDT SDHCI controller");
209 		break;
210 	case SDHCI_FDT_XLNX_ZY7:
211 		sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
212 		device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
213 		break;
214 	default:
215 		return (ENXIO);
216 	}
217 
218 	node = ofw_bus_get_node(dev);
219 
220 	/* Allow dts to patch quirks, slots, and max-frequency. */
221 	if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
222 		sc->quirks = cid;
223 	if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0)
224 		sc->num_slots = cid;
225 	if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
226 		sc->max_clk = cid;
227 	if (OF_hasprop(node, "no-1-8-v"))
228 		sc->no_18v = true;
229 	if (OF_hasprop(node, "wp-inverted"))
230 		sc->wp_inverted = true;
231 
232 	return (0);
233 }
234 
235 static int
236 sdhci_fdt_attach(device_t dev)
237 {
238 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
239 	struct sdhci_slot *slot;
240 	int err, slots, rid, i;
241 
242 	sc->dev = dev;
243 
244 	/* Allocate IRQ. */
245 	rid = 0;
246 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
247 	    RF_ACTIVE);
248 	if (sc->irq_res == NULL) {
249 		device_printf(dev, "Can't allocate IRQ\n");
250 		return (ENOMEM);
251 	}
252 
253 	/* Scan all slots. */
254 	slots = sc->num_slots;	/* number of slots determined in probe(). */
255 	sc->num_slots = 0;
256 	for (i = 0; i < slots; i++) {
257 		slot = &sc->slots[sc->num_slots];
258 
259 		/* Allocate memory. */
260 		rid = 0;
261 		sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
262 							&rid, RF_ACTIVE);
263 		if (sc->mem_res[i] == NULL) {
264 			device_printf(dev,
265 			    "Can't allocate memory for slot %d\n", i);
266 			continue;
267 		}
268 
269 		slot->quirks = sc->quirks;
270 		slot->caps = sc->caps;
271 		slot->max_clk = sc->max_clk;
272 
273 		if (sdhci_init_slot(dev, slot, i) != 0)
274 			continue;
275 
276 		sc->num_slots++;
277 	}
278 	device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
279 
280 	/* Activate the interrupt */
281 	err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
282 	    NULL, sdhci_fdt_intr, sc, &sc->intrhand);
283 	if (err) {
284 		device_printf(dev, "Cannot setup IRQ\n");
285 		return (err);
286 	}
287 
288 	/* Process cards detection. */
289 	for (i = 0; i < sc->num_slots; i++)
290 		sdhci_start_slot(&sc->slots[i]);
291 
292 	return (0);
293 }
294 
295 static int
296 sdhci_fdt_detach(device_t dev)
297 {
298 	struct sdhci_fdt_softc *sc = device_get_softc(dev);
299 	int i;
300 
301 	bus_generic_detach(dev);
302 	bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
303 	bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
304 	    sc->irq_res);
305 
306 	for (i = 0; i < sc->num_slots; i++) {
307 		sdhci_cleanup_slot(&sc->slots[i]);
308 		bus_release_resource(dev, SYS_RES_MEMORY,
309 		    rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
310 	}
311 
312 	return (0);
313 }
314 
315 static device_method_t sdhci_fdt_methods[] = {
316 	/* device_if */
317 	DEVMETHOD(device_probe,		sdhci_fdt_probe),
318 	DEVMETHOD(device_attach,	sdhci_fdt_attach),
319 	DEVMETHOD(device_detach,	sdhci_fdt_detach),
320 
321 	/* Bus interface */
322 	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
323 	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
324 
325 	/* mmcbr_if */
326 	DEVMETHOD(mmcbr_update_ios,	sdhci_generic_update_ios),
327 	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
328 	DEVMETHOD(mmcbr_get_ro,		sdhci_fdt_get_ro),
329 	DEVMETHOD(mmcbr_acquire_host,	sdhci_generic_acquire_host),
330 	DEVMETHOD(mmcbr_release_host,	sdhci_generic_release_host),
331 
332 	/* SDHCI registers accessors */
333 	DEVMETHOD(sdhci_read_1,		sdhci_fdt_read_1),
334 	DEVMETHOD(sdhci_read_2,		sdhci_fdt_read_2),
335 	DEVMETHOD(sdhci_read_4,		sdhci_fdt_read_4),
336 	DEVMETHOD(sdhci_read_multi_4,	sdhci_fdt_read_multi_4),
337 	DEVMETHOD(sdhci_write_1,	sdhci_fdt_write_1),
338 	DEVMETHOD(sdhci_write_2,	sdhci_fdt_write_2),
339 	DEVMETHOD(sdhci_write_4,	sdhci_fdt_write_4),
340 	DEVMETHOD(sdhci_write_multi_4,	sdhci_fdt_write_multi_4),
341 
342 	DEVMETHOD_END
343 };
344 
345 static driver_t sdhci_fdt_driver = {
346 	"sdhci_fdt",
347 	sdhci_fdt_methods,
348 	sizeof(struct sdhci_fdt_softc),
349 };
350 static devclass_t sdhci_fdt_devclass;
351 
352 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass,
353     NULL, NULL);
354 MODULE_DEPEND(sdhci_fdt, sdhci, 1, 1, 1);
355 MMC_DECLARE_BRIDGE(sdhci_fdt);
356