1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Thomas Skibo 5 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* Generic driver to attach sdhci controllers on simplebus. 30 * Derived mainly from sdhci_pci.c 31 */ 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <dev/ofw/ofw_subr.h> 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/clk/clk_fixed.h> 56 #include <dev/extres/syscon/syscon.h> 57 #include <dev/extres/phy/phy.h> 58 59 #include <dev/mmc/bridge.h> 60 61 #include <dev/sdhci/sdhci.h> 62 63 #include "mmcbr_if.h" 64 #include "sdhci_if.h" 65 66 #include "opt_mmccam.h" 67 68 #include "clkdev_if.h" 69 #include "syscon_if.h" 70 71 #define MAX_SLOTS 6 72 #define SDHCI_FDT_ARMADA38X 1 73 #define SDHCI_FDT_XLNX_ZY7 2 74 #define SDHCI_FDT_QUALCOMM 3 75 #define SDHCI_FDT_RK3399 4 76 #define SDHCI_FDT_RK3568 5 77 #define SDHCI_FDT_XLNX_ZMP 6 78 79 #define RK3399_GRF_EMMCCORE_CON0 0xf000 80 #define RK3399_CORECFG_BASECLKFREQ 0xff00 81 #define RK3399_CORECFG_TIMEOUTCLKUNIT (1 << 7) 82 #define RK3399_CORECFG_TUNINGCOUNT 0x3f 83 #define RK3399_GRF_EMMCCORE_CON11 0xf02c 84 #define RK3399_CORECFG_CLOCKMULTIPLIER 0xff 85 86 #define RK3568_EMMC_HOST_CTRL 0x0508 87 #define RK3568_EMMC_EMMC_CTRL 0x052c 88 #define RK3568_EMMC_ATCTRL 0x0540 89 #define RK3568_EMMC_DLL_CTRL 0x0800 90 #define DLL_CTRL_SRST 0x00000001 91 #define DLL_CTRL_START 0x00000002 92 #define DLL_CTRL_START_POINT_DEFAULT 0x00050000 93 #define DLL_CTRL_INCREMENT_DEFAULT 0x00000200 94 95 #define RK3568_EMMC_DLL_RXCLK 0x0804 96 #define DLL_RXCLK_DELAY_ENABLE 0x08000000 97 #define DLL_RXCLK_NO_INV 0x20000000 98 99 #define RK3568_EMMC_DLL_TXCLK 0x0808 100 #define DLL_TXCLK_DELAY_ENABLE 0x08000000 101 #define DLL_TXCLK_TAPNUM_DEFAULT 0x00000008 102 #define DLL_TXCLK_TAPNUM_FROM_SW 0x01000000 103 104 #define RK3568_EMMC_DLL_STRBIN 0x080c 105 #define DLL_STRBIN_DELAY_ENABLE 0x08000000 106 #define DLL_STRBIN_TAPNUM_DEFAULT 0x00000008 107 #define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000 108 109 #define RK3568_EMMC_DLL_STATUS0 0x0840 110 #define DLL_STATUS0_DLL_LOCK 0x00000100 111 #define DLL_STATUS0_DLL_TIMEOUT 0x00000200 112 113 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) 114 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) 115 116 static struct ofw_compat_data compat_data[] = { 117 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, 118 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM }, 119 { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 }, 120 { "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 }, 121 { "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 }, 122 { "xlnx,zynqmp-8.9a", SDHCI_FDT_XLNX_ZMP }, 123 { NULL, 0 } 124 }; 125 126 struct sdhci_fdt_softc { 127 device_t dev; /* Controller device */ 128 u_int quirks; /* Chip specific quirks */ 129 u_int caps; /* If we override SDHCI_CAPABILITIES */ 130 uint32_t max_clk; /* Max possible freq */ 131 uint8_t sdma_boundary; /* If we override the SDMA boundary */ 132 struct resource *irq_res; /* IRQ resource */ 133 void *intrhand; /* Interrupt handle */ 134 135 int num_slots; /* Number of slots on this controller*/ 136 struct sdhci_slot slots[MAX_SLOTS]; 137 struct resource *mem_res[MAX_SLOTS]; /* Memory resource */ 138 139 bool wp_inverted; /* WP pin is inverted */ 140 bool wp_disabled; /* WP pin is not supported */ 141 bool no_18v; /* No 1.8V support */ 142 143 clk_t clk_xin; /* xin24m fixed clock */ 144 clk_t clk_ahb; /* ahb clock */ 145 clk_t clk_core; /* core clock */ 146 phy_t phy; /* phy to be used */ 147 148 struct syscon *syscon; /* Handle to the syscon */ 149 }; 150 151 struct sdhci_exported_clocks_sc { 152 device_t clkdev; 153 }; 154 155 static int 156 sdhci_exported_clocks_init(struct clknode *clk, device_t dev) 157 { 158 159 clknode_init_parent_idx(clk, 0); 160 return (0); 161 } 162 163 static clknode_method_t sdhci_exported_clocks_clknode_methods[] = { 164 /* Device interface */ 165 CLKNODEMETHOD(clknode_init, sdhci_exported_clocks_init), 166 CLKNODEMETHOD_END 167 }; 168 DEFINE_CLASS_1(sdhci_exported_clocks_clknode, sdhci_exported_clocks_clknode_class, 169 sdhci_exported_clocks_clknode_methods, sizeof(struct sdhci_exported_clocks_sc), 170 clknode_class); 171 172 static int 173 sdhci_clock_ofw_map(struct clkdom *clkdom, uint32_t ncells, 174 phandle_t *cells, struct clknode **clk) 175 { 176 int id = 1; /* Our clock id starts at 1 */ 177 178 if (ncells != 0) 179 id = cells[1]; 180 *clk = clknode_find_by_id(clkdom, id); 181 182 if (*clk == NULL) 183 return (ENXIO); 184 return (0); 185 } 186 187 static void 188 sdhci_export_clocks(struct sdhci_fdt_softc *sc) 189 { 190 struct clknode_init_def def; 191 struct sdhci_exported_clocks_sc *clksc; 192 struct clkdom *clkdom; 193 struct clknode *clk; 194 bus_addr_t paddr; 195 bus_size_t psize; 196 const char **clknames; 197 phandle_t node; 198 int i, nclocks, ncells, error; 199 200 node = ofw_bus_get_node(sc->dev); 201 202 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 203 device_printf(sc->dev, "cannot parse 'reg' property\n"); 204 return; 205 } 206 207 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 208 "#clock-cells", &ncells); 209 if (error != 0 || ncells != 2) { 210 device_printf(sc->dev, "couldn't find parent clocks\n"); 211 return; 212 } 213 214 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", 215 &clknames); 216 /* No clocks to export */ 217 if (nclocks <= 0) 218 return; 219 220 clkdom = clkdom_create(sc->dev); 221 clkdom_set_ofw_mapper(clkdom, sdhci_clock_ofw_map); 222 223 for (i = 0; i < nclocks; i++) { 224 memset(&def, 0, sizeof(def)); 225 def.id = i + 1; /* Exported clock IDs starts at 1 */ 226 def.name = clknames[i]; 227 def.parent_names = malloc(sizeof(char *) * 1, M_OFWPROP, M_WAITOK); 228 def.parent_names[0] = clk_get_name(sc->clk_xin); 229 def.parent_cnt = 1; 230 231 clk = clknode_create(clkdom, &sdhci_exported_clocks_clknode_class, &def); 232 if (clk == NULL) { 233 device_printf(sc->dev, "cannot create clknode\n"); 234 return; 235 } 236 237 clksc = clknode_get_softc(clk); 238 clksc->clkdev = device_get_parent(sc->dev); 239 240 clknode_register(clkdom, clk); 241 } 242 243 if (clkdom_finit(clkdom) != 0) { 244 device_printf(sc->dev, "cannot finalize clkdom initialization\n"); 245 return; 246 } 247 248 if (bootverbose) 249 clkdom_dump(clkdom); 250 } 251 252 static int 253 sdhci_init_clocks(device_t dev) 254 { 255 struct sdhci_fdt_softc *sc = device_get_softc(dev); 256 int error; 257 258 /* Get and activate clocks */ 259 error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin); 260 if (error != 0) { 261 device_printf(dev, "cannot get xin clock\n"); 262 return (ENXIO); 263 } 264 error = clk_enable(sc->clk_xin); 265 if (error != 0) { 266 device_printf(dev, "cannot enable xin clock\n"); 267 return (ENXIO); 268 } 269 error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb); 270 if (error != 0) { 271 device_printf(dev, "cannot get ahb clock\n"); 272 return (ENXIO); 273 } 274 error = clk_enable(sc->clk_ahb); 275 if (error != 0) { 276 device_printf(dev, "cannot enable ahb clock\n"); 277 return (ENXIO); 278 } 279 280 return (0); 281 } 282 283 static int 284 sdhci_init_phy(struct sdhci_fdt_softc *sc) 285 { 286 int error; 287 288 /* Enable PHY */ 289 error = phy_get_by_ofw_name(sc->dev, 0, "phy_arasan", &sc->phy); 290 if (error == ENOENT) 291 return (0); 292 if (error != 0) { 293 device_printf(sc->dev, "Could not get phy\n"); 294 return (ENXIO); 295 } 296 error = phy_enable(sc->phy); 297 if (error != 0) { 298 device_printf(sc->dev, "Could not enable phy\n"); 299 return (ENXIO); 300 } 301 302 return (0); 303 } 304 305 static int 306 sdhci_get_syscon(struct sdhci_fdt_softc *sc) 307 { 308 phandle_t node; 309 310 /* Get syscon */ 311 node = ofw_bus_get_node(sc->dev); 312 if (OF_hasprop(node, "arasan,soc-ctl-syscon") && 313 syscon_get_by_ofw_property(sc->dev, node, 314 "arasan,soc-ctl-syscon", &sc->syscon) != 0) { 315 device_printf(sc->dev, "cannot get syscon handle\n"); 316 return (ENXIO); 317 } 318 319 return (0); 320 } 321 322 static int 323 sdhci_init_rk3399(device_t dev) 324 { 325 struct sdhci_fdt_softc *sc = device_get_softc(dev); 326 uint64_t freq; 327 uint32_t mask, val; 328 int error; 329 330 error = clk_get_freq(sc->clk_xin, &freq); 331 if (error != 0) { 332 device_printf(dev, "cannot get xin clock frequency\n"); 333 return (ENXIO); 334 } 335 336 /* Disable clock multiplier */ 337 mask = RK3399_CORECFG_CLOCKMULTIPLIER; 338 val = 0; 339 SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val); 340 341 /* Set base clock frequency */ 342 mask = RK3399_CORECFG_BASECLKFREQ; 343 val = SHIFTIN((freq + (1000000 / 2)) / 1000000, 344 RK3399_CORECFG_BASECLKFREQ); 345 SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val); 346 347 return (0); 348 } 349 350 static uint8_t 351 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 352 { 353 struct sdhci_fdt_softc *sc = device_get_softc(dev); 354 355 return (bus_read_1(sc->mem_res[slot->num], off)); 356 } 357 358 static void 359 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 360 uint8_t val) 361 { 362 struct sdhci_fdt_softc *sc = device_get_softc(dev); 363 364 bus_write_1(sc->mem_res[slot->num], off, val); 365 } 366 367 static uint16_t 368 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 369 { 370 struct sdhci_fdt_softc *sc = device_get_softc(dev); 371 372 return (bus_read_2(sc->mem_res[slot->num], off)); 373 } 374 375 static void 376 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 377 uint16_t val) 378 { 379 struct sdhci_fdt_softc *sc = device_get_softc(dev); 380 381 bus_write_2(sc->mem_res[slot->num], off, val); 382 } 383 384 static uint32_t 385 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 386 { 387 struct sdhci_fdt_softc *sc = device_get_softc(dev); 388 uint32_t val32; 389 390 val32 = bus_read_4(sc->mem_res[slot->num], off); 391 if (off == SDHCI_CAPABILITIES && sc->no_18v) 392 val32 &= ~SDHCI_CAN_VDD_180; 393 394 return (val32); 395 } 396 397 static void 398 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 399 uint32_t val) 400 { 401 struct sdhci_fdt_softc *sc = device_get_softc(dev); 402 403 bus_write_4(sc->mem_res[slot->num], off, val); 404 } 405 406 static void 407 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 408 bus_size_t off, uint32_t *data, bus_size_t count) 409 { 410 struct sdhci_fdt_softc *sc = device_get_softc(dev); 411 412 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 413 } 414 415 static void 416 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 417 bus_size_t off, uint32_t *data, bus_size_t count) 418 { 419 struct sdhci_fdt_softc *sc = device_get_softc(dev); 420 421 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 422 } 423 424 static void 425 sdhci_fdt_intr(void *arg) 426 { 427 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 428 int i; 429 430 for (i = 0; i < sc->num_slots; i++) 431 sdhci_generic_intr(&sc->slots[i]); 432 } 433 434 static int 435 sdhci_fdt_get_ro(device_t bus, device_t dev) 436 { 437 struct sdhci_fdt_softc *sc = device_get_softc(bus); 438 439 if (sc->wp_disabled) 440 return (false); 441 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 442 } 443 444 static int 445 sdhci_fdt_set_clock(device_t dev, struct sdhci_slot *slot, int clock) 446 { 447 struct sdhci_fdt_softc *sc = device_get_softc(dev); 448 int32_t val; 449 int i; 450 451 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 452 SDHCI_FDT_RK3568) { 453 if (clock == 400000) 454 clock = 375000; 455 456 if (clock) { 457 clk_set_freq(sc->clk_core, clock, 0); 458 459 if (clock <= 52000000) { 460 bus_write_4(sc->mem_res[slot->num], 461 RK3568_EMMC_DLL_CTRL, 0x0); 462 bus_write_4(sc->mem_res[slot->num], 463 RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_NO_INV); 464 bus_write_4(sc->mem_res[slot->num], 465 RK3568_EMMC_DLL_TXCLK, 0x0); 466 bus_write_4(sc->mem_res[slot->num], 467 RK3568_EMMC_DLL_STRBIN, 0x0); 468 return (clock); 469 } 470 471 bus_write_4(sc->mem_res[slot->num], 472 RK3568_EMMC_DLL_CTRL, DLL_CTRL_START); 473 DELAY(1000); 474 bus_write_4(sc->mem_res[slot->num], 475 RK3568_EMMC_DLL_CTRL, 0); 476 bus_write_4(sc->mem_res[slot->num], 477 RK3568_EMMC_DLL_CTRL, DLL_CTRL_START_POINT_DEFAULT | 478 DLL_CTRL_INCREMENT_DEFAULT | DLL_CTRL_START); 479 for (i = 0; i < 500; i++) { 480 val = bus_read_4(sc->mem_res[slot->num], 481 RK3568_EMMC_DLL_STATUS0); 482 if (val & DLL_STATUS0_DLL_LOCK && 483 !(val & DLL_STATUS0_DLL_TIMEOUT)) 484 break; 485 DELAY(1000); 486 } 487 bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL, 488 (0x1 << 16 | 0x2 << 17 | 0x3 << 19)); 489 bus_write_4(sc->mem_res[slot->num], 490 RK3568_EMMC_DLL_RXCLK, 491 DLL_RXCLK_DELAY_ENABLE | DLL_RXCLK_NO_INV); 492 bus_write_4(sc->mem_res[slot->num], 493 RK3568_EMMC_DLL_TXCLK, DLL_TXCLK_DELAY_ENABLE | 494 DLL_TXCLK_TAPNUM_DEFAULT|DLL_TXCLK_TAPNUM_FROM_SW); 495 bus_write_4(sc->mem_res[slot->num], 496 RK3568_EMMC_DLL_STRBIN, DLL_STRBIN_DELAY_ENABLE | 497 DLL_STRBIN_TAPNUM_DEFAULT | 498 DLL_STRBIN_TAPNUM_FROM_SW); 499 } 500 } 501 return (clock); 502 } 503 504 static int 505 sdhci_fdt_probe(device_t dev) 506 { 507 struct sdhci_fdt_softc *sc = device_get_softc(dev); 508 phandle_t node; 509 pcell_t cid; 510 511 sc->quirks = 0; 512 sc->num_slots = 1; 513 sc->max_clk = 0; 514 515 if (!ofw_bus_status_okay(dev)) 516 return (ENXIO); 517 518 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 519 case SDHCI_FDT_ARMADA38X: 520 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; 521 device_set_desc(dev, "ARMADA38X SDHCI controller"); 522 break; 523 case SDHCI_FDT_QUALCOMM: 524 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 525 SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY; 526 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 527 device_set_desc(dev, "Qualcomm FDT SDHCI controller"); 528 break; 529 case SDHCI_FDT_RK3399: 530 device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller"); 531 break; 532 case SDHCI_FDT_XLNX_ZY7: 533 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 534 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 535 break; 536 case SDHCI_FDT_RK3568: 537 device_set_desc(dev, "Rockchip RK3568 fdt SDHCI controller"); 538 break; 539 case SDHCI_FDT_XLNX_ZMP: 540 device_set_desc(dev, "ZynqMP generic fdt SDHCI controller"); 541 break; 542 default: 543 return (ENXIO); 544 } 545 546 node = ofw_bus_get_node(dev); 547 548 /* Allow dts to patch quirks, slots, and max-frequency. */ 549 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 550 sc->quirks = cid; 551 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) 552 sc->num_slots = cid; 553 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 554 sc->max_clk = cid; 555 if (OF_hasprop(node, "no-1-8-v")) 556 sc->no_18v = true; 557 if (OF_hasprop(node, "wp-inverted")) 558 sc->wp_inverted = true; 559 if (OF_hasprop(node, "disable-wp")) 560 sc->wp_disabled = true; 561 562 return (0); 563 } 564 565 static int 566 sdhci_fdt_attach(device_t dev) 567 { 568 struct sdhci_fdt_softc *sc = device_get_softc(dev); 569 struct sdhci_slot *slot; 570 int err, slots, rid, i, compat; 571 572 sc->dev = dev; 573 574 /* Allocate IRQ. */ 575 rid = 0; 576 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 577 RF_ACTIVE); 578 if (sc->irq_res == NULL) { 579 device_printf(dev, "Can't allocate IRQ\n"); 580 return (ENOMEM); 581 } 582 583 compat = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 584 switch (compat) { 585 case SDHCI_FDT_RK3399: 586 case SDHCI_FDT_XLNX_ZMP: 587 err = sdhci_init_clocks(dev); 588 if (err != 0) { 589 device_printf(dev, "Cannot init clocks\n"); 590 return (err); 591 } 592 sdhci_export_clocks(sc); 593 if ((err = sdhci_init_phy(sc)) != 0) { 594 device_printf(dev, "Cannot init phy\n"); 595 return (err); 596 } 597 if ((err = sdhci_get_syscon(sc)) != 0) { 598 device_printf(dev, "Cannot get syscon handle\n"); 599 return (err); 600 } 601 if (compat == SDHCI_FDT_RK3399) { 602 err = sdhci_init_rk3399(dev); 603 if (err != 0) { 604 device_printf(dev, "Cannot init RK3399 SDHCI\n"); 605 return (err); 606 } 607 } 608 break; 609 case SDHCI_FDT_RK3568: 610 /* setup & enable clocks */ 611 if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) { 612 device_printf(dev, "cannot get core clock\n"); 613 return (ENXIO); 614 } 615 clk_enable(sc->clk_core); 616 break; 617 default: 618 break; 619 } 620 621 /* Scan all slots. */ 622 slots = sc->num_slots; /* number of slots determined in probe(). */ 623 sc->num_slots = 0; 624 for (i = 0; i < slots; i++) { 625 slot = &sc->slots[sc->num_slots]; 626 627 /* Allocate memory. */ 628 rid = 0; 629 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 630 &rid, RF_ACTIVE); 631 if (sc->mem_res[i] == NULL) { 632 device_printf(dev, 633 "Can't allocate memory for slot %d\n", i); 634 continue; 635 } 636 637 slot->quirks = sc->quirks; 638 slot->caps = sc->caps; 639 slot->max_clk = sc->max_clk; 640 slot->sdma_boundary = sc->sdma_boundary; 641 642 if (sdhci_init_slot(dev, slot, i) != 0) 643 continue; 644 645 sc->num_slots++; 646 } 647 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 648 649 /* Activate the interrupt */ 650 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 651 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 652 if (err) { 653 device_printf(dev, "Cannot setup IRQ\n"); 654 return (err); 655 } 656 657 /* Process cards detection. */ 658 for (i = 0; i < sc->num_slots; i++) 659 sdhci_start_slot(&sc->slots[i]); 660 661 return (0); 662 } 663 664 static int 665 sdhci_fdt_detach(device_t dev) 666 { 667 struct sdhci_fdt_softc *sc = device_get_softc(dev); 668 int i; 669 670 bus_generic_detach(dev); 671 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 672 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 673 sc->irq_res); 674 675 for (i = 0; i < sc->num_slots; i++) { 676 sdhci_cleanup_slot(&sc->slots[i]); 677 bus_release_resource(dev, SYS_RES_MEMORY, 678 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 679 } 680 681 return (0); 682 } 683 684 static device_method_t sdhci_fdt_methods[] = { 685 /* device_if */ 686 DEVMETHOD(device_probe, sdhci_fdt_probe), 687 DEVMETHOD(device_attach, sdhci_fdt_attach), 688 DEVMETHOD(device_detach, sdhci_fdt_detach), 689 690 /* Bus interface */ 691 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 692 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 693 694 /* mmcbr_if */ 695 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 696 DEVMETHOD(mmcbr_request, sdhci_generic_request), 697 DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), 698 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 699 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 700 701 /* SDHCI registers accessors */ 702 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 703 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 704 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 705 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 706 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 707 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 708 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 709 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 710 DEVMETHOD(sdhci_set_clock, sdhci_fdt_set_clock), 711 712 DEVMETHOD_END 713 }; 714 715 static driver_t sdhci_fdt_driver = { 716 "sdhci_fdt", 717 sdhci_fdt_methods, 718 sizeof(struct sdhci_fdt_softc), 719 }; 720 721 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, NULL, NULL); 722 SDHCI_DEPEND(sdhci_fdt); 723 #ifndef MMCCAM 724 MMC_DECLARE_BRIDGE(sdhci_fdt); 725 #endif 726