1 /*- 2 * Copyright (c) 2012 Thomas Skibo 3 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* Generic driver to attach sdhci controllers on simplebus. 28 * Derived mainly from sdhci_pci.c 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <dev/mmc/bridge.h> 54 55 #include <dev/sdhci/sdhci.h> 56 57 #include "mmcbr_if.h" 58 #include "sdhci_if.h" 59 60 #define MAX_SLOTS 6 61 #define SDHCI_FDT_ARMADA38X 1 62 #define SDHCI_FDT_GENERIC 2 63 #define SDHCI_FDT_XLNX_ZY7 3 64 65 static struct ofw_compat_data compat_data[] = { 66 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, 67 { "sdhci_generic", SDHCI_FDT_GENERIC }, 68 { "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 }, 69 { NULL, 0 } 70 }; 71 72 struct sdhci_fdt_softc { 73 device_t dev; /* Controller device */ 74 u_int quirks; /* Chip specific quirks */ 75 u_int caps; /* If we override SDHCI_CAPABILITIES */ 76 uint32_t max_clk; /* Max possible freq */ 77 struct resource *irq_res; /* IRQ resource */ 78 void *intrhand; /* Interrupt handle */ 79 80 int num_slots; /* Number of slots on this controller*/ 81 struct sdhci_slot slots[MAX_SLOTS]; 82 struct resource *mem_res[MAX_SLOTS]; /* Memory resource */ 83 84 bool wp_inverted; /* WP pin is inverted */ 85 bool no_18v; /* No 1.8V support */ 86 }; 87 88 static uint8_t 89 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 90 { 91 struct sdhci_fdt_softc *sc = device_get_softc(dev); 92 93 return (bus_read_1(sc->mem_res[slot->num], off)); 94 } 95 96 static void 97 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 98 uint8_t val) 99 { 100 struct sdhci_fdt_softc *sc = device_get_softc(dev); 101 102 bus_write_1(sc->mem_res[slot->num], off, val); 103 } 104 105 static uint16_t 106 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 107 { 108 struct sdhci_fdt_softc *sc = device_get_softc(dev); 109 110 return (bus_read_2(sc->mem_res[slot->num], off)); 111 } 112 113 static void 114 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 115 uint16_t val) 116 { 117 struct sdhci_fdt_softc *sc = device_get_softc(dev); 118 119 bus_write_2(sc->mem_res[slot->num], off, val); 120 } 121 122 static uint32_t 123 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 124 { 125 struct sdhci_fdt_softc *sc = device_get_softc(dev); 126 uint32_t val32; 127 128 val32 = bus_read_4(sc->mem_res[slot->num], off); 129 if (off == SDHCI_CAPABILITIES && sc->no_18v) 130 val32 &= ~SDHCI_CAN_VDD_180; 131 132 return (val32); 133 } 134 135 static void 136 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 137 uint32_t val) 138 { 139 struct sdhci_fdt_softc *sc = device_get_softc(dev); 140 141 bus_write_4(sc->mem_res[slot->num], off, val); 142 } 143 144 static void 145 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 146 bus_size_t off, uint32_t *data, bus_size_t count) 147 { 148 struct sdhci_fdt_softc *sc = device_get_softc(dev); 149 150 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 151 } 152 153 static void 154 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 155 bus_size_t off, uint32_t *data, bus_size_t count) 156 { 157 struct sdhci_fdt_softc *sc = device_get_softc(dev); 158 159 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 160 } 161 162 static void 163 sdhci_fdt_intr(void *arg) 164 { 165 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 166 int i; 167 168 for (i = 0; i < sc->num_slots; i++) 169 sdhci_generic_intr(&sc->slots[i]); 170 } 171 172 static int 173 sdhci_fdt_get_ro(device_t bus, device_t dev) 174 { 175 struct sdhci_fdt_softc *sc = device_get_softc(bus); 176 177 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 178 } 179 180 static int 181 sdhci_fdt_probe(device_t dev) 182 { 183 struct sdhci_fdt_softc *sc = device_get_softc(dev); 184 phandle_t node; 185 pcell_t cid; 186 187 sc->quirks = 0; 188 sc->num_slots = 1; 189 sc->max_clk = 0; 190 191 if (!ofw_bus_status_okay(dev)) 192 return (ENXIO); 193 194 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 195 case SDHCI_FDT_ARMADA38X: 196 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; 197 device_set_desc(dev, "ARMADA38X SDHCI controller"); 198 break; 199 case SDHCI_FDT_GENERIC: 200 device_set_desc(dev, "generic fdt SDHCI controller"); 201 break; 202 case SDHCI_FDT_XLNX_ZY7: 203 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 204 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 205 break; 206 default: 207 return (ENXIO); 208 } 209 210 node = ofw_bus_get_node(dev); 211 212 /* Allow dts to patch quirks, slots, and max-frequency. */ 213 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 214 sc->quirks = cid; 215 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) 216 sc->num_slots = cid; 217 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 218 sc->max_clk = cid; 219 if (OF_hasprop(node, "no-1-8-v")) 220 sc->no_18v = true; 221 if (OF_hasprop(node, "wp-inverted")) 222 sc->wp_inverted = true; 223 224 return (0); 225 } 226 227 static int 228 sdhci_fdt_attach(device_t dev) 229 { 230 struct sdhci_fdt_softc *sc = device_get_softc(dev); 231 struct sdhci_slot *slot; 232 int err, slots, rid, i; 233 234 sc->dev = dev; 235 236 /* Allocate IRQ. */ 237 rid = 0; 238 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 239 RF_ACTIVE); 240 if (sc->irq_res == NULL) { 241 device_printf(dev, "Can't allocate IRQ\n"); 242 return (ENOMEM); 243 } 244 245 /* Scan all slots. */ 246 slots = sc->num_slots; /* number of slots determined in probe(). */ 247 sc->num_slots = 0; 248 for (i = 0; i < slots; i++) { 249 slot = &sc->slots[sc->num_slots]; 250 251 /* Allocate memory. */ 252 rid = 0; 253 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 254 &rid, RF_ACTIVE); 255 if (sc->mem_res[i] == NULL) { 256 device_printf(dev, 257 "Can't allocate memory for slot %d\n", i); 258 continue; 259 } 260 261 slot->quirks = sc->quirks; 262 slot->caps = sc->caps; 263 slot->max_clk = sc->max_clk; 264 265 if (sdhci_init_slot(dev, slot, i) != 0) 266 continue; 267 268 sc->num_slots++; 269 } 270 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 271 272 /* Activate the interrupt */ 273 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 274 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 275 if (err) { 276 device_printf(dev, "Cannot setup IRQ\n"); 277 return (err); 278 } 279 280 /* Process cards detection. */ 281 for (i = 0; i < sc->num_slots; i++) 282 sdhci_start_slot(&sc->slots[i]); 283 284 return (0); 285 } 286 287 static int 288 sdhci_fdt_detach(device_t dev) 289 { 290 struct sdhci_fdt_softc *sc = device_get_softc(dev); 291 int i; 292 293 bus_generic_detach(dev); 294 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 295 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 296 sc->irq_res); 297 298 for (i = 0; i < sc->num_slots; i++) { 299 sdhci_cleanup_slot(&sc->slots[i]); 300 bus_release_resource(dev, SYS_RES_MEMORY, 301 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 302 } 303 304 return (0); 305 } 306 307 static device_method_t sdhci_fdt_methods[] = { 308 /* device_if */ 309 DEVMETHOD(device_probe, sdhci_fdt_probe), 310 DEVMETHOD(device_attach, sdhci_fdt_attach), 311 DEVMETHOD(device_detach, sdhci_fdt_detach), 312 313 /* Bus interface */ 314 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 315 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 316 317 /* mmcbr_if */ 318 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 319 DEVMETHOD(mmcbr_request, sdhci_generic_request), 320 DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), 321 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 322 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 323 324 /* SDHCI registers accessors */ 325 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 326 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 327 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 328 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 329 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 330 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 331 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 332 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 333 334 DEVMETHOD_END 335 }; 336 337 static driver_t sdhci_fdt_driver = { 338 "sdhci_fdt", 339 sdhci_fdt_methods, 340 sizeof(struct sdhci_fdt_softc), 341 }; 342 static devclass_t sdhci_fdt_devclass; 343 344 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass, 345 NULL, NULL); 346 MODULE_DEPEND(sdhci_fdt, sdhci, 1, 1, 1); 347 MMC_DECLARE_BRIDGE(sdhci_fdt); 348