1 /*- 2 * Copyright (c) 2012 Thomas Skibo 3 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* Generic driver to attach sdhci controllers on simplebus. 28 * Derived mainly from sdhci_pci.c 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <machine/stdarg.h> 50 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/mmc/bridge.h> 56 #include <dev/mmc/mmcreg.h> 57 #include <dev/mmc/mmcbrvar.h> 58 #include <dev/sdhci/sdhci.h> 59 60 #include "mmcbr_if.h" 61 #include "sdhci_if.h" 62 63 #define MAX_SLOTS 6 64 65 struct sdhci_fdt_softc { 66 device_t dev; /* Controller device */ 67 u_int quirks; /* Chip specific quirks */ 68 u_int caps; /* If we override SDHCI_CAPABILITIES */ 69 struct resource *irq_res; /* IRQ resource */ 70 void *intrhand; /* Interrupt handle */ 71 72 int num_slots; /* Number of slots on this controller*/ 73 struct sdhci_slot slots[MAX_SLOTS]; 74 struct resource *mem_res[MAX_SLOTS]; /* Memory resource */ 75 }; 76 77 static uint8_t 78 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 79 { 80 struct sdhci_fdt_softc *sc = device_get_softc(dev); 81 return (bus_read_1(sc->mem_res[slot->num], off)); 82 } 83 84 static void 85 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 86 uint8_t val) 87 { 88 struct sdhci_fdt_softc *sc = device_get_softc(dev); 89 bus_write_1(sc->mem_res[slot->num], off, val); 90 } 91 92 static uint16_t 93 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 94 { 95 struct sdhci_fdt_softc *sc = device_get_softc(dev); 96 return (bus_read_2(sc->mem_res[slot->num], off)); 97 } 98 99 static void 100 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 101 uint16_t val) 102 { 103 struct sdhci_fdt_softc *sc = device_get_softc(dev); 104 bus_write_2(sc->mem_res[slot->num], off, val); 105 } 106 107 static uint32_t 108 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 109 { 110 struct sdhci_fdt_softc *sc = device_get_softc(dev); 111 return (bus_read_4(sc->mem_res[slot->num], off)); 112 } 113 114 static void 115 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 116 uint32_t val) 117 { 118 struct sdhci_fdt_softc *sc = device_get_softc(dev); 119 bus_write_4(sc->mem_res[slot->num], off, val); 120 } 121 122 static void 123 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 124 bus_size_t off, uint32_t *data, bus_size_t count) 125 { 126 struct sdhci_fdt_softc *sc = device_get_softc(dev); 127 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 128 } 129 130 static void 131 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 132 bus_size_t off, uint32_t *data, bus_size_t count) 133 { 134 struct sdhci_fdt_softc *sc = device_get_softc(dev); 135 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 136 } 137 138 static void 139 sdhci_fdt_intr(void *arg) 140 { 141 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 142 int i; 143 144 for (i = 0; i < sc->num_slots; i++) { 145 struct sdhci_slot *slot = &sc->slots[i]; 146 sdhci_generic_intr(slot); 147 } 148 } 149 150 static int 151 sdhci_fdt_probe(device_t dev) 152 { 153 struct sdhci_fdt_softc *sc = device_get_softc(dev); 154 phandle_t node; 155 pcell_t cid; 156 157 sc->quirks = 0; 158 sc->num_slots = 1; 159 160 if (!ofw_bus_status_okay(dev)) 161 return (ENXIO); 162 163 if (ofw_bus_is_compatible(dev, "sdhci_generic")) { 164 device_set_desc(dev, "generic fdt SDHCI controller"); 165 } else if (ofw_bus_is_compatible(dev, "xlnx,zy7_sdhci")) { 166 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 167 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 168 } else 169 return (ENXIO); 170 171 node = ofw_bus_get_node(dev); 172 173 /* Allow dts to patch quirks and slots. */ 174 if ((OF_getprop(node, "quirks", &cid, sizeof(cid))) > 0) 175 sc->quirks = fdt32_to_cpu(cid); 176 if ((OF_getprop(node, "num-slots", &cid, sizeof(cid))) > 0) 177 sc->num_slots = fdt32_to_cpu(cid); 178 179 return (0); 180 } 181 182 static int 183 sdhci_fdt_attach(device_t dev) 184 { 185 struct sdhci_fdt_softc *sc = device_get_softc(dev); 186 int err, slots, rid, i; 187 188 sc->dev = dev; 189 190 /* Allocate IRQ. */ 191 rid = 0; 192 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 193 RF_ACTIVE); 194 if (sc->irq_res == NULL) { 195 device_printf(dev, "Can't allocate IRQ\n"); 196 return (ENOMEM); 197 } 198 199 /* Scan all slots. */ 200 slots = sc->num_slots; /* number of slots determined in probe(). */ 201 sc->num_slots = 0; 202 for (i = 0; i < slots; i++) { 203 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 204 205 /* Allocate memory. */ 206 rid = 0; 207 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 208 &rid, RF_ACTIVE); 209 if (sc->mem_res[i] == NULL) { 210 device_printf(dev, "Can't allocate memory for " 211 "slot %d\n", i); 212 continue; 213 } 214 215 slot->quirks = sc->quirks; 216 slot->caps = sc->caps; 217 218 if (sdhci_init_slot(dev, slot, i) != 0) 219 continue; 220 221 sc->num_slots++; 222 } 223 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 224 225 /* Activate the interrupt */ 226 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 227 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 228 if (err) { 229 device_printf(dev, "Cannot setup IRQ\n"); 230 return (err); 231 } 232 233 /* Process cards detection. */ 234 for (i = 0; i < sc->num_slots; i++) { 235 struct sdhci_slot *slot = &sc->slots[i]; 236 sdhci_start_slot(slot); 237 } 238 239 return (0); 240 } 241 242 static int 243 sdhci_fdt_detach(device_t dev) 244 { 245 struct sdhci_fdt_softc *sc = device_get_softc(dev); 246 int i; 247 248 bus_generic_detach(dev); 249 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 250 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 251 sc->irq_res); 252 253 for (i = 0; i < sc->num_slots; i++) { 254 struct sdhci_slot *slot = &sc->slots[i]; 255 256 sdhci_cleanup_slot(slot); 257 bus_release_resource(dev, SYS_RES_MEMORY, 258 rman_get_rid(sc->mem_res[i]), 259 sc->mem_res[i]); 260 } 261 262 return (0); 263 } 264 265 static device_method_t sdhci_fdt_methods[] = { 266 /* device_if */ 267 DEVMETHOD(device_probe, sdhci_fdt_probe), 268 DEVMETHOD(device_attach, sdhci_fdt_attach), 269 DEVMETHOD(device_detach, sdhci_fdt_detach), 270 271 /* Bus interface */ 272 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 273 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 274 275 /* mmcbr_if */ 276 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 277 DEVMETHOD(mmcbr_request, sdhci_generic_request), 278 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 279 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 280 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 281 282 /* SDHCI registers accessors */ 283 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 284 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 285 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 286 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 287 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 288 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 289 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 290 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 291 292 DEVMETHOD_END 293 }; 294 295 static driver_t sdhci_fdt_driver = { 296 "sdhci_fdt", 297 sdhci_fdt_methods, 298 sizeof(struct sdhci_fdt_softc), 299 }; 300 static devclass_t sdhci_fdt_devclass; 301 302 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, sdhci_fdt_devclass, 0,0); 303 MODULE_DEPEND(sdhci_fdt, sdhci, 1, 1, 1); 304