1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Thomas Skibo 5 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* Generic driver to attach sdhci controllers on simplebus. 30 * Derived mainly from sdhci_pci.c 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 #include <sys/taskqueue.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 48 #include <dev/fdt/fdt_common.h> 49 #include <dev/ofw/ofw_bus.h> 50 51 #include <dev/clk/clk.h> 52 #include <dev/clk/clk_fixed.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/ofw/ofw_subr.h> 56 #include <dev/ofw/openfirm.h> 57 #include <dev/syscon/syscon.h> 58 #include <dev/phy/phy.h> 59 60 #include <dev/mmc/bridge.h> 61 62 #include <dev/sdhci/sdhci.h> 63 #include <dev/sdhci/sdhci_fdt.h> 64 65 #include "mmcbr_if.h" 66 #include "sdhci_if.h" 67 68 #include "opt_mmccam.h" 69 70 #define SDHCI_FDT_ARMADA38X 1 71 #define SDHCI_FDT_XLNX_ZY7 2 72 #define SDHCI_FDT_QUALCOMM 3 73 74 static struct ofw_compat_data compat_data[] = { 75 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, 76 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM }, 77 { "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 }, 78 { NULL, 0 } 79 }; 80 81 struct sdhci_exported_clocks_sc { 82 device_t clkdev; 83 }; 84 85 static int 86 sdhci_exported_clocks_init(struct clknode *clk, device_t dev) 87 { 88 89 clknode_init_parent_idx(clk, 0); 90 return (0); 91 } 92 93 static clknode_method_t sdhci_exported_clocks_clknode_methods[] = { 94 /* Device interface */ 95 CLKNODEMETHOD(clknode_init, sdhci_exported_clocks_init), 96 CLKNODEMETHOD_END 97 }; 98 DEFINE_CLASS_1(sdhci_exported_clocks_clknode, sdhci_exported_clocks_clknode_class, 99 sdhci_exported_clocks_clknode_methods, sizeof(struct sdhci_exported_clocks_sc), 100 clknode_class); 101 102 int 103 sdhci_clock_ofw_map(struct clkdom *clkdom, uint32_t ncells, 104 phandle_t *cells, struct clknode **clk) 105 { 106 int id = 1; /* Our clock id starts at 1 */ 107 108 if (ncells != 0) 109 id = cells[1]; 110 *clk = clknode_find_by_id(clkdom, id); 111 112 if (*clk == NULL) 113 return (ENXIO); 114 return (0); 115 } 116 117 void 118 sdhci_export_clocks(struct sdhci_fdt_softc *sc) 119 { 120 struct clknode_init_def def; 121 struct sdhci_exported_clocks_sc *clksc; 122 struct clkdom *clkdom; 123 struct clknode *clk; 124 bus_addr_t paddr; 125 bus_size_t psize; 126 const char **clknames; 127 phandle_t node; 128 int i, nclocks, ncells, error; 129 130 node = ofw_bus_get_node(sc->dev); 131 132 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 133 device_printf(sc->dev, "cannot parse 'reg' property\n"); 134 return; 135 } 136 137 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 138 "#clock-cells", &ncells); 139 if (error != 0 || ncells != 2) { 140 device_printf(sc->dev, "couldn't find parent clocks\n"); 141 return; 142 } 143 144 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", 145 &clknames); 146 /* No clocks to export */ 147 if (nclocks <= 0) 148 return; 149 150 clkdom = clkdom_create(sc->dev); 151 clkdom_set_ofw_mapper(clkdom, sdhci_clock_ofw_map); 152 153 for (i = 0; i < nclocks; i++) { 154 memset(&def, 0, sizeof(def)); 155 def.id = i + 1; /* Exported clock IDs starts at 1 */ 156 def.name = clknames[i]; 157 def.parent_names = malloc(sizeof(char *) * 1, M_OFWPROP, M_WAITOK); 158 def.parent_names[0] = clk_get_name(sc->clk_xin); 159 def.parent_cnt = 1; 160 161 clk = clknode_create(clkdom, &sdhci_exported_clocks_clknode_class, &def); 162 if (clk == NULL) { 163 device_printf(sc->dev, "cannot create clknode\n"); 164 return; 165 } 166 167 clksc = clknode_get_softc(clk); 168 clksc->clkdev = device_get_parent(sc->dev); 169 170 clknode_register(clkdom, clk); 171 } 172 173 if (clkdom_finit(clkdom) != 0) { 174 device_printf(sc->dev, "cannot finalize clkdom initialization\n"); 175 return; 176 } 177 178 if (bootverbose) 179 clkdom_dump(clkdom); 180 } 181 182 int 183 sdhci_init_clocks(device_t dev) 184 { 185 struct sdhci_fdt_softc *sc = device_get_softc(dev); 186 int error; 187 188 /* Get and activate clocks */ 189 error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin); 190 if (error != 0) { 191 device_printf(dev, "cannot get xin clock\n"); 192 return (ENXIO); 193 } 194 error = clk_enable(sc->clk_xin); 195 if (error != 0) { 196 device_printf(dev, "cannot enable xin clock\n"); 197 return (ENXIO); 198 } 199 error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb); 200 if (error != 0) { 201 device_printf(dev, "cannot get ahb clock\n"); 202 return (ENXIO); 203 } 204 error = clk_enable(sc->clk_ahb); 205 if (error != 0) { 206 device_printf(dev, "cannot enable ahb clock\n"); 207 return (ENXIO); 208 } 209 210 return (0); 211 } 212 213 int 214 sdhci_init_phy(struct sdhci_fdt_softc *sc) 215 { 216 int error; 217 218 /* Enable PHY */ 219 error = phy_get_by_ofw_name(sc->dev, 0, "phy_arasan", &sc->phy); 220 if (error == ENOENT) 221 return (0); 222 if (error != 0) { 223 device_printf(sc->dev, "Could not get phy\n"); 224 return (ENXIO); 225 } 226 error = phy_enable(sc->phy); 227 if (error != 0) { 228 device_printf(sc->dev, "Could not enable phy\n"); 229 return (ENXIO); 230 } 231 232 return (0); 233 } 234 235 int 236 sdhci_get_syscon(struct sdhci_fdt_softc *sc) 237 { 238 phandle_t node; 239 240 /* Get syscon */ 241 node = ofw_bus_get_node(sc->dev); 242 if (OF_hasprop(node, "arasan,soc-ctl-syscon") && 243 syscon_get_by_ofw_property(sc->dev, node, 244 "arasan,soc-ctl-syscon", &sc->syscon) != 0) { 245 device_printf(sc->dev, "cannot get syscon handle\n"); 246 return (ENXIO); 247 } 248 249 return (0); 250 } 251 252 static uint8_t 253 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 254 { 255 struct sdhci_fdt_softc *sc = device_get_softc(dev); 256 257 return (bus_read_1(sc->mem_res[slot->num], off)); 258 } 259 260 static void 261 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 262 uint8_t val) 263 { 264 struct sdhci_fdt_softc *sc = device_get_softc(dev); 265 266 bus_write_1(sc->mem_res[slot->num], off, val); 267 } 268 269 static uint16_t 270 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 271 { 272 struct sdhci_fdt_softc *sc = device_get_softc(dev); 273 274 return (bus_read_2(sc->mem_res[slot->num], off)); 275 } 276 277 static void 278 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 279 uint16_t val) 280 { 281 struct sdhci_fdt_softc *sc = device_get_softc(dev); 282 283 bus_write_2(sc->mem_res[slot->num], off, val); 284 } 285 286 static uint32_t 287 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 288 { 289 struct sdhci_fdt_softc *sc = device_get_softc(dev); 290 uint32_t val32; 291 292 val32 = bus_read_4(sc->mem_res[slot->num], off); 293 if (off == SDHCI_CAPABILITIES && sc->no_18v) 294 val32 &= ~SDHCI_CAN_VDD_180; 295 296 return (val32); 297 } 298 299 static void 300 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 301 uint32_t val) 302 { 303 struct sdhci_fdt_softc *sc = device_get_softc(dev); 304 305 bus_write_4(sc->mem_res[slot->num], off, val); 306 } 307 308 static void 309 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 310 bus_size_t off, uint32_t *data, bus_size_t count) 311 { 312 struct sdhci_fdt_softc *sc = device_get_softc(dev); 313 314 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 315 } 316 317 static void 318 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 319 bus_size_t off, uint32_t *data, bus_size_t count) 320 { 321 struct sdhci_fdt_softc *sc = device_get_softc(dev); 322 323 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 324 } 325 326 static void 327 sdhci_fdt_intr(void *arg) 328 { 329 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 330 int i; 331 332 for (i = 0; i < sc->num_slots; i++) 333 sdhci_generic_intr(&sc->slots[i]); 334 } 335 336 static int 337 sdhci_fdt_get_ro(device_t bus, device_t dev) 338 { 339 struct sdhci_fdt_softc *sc = device_get_softc(bus); 340 341 if (sc->wp_disabled) 342 return (false); 343 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 344 } 345 346 static int 347 sdhci_fdt_probe(device_t dev) 348 { 349 struct sdhci_fdt_softc *sc = device_get_softc(dev); 350 351 if (!ofw_bus_status_okay(dev)) 352 return (ENXIO); 353 354 sc->quirks = 0; 355 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 356 case SDHCI_FDT_ARMADA38X: 357 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; 358 device_set_desc(dev, "ARMADA38X SDHCI controller"); 359 break; 360 case SDHCI_FDT_QUALCOMM: 361 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 362 SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY; 363 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 364 device_set_desc(dev, "Qualcomm FDT SDHCI controller"); 365 break; 366 case SDHCI_FDT_XLNX_ZY7: 367 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 368 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 369 break; 370 default: 371 return (ENXIO); 372 } 373 374 return (0); 375 } 376 377 int 378 sdhci_fdt_attach(device_t dev) 379 { 380 struct sdhci_fdt_softc *sc = device_get_softc(dev); 381 struct sdhci_slot *slot; 382 int err, slots, rid, i; 383 phandle_t node; 384 pcell_t cid; 385 386 sc->dev = dev; 387 388 node = ofw_bus_get_node(dev); 389 390 sc->num_slots = 1; 391 sc->max_clk = 0; 392 393 /* Allow dts to patch quirks, slots, and max-frequency. */ 394 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 395 sc->quirks = cid; 396 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) 397 sc->num_slots = cid; 398 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 399 sc->max_clk = cid; 400 if (OF_hasprop(node, "no-1-8-v")) 401 sc->no_18v = true; 402 if (OF_hasprop(node, "wp-inverted")) 403 sc->wp_inverted = true; 404 if (OF_hasprop(node, "disable-wp")) 405 sc->wp_disabled = true; 406 407 /* Allocate IRQ. */ 408 rid = 0; 409 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 410 RF_ACTIVE); 411 if (sc->irq_res == NULL) { 412 device_printf(dev, "Can't allocate IRQ\n"); 413 return (ENOMEM); 414 } 415 416 /* Scan all slots. */ 417 slots = sc->num_slots; /* number of slots determined in probe(). */ 418 sc->num_slots = 0; 419 for (i = 0; i < slots; i++) { 420 slot = &sc->slots[sc->num_slots]; 421 422 /* Allocate memory. */ 423 rid = 0; 424 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 425 &rid, RF_ACTIVE); 426 if (sc->mem_res[i] == NULL) { 427 device_printf(dev, 428 "Can't allocate memory for slot %d\n", i); 429 continue; 430 } 431 432 slot->quirks = sc->quirks; 433 slot->caps = sc->caps; 434 slot->max_clk = sc->max_clk; 435 slot->sdma_boundary = sc->sdma_boundary; 436 437 if (sdhci_init_slot(dev, slot, i) != 0) 438 continue; 439 sc->num_slots++; 440 } 441 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 442 443 /* Activate the interrupt */ 444 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 445 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 446 if (err) { 447 device_printf(dev, "Cannot setup IRQ\n"); 448 return (err); 449 } 450 451 /* Process cards detection. */ 452 for (i = 0; i < sc->num_slots; i++) 453 sdhci_start_slot(&sc->slots[i]); 454 455 return (0); 456 } 457 458 int 459 sdhci_fdt_detach(device_t dev) 460 { 461 struct sdhci_fdt_softc *sc = device_get_softc(dev); 462 int i; 463 464 bus_detach_children(dev); 465 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 466 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 467 sc->irq_res); 468 469 for (i = 0; i < sc->num_slots; i++) { 470 sdhci_cleanup_slot(&sc->slots[i]); 471 bus_release_resource(dev, SYS_RES_MEMORY, 472 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 473 } 474 475 return (0); 476 } 477 478 int 479 sdhci_fdt_set_clock(device_t dev, struct sdhci_slot *slot, int clock) 480 { 481 482 return (clock); 483 } 484 485 486 static device_method_t sdhci_fdt_methods[] = { 487 /* device_if */ 488 DEVMETHOD(device_probe, sdhci_fdt_probe), 489 DEVMETHOD(device_attach, sdhci_fdt_attach), 490 DEVMETHOD(device_detach, sdhci_fdt_detach), 491 492 /* Bus interface */ 493 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 494 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 495 496 /* mmcbr_if */ 497 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 498 DEVMETHOD(mmcbr_request, sdhci_generic_request), 499 DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), 500 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 501 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 502 503 /* SDHCI registers accessors */ 504 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 505 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 506 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 507 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 508 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 509 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 510 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 511 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 512 DEVMETHOD(sdhci_set_clock, sdhci_fdt_set_clock), 513 514 DEVMETHOD_END 515 }; 516 517 driver_t sdhci_fdt_driver = { 518 "sdhci_fdt", 519 sdhci_fdt_methods, 520 sizeof(struct sdhci_fdt_softc), 521 }; 522 523 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, NULL, NULL); 524 SDHCI_DEPEND(sdhci_fdt); 525 #ifndef MMCCAM 526 MMC_DECLARE_BRIDGE(sdhci_fdt); 527 #endif 528