1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Thomas Skibo 5 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* Generic driver to attach sdhci controllers on simplebus. 30 * Derived mainly from sdhci_pci.c 31 */ 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include <dev/ofw/ofw_subr.h> 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/clk/clk_fixed.h> 56 #include <dev/extres/syscon/syscon.h> 57 #include <dev/extres/phy/phy.h> 58 59 #include <dev/mmc/bridge.h> 60 61 #include <dev/sdhci/sdhci.h> 62 63 #include "mmcbr_if.h" 64 #include "sdhci_if.h" 65 66 #include "opt_mmccam.h" 67 68 #include "clkdev_if.h" 69 #include "syscon_if.h" 70 71 #define MAX_SLOTS 6 72 #define SDHCI_FDT_ARMADA38X 1 73 #define SDHCI_FDT_GENERIC 2 74 #define SDHCI_FDT_XLNX_ZY7 3 75 #define SDHCI_FDT_QUALCOMM 4 76 #define SDHCI_FDT_RK3399 5 77 #define SDHCI_FDT_RK3568 6 78 #define SDHCI_FDT_XLNX_ZMP 7 79 80 #define RK3399_GRF_EMMCCORE_CON0 0xf000 81 #define RK3399_CORECFG_BASECLKFREQ 0xff00 82 #define RK3399_CORECFG_TIMEOUTCLKUNIT (1 << 7) 83 #define RK3399_CORECFG_TUNINGCOUNT 0x3f 84 #define RK3399_GRF_EMMCCORE_CON11 0xf02c 85 #define RK3399_CORECFG_CLOCKMULTIPLIER 0xff 86 87 #define RK3568_EMMC_HOST_CTRL 0x0508 88 #define RK3568_EMMC_EMMC_CTRL 0x052c 89 #define RK3568_EMMC_ATCTRL 0x0540 90 #define RK3568_EMMC_DLL_CTRL 0x0800 91 #define DLL_CTRL_SRST 0x00000001 92 #define DLL_CTRL_START 0x00000002 93 #define DLL_CTRL_START_POINT_DEFAULT 0x00050000 94 #define DLL_CTRL_INCREMENT_DEFAULT 0x00000200 95 96 #define RK3568_EMMC_DLL_RXCLK 0x0804 97 #define DLL_RXCLK_DELAY_ENABLE 0x08000000 98 #define DLL_RXCLK_NO_INV 0x20000000 99 100 #define RK3568_EMMC_DLL_TXCLK 0x0808 101 #define DLL_TXCLK_DELAY_ENABLE 0x08000000 102 #define DLL_TXCLK_TAPNUM_DEFAULT 0x00000008 103 #define DLL_TXCLK_TAPNUM_FROM_SW 0x01000000 104 105 #define RK3568_EMMC_DLL_STRBIN 0x080c 106 #define DLL_STRBIN_DELAY_ENABLE 0x08000000 107 #define DLL_STRBIN_TAPNUM_DEFAULT 0x00000008 108 #define DLL_STRBIN_TAPNUM_FROM_SW 0x01000000 109 110 #define RK3568_EMMC_DLL_STATUS0 0x0840 111 #define DLL_STATUS0_DLL_LOCK 0x00000100 112 #define DLL_STATUS0_DLL_TIMEOUT 0x00000200 113 114 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) 115 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) 116 117 #define EMMCCARDCLK_ID 1000 118 119 static struct ofw_compat_data compat_data[] = { 120 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, 121 { "sdhci_generic", SDHCI_FDT_GENERIC }, 122 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM }, 123 { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 }, 124 { "xlnx,zy7_sdhci", SDHCI_FDT_XLNX_ZY7 }, 125 { "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 }, 126 { "xlnx,zynqmp-8.9a", SDHCI_FDT_XLNX_ZMP }, 127 { NULL, 0 } 128 }; 129 130 struct sdhci_fdt_softc { 131 device_t dev; /* Controller device */ 132 u_int quirks; /* Chip specific quirks */ 133 u_int caps; /* If we override SDHCI_CAPABILITIES */ 134 uint32_t max_clk; /* Max possible freq */ 135 uint8_t sdma_boundary; /* If we override the SDMA boundary */ 136 struct resource *irq_res; /* IRQ resource */ 137 void *intrhand; /* Interrupt handle */ 138 139 int num_slots; /* Number of slots on this controller*/ 140 struct sdhci_slot slots[MAX_SLOTS]; 141 struct resource *mem_res[MAX_SLOTS]; /* Memory resource */ 142 143 bool wp_inverted; /* WP pin is inverted */ 144 bool wp_disabled; /* WP pin is not supported */ 145 bool no_18v; /* No 1.8V support */ 146 147 clk_t clk_xin; /* xin24m fixed clock */ 148 clk_t clk_ahb; /* ahb clock */ 149 clk_t clk_core; /* core clock */ 150 phy_t phy; /* phy to be used */ 151 }; 152 153 struct rk3399_emmccardclk_sc { 154 device_t clkdev; 155 bus_addr_t reg; 156 }; 157 158 static int 159 rk3399_emmccardclk_init(struct clknode *clk, device_t dev) 160 { 161 162 clknode_init_parent_idx(clk, 0); 163 return (0); 164 } 165 166 static clknode_method_t rk3399_emmccardclk_clknode_methods[] = { 167 /* Device interface */ 168 CLKNODEMETHOD(clknode_init, rk3399_emmccardclk_init), 169 CLKNODEMETHOD_END 170 }; 171 DEFINE_CLASS_1(rk3399_emmccardclk_clknode, rk3399_emmccardclk_clknode_class, 172 rk3399_emmccardclk_clknode_methods, sizeof(struct rk3399_emmccardclk_sc), 173 clknode_class); 174 175 static int 176 rk3399_ofw_map(struct clkdom *clkdom, uint32_t ncells, 177 phandle_t *cells, struct clknode **clk) 178 { 179 180 if (ncells == 0) 181 *clk = clknode_find_by_id(clkdom, EMMCCARDCLK_ID); 182 else 183 return (ERANGE); 184 185 if (*clk == NULL) 186 return (ENXIO); 187 return (0); 188 } 189 190 static void 191 sdhci_init_rk3399_emmccardclk(device_t dev) 192 { 193 struct clknode_init_def def; 194 struct rk3399_emmccardclk_sc *sc; 195 struct clkdom *clkdom; 196 struct clknode *clk; 197 clk_t clk_parent; 198 bus_addr_t paddr; 199 bus_size_t psize; 200 const char **clknames; 201 phandle_t node; 202 int i, nclocks, ncells, error; 203 204 node = ofw_bus_get_node(dev); 205 206 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 207 device_printf(dev, "cannot parse 'reg' property\n"); 208 return; 209 } 210 211 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 212 "#clock-cells", &ncells); 213 if (error != 0 || ncells != 2) { 214 device_printf(dev, "couldn't find parent clocks\n"); 215 return; 216 } 217 218 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", 219 &clknames); 220 /* No clocks to export */ 221 if (nclocks <= 0) 222 return; 223 224 if (nclocks != 1) { 225 device_printf(dev, "Having %d clock instead of 1, aborting\n", 226 nclocks); 227 return; 228 } 229 230 clkdom = clkdom_create(dev); 231 clkdom_set_ofw_mapper(clkdom, rk3399_ofw_map); 232 233 memset(&def, 0, sizeof(def)); 234 def.id = EMMCCARDCLK_ID; 235 def.name = clknames[0]; 236 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); 237 for (i = 0; i < ncells; i++) { 238 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); 239 if (error != 0) { 240 device_printf(dev, "cannot get clock %d\n", error); 241 return; 242 } 243 def.parent_names[i] = clk_get_name(clk_parent); 244 if (bootverbose) 245 device_printf(dev, "clk parent: %s\n", 246 def.parent_names[i]); 247 clk_release(clk_parent); 248 } 249 def.parent_cnt = ncells; 250 251 clk = clknode_create(clkdom, &rk3399_emmccardclk_clknode_class, &def); 252 if (clk == NULL) { 253 device_printf(dev, "cannot create clknode\n"); 254 return; 255 } 256 257 sc = clknode_get_softc(clk); 258 sc->reg = paddr; 259 sc->clkdev = device_get_parent(dev); 260 261 clknode_register(clkdom, clk); 262 263 if (clkdom_finit(clkdom) != 0) { 264 device_printf(dev, "cannot finalize clkdom initialization\n"); 265 return; 266 } 267 268 if (bootverbose) 269 clkdom_dump(clkdom); 270 } 271 272 static int 273 sdhci_init_rk3399(device_t dev) 274 { 275 struct sdhci_fdt_softc *sc = device_get_softc(dev); 276 struct syscon *grf = NULL; 277 phandle_t node; 278 uint64_t freq; 279 uint32_t mask, val; 280 int error; 281 282 /* Get and activate clocks */ 283 error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin); 284 if (error != 0) { 285 device_printf(dev, "cannot get xin clock\n"); 286 return (ENXIO); 287 } 288 error = clk_enable(sc->clk_xin); 289 if (error != 0) { 290 device_printf(dev, "cannot enable xin clock\n"); 291 return (ENXIO); 292 } 293 error = clk_get_freq(sc->clk_xin, &freq); 294 if (error != 0) { 295 device_printf(dev, "cannot get xin clock frequency\n"); 296 return (ENXIO); 297 } 298 error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb); 299 if (error != 0) { 300 device_printf(dev, "cannot get ahb clock\n"); 301 return (ENXIO); 302 } 303 error = clk_enable(sc->clk_ahb); 304 if (error != 0) { 305 device_printf(dev, "cannot enable ahb clock\n"); 306 return (ENXIO); 307 } 308 309 /* Register clock */ 310 sdhci_init_rk3399_emmccardclk(dev); 311 312 /* Enable PHY */ 313 error = phy_get_by_ofw_name(dev, 0, "phy_arasan", &sc->phy); 314 if (error != 0) { 315 device_printf(dev, "Could not get phy\n"); 316 return (ENXIO); 317 } 318 error = phy_enable(sc->phy); 319 if (error != 0) { 320 device_printf(dev, "Could not enable phy\n"); 321 return (ENXIO); 322 } 323 /* Get syscon */ 324 node = ofw_bus_get_node(dev); 325 if (OF_hasprop(node, "arasan,soc-ctl-syscon") && 326 syscon_get_by_ofw_property(dev, node, 327 "arasan,soc-ctl-syscon", &grf) != 0) { 328 device_printf(dev, "cannot get grf driver handle\n"); 329 return (ENXIO); 330 } 331 332 /* Disable clock multiplier */ 333 mask = RK3399_CORECFG_CLOCKMULTIPLIER; 334 val = 0; 335 SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val); 336 337 /* Set base clock frequency */ 338 mask = RK3399_CORECFG_BASECLKFREQ; 339 val = SHIFTIN((freq + (1000000 / 2)) / 1000000, 340 RK3399_CORECFG_BASECLKFREQ); 341 SYSCON_WRITE_4(grf, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val); 342 343 return (0); 344 } 345 346 static uint8_t 347 sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 348 { 349 struct sdhci_fdt_softc *sc = device_get_softc(dev); 350 351 return (bus_read_1(sc->mem_res[slot->num], off)); 352 } 353 354 static void 355 sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 356 uint8_t val) 357 { 358 struct sdhci_fdt_softc *sc = device_get_softc(dev); 359 360 bus_write_1(sc->mem_res[slot->num], off, val); 361 } 362 363 static uint16_t 364 sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 365 { 366 struct sdhci_fdt_softc *sc = device_get_softc(dev); 367 368 return (bus_read_2(sc->mem_res[slot->num], off)); 369 } 370 371 static void 372 sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 373 uint16_t val) 374 { 375 struct sdhci_fdt_softc *sc = device_get_softc(dev); 376 377 bus_write_2(sc->mem_res[slot->num], off, val); 378 } 379 380 static uint32_t 381 sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 382 { 383 struct sdhci_fdt_softc *sc = device_get_softc(dev); 384 uint32_t val32; 385 386 val32 = bus_read_4(sc->mem_res[slot->num], off); 387 if (off == SDHCI_CAPABILITIES && sc->no_18v) 388 val32 &= ~SDHCI_CAN_VDD_180; 389 390 return (val32); 391 } 392 393 static void 394 sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 395 uint32_t val) 396 { 397 struct sdhci_fdt_softc *sc = device_get_softc(dev); 398 399 bus_write_4(sc->mem_res[slot->num], off, val); 400 } 401 402 static void 403 sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, 404 bus_size_t off, uint32_t *data, bus_size_t count) 405 { 406 struct sdhci_fdt_softc *sc = device_get_softc(dev); 407 408 bus_read_multi_4(sc->mem_res[slot->num], off, data, count); 409 } 410 411 static void 412 sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 413 bus_size_t off, uint32_t *data, bus_size_t count) 414 { 415 struct sdhci_fdt_softc *sc = device_get_softc(dev); 416 417 bus_write_multi_4(sc->mem_res[slot->num], off, data, count); 418 } 419 420 static void 421 sdhci_fdt_intr(void *arg) 422 { 423 struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; 424 int i; 425 426 for (i = 0; i < sc->num_slots; i++) 427 sdhci_generic_intr(&sc->slots[i]); 428 } 429 430 static int 431 sdhci_fdt_get_ro(device_t bus, device_t dev) 432 { 433 struct sdhci_fdt_softc *sc = device_get_softc(bus); 434 435 if (sc->wp_disabled) 436 return (false); 437 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); 438 } 439 440 static int 441 sdhci_fdt_set_clock(device_t dev, struct sdhci_slot *slot, int clock) 442 { 443 struct sdhci_fdt_softc *sc = device_get_softc(dev); 444 int32_t val; 445 int i; 446 447 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 448 SDHCI_FDT_RK3568) { 449 if (clock == 400000) 450 clock = 375000; 451 452 if (clock) { 453 clk_set_freq(sc->clk_core, clock, 0); 454 455 if (clock <= 52000000) { 456 bus_write_4(sc->mem_res[slot->num], 457 RK3568_EMMC_DLL_CTRL, 0x0); 458 bus_write_4(sc->mem_res[slot->num], 459 RK3568_EMMC_DLL_RXCLK, DLL_RXCLK_NO_INV); 460 bus_write_4(sc->mem_res[slot->num], 461 RK3568_EMMC_DLL_TXCLK, 0x0); 462 bus_write_4(sc->mem_res[slot->num], 463 RK3568_EMMC_DLL_STRBIN, 0x0); 464 return (clock); 465 } 466 467 bus_write_4(sc->mem_res[slot->num], 468 RK3568_EMMC_DLL_CTRL, DLL_CTRL_START); 469 DELAY(1000); 470 bus_write_4(sc->mem_res[slot->num], 471 RK3568_EMMC_DLL_CTRL, 0); 472 bus_write_4(sc->mem_res[slot->num], 473 RK3568_EMMC_DLL_CTRL, DLL_CTRL_START_POINT_DEFAULT | 474 DLL_CTRL_INCREMENT_DEFAULT | DLL_CTRL_START); 475 for (i = 0; i < 500; i++) { 476 val = bus_read_4(sc->mem_res[slot->num], 477 RK3568_EMMC_DLL_STATUS0); 478 if (val & DLL_STATUS0_DLL_LOCK && 479 !(val & DLL_STATUS0_DLL_TIMEOUT)) 480 break; 481 DELAY(1000); 482 } 483 bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL, 484 (0x1 << 16 | 0x2 << 17 | 0x3 << 19)); 485 bus_write_4(sc->mem_res[slot->num], 486 RK3568_EMMC_DLL_RXCLK, 487 DLL_RXCLK_DELAY_ENABLE | DLL_RXCLK_NO_INV); 488 bus_write_4(sc->mem_res[slot->num], 489 RK3568_EMMC_DLL_TXCLK, DLL_TXCLK_DELAY_ENABLE | 490 DLL_TXCLK_TAPNUM_DEFAULT|DLL_TXCLK_TAPNUM_FROM_SW); 491 bus_write_4(sc->mem_res[slot->num], 492 RK3568_EMMC_DLL_STRBIN, DLL_STRBIN_DELAY_ENABLE | 493 DLL_STRBIN_TAPNUM_DEFAULT | 494 DLL_STRBIN_TAPNUM_FROM_SW); 495 } 496 } 497 return (clock); 498 } 499 500 static int 501 sdhci_fdt_probe(device_t dev) 502 { 503 struct sdhci_fdt_softc *sc = device_get_softc(dev); 504 phandle_t node; 505 pcell_t cid; 506 507 sc->quirks = 0; 508 sc->num_slots = 1; 509 sc->max_clk = 0; 510 511 if (!ofw_bus_status_okay(dev)) 512 return (ENXIO); 513 514 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 515 case SDHCI_FDT_ARMADA38X: 516 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP; 517 device_set_desc(dev, "ARMADA38X SDHCI controller"); 518 break; 519 case SDHCI_FDT_GENERIC: 520 device_set_desc(dev, "generic fdt SDHCI controller"); 521 break; 522 case SDHCI_FDT_QUALCOMM: 523 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 524 SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY; 525 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 526 device_set_desc(dev, "Qualcomm FDT SDHCI controller"); 527 break; 528 case SDHCI_FDT_RK3399: 529 device_set_desc(dev, "Rockchip RK3399 fdt SDHCI controller"); 530 break; 531 case SDHCI_FDT_XLNX_ZY7: 532 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 533 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); 534 break; 535 case SDHCI_FDT_RK3568: 536 device_set_desc(dev, "Rockchip RK3568 fdt SDHCI controller"); 537 break; 538 case SDHCI_FDT_XLNX_ZMP: 539 device_set_desc(dev, "ZynqMP generic fdt SDHCI controller"); 540 break; 541 default: 542 return (ENXIO); 543 } 544 545 node = ofw_bus_get_node(dev); 546 547 /* Allow dts to patch quirks, slots, and max-frequency. */ 548 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 549 sc->quirks = cid; 550 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) 551 sc->num_slots = cid; 552 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 553 sc->max_clk = cid; 554 if (OF_hasprop(node, "no-1-8-v")) 555 sc->no_18v = true; 556 if (OF_hasprop(node, "wp-inverted")) 557 sc->wp_inverted = true; 558 if (OF_hasprop(node, "disable-wp")) 559 sc->wp_disabled = true; 560 561 return (0); 562 } 563 564 static int 565 sdhci_fdt_attach(device_t dev) 566 { 567 struct sdhci_fdt_softc *sc = device_get_softc(dev); 568 struct sdhci_slot *slot; 569 int err, slots, rid, i; 570 571 sc->dev = dev; 572 573 /* Allocate IRQ. */ 574 rid = 0; 575 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 576 RF_ACTIVE); 577 if (sc->irq_res == NULL) { 578 device_printf(dev, "Can't allocate IRQ\n"); 579 return (ENOMEM); 580 } 581 582 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 583 SDHCI_FDT_RK3399) { 584 /* Initialize SDHCI */ 585 err = sdhci_init_rk3399(dev); 586 if (err != 0) { 587 device_printf(dev, "Cannot init RK3399 SDHCI\n"); 588 return (err); 589 } 590 } 591 592 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 593 SDHCI_FDT_RK3568) { 594 /* setup & enable clocks */ 595 if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) { 596 device_printf(dev, "cannot get core clock\n"); 597 return (ENXIO); 598 } 599 clk_enable(sc->clk_core); 600 } 601 602 /* Scan all slots. */ 603 slots = sc->num_slots; /* number of slots determined in probe(). */ 604 sc->num_slots = 0; 605 for (i = 0; i < slots; i++) { 606 slot = &sc->slots[sc->num_slots]; 607 608 /* Allocate memory. */ 609 rid = 0; 610 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 611 &rid, RF_ACTIVE); 612 if (sc->mem_res[i] == NULL) { 613 device_printf(dev, 614 "Can't allocate memory for slot %d\n", i); 615 continue; 616 } 617 618 slot->quirks = sc->quirks; 619 slot->caps = sc->caps; 620 slot->max_clk = sc->max_clk; 621 slot->sdma_boundary = sc->sdma_boundary; 622 623 if (sdhci_init_slot(dev, slot, i) != 0) 624 continue; 625 626 sc->num_slots++; 627 } 628 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 629 630 /* Activate the interrupt */ 631 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 632 NULL, sdhci_fdt_intr, sc, &sc->intrhand); 633 if (err) { 634 device_printf(dev, "Cannot setup IRQ\n"); 635 return (err); 636 } 637 638 /* Process cards detection. */ 639 for (i = 0; i < sc->num_slots; i++) 640 sdhci_start_slot(&sc->slots[i]); 641 642 return (0); 643 } 644 645 static int 646 sdhci_fdt_detach(device_t dev) 647 { 648 struct sdhci_fdt_softc *sc = device_get_softc(dev); 649 int i; 650 651 bus_generic_detach(dev); 652 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 653 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 654 sc->irq_res); 655 656 for (i = 0; i < sc->num_slots; i++) { 657 sdhci_cleanup_slot(&sc->slots[i]); 658 bus_release_resource(dev, SYS_RES_MEMORY, 659 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 660 } 661 662 return (0); 663 } 664 665 static device_method_t sdhci_fdt_methods[] = { 666 /* device_if */ 667 DEVMETHOD(device_probe, sdhci_fdt_probe), 668 DEVMETHOD(device_attach, sdhci_fdt_attach), 669 DEVMETHOD(device_detach, sdhci_fdt_detach), 670 671 /* Bus interface */ 672 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 673 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 674 675 /* mmcbr_if */ 676 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 677 DEVMETHOD(mmcbr_request, sdhci_generic_request), 678 DEVMETHOD(mmcbr_get_ro, sdhci_fdt_get_ro), 679 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 680 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 681 682 /* SDHCI registers accessors */ 683 DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1), 684 DEVMETHOD(sdhci_read_2, sdhci_fdt_read_2), 685 DEVMETHOD(sdhci_read_4, sdhci_fdt_read_4), 686 DEVMETHOD(sdhci_read_multi_4, sdhci_fdt_read_multi_4), 687 DEVMETHOD(sdhci_write_1, sdhci_fdt_write_1), 688 DEVMETHOD(sdhci_write_2, sdhci_fdt_write_2), 689 DEVMETHOD(sdhci_write_4, sdhci_fdt_write_4), 690 DEVMETHOD(sdhci_write_multi_4, sdhci_fdt_write_multi_4), 691 DEVMETHOD(sdhci_set_clock, sdhci_fdt_set_clock), 692 693 DEVMETHOD_END 694 }; 695 696 static driver_t sdhci_fdt_driver = { 697 "sdhci_fdt", 698 sdhci_fdt_methods, 699 sizeof(struct sdhci_fdt_softc), 700 }; 701 702 DRIVER_MODULE(sdhci_fdt, simplebus, sdhci_fdt_driver, NULL, NULL); 703 SDHCI_DEPEND(sdhci_fdt); 704 #ifndef MMCCAM 705 MMC_DECLARE_BRIDGE(sdhci_fdt); 706 #endif 707