1 /*- 2 * Copyright (c) 2017 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/lock.h> 32 #include <sys/module.h> 33 #include <sys/mutex.h> 34 #include <sys/resource.h> 35 #include <sys/rman.h> 36 #include <sys/sysctl.h> 37 #include <sys/taskqueue.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 42 #include <contrib/dev/acpica/include/acpi.h> 43 #include <dev/acpica/acpivar.h> 44 45 #include <dev/mmc/bridge.h> 46 #include <dev/mmc/mmcreg.h> 47 48 #include <dev/sdhci/sdhci.h> 49 50 #include "mmcbr_if.h" 51 #include "sdhci_if.h" 52 53 #define SDHCI_AMD_RESET_DLL_REG 0x908 54 55 static const struct sdhci_acpi_device { 56 const char* hid; 57 int uid; 58 const char *desc; 59 u_int quirks; 60 } sdhci_acpi_devices[] = { 61 { "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller", 62 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 63 SDHCI_QUIRK_WAIT_WHILE_BUSY | 64 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 65 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 66 { "80860F14", 3, "Intel Bay Trail/Braswell SDXC Controller", 67 SDHCI_QUIRK_WAIT_WHILE_BUSY | 68 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 69 { "80860F16", 0, "Intel Bay Trail/Braswell SDXC Controller", 70 SDHCI_QUIRK_WAIT_WHILE_BUSY | 71 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 72 { "80865ACA", 0, "Intel Apollo Lake SDXC Controller", 73 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 74 SDHCI_QUIRK_WAIT_WHILE_BUSY | 75 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 76 { "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller", 77 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 78 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 79 SDHCI_QUIRK_WAIT_WHILE_BUSY | 80 SDHCI_QUIRK_MMC_DDR52 | 81 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 82 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 83 { "AMDI0040", 0, "AMD eMMC 5.0 Controller", 84 SDHCI_QUIRK_32BIT_DMA_SIZE | 85 SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 }, 86 { NULL, 0, NULL, 0} 87 }; 88 89 static char *sdhci_ids[] = { 90 "80860F14", 91 "80860F16", 92 "80865ACA", 93 "80865ACC", 94 "AMDI0040", 95 NULL 96 }; 97 98 struct sdhci_acpi_softc { 99 struct sdhci_slot slot; 100 struct resource *mem_res; /* Memory resource */ 101 struct resource *irq_res; /* IRQ resource */ 102 void *intrhand; /* Interrupt handle */ 103 const struct sdhci_acpi_device *acpi_dev; 104 }; 105 106 static void sdhci_acpi_intr(void *arg); 107 static int sdhci_acpi_detach(device_t dev); 108 109 static uint8_t 110 sdhci_acpi_read_1(device_t dev, struct sdhci_slot *slot __unused, 111 bus_size_t off) 112 { 113 struct sdhci_acpi_softc *sc = device_get_softc(dev); 114 115 bus_barrier(sc->mem_res, 0, 0xFF, 116 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 117 return bus_read_1(sc->mem_res, off); 118 } 119 120 static void 121 sdhci_acpi_write_1(device_t dev, struct sdhci_slot *slot __unused, 122 bus_size_t off, uint8_t val) 123 { 124 struct sdhci_acpi_softc *sc = device_get_softc(dev); 125 126 bus_barrier(sc->mem_res, 0, 0xFF, 127 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 128 bus_write_1(sc->mem_res, off, val); 129 } 130 131 static uint16_t 132 sdhci_acpi_read_2(device_t dev, struct sdhci_slot *slot __unused, 133 bus_size_t off) 134 { 135 struct sdhci_acpi_softc *sc = device_get_softc(dev); 136 137 bus_barrier(sc->mem_res, 0, 0xFF, 138 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 139 return bus_read_2(sc->mem_res, off); 140 } 141 142 static void 143 sdhci_acpi_write_2(device_t dev, struct sdhci_slot *slot __unused, 144 bus_size_t off, uint16_t val) 145 { 146 struct sdhci_acpi_softc *sc = device_get_softc(dev); 147 148 bus_barrier(sc->mem_res, 0, 0xFF, 149 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 150 bus_write_2(sc->mem_res, off, val); 151 } 152 153 static uint32_t 154 sdhci_acpi_read_4(device_t dev, struct sdhci_slot *slot __unused, 155 bus_size_t off) 156 { 157 struct sdhci_acpi_softc *sc = device_get_softc(dev); 158 159 bus_barrier(sc->mem_res, 0, 0xFF, 160 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 161 return bus_read_4(sc->mem_res, off); 162 } 163 164 static void 165 sdhci_acpi_write_4(device_t dev, struct sdhci_slot *slot __unused, 166 bus_size_t off, uint32_t val) 167 { 168 struct sdhci_acpi_softc *sc = device_get_softc(dev); 169 170 bus_barrier(sc->mem_res, 0, 0xFF, 171 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 172 bus_write_4(sc->mem_res, off, val); 173 } 174 175 static void 176 sdhci_acpi_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 177 bus_size_t off, uint32_t *data, bus_size_t count) 178 { 179 struct sdhci_acpi_softc *sc = device_get_softc(dev); 180 181 bus_read_multi_stream_4(sc->mem_res, off, data, count); 182 } 183 184 static void 185 sdhci_acpi_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 186 bus_size_t off, uint32_t *data, bus_size_t count) 187 { 188 struct sdhci_acpi_softc *sc = device_get_softc(dev); 189 190 bus_write_multi_stream_4(sc->mem_res, off, data, count); 191 } 192 193 static void 194 sdhci_acpi_set_uhs_timing(device_t dev, struct sdhci_slot *slot) 195 { 196 const struct sdhci_acpi_softc *sc; 197 const struct sdhci_acpi_device *acpi_dev; 198 const struct mmc_ios *ios; 199 device_t bus; 200 uint16_t old_timing; 201 enum mmc_bus_timing timing; 202 203 bus = slot->bus; 204 old_timing = SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2); 205 old_timing &= SDHCI_CTRL2_UHS_MASK; 206 sdhci_generic_set_uhs_timing(dev, slot); 207 208 sc = device_get_softc(dev); 209 acpi_dev = sc->acpi_dev; 210 /* 211 * AMDI0040 controllers require SDHCI_CTRL2_SAMPLING_CLOCK to be 212 * disabled when switching from HS200 to high speed and to always 213 * be turned on again when tuning for HS400. In the later case, 214 * an AMD-specific DLL reset additionally is needed. 215 */ 216 if (strcmp(acpi_dev->hid, "AMDI0040") == 0 && acpi_dev->uid == 0) { 217 ios = &slot->host.ios; 218 timing = ios->timing; 219 if (old_timing == SDHCI_CTRL2_UHS_SDR104 && 220 timing == bus_timing_hs) 221 SDHCI_WRITE_2(bus, slot, SDHCI_HOST_CONTROL2, 222 SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2) & 223 ~SDHCI_CTRL2_SAMPLING_CLOCK); 224 if (ios->clock > SD_SDR50_MAX && 225 old_timing != SDHCI_CTRL2_MMC_HS400 && 226 timing == bus_timing_mmc_hs400) { 227 SDHCI_WRITE_2(bus, slot, SDHCI_HOST_CONTROL2, 228 SDHCI_READ_2(bus, slot, SDHCI_HOST_CONTROL2) | 229 SDHCI_CTRL2_SAMPLING_CLOCK); 230 SDHCI_WRITE_4(bus, slot, SDHCI_AMD_RESET_DLL_REG, 231 0x40003210); 232 DELAY(20); 233 SDHCI_WRITE_4(bus, slot, SDHCI_AMD_RESET_DLL_REG, 234 0x40033210); 235 } 236 } 237 } 238 239 static const struct sdhci_acpi_device * 240 sdhci_acpi_find_device(device_t dev) 241 { 242 char *hid; 243 int i, uid; 244 ACPI_HANDLE handle; 245 ACPI_STATUS status; 246 int rv; 247 248 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, sdhci_ids, &hid); 249 if (rv > 0) 250 return (NULL); 251 252 handle = acpi_get_handle(dev); 253 status = acpi_GetInteger(handle, "_UID", &uid); 254 if (ACPI_FAILURE(status)) 255 uid = 0; 256 257 for (i = 0; sdhci_acpi_devices[i].hid != NULL; i++) { 258 if (strcmp(sdhci_acpi_devices[i].hid, hid) != 0) 259 continue; 260 if ((sdhci_acpi_devices[i].uid != 0) && 261 (sdhci_acpi_devices[i].uid != uid)) 262 continue; 263 return (&sdhci_acpi_devices[i]); 264 } 265 266 return (NULL); 267 } 268 269 static int 270 sdhci_acpi_probe(device_t dev) 271 { 272 const struct sdhci_acpi_device *acpi_dev; 273 274 acpi_dev = sdhci_acpi_find_device(dev); 275 if (acpi_dev == NULL) 276 return (ENXIO); 277 278 device_set_desc(dev, acpi_dev->desc); 279 280 return (BUS_PROBE_DEFAULT); 281 } 282 283 static int 284 sdhci_acpi_attach(device_t dev) 285 { 286 struct sdhci_acpi_softc *sc = device_get_softc(dev); 287 int rid, err; 288 u_int quirks; 289 const struct sdhci_acpi_device *acpi_dev; 290 291 acpi_dev = sdhci_acpi_find_device(dev); 292 if (acpi_dev == NULL) 293 return (ENXIO); 294 295 sc->acpi_dev = acpi_dev; 296 quirks = acpi_dev->quirks; 297 298 /* Allocate IRQ. */ 299 rid = 0; 300 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 301 RF_ACTIVE); 302 if (sc->irq_res == NULL) { 303 device_printf(dev, "can't allocate IRQ\n"); 304 return (ENOMEM); 305 } 306 307 rid = 0; 308 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 309 &rid, RF_ACTIVE); 310 if (sc->mem_res == NULL) { 311 device_printf(dev, "can't allocate memory resource for slot\n"); 312 sdhci_acpi_detach(dev); 313 return (ENOMEM); 314 } 315 316 /* 317 * Intel Bay Trail and Braswell eMMC controllers share the same IDs, 318 * but while with these former DDR52 is affected by the VLI54 erratum, 319 * these latter require the timeout clock to be hardcoded to 1 MHz. 320 */ 321 if (strcmp(acpi_dev->hid, "80860F14") == 0 && acpi_dev->uid == 1 && 322 SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES) == 0x446cc8b2 && 323 SDHCI_READ_4(dev, &sc->slot, SDHCI_CAPABILITIES2) == 0x00000807) 324 quirks |= SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_DATA_TIMEOUT_1MHZ; 325 quirks &= ~sdhci_quirk_clear; 326 quirks |= sdhci_quirk_set; 327 sc->slot.quirks = quirks; 328 329 err = sdhci_init_slot(dev, &sc->slot, 0); 330 if (err) { 331 device_printf(dev, "failed to init slot\n"); 332 sdhci_acpi_detach(dev); 333 return (err); 334 } 335 336 /* Activate the interrupt */ 337 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 338 NULL, sdhci_acpi_intr, sc, &sc->intrhand); 339 if (err) { 340 device_printf(dev, "can't setup IRQ\n"); 341 sdhci_acpi_detach(dev); 342 return (err); 343 } 344 345 /* Process cards detection. */ 346 sdhci_start_slot(&sc->slot); 347 348 return (0); 349 } 350 351 static int 352 sdhci_acpi_detach(device_t dev) 353 { 354 struct sdhci_acpi_softc *sc = device_get_softc(dev); 355 356 if (sc->intrhand) 357 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 358 if (sc->irq_res) 359 bus_release_resource(dev, SYS_RES_IRQ, 360 rman_get_rid(sc->irq_res), sc->irq_res); 361 362 if (sc->mem_res) { 363 sdhci_cleanup_slot(&sc->slot); 364 bus_release_resource(dev, SYS_RES_MEMORY, 365 rman_get_rid(sc->mem_res), sc->mem_res); 366 } 367 368 return (0); 369 } 370 371 static int 372 sdhci_acpi_shutdown(device_t dev) 373 { 374 375 return (0); 376 } 377 378 static int 379 sdhci_acpi_suspend(device_t dev) 380 { 381 struct sdhci_acpi_softc *sc = device_get_softc(dev); 382 int err; 383 384 err = bus_generic_suspend(dev); 385 if (err) 386 return (err); 387 sdhci_generic_suspend(&sc->slot); 388 return (0); 389 } 390 391 static int 392 sdhci_acpi_resume(device_t dev) 393 { 394 struct sdhci_acpi_softc *sc = device_get_softc(dev); 395 int err; 396 397 sdhci_generic_resume(&sc->slot); 398 err = bus_generic_resume(dev); 399 if (err) 400 return (err); 401 return (0); 402 } 403 404 static void 405 sdhci_acpi_intr(void *arg) 406 { 407 struct sdhci_acpi_softc *sc = (struct sdhci_acpi_softc *)arg; 408 409 sdhci_generic_intr(&sc->slot); 410 } 411 412 static device_method_t sdhci_methods[] = { 413 /* device_if */ 414 DEVMETHOD(device_probe, sdhci_acpi_probe), 415 DEVMETHOD(device_attach, sdhci_acpi_attach), 416 DEVMETHOD(device_detach, sdhci_acpi_detach), 417 DEVMETHOD(device_shutdown, sdhci_acpi_shutdown), 418 DEVMETHOD(device_suspend, sdhci_acpi_suspend), 419 DEVMETHOD(device_resume, sdhci_acpi_resume), 420 421 /* Bus interface */ 422 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 423 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 424 425 /* mmcbr_if */ 426 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 427 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 428 DEVMETHOD(mmcbr_tune, sdhci_generic_tune), 429 DEVMETHOD(mmcbr_retune, sdhci_generic_retune), 430 DEVMETHOD(mmcbr_request, sdhci_generic_request), 431 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 432 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 433 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 434 435 /* SDHCI accessors */ 436 DEVMETHOD(sdhci_read_1, sdhci_acpi_read_1), 437 DEVMETHOD(sdhci_read_2, sdhci_acpi_read_2), 438 DEVMETHOD(sdhci_read_4, sdhci_acpi_read_4), 439 DEVMETHOD(sdhci_read_multi_4, sdhci_acpi_read_multi_4), 440 DEVMETHOD(sdhci_write_1, sdhci_acpi_write_1), 441 DEVMETHOD(sdhci_write_2, sdhci_acpi_write_2), 442 DEVMETHOD(sdhci_write_4, sdhci_acpi_write_4), 443 DEVMETHOD(sdhci_write_multi_4, sdhci_acpi_write_multi_4), 444 DEVMETHOD(sdhci_set_uhs_timing, sdhci_acpi_set_uhs_timing), 445 446 DEVMETHOD_END 447 }; 448 449 static driver_t sdhci_acpi_driver = { 450 "sdhci_acpi", 451 sdhci_methods, 452 sizeof(struct sdhci_acpi_softc), 453 }; 454 455 DRIVER_MODULE(sdhci_acpi, acpi, sdhci_acpi_driver, NULL, NULL); 456 SDHCI_DEPEND(sdhci_acpi); 457 458 #ifndef MMCCAM 459 MMC_DECLARE_BRIDGE(sdhci_acpi); 460 #endif 461