1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef __SDHCI_H__ 29 #define __SDHCI_H__ 30 31 #define DMA_BLOCK_SIZE 4096 32 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 34 /* Controller doesn't honor resets unless we touch the clock register */ 35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 36 /* Controller really supports DMA */ 37 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 38 /* Controller has unusable DMA engine */ 39 #define SDHCI_QUIRK_BROKEN_DMA (1<<2) 40 /* Controller doesn't like to be reset when there is no card inserted. */ 41 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 42 /* Controller has flaky internal state so reset it on each ios change */ 43 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 44 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 45 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 46 /* Controller needs to be reset after each request to stay stable */ 47 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 48 /* Controller has an off-by-one issue with timeout value */ 49 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 50 /* Controller has broken read timings */ 51 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 52 /* Controller needs lowered frequency */ 53 #define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) 54 /* Data timeout is invalid, should use SD clock */ 55 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10) 56 /* Timeout value is invalid, should be overriden */ 57 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) 58 /* SDHCI_CAPABILITIES is invalid */ 59 #define SDHCI_QUIRK_MISSING_CAPS (1<<12) 60 /* Hardware shifts the 136-bit response, don't do it in software. */ 61 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) 62 /* Wait to see reset bit asserted before waiting for de-asserted */ 63 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) 64 65 /* 66 * Controller registers 67 */ 68 #define SDHCI_DMA_ADDRESS 0x00 69 70 #define SDHCI_BLOCK_SIZE 0x04 71 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 72 73 #define SDHCI_BLOCK_COUNT 0x06 74 75 #define SDHCI_ARGUMENT 0x08 76 77 #define SDHCI_TRANSFER_MODE 0x0C 78 #define SDHCI_TRNS_DMA 0x01 79 #define SDHCI_TRNS_BLK_CNT_EN 0x02 80 #define SDHCI_TRNS_ACMD12 0x04 81 #define SDHCI_TRNS_READ 0x10 82 #define SDHCI_TRNS_MULTI 0x20 83 84 #define SDHCI_COMMAND_FLAGS 0x0E 85 #define SDHCI_CMD_RESP_NONE 0x00 86 #define SDHCI_CMD_RESP_LONG 0x01 87 #define SDHCI_CMD_RESP_SHORT 0x02 88 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 89 #define SDHCI_CMD_RESP_MASK 0x03 90 #define SDHCI_CMD_CRC 0x08 91 #define SDHCI_CMD_INDEX 0x10 92 #define SDHCI_CMD_DATA 0x20 93 #define SDHCI_CMD_TYPE_NORMAL 0x00 94 #define SDHCI_CMD_TYPE_SUSPEND 0x40 95 #define SDHCI_CMD_TYPE_RESUME 0x80 96 #define SDHCI_CMD_TYPE_ABORT 0xc0 97 #define SDHCI_CMD_TYPE_MASK 0xc0 98 99 #define SDHCI_COMMAND 0x0F 100 101 #define SDHCI_RESPONSE 0x10 102 103 #define SDHCI_BUFFER 0x20 104 105 #define SDHCI_PRESENT_STATE 0x24 106 #define SDHCI_CMD_INHIBIT 0x00000001 107 #define SDHCI_DAT_INHIBIT 0x00000002 108 #define SDHCI_DAT_ACTIVE 0x00000004 109 #define SDHCI_RETUNE_REQUEST 0x00000008 110 #define SDHCI_DOING_WRITE 0x00000100 111 #define SDHCI_DOING_READ 0x00000200 112 #define SDHCI_SPACE_AVAILABLE 0x00000400 113 #define SDHCI_DATA_AVAILABLE 0x00000800 114 #define SDHCI_CARD_PRESENT 0x00010000 115 #define SDHCI_CARD_STABLE 0x00020000 116 #define SDHCI_CARD_PIN 0x00040000 117 #define SDHCI_WRITE_PROTECT 0x00080000 118 #define SDHCI_STATE_DAT_MASK 0x00f00000 119 #define SDHCI_STATE_CMD 0x01000000 120 121 #define SDHCI_HOST_CONTROL 0x28 122 #define SDHCI_CTRL_LED 0x01 123 #define SDHCI_CTRL_4BITBUS 0x02 124 #define SDHCI_CTRL_HISPD 0x04 125 #define SDHCI_CTRL_SDMA 0x08 126 #define SDHCI_CTRL_ADMA2 0x10 127 #define SDHCI_CTRL_ADMA264 0x18 128 #define SDHCI_CTRL_DMA_MASK 0x18 129 #define SDHCI_CTRL_8BITBUS 0x20 130 #define SDHCI_CTRL_CARD_DET 0x40 131 #define SDHCI_CTRL_FORCE_CARD 0x80 132 133 #define SDHCI_POWER_CONTROL 0x29 134 #define SDHCI_POWER_ON 0x01 135 #define SDHCI_POWER_180 0x0A 136 #define SDHCI_POWER_300 0x0C 137 #define SDHCI_POWER_330 0x0E 138 139 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 140 141 #define SDHCI_WAKE_UP_CONTROL 0x2B 142 143 #define SDHCI_CLOCK_CONTROL 0x2C 144 #define SDHCI_DIVIDER_MASK 0xff 145 #define SDHCI_DIVIDER_MASK_LEN 8 146 #define SDHCI_DIVIDER_SHIFT 8 147 #define SDHCI_DIVIDER_HI_MASK 3 148 #define SDHCI_DIVIDER_HI_SHIFT 6 149 #define SDHCI_CLOCK_CARD_EN 0x0004 150 #define SDHCI_CLOCK_INT_STABLE 0x0002 151 #define SDHCI_CLOCK_INT_EN 0x0001 152 153 #define SDHCI_TIMEOUT_CONTROL 0x2E 154 155 #define SDHCI_SOFTWARE_RESET 0x2F 156 #define SDHCI_RESET_ALL 0x01 157 #define SDHCI_RESET_CMD 0x02 158 #define SDHCI_RESET_DATA 0x04 159 160 #define SDHCI_INT_STATUS 0x30 161 #define SDHCI_INT_ENABLE 0x34 162 #define SDHCI_SIGNAL_ENABLE 0x38 163 #define SDHCI_INT_RESPONSE 0x00000001 164 #define SDHCI_INT_DATA_END 0x00000002 165 #define SDHCI_INT_BLOCK_GAP 0x00000004 166 #define SDHCI_INT_DMA_END 0x00000008 167 #define SDHCI_INT_SPACE_AVAIL 0x00000010 168 #define SDHCI_INT_DATA_AVAIL 0x00000020 169 #define SDHCI_INT_CARD_INSERT 0x00000040 170 #define SDHCI_INT_CARD_REMOVE 0x00000080 171 #define SDHCI_INT_CARD_INT 0x00000100 172 #define SDHCI_INT_ERROR 0x00008000 173 #define SDHCI_INT_TIMEOUT 0x00010000 174 #define SDHCI_INT_CRC 0x00020000 175 #define SDHCI_INT_END_BIT 0x00040000 176 #define SDHCI_INT_INDEX 0x00080000 177 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 178 #define SDHCI_INT_DATA_CRC 0x00200000 179 #define SDHCI_INT_DATA_END_BIT 0x00400000 180 #define SDHCI_INT_BUS_POWER 0x00800000 181 #define SDHCI_INT_ACMD12ERR 0x01000000 182 #define SDHCI_INT_ADMAERR 0x02000000 183 184 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 185 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 186 187 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 188 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 189 190 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 191 192 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 193 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 194 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 195 SDHCI_INT_DATA_END_BIT) 196 197 #define SDHCI_ACMD12_ERR 0x3C 198 199 #define SDHCI_CAPABILITIES 0x40 200 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 201 #define SDHCI_TIMEOUT_CLK_SHIFT 0 202 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 203 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 204 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 205 #define SDHCI_CLOCK_BASE_SHIFT 8 206 #define SDHCI_MAX_BLOCK_MASK 0x00030000 207 #define SDHCI_MAX_BLOCK_SHIFT 16 208 #define SDHCI_CAN_DO_8BITBUS 0x00040000 209 #define SDHCI_CAN_DO_ADMA2 0x00080000 210 #define SDHCI_CAN_DO_HISPD 0x00200000 211 #define SDHCI_CAN_DO_DMA 0x00400000 212 #define SDHCI_CAN_DO_SUSPEND 0x00800000 213 #define SDHCI_CAN_VDD_330 0x01000000 214 #define SDHCI_CAN_VDD_300 0x02000000 215 #define SDHCI_CAN_VDD_180 0x04000000 216 #define SDHCI_CAN_DO_64BIT 0x10000000 217 218 #define SDHCI_MAX_CURRENT 0x48 219 220 #define SDHCI_SLOT_INT_STATUS 0xFC 221 222 #define SDHCI_HOST_VERSION 0xFE 223 #define SDHCI_VENDOR_VER_MASK 0xFF00 224 #define SDHCI_VENDOR_VER_SHIFT 8 225 #define SDHCI_SPEC_VER_MASK 0x00FF 226 #define SDHCI_SPEC_VER_SHIFT 0 227 #define SDHCI_SPEC_100 0 228 #define SDHCI_SPEC_200 1 229 #define SDHCI_SPEC_300 2 230 231 SYSCTL_DECL(_hw_sdhci); 232 233 struct sdhci_slot { 234 u_int quirks; /* Chip specific quirks */ 235 u_int caps; /* Override SDHCI_CAPABILITIES */ 236 device_t bus; /* Bus device */ 237 device_t dev; /* Slot device */ 238 u_char num; /* Slot number */ 239 u_char opt; /* Slot options */ 240 #define SDHCI_HAVE_DMA 1 241 #define SDHCI_PLATFORM_TRANSFER 2 242 u_char version; 243 uint32_t max_clk; /* Max possible freq */ 244 uint32_t timeout_clk; /* Timeout freq */ 245 bus_dma_tag_t dmatag; 246 bus_dmamap_t dmamap; 247 u_char *dmamem; 248 bus_addr_t paddr; /* DMA buffer address */ 249 struct task card_task; /* Card presence check task */ 250 struct callout card_callout; /* Card insert delay callout */ 251 struct callout timeout_callout;/* Card command/data response timeout */ 252 struct mmc_host host; /* Host parameters */ 253 struct mmc_request *req; /* Current request */ 254 struct mmc_command *curcmd; /* Current command of current request */ 255 256 uint32_t intmask; /* Current interrupt mask */ 257 uint32_t clock; /* Current clock freq. */ 258 size_t offset; /* Data buffer offset */ 259 uint8_t hostctrl; /* Current host control register */ 260 u_char power; /* Current power */ 261 u_char bus_busy; /* Bus busy status */ 262 u_char cmd_done; /* CMD command part done flag */ 263 u_char data_done; /* DAT command part done flag */ 264 u_char flags; /* Request execution flags */ 265 #define CMD_STARTED 1 266 #define STOP_STARTED 2 267 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 268 #define PLATFORM_DATA_STARTED 8 /* Data transfer is handled by platform */ 269 struct mtx mtx; /* Slot mutex */ 270 }; 271 272 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 273 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 274 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 275 void sdhci_start_slot(struct sdhci_slot *slot); 276 /* performs generic clean-up for platform transfers */ 277 void sdhci_finish_data(struct sdhci_slot *slot); 278 int sdhci_cleanup_slot(struct sdhci_slot *slot); 279 int sdhci_generic_suspend(struct sdhci_slot *slot); 280 int sdhci_generic_resume(struct sdhci_slot *slot); 281 int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 282 int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req); 283 int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 284 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 285 int sdhci_generic_release_host(device_t brdev, device_t reqdev); 286 void sdhci_generic_intr(struct sdhci_slot *slot); 287 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); 288 289 #endif /* __SDHCI_H__ */ 290