1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef __SDHCI_H__ 29 #define __SDHCI_H__ 30 31 #define DMA_BLOCK_SIZE 4096 32 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 34 /* Controller doesn't honor resets unless we touch the clock register */ 35 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) 36 /* Controller really supports DMA */ 37 #define SDHCI_QUIRK_FORCE_DMA (1 << 1) 38 /* Controller has unusable DMA engine */ 39 #define SDHCI_QUIRK_BROKEN_DMA (1 << 2) 40 /* Controller doesn't like to be reset when there is no card inserted. */ 41 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) 42 /* Controller has flaky internal state so reset it on each ios change */ 43 #define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) 44 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 45 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) 46 /* Controller needs to be reset after each request to stay stable */ 47 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) 48 /* Controller has an off-by-one issue with timeout value */ 49 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) 50 /* Controller has broken read timings */ 51 #define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) 52 /* Controller needs lowered frequency */ 53 #define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) 54 /* Data timeout is invalid, should use SD clock */ 55 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) 56 /* Timeout value is invalid, should be overriden */ 57 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) 58 /* SDHCI_CAPABILITIES is invalid */ 59 #define SDHCI_QUIRK_MISSING_CAPS (1 << 12) 60 /* Hardware shifts the 136-bit response, don't do it in software. */ 61 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) 62 /* Wait to see reset bit asserted before waiting for de-asserted */ 63 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) 64 /* Leave controller in standard mode when putting card in HS mode. */ 65 #define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) 66 /* Alternate clock source is required when supplying a 400 KHz clock. */ 67 #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) 68 /* Card insert/remove interrupts don't work, polling required. */ 69 #define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) 70 /* All controller slots are non-removable. */ 71 #define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) 72 /* Issue custom Intel controller reset sequence after power-up. */ 73 #define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) 74 /* Data timeout is invalid, use 1 MHz clock instead. */ 75 #define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) 76 /* Controller doesn't allow access boot partitions. */ 77 #define SDHCI_QUIRK_BOOT_NOACC (1 << 21) 78 /* Controller waits for busy responses. */ 79 #define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22) 80 81 /* 82 * Controller registers 83 */ 84 #define SDHCI_DMA_ADDRESS 0x00 85 86 #define SDHCI_BLOCK_SIZE 0x04 87 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 88 89 #define SDHCI_BLOCK_COUNT 0x06 90 91 #define SDHCI_ARGUMENT 0x08 92 93 #define SDHCI_TRANSFER_MODE 0x0C 94 #define SDHCI_TRNS_DMA 0x01 95 #define SDHCI_TRNS_BLK_CNT_EN 0x02 96 #define SDHCI_TRNS_ACMD12 0x04 97 #define SDHCI_TRNS_READ 0x10 98 #define SDHCI_TRNS_MULTI 0x20 99 100 #define SDHCI_COMMAND_FLAGS 0x0E 101 #define SDHCI_CMD_RESP_NONE 0x00 102 #define SDHCI_CMD_RESP_LONG 0x01 103 #define SDHCI_CMD_RESP_SHORT 0x02 104 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 105 #define SDHCI_CMD_RESP_MASK 0x03 106 #define SDHCI_CMD_CRC 0x08 107 #define SDHCI_CMD_INDEX 0x10 108 #define SDHCI_CMD_DATA 0x20 109 #define SDHCI_CMD_TYPE_NORMAL 0x00 110 #define SDHCI_CMD_TYPE_SUSPEND 0x40 111 #define SDHCI_CMD_TYPE_RESUME 0x80 112 #define SDHCI_CMD_TYPE_ABORT 0xc0 113 #define SDHCI_CMD_TYPE_MASK 0xc0 114 115 #define SDHCI_COMMAND 0x0F 116 117 #define SDHCI_RESPONSE 0x10 118 119 #define SDHCI_BUFFER 0x20 120 121 #define SDHCI_PRESENT_STATE 0x24 122 #define SDHCI_CMD_INHIBIT 0x00000001 123 #define SDHCI_DAT_INHIBIT 0x00000002 124 #define SDHCI_DAT_ACTIVE 0x00000004 125 #define SDHCI_RETUNE_REQUEST 0x00000008 126 #define SDHCI_DOING_WRITE 0x00000100 127 #define SDHCI_DOING_READ 0x00000200 128 #define SDHCI_SPACE_AVAILABLE 0x00000400 129 #define SDHCI_DATA_AVAILABLE 0x00000800 130 #define SDHCI_CARD_PRESENT 0x00010000 131 #define SDHCI_CARD_STABLE 0x00020000 132 #define SDHCI_CARD_PIN 0x00040000 133 #define SDHCI_WRITE_PROTECT 0x00080000 134 #define SDHCI_STATE_DAT_MASK 0x00f00000 135 #define SDHCI_STATE_CMD 0x01000000 136 137 #define SDHCI_HOST_CONTROL 0x28 138 #define SDHCI_CTRL_LED 0x01 139 #define SDHCI_CTRL_4BITBUS 0x02 140 #define SDHCI_CTRL_HISPD 0x04 141 #define SDHCI_CTRL_SDMA 0x08 142 #define SDHCI_CTRL_ADMA2 0x10 143 #define SDHCI_CTRL_ADMA264 0x18 144 #define SDHCI_CTRL_DMA_MASK 0x18 145 #define SDHCI_CTRL_8BITBUS 0x20 146 #define SDHCI_CTRL_CARD_DET 0x40 147 #define SDHCI_CTRL_FORCE_CARD 0x80 148 149 #define SDHCI_POWER_CONTROL 0x29 150 #define SDHCI_POWER_ON 0x01 151 #define SDHCI_POWER_180 0x0A 152 #define SDHCI_POWER_300 0x0C 153 #define SDHCI_POWER_330 0x0E 154 155 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 156 157 #define SDHCI_WAKE_UP_CONTROL 0x2B 158 159 #define SDHCI_CLOCK_CONTROL 0x2C 160 #define SDHCI_DIVIDER_MASK 0xff 161 #define SDHCI_DIVIDER_MASK_LEN 8 162 #define SDHCI_DIVIDER_SHIFT 8 163 #define SDHCI_DIVIDER_HI_MASK 3 164 #define SDHCI_DIVIDER_HI_SHIFT 6 165 #define SDHCI_CLOCK_CARD_EN 0x0004 166 #define SDHCI_CLOCK_INT_STABLE 0x0002 167 #define SDHCI_CLOCK_INT_EN 0x0001 168 #define SDHCI_DIVIDERS_MASK \ 169 ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ 170 (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) 171 172 #define SDHCI_TIMEOUT_CONTROL 0x2E 173 174 #define SDHCI_SOFTWARE_RESET 0x2F 175 #define SDHCI_RESET_ALL 0x01 176 #define SDHCI_RESET_CMD 0x02 177 #define SDHCI_RESET_DATA 0x04 178 179 #define SDHCI_INT_STATUS 0x30 180 #define SDHCI_INT_ENABLE 0x34 181 #define SDHCI_SIGNAL_ENABLE 0x38 182 #define SDHCI_INT_RESPONSE 0x00000001 183 #define SDHCI_INT_DATA_END 0x00000002 184 #define SDHCI_INT_BLOCK_GAP 0x00000004 185 #define SDHCI_INT_DMA_END 0x00000008 186 #define SDHCI_INT_SPACE_AVAIL 0x00000010 187 #define SDHCI_INT_DATA_AVAIL 0x00000020 188 #define SDHCI_INT_CARD_INSERT 0x00000040 189 #define SDHCI_INT_CARD_REMOVE 0x00000080 190 #define SDHCI_INT_CARD_INT 0x00000100 191 #define SDHCI_INT_INT_A 0x00000200 192 #define SDHCI_INT_INT_B 0x00000400 193 #define SDHCI_INT_INT_C 0x00000800 194 #define SDHCI_INT_RETUNE 0x00001000 195 #define SDHCI_INT_ERROR 0x00008000 196 #define SDHCI_INT_TIMEOUT 0x00010000 197 #define SDHCI_INT_CRC 0x00020000 198 #define SDHCI_INT_END_BIT 0x00040000 199 #define SDHCI_INT_INDEX 0x00080000 200 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 201 #define SDHCI_INT_DATA_CRC 0x00200000 202 #define SDHCI_INT_DATA_END_BIT 0x00400000 203 #define SDHCI_INT_BUS_POWER 0x00800000 204 #define SDHCI_INT_ACMD12ERR 0x01000000 205 #define SDHCI_INT_ADMAERR 0x02000000 206 #define SDHCI_INT_TUNEERR 0x04000000 207 208 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 209 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 210 211 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 212 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 213 214 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 215 216 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 217 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 218 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 219 SDHCI_INT_DATA_END_BIT) 220 221 #define SDHCI_ACMD12_ERR 0x3C 222 #define SDHCI_HOST_CONTROL2 0x3E 223 224 #define SDHCI_CAPABILITIES 0x40 225 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 226 #define SDHCI_TIMEOUT_CLK_SHIFT 0 227 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 228 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 229 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 230 #define SDHCI_CLOCK_BASE_SHIFT 8 231 #define SDHCI_MAX_BLOCK_MASK 0x00030000 232 #define SDHCI_MAX_BLOCK_SHIFT 16 233 #define SDHCI_CAN_DO_8BITBUS 0x00040000 234 #define SDHCI_CAN_DO_ADMA2 0x00080000 235 #define SDHCI_CAN_DO_HISPD 0x00200000 236 #define SDHCI_CAN_DO_DMA 0x00400000 237 #define SDHCI_CAN_DO_SUSPEND 0x00800000 238 #define SDHCI_CAN_VDD_330 0x01000000 239 #define SDHCI_CAN_VDD_300 0x02000000 240 #define SDHCI_CAN_VDD_180 0x04000000 241 #define SDHCI_CAN_DO_64BIT 0x10000000 242 #define SDHCI_CAN_ASYNC_INTR 0x20000000 243 244 #define SDHCI_CAPABILITIES2 0x44 245 #define SDHCI_CAN_SDR50 0x00000001 246 #define SDHCI_CAN_SDR104 0x00000002 247 #define SDHCI_CAN_DDR50 0x00000004 248 #define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 249 #define SDHCI_CAN_DRIVE_TYPE_B 0x00000020 250 #define SDHCI_CAN_DRIVE_TYPE_C 0x00000040 251 #define SDHCI_RETUNE_CNT_MASK 0x00000F00 252 #define SDHCI_RETUNE_CNT_SHIFT 8 253 #define SDHCI_TUNE_SDR50 0x00002000 254 #define SDHCI_RETUNE_MODES_MASK 0x0000C000 255 #define SDHCI_RETUNE_MODES_SHIFT 14 256 #define SDHCI_CLOCK_MULT_MASK 0x00FF0000 257 #define SDHCI_CLOCK_MULT_SHIFT 16 258 259 #define SDHCI_MAX_CURRENT 0x48 260 #define SDHCI_FORCE_AUTO_EVENT 0x50 261 #define SDHCI_FORCE_INTR_EVENT 0x52 262 #define SDHCI_ADMA_ERR 0x54 263 #define SDHCI_ADMA_ADDRESS_LOW 0x58 264 #define SDHCI_ADMA_ADDRESS_HI 0x5C 265 #define SDHCI_PRESET_VALUE 0x60 266 #define SDHCI_SHARED_BUS_CTRL 0xE0 267 268 #define SDHCI_SLOT_INT_STATUS 0xFC 269 270 #define SDHCI_HOST_VERSION 0xFE 271 #define SDHCI_VENDOR_VER_MASK 0xFF00 272 #define SDHCI_VENDOR_VER_SHIFT 8 273 #define SDHCI_SPEC_VER_MASK 0x00FF 274 #define SDHCI_SPEC_VER_SHIFT 0 275 #define SDHCI_SPEC_100 0 276 #define SDHCI_SPEC_200 1 277 #define SDHCI_SPEC_300 2 278 279 SYSCTL_DECL(_hw_sdhci); 280 281 struct sdhci_slot { 282 u_int quirks; /* Chip specific quirks */ 283 u_int caps; /* Override SDHCI_CAPABILITIES */ 284 device_t bus; /* Bus device */ 285 device_t dev; /* Slot device */ 286 u_char num; /* Slot number */ 287 u_char opt; /* Slot options */ 288 #define SDHCI_HAVE_DMA 0x01 289 #define SDHCI_PLATFORM_TRANSFER 0x02 290 #define SDHCI_NON_REMOVABLE 0x04 291 u_char version; 292 int timeout; /* Transfer timeout */ 293 uint32_t max_clk; /* Max possible freq */ 294 uint32_t timeout_clk; /* Timeout freq */ 295 bus_dma_tag_t dmatag; 296 bus_dmamap_t dmamap; 297 u_char *dmamem; 298 bus_addr_t paddr; /* DMA buffer address */ 299 struct task card_task; /* Card presence check task */ 300 struct timeout_task 301 card_delayed_task;/* Card insert delayed task */ 302 struct callout card_poll_callout;/* Card present polling callout */ 303 struct callout timeout_callout;/* Card command/data response timeout */ 304 struct mmc_host host; /* Host parameters */ 305 struct mmc_request *req; /* Current request */ 306 struct mmc_command *curcmd; /* Current command of current request */ 307 308 uint32_t intmask; /* Current interrupt mask */ 309 uint32_t clock; /* Current clock freq. */ 310 size_t offset; /* Data buffer offset */ 311 uint8_t hostctrl; /* Current host control register */ 312 u_char power; /* Current power */ 313 u_char bus_busy; /* Bus busy status */ 314 u_char cmd_done; /* CMD command part done flag */ 315 u_char data_done; /* DAT command part done flag */ 316 u_char flags; /* Request execution flags */ 317 #define CMD_STARTED 1 318 #define STOP_STARTED 2 319 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 320 #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ 321 struct mtx mtx; /* Slot mutex */ 322 }; 323 324 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, 325 uintptr_t *result); 326 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, 327 uintptr_t value); 328 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 329 void sdhci_start_slot(struct sdhci_slot *slot); 330 /* performs generic clean-up for platform transfers */ 331 void sdhci_finish_data(struct sdhci_slot *slot); 332 int sdhci_cleanup_slot(struct sdhci_slot *slot); 333 int sdhci_generic_suspend(struct sdhci_slot *slot); 334 int sdhci_generic_resume(struct sdhci_slot *slot); 335 int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 336 int sdhci_generic_request(device_t brdev, device_t reqdev, 337 struct mmc_request *req); 338 int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 339 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 340 int sdhci_generic_release_host(device_t brdev, device_t reqdev); 341 void sdhci_generic_intr(struct sdhci_slot *slot); 342 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); 343 bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot); 344 void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present); 345 346 #endif /* __SDHCI_H__ */ 347