1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/kobj.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/stdarg.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcreg.h> 54 #include <dev/mmc/mmcbrvar.h> 55 56 #include <dev/sdhci/sdhci.h> 57 58 #include <cam/cam.h> 59 #include <cam/cam_ccb.h> 60 #include <cam/cam_debug.h> 61 #include <cam/cam_sim.h> 62 #include <cam/cam_xpt_sim.h> 63 64 #include "mmcbr_if.h" 65 #include "sdhci_if.h" 66 67 #include "opt_mmccam.h" 68 69 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 70 71 static int sdhci_debug = 0; 72 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 73 "Debug level"); 74 u_int sdhci_quirk_clear = 0; 75 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 76 0, "Mask of quirks to clear"); 77 u_int sdhci_quirk_set = 0; 78 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 79 "Mask of quirks to set"); 80 81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 84 #define RD_MULTI_4(slot, off, ptr, count) \ 85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 86 87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 90 #define WR_MULTI_4(slot, off, ptr, count) \ 91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 92 93 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err); 94 static void sdhci_card_poll(void *arg); 95 static void sdhci_card_task(void *arg, int pending); 96 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask); 97 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask); 98 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 99 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot, 100 bool is_present); 101 static void sdhci_finish_command(struct sdhci_slot *slot); 102 static void sdhci_init(struct sdhci_slot *slot); 103 static void sdhci_read_block_pio(struct sdhci_slot *slot); 104 static void sdhci_req_done(struct sdhci_slot *slot); 105 static void sdhci_req_wakeup(struct mmc_request *req); 106 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask); 107 static void sdhci_retune(void *arg); 108 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 109 static void sdhci_set_power(struct sdhci_slot *slot, u_char power); 110 static void sdhci_set_transfer_mode(struct sdhci_slot *slot, 111 struct mmc_data *data); 112 static void sdhci_start(struct sdhci_slot *slot); 113 static void sdhci_timeout(void *arg); 114 static void sdhci_start_command(struct sdhci_slot *slot, 115 struct mmc_command *cmd); 116 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 117 static void sdhci_write_block_pio(struct sdhci_slot *slot); 118 static void sdhci_transfer_pio(struct sdhci_slot *slot); 119 120 #ifdef MMCCAM 121 /* CAM-related */ 122 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 123 static int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, 124 int proposed_clock); 125 static void sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb); 126 static void sdhci_cam_poll(struct cam_sim *sim); 127 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 128 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 129 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 130 #endif 131 132 /* helper routines */ 133 static void sdhci_dumpregs(struct sdhci_slot *slot); 134 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 135 int error); 136 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 137 __printflike(2, 3); 138 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot); 139 140 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 141 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 142 #define SDHCI_LOCK_INIT(_slot) \ 143 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 144 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 145 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 146 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 147 148 #define SDHCI_DEFAULT_MAX_FREQ 50 149 150 #define SDHCI_200_MAX_DIVIDER 256 151 #define SDHCI_300_MAX_DIVIDER 2046 152 153 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 154 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 155 156 /* 157 * Broadcom BCM577xx Controller Constants 158 */ 159 /* Maximum divider supported by the default clock source. */ 160 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 161 /* Alternative clock's base frequency. */ 162 #define BCM577XX_ALT_CLOCK_BASE 63000000 163 164 #define BCM577XX_HOST_CONTROL 0x198 165 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 166 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 167 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 168 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 169 170 static void 171 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 172 { 173 174 if (error != 0) { 175 printf("getaddr: error %d\n", error); 176 return; 177 } 178 *(bus_addr_t *)arg = segs[0].ds_addr; 179 } 180 181 static int 182 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 183 { 184 va_list ap; 185 int retval; 186 187 retval = printf("%s-slot%d: ", 188 device_get_nameunit(slot->bus), slot->num); 189 190 va_start(ap, fmt); 191 retval += vprintf(fmt, ap); 192 va_end(ap); 193 return (retval); 194 } 195 196 static void 197 sdhci_dumpregs(struct sdhci_slot *slot) 198 { 199 200 slot_printf(slot, 201 "============== REGISTER DUMP ==============\n"); 202 203 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 204 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 205 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 206 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 207 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 208 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 209 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 210 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 211 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 212 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 213 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 214 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 215 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 216 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 217 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 218 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 219 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 220 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 221 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 222 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 223 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 224 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 225 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 226 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 227 228 slot_printf(slot, 229 "===========================================\n"); 230 } 231 232 static void 233 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 234 { 235 int timeout; 236 uint32_t clock; 237 238 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 239 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 240 return; 241 } 242 243 /* Some controllers need this kick or reset won't work. */ 244 if ((mask & SDHCI_RESET_ALL) == 0 && 245 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 246 /* This is to force an update */ 247 clock = slot->clock; 248 slot->clock = 0; 249 sdhci_set_clock(slot, clock); 250 } 251 252 if (mask & SDHCI_RESET_ALL) { 253 slot->clock = 0; 254 slot->power = 0; 255 } 256 257 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 258 259 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 260 /* 261 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 262 * specification. The reset bit has internal propagation delay, 263 * so a fast read after write returns 0 even if reset process is 264 * in progress. The workaround is to poll for 1 before polling 265 * for 0. In the worst case, if we miss seeing it asserted the 266 * time we spent waiting is enough to ensure the reset finishes. 267 */ 268 timeout = 10000; 269 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 270 if (timeout <= 0) 271 break; 272 timeout--; 273 DELAY(1); 274 } 275 } 276 277 /* Wait max 100 ms */ 278 timeout = 10000; 279 /* Controller clears the bits when it's done */ 280 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 281 if (timeout <= 0) { 282 slot_printf(slot, "Reset 0x%x never completed.\n", 283 mask); 284 sdhci_dumpregs(slot); 285 return; 286 } 287 timeout--; 288 DELAY(10); 289 } 290 } 291 292 static uint32_t 293 sdhci_tuning_intmask(struct sdhci_slot *slot) 294 { 295 uint32_t intmask; 296 297 intmask = 0; 298 if (slot->opt & SDHCI_TUNING_ENABLED) { 299 intmask |= SDHCI_INT_TUNEERR; 300 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 301 slot->retune_mode == SDHCI_RETUNE_MODE_3) 302 intmask |= SDHCI_INT_RETUNE; 303 } 304 return (intmask); 305 } 306 307 static void 308 sdhci_init(struct sdhci_slot *slot) 309 { 310 311 sdhci_reset(slot, SDHCI_RESET_ALL); 312 313 /* Enable interrupts. */ 314 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 315 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 316 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 317 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 318 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 319 SDHCI_INT_ACMD12ERR; 320 321 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 322 !(slot->opt & SDHCI_NON_REMOVABLE)) { 323 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 324 } 325 326 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 327 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 328 } 329 330 static void 331 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 332 { 333 uint32_t clk_base; 334 uint32_t clk_sel; 335 uint32_t res; 336 uint16_t clk; 337 uint16_t div; 338 int timeout; 339 340 if (clock == slot->clock) 341 return; 342 slot->clock = clock; 343 344 /* Turn off the clock. */ 345 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 346 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 347 /* If no clock requested - leave it so. */ 348 if (clock == 0) 349 return; 350 351 /* Determine the clock base frequency */ 352 clk_base = slot->max_clk; 353 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 354 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 355 BCM577XX_CTRL_CLKSEL_MASK; 356 357 /* 358 * Select clock source appropriate for the requested frequency. 359 */ 360 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 361 clk_base = BCM577XX_ALT_CLOCK_BASE; 362 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 363 BCM577XX_CTRL_CLKSEL_SHIFT); 364 } else { 365 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 366 BCM577XX_CTRL_CLKSEL_SHIFT); 367 } 368 369 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 370 } 371 372 /* Recalculate timeout clock frequency based on the new sd clock. */ 373 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 374 slot->timeout_clk = slot->clock / 1000; 375 376 if (slot->version < SDHCI_SPEC_300) { 377 /* Looking for highest freq <= clock. */ 378 res = clk_base; 379 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 380 if (res <= clock) 381 break; 382 res >>= 1; 383 } 384 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 385 div >>= 1; 386 } else { 387 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 388 if (clock >= clk_base) 389 div = 0; 390 else { 391 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 392 if ((clk_base / div) <= clock) 393 break; 394 } 395 } 396 div >>= 1; 397 } 398 399 if (bootverbose || sdhci_debug) 400 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 401 div, clock, clk_base); 402 403 /* Now we have got divider, set it. */ 404 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 405 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 406 << SDHCI_DIVIDER_HI_SHIFT; 407 408 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 409 /* Enable clock. */ 410 clk |= SDHCI_CLOCK_INT_EN; 411 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 412 /* Wait up to 10 ms until it stabilize. */ 413 timeout = 10; 414 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 415 & SDHCI_CLOCK_INT_STABLE)) { 416 if (timeout == 0) { 417 slot_printf(slot, 418 "Internal clock never stabilised.\n"); 419 sdhci_dumpregs(slot); 420 return; 421 } 422 timeout--; 423 DELAY(1000); 424 } 425 /* Pass clock signal to the bus. */ 426 clk |= SDHCI_CLOCK_CARD_EN; 427 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 428 } 429 430 static void 431 sdhci_set_power(struct sdhci_slot *slot, u_char power) 432 { 433 int i; 434 uint8_t pwr; 435 436 if (slot->power == power) 437 return; 438 439 slot->power = power; 440 441 /* Turn off the power. */ 442 pwr = 0; 443 WR1(slot, SDHCI_POWER_CONTROL, pwr); 444 /* If power down requested - leave it so. */ 445 if (power == 0) 446 return; 447 /* Set voltage. */ 448 switch (1 << power) { 449 case MMC_OCR_LOW_VOLTAGE: 450 pwr |= SDHCI_POWER_180; 451 break; 452 case MMC_OCR_290_300: 453 case MMC_OCR_300_310: 454 pwr |= SDHCI_POWER_300; 455 break; 456 case MMC_OCR_320_330: 457 case MMC_OCR_330_340: 458 pwr |= SDHCI_POWER_330; 459 break; 460 } 461 WR1(slot, SDHCI_POWER_CONTROL, pwr); 462 /* 463 * Turn on VDD1 power. Note that at least some Intel controllers can 464 * fail to enable bus power on the first try after transiting from D3 465 * to D0, so we give them up to 2 ms. 466 */ 467 pwr |= SDHCI_POWER_ON; 468 for (i = 0; i < 20; i++) { 469 WR1(slot, SDHCI_POWER_CONTROL, pwr); 470 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 471 break; 472 DELAY(100); 473 } 474 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 475 slot_printf(slot, "Bus power failed to enable"); 476 477 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 478 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 479 DELAY(10); 480 WR1(slot, SDHCI_POWER_CONTROL, pwr); 481 DELAY(300); 482 } 483 } 484 485 static void 486 sdhci_read_block_pio(struct sdhci_slot *slot) 487 { 488 uint32_t data; 489 char *buffer; 490 size_t left; 491 492 buffer = slot->curcmd->data->data; 493 buffer += slot->offset; 494 /* Transfer one block at a time. */ 495 left = min(512, slot->curcmd->data->len - slot->offset); 496 slot->offset += left; 497 498 /* If we are too fast, broken controllers return zeroes. */ 499 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 500 DELAY(10); 501 /* Handle unaligned and aligned buffer cases. */ 502 if ((intptr_t)buffer & 3) { 503 while (left > 3) { 504 data = RD4(slot, SDHCI_BUFFER); 505 buffer[0] = data; 506 buffer[1] = (data >> 8); 507 buffer[2] = (data >> 16); 508 buffer[3] = (data >> 24); 509 buffer += 4; 510 left -= 4; 511 } 512 } else { 513 RD_MULTI_4(slot, SDHCI_BUFFER, 514 (uint32_t *)buffer, left >> 2); 515 left &= 3; 516 } 517 /* Handle uneven size case. */ 518 if (left > 0) { 519 data = RD4(slot, SDHCI_BUFFER); 520 while (left > 0) { 521 *(buffer++) = data; 522 data >>= 8; 523 left--; 524 } 525 } 526 } 527 528 static void 529 sdhci_write_block_pio(struct sdhci_slot *slot) 530 { 531 uint32_t data = 0; 532 char *buffer; 533 size_t left; 534 535 buffer = slot->curcmd->data->data; 536 buffer += slot->offset; 537 /* Transfer one block at a time. */ 538 left = min(512, slot->curcmd->data->len - slot->offset); 539 slot->offset += left; 540 541 /* Handle unaligned and aligned buffer cases. */ 542 if ((intptr_t)buffer & 3) { 543 while (left > 3) { 544 data = buffer[0] + 545 (buffer[1] << 8) + 546 (buffer[2] << 16) + 547 (buffer[3] << 24); 548 left -= 4; 549 buffer += 4; 550 WR4(slot, SDHCI_BUFFER, data); 551 } 552 } else { 553 WR_MULTI_4(slot, SDHCI_BUFFER, 554 (uint32_t *)buffer, left >> 2); 555 left &= 3; 556 } 557 /* Handle uneven size case. */ 558 if (left > 0) { 559 while (left > 0) { 560 data <<= 8; 561 data += *(buffer++); 562 left--; 563 } 564 WR4(slot, SDHCI_BUFFER, data); 565 } 566 } 567 568 static void 569 sdhci_transfer_pio(struct sdhci_slot *slot) 570 { 571 572 /* Read as many blocks as possible. */ 573 if (slot->curcmd->data->flags & MMC_DATA_READ) { 574 while (RD4(slot, SDHCI_PRESENT_STATE) & 575 SDHCI_DATA_AVAILABLE) { 576 sdhci_read_block_pio(slot); 577 if (slot->offset >= slot->curcmd->data->len) 578 break; 579 } 580 } else { 581 while (RD4(slot, SDHCI_PRESENT_STATE) & 582 SDHCI_SPACE_AVAILABLE) { 583 sdhci_write_block_pio(slot); 584 if (slot->offset >= slot->curcmd->data->len) 585 break; 586 } 587 } 588 } 589 590 static void 591 sdhci_card_task(void *arg, int pending __unused) 592 { 593 struct sdhci_slot *slot = arg; 594 device_t d; 595 596 SDHCI_LOCK(slot); 597 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 598 #ifdef MMCCAM 599 if (slot->card_present == 0) { 600 #else 601 if (slot->dev == NULL) { 602 #endif 603 /* If card is present - attach mmc bus. */ 604 if (bootverbose || sdhci_debug) 605 slot_printf(slot, "Card inserted\n"); 606 #ifdef MMCCAM 607 slot->card_present = 1; 608 union ccb *ccb; 609 uint32_t pathid; 610 pathid = cam_sim_path(slot->sim); 611 ccb = xpt_alloc_ccb_nowait(); 612 if (ccb == NULL) { 613 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 614 SDHCI_UNLOCK(slot); 615 return; 616 } 617 618 /* 619 * We create a rescan request for BUS:0:0, since the card 620 * will be at lun 0. 621 */ 622 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 623 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 624 slot_printf(slot, "Unable to create path for rescan\n"); 625 SDHCI_UNLOCK(slot); 626 xpt_free_ccb(ccb); 627 return; 628 } 629 SDHCI_UNLOCK(slot); 630 xpt_rescan(ccb); 631 #else 632 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 633 SDHCI_UNLOCK(slot); 634 if (d) { 635 device_set_ivars(d, slot); 636 (void)device_probe_and_attach(d); 637 } 638 #endif 639 } else 640 SDHCI_UNLOCK(slot); 641 } else { 642 #ifdef MMCCAM 643 if (slot->card_present == 1) { 644 #else 645 if (slot->dev != NULL) { 646 #endif 647 /* If no card present - detach mmc bus. */ 648 if (bootverbose || sdhci_debug) 649 slot_printf(slot, "Card removed\n"); 650 d = slot->dev; 651 slot->dev = NULL; 652 #ifdef MMCCAM 653 slot->card_present = 0; 654 union ccb *ccb; 655 uint32_t pathid; 656 pathid = cam_sim_path(slot->sim); 657 ccb = xpt_alloc_ccb_nowait(); 658 if (ccb == NULL) { 659 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 660 SDHCI_UNLOCK(slot); 661 return; 662 } 663 664 /* 665 * We create a rescan request for BUS:0:0, since the card 666 * will be at lun 0. 667 */ 668 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 669 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 670 slot_printf(slot, "Unable to create path for rescan\n"); 671 SDHCI_UNLOCK(slot); 672 xpt_free_ccb(ccb); 673 return; 674 } 675 SDHCI_UNLOCK(slot); 676 xpt_rescan(ccb); 677 #else 678 slot->intmask &= ~sdhci_tuning_intmask(slot); 679 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 680 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 681 slot->opt &= ~SDHCI_TUNING_ENABLED; 682 SDHCI_UNLOCK(slot); 683 callout_drain(&slot->retune_callout); 684 device_delete_child(slot->bus, d); 685 #endif 686 } else 687 SDHCI_UNLOCK(slot); 688 } 689 } 690 691 static void 692 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 693 { 694 bool was_present; 695 696 /* 697 * If there was no card and now there is one, schedule the task to 698 * create the child device after a short delay. The delay is to 699 * debounce the card insert (sometimes the card detect pin stabilizes 700 * before the other pins have made good contact). 701 * 702 * If there was a card present and now it's gone, immediately schedule 703 * the task to delete the child device. No debouncing -- gone is gone, 704 * because once power is removed, a full card re-init is needed, and 705 * that happens by deleting and recreating the child device. 706 */ 707 #ifdef MMCCAM 708 was_present = slot->card_present; 709 #else 710 was_present = slot->dev != NULL; 711 #endif 712 if (!was_present && is_present) { 713 taskqueue_enqueue_timeout(taskqueue_swi_giant, 714 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 715 } else if (was_present && !is_present) { 716 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 717 } 718 } 719 720 void 721 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 722 { 723 724 SDHCI_LOCK(slot); 725 sdhci_handle_card_present_locked(slot, is_present); 726 SDHCI_UNLOCK(slot); 727 } 728 729 static void 730 sdhci_card_poll(void *arg) 731 { 732 struct sdhci_slot *slot = arg; 733 734 sdhci_handle_card_present(slot, 735 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 736 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 737 sdhci_card_poll, slot); 738 } 739 740 int 741 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 742 { 743 kobjop_desc_t kobj_desc; 744 kobj_method_t *kobj_method; 745 uint32_t caps, caps2, freq, host_caps; 746 int err; 747 748 SDHCI_LOCK_INIT(slot); 749 750 slot->num = num; 751 slot->bus = dev; 752 753 /* Allocate DMA tag. */ 754 err = bus_dma_tag_create(bus_get_dma_tag(dev), 755 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 756 BUS_SPACE_MAXADDR, NULL, NULL, 757 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 758 BUS_DMA_ALLOCNOW, NULL, NULL, 759 &slot->dmatag); 760 if (err != 0) { 761 device_printf(dev, "Can't create DMA tag\n"); 762 SDHCI_LOCK_DESTROY(slot); 763 return (err); 764 } 765 /* Allocate DMA memory. */ 766 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 767 BUS_DMA_NOWAIT, &slot->dmamap); 768 if (err != 0) { 769 device_printf(dev, "Can't alloc DMA memory\n"); 770 bus_dma_tag_destroy(slot->dmatag); 771 SDHCI_LOCK_DESTROY(slot); 772 return (err); 773 } 774 /* Map the memory. */ 775 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 776 (void *)slot->dmamem, DMA_BLOCK_SIZE, 777 sdhci_getaddr, &slot->paddr, 0); 778 if (err != 0 || slot->paddr == 0) { 779 device_printf(dev, "Can't load DMA memory\n"); 780 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 781 bus_dma_tag_destroy(slot->dmatag); 782 SDHCI_LOCK_DESTROY(slot); 783 if (err) 784 return (err); 785 else 786 return (EFAULT); 787 } 788 789 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 790 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 791 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 792 caps = slot->caps; 793 caps2 = slot->caps2; 794 } else { 795 caps = RD4(slot, SDHCI_CAPABILITIES); 796 if (slot->version >= SDHCI_SPEC_300) 797 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 798 else 799 caps2 = 0; 800 } 801 if (slot->version >= SDHCI_SPEC_300) { 802 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 803 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 804 device_printf(dev, 805 "Driver doesn't support shared bus slots\n"); 806 bus_dmamap_unload(slot->dmatag, slot->dmamap); 807 bus_dmamem_free(slot->dmatag, slot->dmamem, 808 slot->dmamap); 809 bus_dma_tag_destroy(slot->dmatag); 810 SDHCI_LOCK_DESTROY(slot); 811 return (ENXIO); 812 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 813 SDHCI_SLOTTYPE_EMBEDDED) { 814 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 815 } 816 } 817 /* Calculate base clock frequency. */ 818 if (slot->version >= SDHCI_SPEC_300) 819 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 820 SDHCI_CLOCK_BASE_SHIFT; 821 else 822 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 823 SDHCI_CLOCK_BASE_SHIFT; 824 if (freq != 0) 825 slot->max_clk = freq * 1000000; 826 /* 827 * If the frequency wasn't in the capabilities and the hardware driver 828 * hasn't already set max_clk we're probably not going to work right 829 * with an assumption, so complain about it. 830 */ 831 if (slot->max_clk == 0) { 832 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 833 device_printf(dev, "Hardware doesn't specify base clock " 834 "frequency, using %dMHz as default.\n", 835 SDHCI_DEFAULT_MAX_FREQ); 836 } 837 /* Calculate/set timeout clock frequency. */ 838 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 839 slot->timeout_clk = slot->max_clk / 1000; 840 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 841 slot->timeout_clk = 1000; 842 } else { 843 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 844 SDHCI_TIMEOUT_CLK_SHIFT; 845 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 846 slot->timeout_clk *= 1000; 847 } 848 /* 849 * If the frequency wasn't in the capabilities and the hardware driver 850 * hasn't already set timeout_clk we'll probably work okay using the 851 * max timeout, but still mention it. 852 */ 853 if (slot->timeout_clk == 0) { 854 device_printf(dev, "Hardware doesn't specify timeout clock " 855 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 856 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 857 } 858 859 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 860 slot->host.f_max = slot->max_clk; 861 slot->host.host_ocr = 0; 862 if (caps & SDHCI_CAN_VDD_330) 863 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 864 if (caps & SDHCI_CAN_VDD_300) 865 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 866 /* 1.8V VDD is not supposed to be used for removable cards. */ 867 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) 868 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 869 if (slot->host.host_ocr == 0) { 870 device_printf(dev, "Hardware doesn't report any " 871 "support voltages.\n"); 872 } 873 874 host_caps = MMC_CAP_4_BIT_DATA; 875 if (caps & SDHCI_CAN_DO_8BITBUS) 876 host_caps |= MMC_CAP_8_BIT_DATA; 877 if (caps & SDHCI_CAN_DO_HISPD) 878 host_caps |= MMC_CAP_HSPEED; 879 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 880 host_caps |= MMC_CAP_BOOT_NOACC; 881 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 882 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 883 884 /* Determine supported UHS-I and eMMC modes. */ 885 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 886 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 887 if (caps2 & SDHCI_CAN_SDR104) { 888 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 889 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 890 host_caps |= MMC_CAP_MMC_HS200; 891 } else if (caps2 & SDHCI_CAN_SDR50) 892 host_caps |= MMC_CAP_UHS_SDR50; 893 if (caps2 & SDHCI_CAN_DDR50 && 894 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 895 host_caps |= MMC_CAP_UHS_DDR50; 896 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 897 host_caps |= MMC_CAP_MMC_DDR52; 898 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 899 caps2 & SDHCI_CAN_MMC_HS400) 900 host_caps |= MMC_CAP_MMC_HS400; 901 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 && 902 caps2 & SDHCI_CAN_SDR104) 903 host_caps |= MMC_CAP_MMC_HS400; 904 905 /* 906 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 907 * default NULL implementation. 908 */ 909 kobj_desc = &sdhci_set_uhs_timing_desc; 910 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 911 kobj_desc); 912 if (kobj_method == &kobj_desc->deflt) 913 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 914 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 915 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 916 917 #define SDHCI_CAP_MODES_TUNING(caps2) \ 918 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 919 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 920 MMC_CAP_MMC_HS400) 921 922 /* 923 * Disable UHS-I and eMMC modes that require (re-)tuning if either 924 * the tune or re-tune method is the default NULL implementation. 925 */ 926 kobj_desc = &mmcbr_tune_desc; 927 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 928 kobj_desc); 929 if (kobj_method == &kobj_desc->deflt) 930 goto no_tuning; 931 kobj_desc = &mmcbr_retune_desc; 932 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 933 kobj_desc); 934 if (kobj_method == &kobj_desc->deflt) { 935 no_tuning: 936 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 937 } 938 939 /* Allocate tuning structures and determine tuning parameters. */ 940 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 941 slot->opt |= SDHCI_TUNING_SUPPORTED; 942 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 943 M_WAITOK); 944 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 945 M_WAITOK); 946 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 947 M_WAITOK); 948 if (caps2 & SDHCI_TUNE_SDR50) 949 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 950 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 951 SDHCI_RETUNE_MODES_SHIFT; 952 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 953 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 954 SDHCI_RETUNE_CNT_SHIFT; 955 if (slot->retune_count > 0xb) { 956 device_printf(dev, "Unknown re-tuning count " 957 "%x, using 1 sec\n", slot->retune_count); 958 slot->retune_count = 1; 959 } else if (slot->retune_count != 0) 960 slot->retune_count = 961 1 << (slot->retune_count - 1); 962 } 963 } 964 965 #undef SDHCI_CAP_MODES_TUNING 966 967 /* Determine supported VCCQ signaling levels. */ 968 host_caps |= MMC_CAP_SIGNALING_330; 969 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 970 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 971 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 972 MMC_CAP_MMC_HS400_180)) 973 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 974 975 /* 976 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 977 * default NULL implementation. Disable 1.2 V support if it's the 978 * generic SDHCI implementation. 979 */ 980 kobj_desc = &mmcbr_switch_vccq_desc; 981 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 982 kobj_desc); 983 if (kobj_method == &kobj_desc->deflt) 984 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 985 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 986 host_caps &= ~MMC_CAP_SIGNALING_120; 987 988 /* Determine supported driver types (type B is always mandatory). */ 989 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 990 host_caps |= MMC_CAP_DRIVER_TYPE_A; 991 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 992 host_caps |= MMC_CAP_DRIVER_TYPE_C; 993 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 994 host_caps |= MMC_CAP_DRIVER_TYPE_D; 995 slot->host.caps = host_caps; 996 997 /* Decide if we have usable DMA. */ 998 if (caps & SDHCI_CAN_DO_DMA) 999 slot->opt |= SDHCI_HAVE_DMA; 1000 1001 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 1002 slot->opt &= ~SDHCI_HAVE_DMA; 1003 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 1004 slot->opt |= SDHCI_HAVE_DMA; 1005 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 1006 slot->opt |= SDHCI_NON_REMOVABLE; 1007 1008 /* 1009 * Use platform-provided transfer backend 1010 * with PIO as a fallback mechanism 1011 */ 1012 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 1013 slot->opt &= ~SDHCI_HAVE_DMA; 1014 1015 if (bootverbose || sdhci_debug) { 1016 slot_printf(slot, 1017 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 1018 slot->max_clk / 1000000, 1019 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 1020 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 1021 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 1022 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 1023 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 1024 ((caps & SDHCI_CAN_VDD_180) && 1025 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 1026 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 1027 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 1028 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 1029 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 1030 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 1031 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 1032 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 1033 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 1034 "removable"); 1035 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 1036 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 1037 slot_printf(slot, "eMMC:%s%s%s%s\n", 1038 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 1039 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 1040 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 1041 ((host_caps & 1042 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 1043 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 1044 " HS400ES" : ""); 1045 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1046 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 1047 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 1048 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 1049 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 1050 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 1051 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 1052 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 1053 if (slot->opt & SDHCI_TUNING_SUPPORTED) 1054 slot_printf(slot, "Re-tuning count %d secs, mode %d\n", 1055 slot->retune_count, slot->retune_mode + 1); 1056 sdhci_dumpregs(slot); 1057 } 1058 1059 slot->timeout = 10; 1060 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1061 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1062 "timeout", CTLFLAG_RW, &slot->timeout, 0, 1063 "Maximum timeout for SDHCI transfers (in secs)"); 1064 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1065 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1066 sdhci_card_task, slot); 1067 callout_init(&slot->card_poll_callout, 1); 1068 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1069 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1070 1071 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1072 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1073 callout_reset(&slot->card_poll_callout, 1074 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1075 } 1076 1077 sdhci_init(slot); 1078 1079 return (0); 1080 } 1081 1082 #ifndef MMCCAM 1083 void 1084 sdhci_start_slot(struct sdhci_slot *slot) 1085 { 1086 1087 sdhci_card_task(slot, 0); 1088 } 1089 #endif 1090 1091 int 1092 sdhci_cleanup_slot(struct sdhci_slot *slot) 1093 { 1094 device_t d; 1095 1096 callout_drain(&slot->timeout_callout); 1097 callout_drain(&slot->card_poll_callout); 1098 callout_drain(&slot->retune_callout); 1099 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1100 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1101 1102 SDHCI_LOCK(slot); 1103 d = slot->dev; 1104 slot->dev = NULL; 1105 SDHCI_UNLOCK(slot); 1106 if (d != NULL) 1107 device_delete_child(slot->bus, d); 1108 1109 SDHCI_LOCK(slot); 1110 sdhci_reset(slot, SDHCI_RESET_ALL); 1111 SDHCI_UNLOCK(slot); 1112 bus_dmamap_unload(slot->dmatag, slot->dmamap); 1113 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 1114 bus_dma_tag_destroy(slot->dmatag); 1115 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1116 free(slot->tune_req, M_DEVBUF); 1117 free(slot->tune_cmd, M_DEVBUF); 1118 free(slot->tune_data, M_DEVBUF); 1119 } 1120 1121 SDHCI_LOCK_DESTROY(slot); 1122 1123 return (0); 1124 } 1125 1126 int 1127 sdhci_generic_suspend(struct sdhci_slot *slot) 1128 { 1129 1130 /* 1131 * We expect the MMC layer to issue initial tuning after resume. 1132 * Otherwise, we'd need to indicate re-tuning including circuit reset 1133 * being required at least for re-tuning modes 1 and 2 ourselves. 1134 */ 1135 callout_drain(&slot->retune_callout); 1136 SDHCI_LOCK(slot); 1137 slot->opt &= ~SDHCI_TUNING_ENABLED; 1138 sdhci_reset(slot, SDHCI_RESET_ALL); 1139 SDHCI_UNLOCK(slot); 1140 1141 return (0); 1142 } 1143 1144 int 1145 sdhci_generic_resume(struct sdhci_slot *slot) 1146 { 1147 1148 SDHCI_LOCK(slot); 1149 sdhci_init(slot); 1150 SDHCI_UNLOCK(slot); 1151 1152 return (0); 1153 } 1154 1155 uint32_t 1156 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1157 { 1158 1159 if (slot->version >= SDHCI_SPEC_300) 1160 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1161 else 1162 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1163 } 1164 1165 bool 1166 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1167 { 1168 1169 if (slot->opt & SDHCI_NON_REMOVABLE) 1170 return true; 1171 1172 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1173 } 1174 1175 void 1176 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1177 { 1178 struct mmc_ios *ios; 1179 uint16_t hostctrl2; 1180 1181 if (slot->version < SDHCI_SPEC_300) 1182 return; 1183 1184 SDHCI_ASSERT_LOCKED(slot); 1185 ios = &slot->host.ios; 1186 sdhci_set_clock(slot, 0); 1187 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1188 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1189 if (ios->clock > SD_SDR50_MAX) { 1190 if (ios->timing == bus_timing_mmc_hs400 || 1191 ios->timing == bus_timing_mmc_hs400es) 1192 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1193 else 1194 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1195 } 1196 else if (ios->clock > SD_SDR25_MAX) 1197 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1198 else if (ios->clock > SD_SDR12_MAX) { 1199 if (ios->timing == bus_timing_uhs_ddr50 || 1200 ios->timing == bus_timing_mmc_ddr52) 1201 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1202 else 1203 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1204 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1205 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1206 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1207 sdhci_set_clock(slot, ios->clock); 1208 } 1209 1210 int 1211 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1212 { 1213 struct sdhci_slot *slot = device_get_ivars(reqdev); 1214 struct mmc_ios *ios = &slot->host.ios; 1215 1216 SDHCI_LOCK(slot); 1217 /* Do full reset on bus power down to clear from any state. */ 1218 if (ios->power_mode == power_off) { 1219 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1220 sdhci_init(slot); 1221 } 1222 /* Configure the bus. */ 1223 sdhci_set_clock(slot, ios->clock); 1224 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1225 if (ios->bus_width == bus_width_8) { 1226 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1227 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1228 } else if (ios->bus_width == bus_width_4) { 1229 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1230 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1231 } else if (ios->bus_width == bus_width_1) { 1232 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1233 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1234 } else { 1235 panic("Invalid bus width: %d", ios->bus_width); 1236 } 1237 if (ios->clock > SD_SDR12_MAX && 1238 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1239 slot->hostctrl |= SDHCI_CTRL_HISPD; 1240 else 1241 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1242 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1243 SDHCI_SET_UHS_TIMING(brdev, slot); 1244 /* Some controllers like reset after bus changes. */ 1245 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1246 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1247 1248 SDHCI_UNLOCK(slot); 1249 return (0); 1250 } 1251 1252 int 1253 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1254 { 1255 struct sdhci_slot *slot = device_get_ivars(reqdev); 1256 enum mmc_vccq vccq; 1257 int err; 1258 uint16_t hostctrl2; 1259 1260 if (slot->version < SDHCI_SPEC_300) 1261 return (0); 1262 1263 err = 0; 1264 vccq = slot->host.ios.vccq; 1265 SDHCI_LOCK(slot); 1266 sdhci_set_clock(slot, 0); 1267 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1268 switch (vccq) { 1269 case vccq_330: 1270 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1271 goto done; 1272 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1273 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1274 DELAY(5000); 1275 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1276 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1277 goto done; 1278 err = EAGAIN; 1279 break; 1280 case vccq_180: 1281 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1282 err = EINVAL; 1283 goto done; 1284 } 1285 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1286 goto done; 1287 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1288 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1289 DELAY(5000); 1290 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1291 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1292 goto done; 1293 err = EAGAIN; 1294 break; 1295 default: 1296 slot_printf(slot, 1297 "Attempt to set unsupported signaling voltage\n"); 1298 err = EINVAL; 1299 break; 1300 } 1301 done: 1302 sdhci_set_clock(slot, slot->host.ios.clock); 1303 SDHCI_UNLOCK(slot); 1304 return (err); 1305 } 1306 1307 int 1308 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1309 { 1310 struct sdhci_slot *slot = device_get_ivars(reqdev); 1311 struct mmc_ios *ios = &slot->host.ios; 1312 struct mmc_command *tune_cmd; 1313 struct mmc_data *tune_data; 1314 uint32_t opcode; 1315 int err; 1316 1317 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1318 return (0); 1319 1320 slot->retune_ticks = slot->retune_count * hz; 1321 opcode = MMC_SEND_TUNING_BLOCK; 1322 SDHCI_LOCK(slot); 1323 switch (ios->timing) { 1324 case bus_timing_mmc_hs400: 1325 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1326 SDHCI_UNLOCK(slot); 1327 return (EINVAL); 1328 case bus_timing_mmc_hs200: 1329 /* 1330 * In HS400 mode, controllers use the data strobe line to 1331 * latch data from the devices so periodic re-tuning isn't 1332 * expected to be required. 1333 */ 1334 if (hs400) 1335 slot->retune_ticks = 0; 1336 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1337 break; 1338 case bus_timing_uhs_ddr50: 1339 case bus_timing_uhs_sdr104: 1340 break; 1341 case bus_timing_uhs_sdr50: 1342 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1343 break; 1344 /* FALLTHROUGH */ 1345 default: 1346 SDHCI_UNLOCK(slot); 1347 return (0); 1348 } 1349 1350 tune_cmd = slot->tune_cmd; 1351 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1352 tune_cmd->opcode = opcode; 1353 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1354 tune_data = tune_cmd->data = slot->tune_data; 1355 memset(tune_data, 0, sizeof(*tune_data)); 1356 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1357 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1358 MMC_TUNING_LEN; 1359 tune_data->flags = MMC_DATA_READ; 1360 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1361 1362 slot->opt &= ~SDHCI_TUNING_ENABLED; 1363 err = sdhci_exec_tuning(slot, true); 1364 if (err == 0) { 1365 slot->opt |= SDHCI_TUNING_ENABLED; 1366 slot->intmask |= sdhci_tuning_intmask(slot); 1367 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1368 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1369 if (slot->retune_ticks) { 1370 callout_reset(&slot->retune_callout, slot->retune_ticks, 1371 sdhci_retune, slot); 1372 } 1373 } 1374 SDHCI_UNLOCK(slot); 1375 return (err); 1376 } 1377 1378 int 1379 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1380 { 1381 struct sdhci_slot *slot = device_get_ivars(reqdev); 1382 int err; 1383 1384 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1385 return (0); 1386 1387 /* HS400 must be tuned in HS200 mode. */ 1388 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1389 return (EINVAL); 1390 1391 SDHCI_LOCK(slot); 1392 err = sdhci_exec_tuning(slot, reset); 1393 /* 1394 * There are two ways sdhci_exec_tuning() can fail: 1395 * EBUSY should not actually happen when requests are only issued 1396 * with the host properly acquired, and 1397 * EIO re-tuning failed (but it did work initially). 1398 * 1399 * In both cases, we should retry at later point if periodic re-tuning 1400 * is enabled. Note that due to slot->retune_req not being cleared in 1401 * these failure cases, the MMC layer should trigger another attempt at 1402 * re-tuning with the next request anyway, though. 1403 */ 1404 if (slot->retune_ticks) { 1405 callout_reset(&slot->retune_callout, slot->retune_ticks, 1406 sdhci_retune, slot); 1407 } 1408 SDHCI_UNLOCK(slot); 1409 return (err); 1410 } 1411 1412 static int 1413 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1414 { 1415 struct mmc_request *tune_req; 1416 struct mmc_command *tune_cmd; 1417 int i; 1418 uint32_t intmask; 1419 uint16_t hostctrl2; 1420 u_char opt; 1421 1422 SDHCI_ASSERT_LOCKED(slot); 1423 if (slot->req != NULL) 1424 return (EBUSY); 1425 1426 /* Tuning doesn't work with DMA enabled. */ 1427 opt = slot->opt; 1428 slot->opt = opt & ~SDHCI_HAVE_DMA; 1429 1430 /* 1431 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1432 * kind of interrupt we receive in response to a tuning request. 1433 */ 1434 intmask = slot->intmask; 1435 slot->intmask = SDHCI_INT_DATA_AVAIL; 1436 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL); 1437 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1438 1439 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1440 if (reset) 1441 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1442 else 1443 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1444 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1445 1446 tune_req = slot->tune_req; 1447 tune_cmd = slot->tune_cmd; 1448 for (i = 0; i < MMC_TUNING_MAX; i++) { 1449 memset(tune_req, 0, sizeof(*tune_req)); 1450 tune_req->cmd = tune_cmd; 1451 tune_req->done = sdhci_req_wakeup; 1452 tune_req->done_data = slot; 1453 slot->req = tune_req; 1454 slot->flags = 0; 1455 sdhci_start(slot); 1456 while (!(tune_req->flags & MMC_REQ_DONE)) 1457 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1458 if (!(tune_req->flags & MMC_TUNE_DONE)) 1459 break; 1460 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1461 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1462 break; 1463 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1464 DELAY(1000); 1465 } 1466 1467 /* 1468 * Restore DMA usage and interrupts. 1469 * Note that the interrupt aggregation code might have cleared 1470 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask 1471 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE 1472 * doesn't lose these. 1473 */ 1474 slot->opt = opt; 1475 slot->intmask = intmask; 1476 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END | 1477 SDHCI_INT_RESPONSE); 1478 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1479 1480 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1481 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1482 slot->retune_req = 0; 1483 return (0); 1484 } 1485 1486 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1487 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1488 SDHCI_CTRL2_SAMPLING_CLOCK)); 1489 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1490 return (EIO); 1491 } 1492 1493 static void 1494 sdhci_retune(void *arg) 1495 { 1496 struct sdhci_slot *slot = arg; 1497 1498 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1499 } 1500 1501 #ifdef MMCCAM 1502 static void 1503 sdhci_req_done(struct sdhci_slot *slot) 1504 { 1505 union ccb *ccb; 1506 1507 if (__predict_false(sdhci_debug > 1)) 1508 slot_printf(slot, "%s\n", __func__); 1509 if (slot->ccb != NULL && slot->curcmd != NULL) { 1510 callout_stop(&slot->timeout_callout); 1511 ccb = slot->ccb; 1512 slot->ccb = NULL; 1513 slot->curcmd = NULL; 1514 1515 /* Tell CAM the request is finished */ 1516 struct ccb_mmcio *mmcio; 1517 mmcio = &ccb->mmcio; 1518 1519 ccb->ccb_h.status = 1520 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1521 xpt_done(ccb); 1522 } 1523 } 1524 #else 1525 static void 1526 sdhci_req_done(struct sdhci_slot *slot) 1527 { 1528 struct mmc_request *req; 1529 1530 if (slot->req != NULL && slot->curcmd != NULL) { 1531 callout_stop(&slot->timeout_callout); 1532 req = slot->req; 1533 slot->req = NULL; 1534 slot->curcmd = NULL; 1535 req->done(req); 1536 } 1537 } 1538 #endif 1539 1540 static void 1541 sdhci_req_wakeup(struct mmc_request *req) 1542 { 1543 struct sdhci_slot *slot; 1544 1545 slot = req->done_data; 1546 req->flags |= MMC_REQ_DONE; 1547 wakeup(req); 1548 } 1549 1550 static void 1551 sdhci_timeout(void *arg) 1552 { 1553 struct sdhci_slot *slot = arg; 1554 1555 if (slot->curcmd != NULL) { 1556 slot_printf(slot, "Controller timeout\n"); 1557 sdhci_dumpregs(slot); 1558 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1559 slot->curcmd->error = MMC_ERR_TIMEOUT; 1560 sdhci_req_done(slot); 1561 } else { 1562 slot_printf(slot, "Spurious timeout - no active command\n"); 1563 } 1564 } 1565 1566 static void 1567 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1568 { 1569 uint16_t mode; 1570 1571 if (data == NULL) 1572 return; 1573 1574 mode = SDHCI_TRNS_BLK_CNT_EN; 1575 if (data->len > 512) { 1576 mode |= SDHCI_TRNS_MULTI; 1577 if (__predict_true( 1578 #ifdef MMCCAM 1579 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION && 1580 #else 1581 slot->req->stop != NULL && 1582 #endif 1583 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))) 1584 mode |= SDHCI_TRNS_ACMD12; 1585 } 1586 if (data->flags & MMC_DATA_READ) 1587 mode |= SDHCI_TRNS_READ; 1588 if (slot->flags & SDHCI_USE_DMA) 1589 mode |= SDHCI_TRNS_DMA; 1590 1591 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1592 } 1593 1594 static void 1595 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1596 { 1597 int flags, timeout; 1598 uint32_t mask; 1599 1600 slot->curcmd = cmd; 1601 slot->cmd_done = 0; 1602 1603 cmd->error = MMC_ERR_NONE; 1604 1605 /* This flags combination is not supported by controller. */ 1606 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1607 slot_printf(slot, "Unsupported response type!\n"); 1608 cmd->error = MMC_ERR_FAILED; 1609 sdhci_req_done(slot); 1610 return; 1611 } 1612 1613 /* 1614 * Do not issue command if there is no card, clock or power. 1615 * Controller will not detect timeout without clock active. 1616 */ 1617 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1618 slot->power == 0 || 1619 slot->clock == 0) { 1620 slot_printf(slot, 1621 "Cannot issue a command (power=%d clock=%d)", 1622 slot->power, slot->clock); 1623 cmd->error = MMC_ERR_FAILED; 1624 sdhci_req_done(slot); 1625 return; 1626 } 1627 /* Always wait for free CMD bus. */ 1628 mask = SDHCI_CMD_INHIBIT; 1629 /* Wait for free DAT if we have data or busy signal. */ 1630 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1631 mask |= SDHCI_DAT_INHIBIT; 1632 /* 1633 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1634 * that these latter are also special in that SDHCI_CMD_DATA should 1635 * be set below but no actual data is ever read from the controller. 1636 */ 1637 #ifdef MMCCAM 1638 if (cmd == &slot->ccb->mmcio.stop || 1639 #else 1640 if (cmd == slot->req->stop || 1641 #endif 1642 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1643 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1644 mask &= ~SDHCI_DAT_INHIBIT; 1645 /* 1646 * Wait for bus no more then 250 ms. Typically there will be no wait 1647 * here at all, but when writing a crash dump we may be bypassing the 1648 * host platform's interrupt handler, and in some cases that handler 1649 * may be working around hardware quirks such as not respecting r1b 1650 * busy indications. In those cases, this wait-loop serves the purpose 1651 * of waiting for the prior command and data transfers to be done, and 1652 * SD cards are allowed to take up to 250ms for write and erase ops. 1653 * (It's usually more like 20-30ms in the real world.) 1654 */ 1655 timeout = 250; 1656 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1657 if (timeout == 0) { 1658 slot_printf(slot, "Controller never released " 1659 "inhibit bit(s).\n"); 1660 sdhci_dumpregs(slot); 1661 cmd->error = MMC_ERR_FAILED; 1662 sdhci_req_done(slot); 1663 return; 1664 } 1665 timeout--; 1666 DELAY(1000); 1667 } 1668 1669 /* Prepare command flags. */ 1670 if (!(cmd->flags & MMC_RSP_PRESENT)) 1671 flags = SDHCI_CMD_RESP_NONE; 1672 else if (cmd->flags & MMC_RSP_136) 1673 flags = SDHCI_CMD_RESP_LONG; 1674 else if (cmd->flags & MMC_RSP_BUSY) 1675 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1676 else 1677 flags = SDHCI_CMD_RESP_SHORT; 1678 if (cmd->flags & MMC_RSP_CRC) 1679 flags |= SDHCI_CMD_CRC; 1680 if (cmd->flags & MMC_RSP_OPCODE) 1681 flags |= SDHCI_CMD_INDEX; 1682 if (cmd->data != NULL) 1683 flags |= SDHCI_CMD_DATA; 1684 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1685 flags |= SDHCI_CMD_TYPE_ABORT; 1686 /* Prepare data. */ 1687 sdhci_start_data(slot, cmd->data); 1688 /* 1689 * Interrupt aggregation: To reduce total number of interrupts 1690 * group response interrupt with data interrupt when possible. 1691 * If there going to be data interrupt, mask response one. 1692 */ 1693 if (slot->data_done == 0) { 1694 WR4(slot, SDHCI_SIGNAL_ENABLE, 1695 slot->intmask &= ~SDHCI_INT_RESPONSE); 1696 } 1697 /* Set command argument. */ 1698 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1699 /* Set data transfer mode. */ 1700 sdhci_set_transfer_mode(slot, cmd->data); 1701 if (__predict_false(sdhci_debug > 1)) 1702 slot_printf(slot, "Starting command!\n"); 1703 /* Start command. */ 1704 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1705 /* Start timeout callout. */ 1706 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1707 sdhci_timeout, slot); 1708 } 1709 1710 static void 1711 sdhci_finish_command(struct sdhci_slot *slot) 1712 { 1713 int i; 1714 uint32_t val; 1715 uint8_t extra; 1716 1717 if (__predict_false(sdhci_debug > 1)) 1718 slot_printf(slot, "%s: called, err %d flags %d\n", 1719 __func__, slot->curcmd->error, slot->curcmd->flags); 1720 slot->cmd_done = 1; 1721 /* 1722 * Interrupt aggregation: Restore command interrupt. 1723 * Main restore point for the case when command interrupt 1724 * happened first. 1725 */ 1726 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1727 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1728 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1729 SDHCI_INT_RESPONSE); 1730 /* In case of error - reset host and return. */ 1731 if (slot->curcmd->error) { 1732 if (slot->curcmd->error == MMC_ERR_BADCRC) 1733 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1734 sdhci_reset(slot, SDHCI_RESET_CMD); 1735 sdhci_reset(slot, SDHCI_RESET_DATA); 1736 sdhci_start(slot); 1737 return; 1738 } 1739 /* If command has response - fetch it. */ 1740 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1741 if (slot->curcmd->flags & MMC_RSP_136) { 1742 /* CRC is stripped so we need one byte shift. */ 1743 extra = 0; 1744 for (i = 0; i < 4; i++) { 1745 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1746 if (slot->quirks & 1747 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1748 slot->curcmd->resp[3 - i] = val; 1749 else { 1750 slot->curcmd->resp[3 - i] = 1751 (val << 8) | extra; 1752 extra = val >> 24; 1753 } 1754 } 1755 } else 1756 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1757 } 1758 if (__predict_false(sdhci_debug > 1)) 1759 printf("Resp: %02x %02x %02x %02x\n", 1760 slot->curcmd->resp[0], slot->curcmd->resp[1], 1761 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1762 1763 /* If data ready - finish. */ 1764 if (slot->data_done) 1765 sdhci_start(slot); 1766 } 1767 1768 static void 1769 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1770 { 1771 uint32_t target_timeout, current_timeout; 1772 uint8_t div; 1773 1774 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1775 slot->data_done = 1; 1776 return; 1777 } 1778 1779 slot->data_done = 0; 1780 1781 /* Calculate and set data timeout.*/ 1782 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1783 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1784 div = 0xE; 1785 } else { 1786 target_timeout = 1000000; 1787 div = 0; 1788 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1789 while (current_timeout < target_timeout && div < 0xE) { 1790 ++div; 1791 current_timeout <<= 1; 1792 } 1793 /* Compensate for an off-by-one error in the CaFe chip.*/ 1794 if (div < 0xE && 1795 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1796 ++div; 1797 } 1798 } 1799 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1800 1801 if (data == NULL) 1802 return; 1803 1804 /* Use DMA if possible. */ 1805 if ((slot->opt & SDHCI_HAVE_DMA)) 1806 slot->flags |= SDHCI_USE_DMA; 1807 /* If data is small, broken DMA may return zeroes instead of data, */ 1808 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1809 (data->len <= 512)) 1810 slot->flags &= ~SDHCI_USE_DMA; 1811 /* Some controllers require even block sizes. */ 1812 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1813 ((data->len) & 0x3)) 1814 slot->flags &= ~SDHCI_USE_DMA; 1815 /* Load DMA buffer. */ 1816 if (slot->flags & SDHCI_USE_DMA) { 1817 if (data->flags & MMC_DATA_READ) 1818 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1819 BUS_DMASYNC_PREREAD); 1820 else { 1821 memcpy(slot->dmamem, data->data, 1822 (data->len < DMA_BLOCK_SIZE) ? 1823 data->len : DMA_BLOCK_SIZE); 1824 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1825 BUS_DMASYNC_PREWRITE); 1826 } 1827 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1828 /* Interrupt aggregation: Mask border interrupt 1829 * for the last page and unmask else. */ 1830 if (data->len == DMA_BLOCK_SIZE) 1831 slot->intmask &= ~SDHCI_INT_DMA_END; 1832 else 1833 slot->intmask |= SDHCI_INT_DMA_END; 1834 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1835 } 1836 /* Current data offset for both PIO and DMA. */ 1837 slot->offset = 0; 1838 /* Set block size and request IRQ on 4K border. */ 1839 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1840 (data->len < 512) ? data->len : 512)); 1841 /* Set block count. */ 1842 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1843 1844 if (__predict_false(sdhci_debug > 1)) 1845 slot_printf(slot, "Block size: %02x, count %lu\n", 1846 (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512), 1847 (unsigned long)(data->len + 511) / 512); 1848 } 1849 1850 void 1851 sdhci_finish_data(struct sdhci_slot *slot) 1852 { 1853 struct mmc_data *data = slot->curcmd->data; 1854 size_t left; 1855 1856 /* Interrupt aggregation: Restore command interrupt. 1857 * Auxiliary restore point for the case when data interrupt 1858 * happened first. */ 1859 if (!slot->cmd_done) { 1860 WR4(slot, SDHCI_SIGNAL_ENABLE, 1861 slot->intmask |= SDHCI_INT_RESPONSE); 1862 } 1863 /* Unload rest of data from DMA buffer. */ 1864 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1865 slot->curcmd->data != NULL) { 1866 if (data->flags & MMC_DATA_READ) { 1867 left = data->len - slot->offset; 1868 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1869 BUS_DMASYNC_POSTREAD); 1870 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1871 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1872 } else 1873 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1874 BUS_DMASYNC_POSTWRITE); 1875 } 1876 slot->data_done = 1; 1877 /* If there was error - reset the host. */ 1878 if (slot->curcmd->error) { 1879 if (slot->curcmd->error == MMC_ERR_BADCRC) 1880 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1881 sdhci_reset(slot, SDHCI_RESET_CMD); 1882 sdhci_reset(slot, SDHCI_RESET_DATA); 1883 sdhci_start(slot); 1884 return; 1885 } 1886 /* If we already have command response - finish. */ 1887 if (slot->cmd_done) 1888 sdhci_start(slot); 1889 } 1890 1891 #ifdef MMCCAM 1892 static void 1893 sdhci_start(struct sdhci_slot *slot) 1894 { 1895 union ccb *ccb; 1896 1897 ccb = slot->ccb; 1898 if (ccb == NULL) 1899 return; 1900 1901 struct ccb_mmcio *mmcio; 1902 mmcio = &ccb->mmcio; 1903 1904 if (!(slot->flags & CMD_STARTED)) { 1905 slot->flags |= CMD_STARTED; 1906 sdhci_start_command(slot, &mmcio->cmd); 1907 return; 1908 } 1909 1910 /* 1911 * Old stack doesn't use this! 1912 * Enabling this code causes significant performance degradation 1913 * and IRQ storms on BBB, Wandboard behaves fine. 1914 * Not using this code does no harm... 1915 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1916 slot->flags |= STOP_STARTED; 1917 sdhci_start_command(slot, &mmcio->stop); 1918 return; 1919 } 1920 */ 1921 if (__predict_false(sdhci_debug > 1)) 1922 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1923 if (mmcio->cmd.error == 0 && 1924 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1925 sdhci_reset(slot, SDHCI_RESET_CMD); 1926 sdhci_reset(slot, SDHCI_RESET_DATA); 1927 } 1928 1929 sdhci_req_done(slot); 1930 } 1931 #else 1932 static void 1933 sdhci_start(struct sdhci_slot *slot) 1934 { 1935 struct mmc_request *req; 1936 1937 req = slot->req; 1938 if (req == NULL) 1939 return; 1940 1941 if (!(slot->flags & CMD_STARTED)) { 1942 slot->flags |= CMD_STARTED; 1943 sdhci_start_command(slot, req->cmd); 1944 return; 1945 } 1946 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1947 !(slot->flags & STOP_STARTED) && req->stop) { 1948 slot->flags |= STOP_STARTED; 1949 sdhci_start_command(slot, req->stop); 1950 return; 1951 } 1952 if (__predict_false(sdhci_debug > 1)) 1953 slot_printf(slot, "result: %d\n", req->cmd->error); 1954 if (!req->cmd->error && 1955 ((slot->curcmd == req->stop && 1956 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1957 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1958 sdhci_reset(slot, SDHCI_RESET_CMD); 1959 sdhci_reset(slot, SDHCI_RESET_DATA); 1960 } 1961 1962 sdhci_req_done(slot); 1963 } 1964 #endif 1965 1966 int 1967 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1968 struct mmc_request *req) 1969 { 1970 struct sdhci_slot *slot = device_get_ivars(reqdev); 1971 1972 SDHCI_LOCK(slot); 1973 if (slot->req != NULL) { 1974 SDHCI_UNLOCK(slot); 1975 return (EBUSY); 1976 } 1977 if (__predict_false(sdhci_debug > 1)) { 1978 slot_printf(slot, 1979 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1980 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1981 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1982 (req->cmd->data)?req->cmd->data->flags:0); 1983 } 1984 slot->req = req; 1985 slot->flags = 0; 1986 sdhci_start(slot); 1987 SDHCI_UNLOCK(slot); 1988 if (dumping) { 1989 while (slot->req != NULL) { 1990 sdhci_generic_intr(slot); 1991 DELAY(10); 1992 } 1993 } 1994 return (0); 1995 } 1996 1997 int 1998 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1999 { 2000 struct sdhci_slot *slot = device_get_ivars(reqdev); 2001 uint32_t val; 2002 2003 SDHCI_LOCK(slot); 2004 val = RD4(slot, SDHCI_PRESENT_STATE); 2005 SDHCI_UNLOCK(slot); 2006 return (!(val & SDHCI_WRITE_PROTECT)); 2007 } 2008 2009 int 2010 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 2011 { 2012 struct sdhci_slot *slot = device_get_ivars(reqdev); 2013 int err = 0; 2014 2015 SDHCI_LOCK(slot); 2016 while (slot->bus_busy) 2017 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 2018 slot->bus_busy++; 2019 /* Activate led. */ 2020 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 2021 SDHCI_UNLOCK(slot); 2022 return (err); 2023 } 2024 2025 int 2026 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 2027 { 2028 struct sdhci_slot *slot = device_get_ivars(reqdev); 2029 2030 SDHCI_LOCK(slot); 2031 /* Deactivate led. */ 2032 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 2033 slot->bus_busy--; 2034 SDHCI_UNLOCK(slot); 2035 wakeup(slot); 2036 return (0); 2037 } 2038 2039 static void 2040 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2041 { 2042 2043 if (!slot->curcmd) { 2044 slot_printf(slot, "Got command interrupt 0x%08x, but " 2045 "there is no active command.\n", intmask); 2046 sdhci_dumpregs(slot); 2047 return; 2048 } 2049 if (intmask & SDHCI_INT_TIMEOUT) 2050 slot->curcmd->error = MMC_ERR_TIMEOUT; 2051 else if (intmask & SDHCI_INT_CRC) 2052 slot->curcmd->error = MMC_ERR_BADCRC; 2053 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2054 slot->curcmd->error = MMC_ERR_FIFO; 2055 2056 sdhci_finish_command(slot); 2057 } 2058 2059 static void 2060 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2061 { 2062 struct mmc_data *data; 2063 size_t left; 2064 2065 if (!slot->curcmd) { 2066 slot_printf(slot, "Got data interrupt 0x%08x, but " 2067 "there is no active command.\n", intmask); 2068 sdhci_dumpregs(slot); 2069 return; 2070 } 2071 if (slot->curcmd->data == NULL && 2072 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2073 slot_printf(slot, "Got data interrupt 0x%08x, but " 2074 "there is no active data operation.\n", 2075 intmask); 2076 sdhci_dumpregs(slot); 2077 return; 2078 } 2079 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2080 slot->curcmd->error = MMC_ERR_TIMEOUT; 2081 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2082 slot->curcmd->error = MMC_ERR_BADCRC; 2083 if (slot->curcmd->data == NULL && 2084 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2085 SDHCI_INT_DMA_END))) { 2086 slot_printf(slot, "Got data interrupt 0x%08x, but " 2087 "there is busy-only command.\n", intmask); 2088 sdhci_dumpregs(slot); 2089 slot->curcmd->error = MMC_ERR_INVALID; 2090 } 2091 if (slot->curcmd->error) { 2092 /* No need to continue after any error. */ 2093 goto done; 2094 } 2095 2096 /* Handle tuning completion interrupt. */ 2097 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2098 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2099 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2100 slot->req->flags |= MMC_TUNE_DONE; 2101 sdhci_finish_command(slot); 2102 sdhci_finish_data(slot); 2103 return; 2104 } 2105 /* Handle PIO interrupt. */ 2106 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2107 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2108 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2109 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2110 &intmask); 2111 slot->flags |= PLATFORM_DATA_STARTED; 2112 } else 2113 sdhci_transfer_pio(slot); 2114 } 2115 /* Handle DMA border. */ 2116 if (intmask & SDHCI_INT_DMA_END) { 2117 data = slot->curcmd->data; 2118 2119 /* Unload DMA buffer ... */ 2120 left = data->len - slot->offset; 2121 if (data->flags & MMC_DATA_READ) { 2122 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2123 BUS_DMASYNC_POSTREAD); 2124 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2125 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 2126 } else { 2127 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2128 BUS_DMASYNC_POSTWRITE); 2129 } 2130 /* ... and reload it again. */ 2131 slot->offset += DMA_BLOCK_SIZE; 2132 left = data->len - slot->offset; 2133 if (data->flags & MMC_DATA_READ) { 2134 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2135 BUS_DMASYNC_PREREAD); 2136 } else { 2137 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2138 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 2139 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2140 BUS_DMASYNC_PREWRITE); 2141 } 2142 /* Interrupt aggregation: Mask border interrupt 2143 * for the last page. */ 2144 if (left == DMA_BLOCK_SIZE) { 2145 slot->intmask &= ~SDHCI_INT_DMA_END; 2146 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2147 } 2148 /* Restart DMA. */ 2149 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2150 } 2151 /* We have got all data. */ 2152 if (intmask & SDHCI_INT_DATA_END) { 2153 if (slot->flags & PLATFORM_DATA_STARTED) { 2154 slot->flags &= ~PLATFORM_DATA_STARTED; 2155 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2156 } else 2157 sdhci_finish_data(slot); 2158 } 2159 done: 2160 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2161 if (slot->flags & PLATFORM_DATA_STARTED) { 2162 slot->flags &= ~PLATFORM_DATA_STARTED; 2163 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2164 } else 2165 sdhci_finish_data(slot); 2166 } 2167 } 2168 2169 static void 2170 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) 2171 { 2172 2173 if (!slot->curcmd) { 2174 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2175 "there is no active command.\n", acmd_err); 2176 sdhci_dumpregs(slot); 2177 return; 2178 } 2179 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err); 2180 sdhci_reset(slot, SDHCI_RESET_CMD); 2181 } 2182 2183 void 2184 sdhci_generic_intr(struct sdhci_slot *slot) 2185 { 2186 uint32_t intmask, present; 2187 uint16_t val16; 2188 2189 SDHCI_LOCK(slot); 2190 /* Read slot interrupt status. */ 2191 intmask = RD4(slot, SDHCI_INT_STATUS); 2192 if (intmask == 0 || intmask == 0xffffffff) { 2193 SDHCI_UNLOCK(slot); 2194 return; 2195 } 2196 if (__predict_false(sdhci_debug > 2)) 2197 slot_printf(slot, "Interrupt %#x\n", intmask); 2198 2199 /* Handle tuning error interrupt. */ 2200 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2201 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR); 2202 slot_printf(slot, "Tuning error indicated\n"); 2203 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2204 if (slot->curcmd) { 2205 slot->curcmd->error = MMC_ERR_BADCRC; 2206 sdhci_finish_command(slot); 2207 } 2208 } 2209 /* Handle re-tuning interrupt. */ 2210 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2211 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2212 /* Handle card presence interrupts. */ 2213 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2214 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2215 slot->intmask &= 2216 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2217 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2218 SDHCI_INT_CARD_INSERT; 2219 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2220 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2221 WR4(slot, SDHCI_INT_STATUS, intmask & 2222 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2223 sdhci_handle_card_present_locked(slot, present); 2224 } 2225 /* Handle command interrupts. */ 2226 if (intmask & SDHCI_INT_CMD_MASK) { 2227 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2228 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2229 } 2230 /* Handle data interrupts. */ 2231 if (intmask & SDHCI_INT_DATA_MASK) { 2232 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2233 /* Don't call data_irq in case of errored command. */ 2234 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2235 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2236 } 2237 /* Handle AutoCMD12 error interrupt. */ 2238 if (intmask & SDHCI_INT_ACMD12ERR) { 2239 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */ 2240 val16 = RD2(slot, SDHCI_ACMD12_ERR); 2241 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2242 sdhci_acmd_irq(slot, val16); 2243 } 2244 /* Handle bus power interrupt. */ 2245 if (intmask & SDHCI_INT_BUS_POWER) { 2246 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2247 slot_printf(slot, "Card is consuming too much power!\n"); 2248 } 2249 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2250 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2251 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2252 /* The rest is unknown. */ 2253 if (intmask) { 2254 WR4(slot, SDHCI_INT_STATUS, intmask); 2255 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2256 intmask); 2257 sdhci_dumpregs(slot); 2258 } 2259 2260 SDHCI_UNLOCK(slot); 2261 } 2262 2263 int 2264 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2265 uintptr_t *result) 2266 { 2267 struct sdhci_slot *slot = device_get_ivars(child); 2268 2269 switch (which) { 2270 default: 2271 return (EINVAL); 2272 case MMCBR_IVAR_BUS_MODE: 2273 *result = slot->host.ios.bus_mode; 2274 break; 2275 case MMCBR_IVAR_BUS_WIDTH: 2276 *result = slot->host.ios.bus_width; 2277 break; 2278 case MMCBR_IVAR_CHIP_SELECT: 2279 *result = slot->host.ios.chip_select; 2280 break; 2281 case MMCBR_IVAR_CLOCK: 2282 *result = slot->host.ios.clock; 2283 break; 2284 case MMCBR_IVAR_F_MIN: 2285 *result = slot->host.f_min; 2286 break; 2287 case MMCBR_IVAR_F_MAX: 2288 *result = slot->host.f_max; 2289 break; 2290 case MMCBR_IVAR_HOST_OCR: 2291 *result = slot->host.host_ocr; 2292 break; 2293 case MMCBR_IVAR_MODE: 2294 *result = slot->host.mode; 2295 break; 2296 case MMCBR_IVAR_OCR: 2297 *result = slot->host.ocr; 2298 break; 2299 case MMCBR_IVAR_POWER_MODE: 2300 *result = slot->host.ios.power_mode; 2301 break; 2302 case MMCBR_IVAR_VDD: 2303 *result = slot->host.ios.vdd; 2304 break; 2305 case MMCBR_IVAR_RETUNE_REQ: 2306 if (slot->opt & SDHCI_TUNING_ENABLED) { 2307 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2308 *result = retune_req_reset; 2309 break; 2310 } 2311 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2312 *result = retune_req_normal; 2313 break; 2314 } 2315 } 2316 *result = retune_req_none; 2317 break; 2318 case MMCBR_IVAR_VCCQ: 2319 *result = slot->host.ios.vccq; 2320 break; 2321 case MMCBR_IVAR_CAPS: 2322 *result = slot->host.caps; 2323 break; 2324 case MMCBR_IVAR_TIMING: 2325 *result = slot->host.ios.timing; 2326 break; 2327 case MMCBR_IVAR_MAX_DATA: 2328 /* 2329 * Re-tuning modes 1 and 2 restrict the maximum data length 2330 * per read/write command to 4 MiB. 2331 */ 2332 if (slot->opt & SDHCI_TUNING_ENABLED && 2333 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2334 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2335 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2336 break; 2337 } 2338 *result = 65535; 2339 break; 2340 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2341 /* 2342 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2343 */ 2344 *result = 1000000; 2345 break; 2346 } 2347 return (0); 2348 } 2349 2350 int 2351 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2352 uintptr_t value) 2353 { 2354 struct sdhci_slot *slot = device_get_ivars(child); 2355 uint32_t clock, max_clock; 2356 int i; 2357 2358 if (sdhci_debug > 1) 2359 slot_printf(slot, "%s: var=%d\n", __func__, which); 2360 switch (which) { 2361 default: 2362 return (EINVAL); 2363 case MMCBR_IVAR_BUS_MODE: 2364 slot->host.ios.bus_mode = value; 2365 break; 2366 case MMCBR_IVAR_BUS_WIDTH: 2367 slot->host.ios.bus_width = value; 2368 break; 2369 case MMCBR_IVAR_CHIP_SELECT: 2370 slot->host.ios.chip_select = value; 2371 break; 2372 case MMCBR_IVAR_CLOCK: 2373 if (value > 0) { 2374 max_clock = slot->max_clk; 2375 clock = max_clock; 2376 2377 if (slot->version < SDHCI_SPEC_300) { 2378 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2379 i <<= 1) { 2380 if (clock <= value) 2381 break; 2382 clock >>= 1; 2383 } 2384 } else { 2385 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2386 i += 2) { 2387 if (clock <= value) 2388 break; 2389 clock = max_clock / (i + 2); 2390 } 2391 } 2392 2393 slot->host.ios.clock = clock; 2394 } else 2395 slot->host.ios.clock = 0; 2396 break; 2397 case MMCBR_IVAR_MODE: 2398 slot->host.mode = value; 2399 break; 2400 case MMCBR_IVAR_OCR: 2401 slot->host.ocr = value; 2402 break; 2403 case MMCBR_IVAR_POWER_MODE: 2404 slot->host.ios.power_mode = value; 2405 break; 2406 case MMCBR_IVAR_VDD: 2407 slot->host.ios.vdd = value; 2408 break; 2409 case MMCBR_IVAR_VCCQ: 2410 slot->host.ios.vccq = value; 2411 break; 2412 case MMCBR_IVAR_TIMING: 2413 slot->host.ios.timing = value; 2414 break; 2415 case MMCBR_IVAR_CAPS: 2416 case MMCBR_IVAR_HOST_OCR: 2417 case MMCBR_IVAR_F_MIN: 2418 case MMCBR_IVAR_F_MAX: 2419 case MMCBR_IVAR_MAX_DATA: 2420 case MMCBR_IVAR_RETUNE_REQ: 2421 return (EINVAL); 2422 } 2423 return (0); 2424 } 2425 2426 #ifdef MMCCAM 2427 void 2428 sdhci_start_slot(struct sdhci_slot *slot) 2429 { 2430 if ((slot->devq = cam_simq_alloc(1)) == NULL) { 2431 goto fail; 2432 } 2433 2434 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2435 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2436 "sdhci_slot", slot, device_get_unit(slot->bus), 2437 &slot->sim_mtx, 1, 1, slot->devq); 2438 2439 if (slot->sim == NULL) { 2440 cam_simq_free(slot->devq); 2441 slot_printf(slot, "cannot allocate CAM SIM\n"); 2442 goto fail; 2443 } 2444 2445 mtx_lock(&slot->sim_mtx); 2446 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2447 slot_printf(slot, 2448 "cannot register SCSI pass-through bus\n"); 2449 cam_sim_free(slot->sim, FALSE); 2450 cam_simq_free(slot->devq); 2451 mtx_unlock(&slot->sim_mtx); 2452 goto fail; 2453 } 2454 2455 mtx_unlock(&slot->sim_mtx); 2456 /* End CAM-specific init */ 2457 slot->card_present = 0; 2458 sdhci_card_task(slot, 0); 2459 return; 2460 2461 fail: 2462 if (slot->sim != NULL) { 2463 mtx_lock(&slot->sim_mtx); 2464 xpt_bus_deregister(cam_sim_path(slot->sim)); 2465 cam_sim_free(slot->sim, FALSE); 2466 mtx_unlock(&slot->sim_mtx); 2467 } 2468 2469 if (slot->devq != NULL) 2470 cam_simq_free(slot->devq); 2471 } 2472 2473 static void 2474 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2475 { 2476 struct sdhci_slot *slot; 2477 2478 slot = cam_sim_softc(sim); 2479 2480 sdhci_cam_request(slot, ccb); 2481 } 2482 2483 void 2484 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2485 { 2486 struct sdhci_slot *slot; 2487 2488 slot = cam_sim_softc(sim); 2489 if (slot == NULL) { 2490 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2491 xpt_done(ccb); 2492 return; 2493 } 2494 2495 mtx_assert(&slot->sim_mtx, MA_OWNED); 2496 2497 switch (ccb->ccb_h.func_code) { 2498 case XPT_PATH_INQ: 2499 { 2500 struct ccb_pathinq *cpi; 2501 2502 cpi = &ccb->cpi; 2503 cpi->version_num = 1; 2504 cpi->hba_inquiry = 0; 2505 cpi->target_sprt = 0; 2506 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2507 cpi->hba_eng_cnt = 0; 2508 cpi->max_target = 0; 2509 cpi->max_lun = 0; 2510 cpi->initiator_id = 1; 2511 cpi->maxio = MAXPHYS; 2512 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2513 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2514 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2515 cpi->unit_number = cam_sim_unit(sim); 2516 cpi->bus_id = cam_sim_bus(sim); 2517 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2518 cpi->protocol = PROTO_MMCSD; 2519 cpi->protocol_version = SCSI_REV_0; 2520 cpi->transport = XPORT_MMCSD; 2521 cpi->transport_version = 0; 2522 2523 cpi->ccb_h.status = CAM_REQ_CMP; 2524 break; 2525 } 2526 case XPT_GET_TRAN_SETTINGS: 2527 { 2528 struct ccb_trans_settings *cts = &ccb->cts; 2529 2530 if (sdhci_debug > 1) 2531 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2532 2533 cts->protocol = PROTO_MMCSD; 2534 cts->protocol_version = 1; 2535 cts->transport = XPORT_MMCSD; 2536 cts->transport_version = 1; 2537 cts->xport_specific.valid = 0; 2538 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2539 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2540 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2541 cts->proto_specific.mmc.host_caps = slot->host.caps; 2542 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2543 ccb->ccb_h.status = CAM_REQ_CMP; 2544 break; 2545 } 2546 case XPT_SET_TRAN_SETTINGS: 2547 { 2548 if (sdhci_debug > 1) 2549 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2550 sdhci_cam_settran_settings(slot, ccb); 2551 ccb->ccb_h.status = CAM_REQ_CMP; 2552 break; 2553 } 2554 case XPT_RESET_BUS: 2555 if (sdhci_debug > 1) 2556 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2557 ccb->ccb_h.status = CAM_REQ_CMP; 2558 break; 2559 case XPT_MMC_IO: 2560 /* 2561 * Here is the HW-dependent part of 2562 * sending the command to the underlying h/w 2563 * At some point in the future an interrupt comes. 2564 * Then the request will be marked as completed. 2565 */ 2566 if (__predict_false(sdhci_debug > 1)) 2567 slot_printf(slot, "Got XPT_MMC_IO\n"); 2568 ccb->ccb_h.status = CAM_REQ_INPROG; 2569 2570 sdhci_cam_handle_mmcio(sim, ccb); 2571 return; 2572 /* NOTREACHED */ 2573 break; 2574 default: 2575 ccb->ccb_h.status = CAM_REQ_INVALID; 2576 break; 2577 } 2578 xpt_done(ccb); 2579 return; 2580 } 2581 2582 void 2583 sdhci_cam_poll(struct cam_sim *sim) 2584 { 2585 return; 2586 } 2587 2588 static int 2589 sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) 2590 { 2591 int max_clock, clock, i; 2592 2593 if (proposed_clock == 0) 2594 return 0; 2595 max_clock = slot->max_clk; 2596 clock = max_clock; 2597 2598 if (slot->version < SDHCI_SPEC_300) { 2599 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2600 i <<= 1) { 2601 if (clock <= proposed_clock) 2602 break; 2603 clock >>= 1; 2604 } 2605 } else { 2606 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2607 i += 2) { 2608 if (clock <= proposed_clock) 2609 break; 2610 clock = max_clock / (i + 2); 2611 } 2612 } 2613 return clock; 2614 } 2615 2616 int 2617 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2618 { 2619 struct mmc_ios *ios; 2620 struct mmc_ios *new_ios; 2621 struct ccb_trans_settings_mmc *cts; 2622 2623 ios = &slot->host.ios; 2624 2625 cts = &ccb->cts.proto_specific.mmc; 2626 new_ios = &cts->ios; 2627 2628 /* Update only requested fields */ 2629 if (cts->ios_valid & MMC_CLK) { 2630 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2631 slot_printf(slot, "Clock => %d\n", ios->clock); 2632 } 2633 if (cts->ios_valid & MMC_VDD) { 2634 ios->vdd = new_ios->vdd; 2635 slot_printf(slot, "VDD => %d\n", ios->vdd); 2636 } 2637 if (cts->ios_valid & MMC_CS) { 2638 ios->chip_select = new_ios->chip_select; 2639 slot_printf(slot, "CS => %d\n", ios->chip_select); 2640 } 2641 if (cts->ios_valid & MMC_BW) { 2642 ios->bus_width = new_ios->bus_width; 2643 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2644 } 2645 if (cts->ios_valid & MMC_PM) { 2646 ios->power_mode = new_ios->power_mode; 2647 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2648 } 2649 if (cts->ios_valid & MMC_BT) { 2650 ios->timing = new_ios->timing; 2651 slot_printf(slot, "Timing => %d\n", ios->timing); 2652 } 2653 if (cts->ios_valid & MMC_BM) { 2654 ios->bus_mode = new_ios->bus_mode; 2655 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2656 } 2657 2658 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2659 return (sdhci_cam_update_ios(slot)); 2660 } 2661 2662 int 2663 sdhci_cam_update_ios(struct sdhci_slot *slot) 2664 { 2665 struct mmc_ios *ios = &slot->host.ios; 2666 2667 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2668 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2669 SDHCI_LOCK(slot); 2670 /* Do full reset on bus power down to clear from any state. */ 2671 if (ios->power_mode == power_off) { 2672 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2673 sdhci_init(slot); 2674 } 2675 /* Configure the bus. */ 2676 sdhci_set_clock(slot, ios->clock); 2677 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2678 if (ios->bus_width == bus_width_8) { 2679 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2680 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2681 } else if (ios->bus_width == bus_width_4) { 2682 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2683 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2684 } else if (ios->bus_width == bus_width_1) { 2685 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2686 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2687 } else { 2688 panic("Invalid bus width: %d", ios->bus_width); 2689 } 2690 if (ios->timing == bus_timing_hs && 2691 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2692 slot->hostctrl |= SDHCI_CTRL_HISPD; 2693 else 2694 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2695 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2696 /* Some controllers like reset after bus changes. */ 2697 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2698 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2699 2700 SDHCI_UNLOCK(slot); 2701 return (0); 2702 } 2703 2704 int 2705 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2706 { 2707 struct ccb_mmcio *mmcio; 2708 2709 mmcio = &ccb->mmcio; 2710 2711 SDHCI_LOCK(slot); 2712 /* if (slot->req != NULL) { 2713 SDHCI_UNLOCK(slot); 2714 return (EBUSY); 2715 } 2716 */ 2717 if (__predict_false(sdhci_debug > 1)) { 2718 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2719 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2720 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2721 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 2722 } 2723 if (mmcio->cmd.data != NULL) { 2724 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2725 panic("data->len = %d, data->flags = %d -- something is b0rked", 2726 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2727 } 2728 slot->ccb = ccb; 2729 slot->flags = 0; 2730 sdhci_start(slot); 2731 SDHCI_UNLOCK(slot); 2732 if (dumping) { 2733 while (slot->ccb != NULL) { 2734 sdhci_generic_intr(slot); 2735 DELAY(10); 2736 } 2737 } 2738 return (0); 2739 } 2740 #endif /* MMCCAM */ 2741 2742 MODULE_VERSION(sdhci, 1); 2743